drivers/spi/spi-atmel.c

   1 /*
   2  * Driver for Atmel AT32 and AT91 SPI Controllers
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/clk.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/delay.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmaengine.h>
  18 #include <linux/err.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_data/atmel.h>
  23 #include <linux/platform_data/dma-atmel.h>
  24 #include <linux/of.h>
  25
  26 #include <linux/io.h>
  27 #include <linux/gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/pm_runtime.h>
  30
  31 /* SPI register offsets */
  32 #define SPI_CR                                  0x0000
  33 #define SPI_MR                                  0x0004
  34 #define SPI_RDR                                 0x0008
  35 #define SPI_TDR                                 0x000c
  36 #define SPI_SR                                  0x0010
  37 #define SPI_IER                                 0x0014
  38 #define SPI_IDR                                 0x0018
  39 #define SPI_IMR                                 0x001c
  40 #define SPI_CSR0                                0x0030
  41 #define SPI_CSR1                                0x0034
  42 #define SPI_CSR2                                0x0038
  43 #define SPI_CSR3                                0x003c
  44 #define SPI_VERSION                             0x00fc
  45 #define SPI_RPR                                 0x0100
  46 #define SPI_RCR                                 0x0104
  47 #define SPI_TPR                                 0x0108
  48 #define SPI_TCR                                 0x010c
  49 #define SPI_RNPR                                0x0110
  50 #define SPI_RNCR                                0x0114
  51 #define SPI_TNPR                                0x0118
  52 #define SPI_TNCR                                0x011c
  53 #define SPI_PTCR                                0x0120
  54 #define SPI_PTSR                                0x0124
  55
  56 /* Bitfields in CR */
  57 #define SPI_SPIEN_OFFSET                        0
  58 #define SPI_SPIEN_SIZE                          1
  59 #define SPI_SPIDIS_OFFSET                       1
  60 #define SPI_SPIDIS_SIZE                         1
  61 #define SPI_SWRST_OFFSET                        7
  62 #define SPI_SWRST_SIZE                          1
  63 #define SPI_LASTXFER_OFFSET                     24
  64 #define SPI_LASTXFER_SIZE                       1
  65
  66 /* Bitfields in MR */
  67 #define SPI_MSTR_OFFSET                         0
  68 #define SPI_MSTR_SIZE                           1
  69 #define SPI_PS_OFFSET                           1
  70 #define SPI_PS_SIZE                             1
  71 #define SPI_PCSDEC_OFFSET                       2
  72 #define SPI_PCSDEC_SIZE                         1
  73 #define SPI_FDIV_OFFSET                         3
  74 #define SPI_FDIV_SIZE                           1
  75 #define SPI_MODFDIS_OFFSET                      4
  76 #define SPI_MODFDIS_SIZE                        1
  77 #define SPI_WDRBT_OFFSET                        5
  78 #define SPI_WDRBT_SIZE                          1
  79 #define SPI_LLB_OFFSET                          7
  80 #define SPI_LLB_SIZE                            1
  81 #define SPI_PCS_OFFSET                          16
  82 #define SPI_PCS_SIZE                            4
  83 #define SPI_DLYBCS_OFFSET                       24
  84 #define SPI_DLYBCS_SIZE                         8
  85
  86 /* Bitfields in RDR */
  87 #define SPI_RD_OFFSET                           0
  88 #define SPI_RD_SIZE                             16
  89
  90 /* Bitfields in TDR */
  91 #define SPI_TD_OFFSET                           0
  92 #define SPI_TD_SIZE                             16
  93
  94 /* Bitfields in SR */
  95 #define SPI_RDRF_OFFSET                         0
  96 #define SPI_RDRF_SIZE                           1
  97 #define SPI_TDRE_OFFSET                         1
  98 #define SPI_TDRE_SIZE                           1
  99 #define SPI_MODF_OFFSET                         2
 100 #define SPI_MODF_SIZE                           1
 101 #define SPI_OVRES_OFFSET                        3
 102 #define SPI_OVRES_SIZE                          1
 103 #define SPI_ENDRX_OFFSET                        4
 104 #define SPI_ENDRX_SIZE                          1
 105 #define SPI_ENDTX_OFFSET                        5
 106 #define SPI_ENDTX_SIZE                          1
 107 #define SPI_RXBUFF_OFFSET                       6
 108 #define SPI_RXBUFF_SIZE                         1
 109 #define SPI_TXBUFE_OFFSET                       7
 110 #define SPI_TXBUFE_SIZE                         1
 111 #define SPI_NSSR_OFFSET                         8
 112 #define SPI_NSSR_SIZE                           1
 113 #define SPI_TXEMPTY_OFFSET                      9
 114 #define SPI_TXEMPTY_SIZE                        1
 115 #define SPI_SPIENS_OFFSET                       16
 116 #define SPI_SPIENS_SIZE                         1
 117
 118 /* Bitfields in CSR0 */
 119 #define SPI_CPOL_OFFSET                         0
 120 #define SPI_CPOL_SIZE                           1
 121 #define SPI_NCPHA_OFFSET                        1
 122 #define SPI_NCPHA_SIZE                          1
 123 #define SPI_CSAAT_OFFSET                        3
 124 #define SPI_CSAAT_SIZE                          1
 125 #define SPI_BITS_OFFSET                         4
 126 #define SPI_BITS_SIZE                           4
 127 #define SPI_SCBR_OFFSET                         8
 128 #define SPI_SCBR_SIZE                           8
 129 #define SPI_DLYBS_OFFSET                        16
 130 #define SPI_DLYBS_SIZE                          8
 131 #define SPI_DLYBCT_OFFSET                       24
 132 #define SPI_DLYBCT_SIZE                         8
 133
 134 /* Bitfields in RCR */
 135 #define SPI_RXCTR_OFFSET                        0
 136 #define SPI_RXCTR_SIZE                          16
 137
 138 /* Bitfields in TCR */
 139 #define SPI_TXCTR_OFFSET                        0
 140 #define SPI_TXCTR_SIZE                          16
 141
 142 /* Bitfields in RNCR */
 143 #define SPI_RXNCR_OFFSET                        0
 144 #define SPI_RXNCR_SIZE                          16
 145
 146 /* Bitfields in TNCR */
 147 #define SPI_TXNCR_OFFSET                        0
 148 #define SPI_TXNCR_SIZE                          16
 149
 150 /* Bitfields in PTCR */
 151 #define SPI_RXTEN_OFFSET                        0
 152 #define SPI_RXTEN_SIZE                          1
 153 #define SPI_RXTDIS_OFFSET                       1
 154 #define SPI_RXTDIS_SIZE                         1
 155 #define SPI_TXTEN_OFFSET                        8
 156 #define SPI_TXTEN_SIZE                          1
 157 #define SPI_TXTDIS_OFFSET                       9
 158 #define SPI_TXTDIS_SIZE                         1
 159
 160 /* Constants for BITS */
 161 #define SPI_BITS_8_BPT                          0
 162 #define SPI_BITS_9_BPT                          1
 163 #define SPI_BITS_10_BPT                         2
 164 #define SPI_BITS_11_BPT                         3
 165 #define SPI_BITS_12_BPT                         4
 166 #define SPI_BITS_13_BPT                         5
 167 #define SPI_BITS_14_BPT                         6
 168 #define SPI_BITS_15_BPT                         7
 169 #define SPI_BITS_16_BPT                         8
 170
 171 /* Bit manipulation macros */
 172 #define SPI_BIT(name) \
 173         (1 << SPI_##name##_OFFSET)
 174 #define SPI_BF(name, value) \
 175         (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
 176 #define SPI_BFEXT(name, value) \
 177         (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
 178 #define SPI_BFINS(name, value, old) \
 179         (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
 180           | SPI_BF(name, value))
 181
 182 /* Register access macros */
 183 #define spi_readl(port, reg) \
 184         __raw_readl((port)->regs + SPI_##reg)
 185 #define spi_writel(port, reg, value) \
 186         __raw_writel((value), (port)->regs + SPI_##reg)
 187
 188 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 189  * cache operations; better heuristics consider wordsize and bitrate.
 190  */
 191 #define DMA_MIN_BYTES   16
 192
 193 #define SPI_DMA_TIMEOUT         (msecs_to_jiffies(1000))
 194
 195 #define AUTOSUSPEND_TIMEOUT     2000
 196
 197 struct atmel_spi_dma {
 198         struct dma_chan                 *chan_rx;
 199         struct dma_chan                 *chan_tx;
 200         struct scatterlist              sgrx;
 201         struct scatterlist              sgtx;
 202         struct dma_async_tx_descriptor  *data_desc_rx;
 203         struct dma_async_tx_descriptor  *data_desc_tx;
 204
 205         struct at_dma_slave     dma_slave;
 206 };
 207
 208 struct atmel_spi_caps {
 209         bool    is_spi2;
 210         bool    has_wdrbt;
 211         bool    has_dma_support;
 212 };
 213
 214 /*
 215  * The core SPI transfer engine just talks to a register bank to set up
 216  * DMA transfers; transfer queue progress is driven by IRQs.  The clock
 217  * framework provides the base clock, subdivided for each spi_device.
 218  */
 219 struct atmel_spi {
 220         spinlock_t              lock;
 221         unsigned long           flags;
 222
 223         phys_addr_t             phybase;
 224         void __iomem            *regs;
 225         int                     irq;
 226         struct clk              *clk;
 227         struct platform_device  *pdev;
 228
 229         struct spi_transfer     *current_transfer;
 230         int                     current_remaining_bytes;
 231         int                     done_status;
 232
 233         struct completion       xfer_completion;
 234
 235         /* scratch buffer */
 236         void                    *buffer;
 237         dma_addr_t              buffer_dma;
 238
 239         struct atmel_spi_caps   caps;
 240
 241         bool                    use_dma;
 242         bool                    use_pdc;
 243         /* dmaengine data */
 244         struct atmel_spi_dma    dma;
 245
 246         bool                    keep_cs;
 247         bool                    cs_active;
 248 };
 249
 250 /* Controller-specific per-slave state */
 251 struct atmel_spi_device {
 252         unsigned int            npcs_pin;
 253         u32                     csr;
 254 };
 255
 256 #define BUFFER_SIZE             PAGE_SIZE
 257 #define INVALID_DMA_ADDRESS     0xffffffff
 258
 259 /*
 260  * Version 2 of the SPI controller has
 261  *  - CR.LASTXFER
 262  *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
 263  *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
 264  *  - SPI_CSRx.CSAAT
 265  *  - SPI_CSRx.SBCR allows faster clocking
 266  */
 267 static bool atmel_spi_is_v2(struct atmel_spi *as)
 268 {
 269         return as->caps.is_spi2;
 270 }
 271
 272 /*
 273  * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
 274  * they assume that spi slave device state will not change on deselect, so
 275  * that automagic deselection is OK.  ("NPCSx rises if no data is to be
 276  * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
 277  * controllers have CSAAT and friends.
 278  *
 279  * Since the CSAAT functionality is a bit weird on newer controllers as
 280  * well, we use GPIO to control nCSx pins on all controllers, updating
 281  * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
 282  * support active-high chipselects despite the controller's belief that
 283  * only active-low devices/systems exists.
 284  *
 285  * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
 286  * right when driven with GPIO.  ("Mode Fault does not allow more than one
 287  * Master on Chip Select 0.")  No workaround exists for that ... so for
 288  * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
 289  * and (c) will trigger that first erratum in some cases.
 290  */
 291
 292 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 293 {
 294         struct atmel_spi_device *asd = spi->controller_state;
 295         unsigned active = spi->mode & SPI_CS_HIGH;
 296         u32 mr;
 297
 298         if (atmel_spi_is_v2(as)) {
 299                 spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
 300                 /* For the low SPI version, there is a issue that PDC transfer
 301                  * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
 302                  */
 303                 spi_writel(as, CSR0, asd->csr);
 304                 if (as->caps.has_wdrbt) {
 305                         spi_writel(as, MR,
 306                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 307                                         | SPI_BIT(WDRBT)
 308                                         | SPI_BIT(MODFDIS)
 309                                         | SPI_BIT(MSTR));
 310                 } else {
 311                         spi_writel(as, MR,
 312                                         SPI_BF(PCS, ~(0x01 << spi->chip_select))
 313                                         | SPI_BIT(MODFDIS)
 314                                         | SPI_BIT(MSTR));
 315                 }
 316
 317                 mr = spi_readl(as, MR);
 318                 gpio_set_value(asd->npcs_pin, active);
 319         } else {
 320                 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
 321                 int i;
 322                 u32 csr;
 323
 324                 /* Make sure clock polarity is correct */
 325                 for (i = 0; i < spi->master->num_chipselect; i++) {
 326                         csr = spi_readl(as, CSR0 + 4 * i);
 327                         if ((csr ^ cpol) & SPI_BIT(CPOL))
 328                                 spi_writel(as, CSR0 + 4 * i,
 329                                                 csr ^ SPI_BIT(CPOL));
 330                 }
 331
 332                 mr = spi_readl(as, MR);
 333                 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
 334                 if (spi->chip_select != 0)
 335                         gpio_set_value(asd->npcs_pin, active);
 336                 spi_writel(as, MR, mr);
 337         }
 338
 339         dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
 340                         asd->npcs_pin, active ? " (high)" : "",
 341                         mr);
 342 }
 343
 344 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 345 {
 346         struct atmel_spi_device *asd = spi->controller_state;
 347         unsigned active = spi->mode & SPI_CS_HIGH;
 348         u32 mr;
 349
 350         /* only deactivate *this* device; sometimes transfers to
 351          * another device may be active when this routine is called.
 352          */
 353         mr = spi_readl(as, MR);
 354         if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
 355                 mr = SPI_BFINS(PCS, 0xf, mr);
 356                 spi_writel(as, MR, mr);
 357         }
 358
 359         dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
 360                         asd->npcs_pin, active ? " (low)" : "",
 361                         mr);
 362
 363         if (atmel_spi_is_v2(as) || spi->chip_select != 0)
 364                 gpio_set_value(asd->npcs_pin, !active);
 365 }
 366
 367 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
 368 {
 369         spin_lock_irqsave(&as->lock, as->flags);
 370 }
 371
 372 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
 373 {
 374         spin_unlock_irqrestore(&as->lock, as->flags);
 375 }
 376
 377 static inline bool atmel_spi_use_dma(struct atmel_spi *as,
 378                                 struct spi_transfer *xfer)
 379 {
 380         return as->use_dma && xfer->len >= DMA_MIN_BYTES;
 381 }
 382
 383 static int atmel_spi_dma_slave_config(struct atmel_spi *as,
 384                                 struct dma_slave_config *slave_config,
 385                                 u8 bits_per_word)
 386 {
 387         int err = 0;
 388
 389         if (bits_per_word > 8) {
 390                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 391                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 392         } else {
 393                 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 394                 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 395         }
 396
 397         slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
 398         slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
 399         slave_config->src_maxburst = 1;
 400         slave_config->dst_maxburst = 1;
 401         slave_config->device_fc = false;
 402
 403         slave_config->direction = DMA_MEM_TO_DEV;
 404         if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
 405                 dev_err(&as->pdev->dev,
 406                         "failed to configure tx dma channel\n");
 407                 err = -EINVAL;
 408         }
 409
 410         slave_config->direction = DMA_DEV_TO_MEM;
 411         if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
 412                 dev_err(&as->pdev->dev,
 413                         "failed to configure rx dma channel\n");
 414                 err = -EINVAL;
 415         }
 416
 417         return err;
 418 }
 419
 420 static bool filter(struct dma_chan *chan, void *pdata)
 421 {
 422         struct atmel_spi_dma *sl_pdata = pdata;
 423         struct at_dma_slave *sl;
 424
 425         if (!sl_pdata)
 426                 return false;
 427
 428         sl = &sl_pdata->dma_slave;
 429         if (sl->dma_dev == chan->device->dev) {
 430                 chan->private = sl;
 431                 return true;
 432         } else {
 433                 return false;
 434         }
 435 }
 436
 437 static int atmel_spi_configure_dma(struct atmel_spi *as)
 438 {
 439         struct dma_slave_config slave_config;
 440         struct device *dev = &as->pdev->dev;
 441         int err;
 442
 443         dma_cap_mask_t mask;
 444         dma_cap_zero(mask);
 445         dma_cap_set(DMA_SLAVE, mask);
 446
 447         as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter,
 448                                                            &as->dma,
 449                                                            dev, "tx");
 450         if (!as->dma.chan_tx) {
 451                 dev_err(dev,
 452                         "DMA TX channel not available, SPI unable to use DMA\n");
 453                 err = -EBUSY;
 454                 goto error;
 455         }
 456
 457         as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter,
 458                                                            &as->dma,
 459                                                            dev, "rx");
 460
 461         if (!as->dma.chan_rx) {
 462                 dev_err(dev,
 463                         "DMA RX channel not available, SPI unable to use DMA\n");
 464                 err = -EBUSY;
 465                 goto error;
 466         }
 467
 468         err = atmel_spi_dma_slave_config(as, &slave_config, 8);
 469         if (err)
 470                 goto error;
 471
 472         dev_info(&as->pdev->dev,
 473                         "Using %s (tx) and %s (rx) for DMA transfers\n",
 474                         dma_chan_name(as->dma.chan_tx),
 475                         dma_chan_name(as->dma.chan_rx));
 476         return 0;
 477 error:
 478         if (as->dma.chan_rx)
 479                 dma_release_channel(as->dma.chan_rx);
 480         if (as->dma.chan_tx)
 481                 dma_release_channel(as->dma.chan_tx);
 482         return err;
 483 }
 484
 485 static void atmel_spi_stop_dma(struct atmel_spi *as)
 486 {
 487         if (as->dma.chan_rx)
 488                 dmaengine_terminate_all(as->dma.chan_rx);
 489         if (as->dma.chan_tx)
 490                 dmaengine_terminate_all(as->dma.chan_tx);
 491 }
 492
 493 static void atmel_spi_release_dma(struct atmel_spi *as)
 494 {
 495         if (as->dma.chan_rx)
 496                 dma_release_channel(as->dma.chan_rx);
 497         if (as->dma.chan_tx)
 498                 dma_release_channel(as->dma.chan_tx);
 499 }
 500
 501 /* This function is called by the DMA driver from tasklet context */
 502 static void dma_callback(void *data)
 503 {
 504         struct spi_master       *master = data;
 505         struct atmel_spi        *as = spi_master_get_devdata(master);
 506
 507         complete(&as->xfer_completion);
 508 }
 509
 510 /*
 511  * Next transfer using PIO.
 512  */
 513 static void atmel_spi_next_xfer_pio(struct spi_master *master,
 514                                 struct spi_transfer *xfer)
 515 {
 516         struct atmel_spi        *as = spi_master_get_devdata(master);
 517         unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
 518
 519         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
 520
 521         /* Make sure data is not remaining in RDR */
 522         spi_readl(as, RDR);
 523         while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
 524                 spi_readl(as, RDR);
 525                 cpu_relax();
 526         }
 527
 528         if (xfer->tx_buf) {
 529                 if (xfer->bits_per_word > 8)
 530                         spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
 531                 else
 532                         spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
 533         } else {
 534                 spi_writel(as, TDR, 0);
 535         }
 536
 537         dev_dbg(master->dev.parent,
 538                 "  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
 539                 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
 540                 xfer->bits_per_word);
 541
 542         /* Enable relevant interrupts */
 543         spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
 544 }
 545
 546 /*
 547  * Submit next transfer for DMA.
 548  */
 549 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
 550                                 struct spi_transfer *xfer,
 551                                 u32 *plen)
 552 {
 553         struct atmel_spi        *as = spi_master_get_devdata(master);
 554         struct dma_chan         *rxchan = as->dma.chan_rx;
 555         struct dma_chan         *txchan = as->dma.chan_tx;
 556         struct dma_async_tx_descriptor *rxdesc;
 557         struct dma_async_tx_descriptor *txdesc;
 558         struct dma_slave_config slave_config;
 559         dma_cookie_t            cookie;
 560         u32     len = *plen;
 561
 562         dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
 563
 564         /* Check that the channels are available */
 565         if (!rxchan || !txchan)
 566                 return -ENODEV;
 567
 568         /* release lock for DMA operations */
 569         atmel_spi_unlock(as);
 570
 571         /* prepare the RX dma transfer */
 572         sg_init_table(&as->dma.sgrx, 1);
 573         if (xfer->rx_buf) {
 574                 as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
 575         } else {
 576                 as->dma.sgrx.dma_address = as->buffer_dma;
 577                 if (len > BUFFER_SIZE)
 578                         len = BUFFER_SIZE;
 579         }
 580
 581         /* prepare the TX dma transfer */
 582         sg_init_table(&as->dma.sgtx, 1);
 583         if (xfer->tx_buf) {
 584                 as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
 585         } else {
 586                 as->dma.sgtx.dma_address = as->buffer_dma;
 587                 if (len > BUFFER_SIZE)
 588                         len = BUFFER_SIZE;
 589                 memset(as->buffer, 0, len);
 590         }
 591
 592         sg_dma_len(&as->dma.sgtx) = len;
 593         sg_dma_len(&as->dma.sgrx) = len;
 594
 595         *plen = len;
 596
 597         if (atmel_spi_dma_slave_config(as, &slave_config, 8))
 598                 goto err_exit;
 599
 600         /* Send both scatterlists */
 601         rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1,
 602                                          DMA_FROM_DEVICE,
 603                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 604         if (!rxdesc)
 605                 goto err_dma;
 606
 607         txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1,
 608                                          DMA_TO_DEVICE,
 609                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 610         if (!txdesc)
 611                 goto err_dma;
 612
 613         dev_dbg(master->dev.parent,
 614                 "  start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 615                 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
 616                 xfer->rx_buf, (unsigned long long)xfer->rx_dma);
 617
 618         /* Enable relevant interrupts */
 619         spi_writel(as, IER, SPI_BIT(OVRES));
 620
 621         /* Put the callback on the RX transfer only, that should finish last */
 622         rxdesc->callback = dma_callback;
 623         rxdesc->callback_param = master;
 624
 625         /* Submit and fire RX and TX with TX last so we're ready to read! */
 626         cookie = rxdesc->tx_submit(rxdesc);
 627         if (dma_submit_error(cookie))
 628                 goto err_dma;
 629         cookie = txdesc->tx_submit(txdesc);
 630         if (dma_submit_error(cookie))
 631                 goto err_dma;
 632         rxchan->device->device_issue_pending(rxchan);
 633         txchan->device->device_issue_pending(txchan);
 634
 635         /* take back lock */
 636         atmel_spi_lock(as);
 637         return 0;
 638
 639 err_dma:
 640         spi_writel(as, IDR, SPI_BIT(OVRES));
 641         atmel_spi_stop_dma(as);
 642 err_exit:
 643         atmel_spi_lock(as);
 644         return -ENOMEM;
 645 }
 646
 647 static void atmel_spi_next_xfer_data(struct spi_master *master,
 648                                 struct spi_transfer *xfer,
 649                                 dma_addr_t *tx_dma,
 650                                 dma_addr_t *rx_dma,
 651                                 u32 *plen)
 652 {
 653         struct atmel_spi        *as = spi_master_get_devdata(master);
 654         u32                     len = *plen;
 655
 656         /* use scratch buffer only when rx or tx data is unspecified */
 657         if (xfer->rx_buf)
 658                 *rx_dma = xfer->rx_dma + xfer->len - *plen;
 659         else {
 660                 *rx_dma = as->buffer_dma;
 661                 if (len > BUFFER_SIZE)
 662                         len = BUFFER_SIZE;
 663         }
 664
 665         if (xfer->tx_buf)
 666                 *tx_dma = xfer->tx_dma + xfer->len - *plen;
 667         else {
 668                 *tx_dma = as->buffer_dma;
 669                 if (len > BUFFER_SIZE)
 670                         len = BUFFER_SIZE;
 671                 memset(as->buffer, 0, len);
 672                 dma_sync_single_for_device(&as->pdev->dev,
 673                                 as->buffer_dma, len, DMA_TO_DEVICE);
 674         }
 675
 676         *plen = len;
 677 }
 678
 679 static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
 680                                     struct spi_device *spi,
 681                                     struct spi_transfer *xfer)
 682 {
 683         u32                     scbr, csr;
 684         unsigned long           bus_hz;
 685
 686         /* v1 chips start out at half the peripheral bus speed. */
 687         bus_hz = clk_get_rate(as->clk);
 688         if (!atmel_spi_is_v2(as))
 689                 bus_hz /= 2;
 690
 691         /*
 692          * Calculate the lowest divider that satisfies the
 693          * constraint, assuming div32/fdiv/mbz == 0.
 694          */
 695         if (xfer->speed_hz)
 696                 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
 697         else
 698                 /*
 699                  * This can happend if max_speed is null.
 700                  * In this case, we set the lowest possible speed
 701                  */
 702                 scbr = 0xff;
 703
 704         /*
 705          * If the resulting divider doesn't fit into the
 706          * register bitfield, we can't satisfy the constraint.
 707          */
 708         if (scbr >= (1 << SPI_SCBR_SIZE)) {
 709                 dev_err(&spi->dev,
 710                         "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
 711                         xfer->speed_hz, scbr, bus_hz/255);
 712                 return -EINVAL;
 713         }
 714         if (scbr == 0) {
 715                 dev_err(&spi->dev,
 716                         "setup: %d Hz too high, scbr %u; max %ld Hz\n",
 717                         xfer->speed_hz, scbr, bus_hz);
 718                 return -EINVAL;
 719         }
 720         csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
 721         csr = SPI_BFINS(SCBR, scbr, csr);
 722         spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
 723
 724         return 0;
 725 }
 726
 727 /*
 728  * Submit next transfer for PDC.
 729  * lock is held, spi irq is blocked
 730  */
 731 static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 732                                         struct spi_message *msg,
 733                                         struct spi_transfer *xfer)
 734 {
 735         struct atmel_spi        *as = spi_master_get_devdata(master);
 736         u32                     len;
 737         dma_addr_t              tx_dma, rx_dma;
 738
 739         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 740
 741         len = as->current_remaining_bytes;
 742         atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 743         as->current_remaining_bytes -= len;
 744
 745         spi_writel(as, RPR, rx_dma);
 746         spi_writel(as, TPR, tx_dma);
 747
 748         if (msg->spi->bits_per_word > 8)
 749                 len >>= 1;
 750         spi_writel(as, RCR, len);
 751         spi_writel(as, TCR, len);
 752
 753         dev_dbg(&msg->spi->dev,
 754                 "  start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 755                 xfer, xfer->len, xfer->tx_buf,
 756                 (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 757                 (unsigned long long)xfer->rx_dma);
 758
 759         if (as->current_remaining_bytes) {
 760                 len = as->current_remaining_bytes;
 761                 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
 762                 as->current_remaining_bytes -= len;
 763
 764                 spi_writel(as, RNPR, rx_dma);
 765                 spi_writel(as, TNPR, tx_dma);
 766
 767                 if (msg->spi->bits_per_word > 8)
 768                         len >>= 1;
 769                 spi_writel(as, RNCR, len);
 770                 spi_writel(as, TNCR, len);
 771
 772                 dev_dbg(&msg->spi->dev,
 773                         "  next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
 774                         xfer, xfer->len, xfer->tx_buf,
 775                         (unsigned long long)xfer->tx_dma, xfer->rx_buf,
 776                         (unsigned long long)xfer->rx_dma);
 777         }
 778
 779         /* REVISIT: We're waiting for ENDRX before we start the next
 780          * transfer because we need to handle some difficult timing
 781          * issues otherwise. If we wait for ENDTX in one transfer and
 782          * then starts waiting for ENDRX in the next, it's difficult
 783          * to tell the difference between the ENDRX interrupt we're
 784          * actually waiting for and the ENDRX interrupt of the
 785          * previous transfer.
 786          *
 787          * It should be doable, though. Just not now...
 788          */
 789         spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
 790         spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 791 }
 792
 793 /*
 794  * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
 795  *  - The buffer is either valid for CPU access, else NULL
 796  *  - If the buffer is valid, so is its DMA address
 797  *
 798  * This driver manages the dma address unless message->is_dma_mapped.
 799  */
 800 static int
 801 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
 802 {
 803         struct device   *dev = &as->pdev->dev;
 804
 805         xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
 806         if (xfer->tx_buf) {
 807                 /* tx_buf is a const void* where we need a void * for the dma
 808                  * mapping */
 809                 void *nonconst_tx = (void *)xfer->tx_buf;
 810
 811                 xfer->tx_dma = dma_map_single(dev,
 812                                 nonconst_tx, xfer->len,
 813                                 DMA_TO_DEVICE);
 814                 if (dma_mapping_error(dev, xfer->tx_dma))
 815                         return -ENOMEM;
 816         }
 817         if (xfer->rx_buf) {
 818                 xfer->rx_dma = dma_map_single(dev,
 819                                 xfer->rx_buf, xfer->len,
 820                                 DMA_FROM_DEVICE);
 821                 if (dma_mapping_error(dev, xfer->rx_dma)) {
 822                         if (xfer->tx_buf)
 823                                 dma_unmap_single(dev,
 824                                                 xfer->tx_dma, xfer->len,
 825                                                 DMA_TO_DEVICE);
 826                         return -ENOMEM;
 827                 }
 828         }
 829         return 0;
 830 }
 831
 832 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 833                                      struct spi_transfer *xfer)
 834 {
 835         if (xfer->tx_dma != INVALID_DMA_ADDRESS)
 836                 dma_unmap_single(master->dev.parent, xfer->tx_dma,
 837                                  xfer->len, DMA_TO_DEVICE);
 838         if (xfer->rx_dma != INVALID_DMA_ADDRESS)
 839                 dma_unmap_single(master->dev.parent, xfer->rx_dma,
 840                                  xfer->len, DMA_FROM_DEVICE);
 841 }
 842
 843 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
 844 {
 845         spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 846 }
 847
 848 /* Called from IRQ
 849  *
 850  * Must update "current_remaining_bytes" to keep track of data
 851  * to transfer.
 852  */
 853 static void
 854 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
 855 {
 856         u8              *rxp;
 857         u16             *rxp16;
 858         unsigned long   xfer_pos = xfer->len - as->current_remaining_bytes;
 859
 860         if (xfer->rx_buf) {
 861                 if (xfer->bits_per_word > 8) {
 862                         rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
 863                         *rxp16 = spi_readl(as, RDR);
 864                 } else {
 865                         rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
 866                         *rxp = spi_readl(as, RDR);
 867                 }
 868         } else {
 869                 spi_readl(as, RDR);
 870         }
 871         if (xfer->bits_per_word > 8) {
 872                 if (as->current_remaining_bytes > 2)
 873                         as->current_remaining_bytes -= 2;
 874                 else
 875                         as->current_remaining_bytes = 0;
 876         } else {
 877                 as->current_remaining_bytes--;
 878         }
 879 }
 880
 881 /* Interrupt
 882  *
 883  * No need for locking in this Interrupt handler: done_status is the
 884  * only information modified.
 885  */
 886 static irqreturn_t
 887 atmel_spi_pio_interrupt(int irq, void *dev_id)
 888 {
 889         struct spi_master       *master = dev_id;
 890         struct atmel_spi        *as = spi_master_get_devdata(master);
 891         u32                     status, pending, imr;
 892         struct spi_transfer     *xfer;
 893         int                     ret = IRQ_NONE;
 894
 895         imr = spi_readl(as, IMR);
 896         status = spi_readl(as, SR);
 897         pending = status & imr;
 898
 899         if (pending & SPI_BIT(OVRES)) {
 900                 ret = IRQ_HANDLED;
 901                 spi_writel(as, IDR, SPI_BIT(OVRES));
 902                 dev_warn(master->dev.parent, "overrun\n");
 903
 904                 /*
 905                  * When we get an overrun, we disregard the current
 906                  * transfer. Data will not be copied back from any
 907                  * bounce buffer and msg->actual_len will not be
 908                  * updated with the last xfer.
 909                  *
 910                  * We will also not process any remaning transfers in
 911                  * the message.
 912                  */
 913                 as->done_status = -EIO;
 914                 smp_wmb();
 915
 916                 /* Clear any overrun happening while cleaning up */
 917                 spi_readl(as, SR);
 918
 919                 complete(&as->xfer_completion);
 920
 921         } else if (pending & SPI_BIT(RDRF)) {
 922                 atmel_spi_lock(as);
 923
 924                 if (as->current_remaining_bytes) {
 925                         ret = IRQ_HANDLED;
 926                         xfer = as->current_transfer;
 927                         atmel_spi_pump_pio_data(as, xfer);
 928                         if (!as->current_remaining_bytes)
 929                                 spi_writel(as, IDR, pending);
 930
 931                         complete(&as->xfer_completion);
 932                 }
 933
 934                 atmel_spi_unlock(as);
 935         } else {
 936                 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
 937                 ret = IRQ_HANDLED;
 938                 spi_writel(as, IDR, pending);
 939         }
 940
 941         return ret;
 942 }
 943
 944 static irqreturn_t
 945 atmel_spi_pdc_interrupt(int irq, void *dev_id)
 946 {
 947         struct spi_master       *master = dev_id;
 948         struct atmel_spi        *as = spi_master_get_devdata(master);
 949         u32                     status, pending, imr;
 950         int                     ret = IRQ_NONE;
 951
 952         imr = spi_readl(as, IMR);
 953         status = spi_readl(as, SR);
 954         pending = status & imr;
 955
 956         if (pending & SPI_BIT(OVRES)) {
 957
 958                 ret = IRQ_HANDLED;
 959
 960                 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
 961                                      | SPI_BIT(OVRES)));
 962
 963                 /* Clear any overrun happening while cleaning up */
 964                 spi_readl(as, SR);
 965
 966                 as->done_status = -EIO;
 967
 968                 complete(&as->xfer_completion);
 969
 970         } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
 971                 ret = IRQ_HANDLED;
 972
 973                 spi_writel(as, IDR, pending);
 974
 975                 complete(&as->xfer_completion);
 976         }
 977
 978         return ret;
 979 }
 980
 981 static int atmel_spi_setup(struct spi_device *spi)
 982 {
 983         struct atmel_spi        *as;
 984         struct atmel_spi_device *asd;
 985         u32                     csr;
 986         unsigned int            bits = spi->bits_per_word;
 987         unsigned int            npcs_pin;
 988         int                     ret;
 989
 990         as = spi_master_get_devdata(spi->master);
 991
 992         /* see notes above re chipselect */
 993         if (!atmel_spi_is_v2(as)
 994                         && spi->chip_select == 0
 995                         && (spi->mode & SPI_CS_HIGH)) {
 996                 dev_dbg(&spi->dev, "setup: can't be active-high\n");
 997                 return -EINVAL;
 998         }
 999
1000         csr = SPI_BF(BITS, bits - 8);
1001         if (spi->mode & SPI_CPOL)
1002                 csr |= SPI_BIT(CPOL);
1003         if (!(spi->mode & SPI_CPHA))
1004                 csr |= SPI_BIT(NCPHA);
1005
1006         /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1007          *
1008          * DLYBCT would add delays between words, slowing down transfers.
1009          * It could potentially be useful to cope with DMA bottlenecks, but
1010          * in those cases it's probably best to just use a lower bitrate.
1011          */
1012         csr |= SPI_BF(DLYBS, 0);
1013         csr |= SPI_BF(DLYBCT, 0);
1014
1015         /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1016         npcs_pin = (unsigned long)spi->controller_data;
1017
1018         if (gpio_is_valid(spi->cs_gpio))
1019                 npcs_pin = spi->cs_gpio;
1020
1021         asd = spi->controller_state;
1022         if (!asd) {
1023                 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
1024                 if (!asd)
1025                         return -ENOMEM;
1026
1027                 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
1028                 if (ret) {
1029                         kfree(asd);
1030                         return ret;
1031                 }
1032
1033                 asd->npcs_pin = npcs_pin;
1034                 spi->controller_state = asd;
1035                 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
1036         }
1037
1038         asd->csr = csr;
1039
1040         dev_dbg(&spi->dev,
1041                 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1042                 bits, spi->mode, spi->chip_select, csr);
1043
1044         if (!atmel_spi_is_v2(as))
1045                 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
1046
1047         return 0;
1048 }
1049
1050 static int atmel_spi_one_transfer(struct spi_master *master,
1051                                         struct spi_message *msg,
1052                                         struct spi_transfer *xfer)
1053 {
1054         struct atmel_spi        *as;
1055         struct spi_device       *spi = msg->spi;
1056         u8                      bits;
1057         u32                     len;
1058         struct atmel_spi_device *asd;
1059         int                     timeout;
1060         int                     ret;
1061
1062         as = spi_master_get_devdata(master);
1063
1064         if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1065                 dev_dbg(&spi->dev, "missing rx or tx buf\n");
1066                 return -EINVAL;
1067         }
1068
1069         if (xfer->bits_per_word) {
1070                 asd = spi->controller_state;
1071                 bits = (asd->csr >> 4) & 0xf;
1072                 if (bits != xfer->bits_per_word - 8) {
1073                         dev_dbg(&spi->dev,
1074                         "you can't yet change bits_per_word in transfers\n");
1075                         return -ENOPROTOOPT;
1076                 }
1077         }
1078
1079         /*
1080          * DMA map early, for performance (empties dcache ASAP) and
1081          * better fault reporting.
1082          */
1083         if ((!msg->is_dma_mapped)
1084                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) {
1085                 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
1086                         return -ENOMEM;
1087         }
1088
1089         atmel_spi_set_xfer_speed(as, msg->spi, xfer);
1090
1091         as->done_status = 0;
1092         as->current_transfer = xfer;
1093         as->current_remaining_bytes = xfer->len;
1094         while (as->current_remaining_bytes) {
1095                 reinit_completion(&as->xfer_completion);
1096
1097                 if (as->use_pdc) {
1098                         atmel_spi_pdc_next_xfer(master, msg, xfer);
1099                 } else if (atmel_spi_use_dma(as, xfer)) {
1100                         len = as->current_remaining_bytes;
1101                         ret = atmel_spi_next_xfer_dma_submit(master,
1102                                                                 xfer, &len);
1103                         if (ret) {
1104                                 dev_err(&spi->dev,
1105                                         "unable to use DMA, fallback to PIO\n");
1106                                 atmel_spi_next_xfer_pio(master, xfer);
1107                         } else {
1108                                 as->current_remaining_bytes -= len;
1109                                 if (as->current_remaining_bytes < 0)
1110                                         as->current_remaining_bytes = 0;
1111                         }
1112                 } else {
1113                         atmel_spi_next_xfer_pio(master, xfer);
1114                 }
1115
1116                 /* interrupts are disabled, so free the lock for schedule */
1117                 atmel_spi_unlock(as);
1118                 ret = wait_for_completion_timeout(&as->xfer_completion,
1119                                                         SPI_DMA_TIMEOUT);
1120                 atmel_spi_lock(as);
1121                 if (WARN_ON(ret == 0)) {
1122                         dev_err(&spi->dev,
1123                                 "spi trasfer timeout, err %d\n", ret);
1124                         as->done_status = -EIO;
1125                 } else {
1126                         ret = 0;
1127                 }
1128
1129                 if (as->done_status)
1130                         break;
1131         }
1132
1133         if (as->done_status) {
1134                 if (as->use_pdc) {
1135                         dev_warn(master->dev.parent,
1136                                 "overrun (%u/%u remaining)\n",
1137                                 spi_readl(as, TCR), spi_readl(as, RCR));
1138
1139                         /*
1140                          * Clean up DMA registers and make sure the data
1141                          * registers are empty.
1142                          */
1143                         spi_writel(as, RNCR, 0);
1144                         spi_writel(as, TNCR, 0);
1145                         spi_writel(as, RCR, 0);
1146                         spi_writel(as, TCR, 0);
1147                         for (timeout = 1000; timeout; timeout--)
1148                                 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
1149                                         break;
1150                         if (!timeout)
1151                                 dev_warn(master->dev.parent,
1152                                          "timeout waiting for TXEMPTY");
1153                         while (spi_readl(as, SR) & SPI_BIT(RDRF))
1154                                 spi_readl(as, RDR);
1155
1156                         /* Clear any overrun happening while cleaning up */
1157                         spi_readl(as, SR);
1158
1159                 } else if (atmel_spi_use_dma(as, xfer)) {
1160                         atmel_spi_stop_dma(as);
1161                 }
1162
1163                 if (!msg->is_dma_mapped
1164                         && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1165                         atmel_spi_dma_unmap_xfer(master, xfer);
1166
1167                 return 0;
1168
1169         } else {
1170                 /* only update length if no error */
1171                 msg->actual_length += xfer->len;
1172         }
1173
1174         if (!msg->is_dma_mapped
1175                 && (atmel_spi_use_dma(as, xfer) || as->use_pdc))
1176                 atmel_spi_dma_unmap_xfer(master, xfer);
1177
1178         if (xfer->delay_usecs)
1179                 udelay(xfer->delay_usecs);
1180
1181         if (xfer->cs_change) {
1182                 if (list_is_last(&xfer->transfer_list,
1183                                  &msg->transfers)) {
1184                         as->keep_cs = true;
1185                 } else {
1186                         as->cs_active = !as->cs_active;
1187                         if (as->cs_active)
1188                                 cs_activate(as, msg->spi);
1189                         else
1190                                 cs_deactivate(as, msg->spi);
1191                 }
1192         }
1193
1194         return 0;
1195 }
1196
1197 static int atmel_spi_transfer_one_message(struct spi_master *master,
1198                                                 struct spi_message *msg)
1199 {
1200         struct atmel_spi *as;
1201         struct spi_transfer *xfer;
1202         struct spi_device *spi = msg->spi;
1203         int ret = 0;
1204
1205         as = spi_master_get_devdata(master);
1206
1207         dev_dbg(&spi->dev, "new message %p submitted for %s\n",
1208                                         msg, dev_name(&spi->dev));
1209
1210         atmel_spi_lock(as);
1211         cs_activate(as, spi);
1212
1213         as->cs_active = true;
1214         as->keep_cs = false;
1215
1216         msg->status = 0;
1217         msg->actual_length = 0;
1218
1219         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1220                 ret = atmel_spi_one_transfer(master, msg, xfer);
1221                 if (ret)
1222                         goto msg_done;
1223         }
1224
1225         if (as->use_pdc)
1226                 atmel_spi_disable_pdc_transfer(as);
1227
1228         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1229                 dev_dbg(&spi->dev,
1230                         "  xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1231                         xfer, xfer->len,
1232                         xfer->tx_buf, &xfer->tx_dma,
1233                         xfer->rx_buf, &xfer->rx_dma);
1234         }
1235
1236 msg_done:
1237         if (!as->keep_cs)
1238                 cs_deactivate(as, msg->spi);
1239
1240         atmel_spi_unlock(as);
1241
1242         msg->status = as->done_status;
1243         spi_finalize_current_message(spi->master);
1244
1245         return ret;
1246 }
1247
1248 static void atmel_spi_cleanup(struct spi_device *spi)
1249 {
1250         struct atmel_spi_device *asd = spi->controller_state;
1251         unsigned                gpio = (unsigned long) spi->controller_data;
1252
1253         if (!asd)
1254                 return;
1255
1256         spi->controller_state = NULL;
1257         gpio_free(gpio);
1258         kfree(asd);
1259 }
1260
1261 static inline unsigned int atmel_get_version(struct atmel_spi *as)
1262 {
1263         return spi_readl(as, VERSION) & 0x00000fff;
1264 }
1265
1266 static void atmel_get_caps(struct atmel_spi *as)
1267 {
1268         unsigned int version;
1269
1270         version = atmel_get_version(as);
1271         dev_info(&as->pdev->dev, "version: 0x%x\n", version);
1272
1273         as->caps.is_spi2 = version > 0x121;
1274         as->caps.has_wdrbt = version >= 0x210;
1275         as->caps.has_dma_support = version >= 0x212;
1276 }
1277
1278 /*-------------------------------------------------------------------------*/
1279
1280 static int atmel_spi_probe(struct platform_device *pdev)
1281 {
1282         struct resource         *regs;
1283         int                     irq;
1284         struct clk              *clk;
1285         int                     ret;
1286         struct spi_master       *master;
1287         struct atmel_spi        *as;
1288
1289         /* Select default pin state */
1290         pinctrl_pm_select_default_state(&pdev->dev);
1291
1292         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293         if (!regs)
1294                 return -ENXIO;
1295
1296         irq = platform_get_irq(pdev, 0);
1297         if (irq < 0)
1298                 return irq;
1299
1300         clk = devm_clk_get(&pdev->dev, "spi_clk");
1301         if (IS_ERR(clk))
1302                 return PTR_ERR(clk);
1303
1304         /* setup spi core then atmel-specific driver state */
1305         ret = -ENOMEM;
1306         master = spi_alloc_master(&pdev->dev, sizeof(*as));
1307         if (!master)
1308                 goto out_free;
1309
1310         /* the spi->mode bits understood by this driver: */
1311         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1312         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
1313         master->dev.of_node = pdev->dev.of_node;
1314         master->bus_num = pdev->id;
1315         master->num_chipselect = master->dev.of_node ? 0 : 4;
1316         master->setup = atmel_spi_setup;
1317         master->transfer_one_message = atmel_spi_transfer_one_message;
1318         master->cleanup = atmel_spi_cleanup;
1319         master->auto_runtime_pm = true;
1320         platform_set_drvdata(pdev, master);
1321
1322         as = spi_master_get_devdata(master);
1323
1324         /*
1325          * Scratch buffer is used for throwaway rx and tx data.
1326          * It's coherent to minimize dcache pollution.
1327          */
1328         as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
1329                                         &as->buffer_dma, GFP_KERNEL);
1330         if (!as->buffer)
1331                 goto out_free;
1332
1333         spin_lock_init(&as->lock);
1334
1335         as->pdev = pdev;
1336         as->regs = devm_ioremap_resource(&pdev->dev, regs);
1337         if (IS_ERR(as->regs)) {
1338                 ret = PTR_ERR(as->regs);
1339                 goto out_free_buffer;
1340         }
1341         as->phybase = regs->start;
1342         as->irq = irq;
1343         as->clk = clk;
1344
1345         init_completion(&as->xfer_completion);
1346
1347         atmel_get_caps(as);
1348
1349         as->use_dma = false;
1350         as->use_pdc = false;
1351         if (as->caps.has_dma_support) {
1352                 if (atmel_spi_configure_dma(as) == 0)
1353                         as->use_dma = true;
1354         } else {
1355                 as->use_pdc = true;
1356         }
1357
1358         if (as->caps.has_dma_support && !as->use_dma)
1359                 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
1360
1361         if (as->use_pdc) {
1362                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
1363                                         0, dev_name(&pdev->dev), master);
1364         } else {
1365                 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
1366                                         0, dev_name(&pdev->dev), master);
1367         }
1368         if (ret)
1369                 goto out_unmap_regs;
1370
1371         /* Initialize the hardware */
1372         ret = clk_prepare_enable(clk);
1373         if (ret)
1374                 goto out_free_irq;
1375         spi_writel(as, CR, SPI_BIT(SWRST));
1376         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1377         if (as->caps.has_wdrbt) {
1378                 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
1379                                 | SPI_BIT(MSTR));
1380         } else {
1381                 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
1382         }
1383
1384         if (as->use_pdc)
1385                 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
1386         spi_writel(as, CR, SPI_BIT(SPIEN));
1387
1388         /* go! */
1389         dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1390                         (unsigned long)regs->start, irq);
1391
1392         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1393         pm_runtime_use_autosuspend(&pdev->dev);
1394         pm_runtime_set_active(&pdev->dev);
1395         pm_runtime_enable(&pdev->dev);
1396
1397         ret = devm_spi_register_master(&pdev->dev, master);
1398         if (ret)
1399                 goto out_free_dma;
1400
1401         return 0;
1402
1403 out_free_dma:
1404         pm_runtime_disable(&pdev->dev);
1405         pm_runtime_set_suspended(&pdev->dev);
1406
1407         if (as->use_dma)
1408                 atmel_spi_release_dma(as);
1409
1410         spi_writel(as, CR, SPI_BIT(SWRST));
1411         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1412         clk_disable_unprepare(clk);
1413 out_free_irq:
1414 out_unmap_regs:
1415 out_free_buffer:
1416         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1417                         as->buffer_dma);
1418 out_free:
1419         spi_master_put(master);
1420         return ret;
1421 }
1422
1423 static int atmel_spi_remove(struct platform_device *pdev)
1424 {
1425         struct spi_master       *master = platform_get_drvdata(pdev);
1426         struct atmel_spi        *as = spi_master_get_devdata(master);
1427
1428         pm_runtime_get_sync(&pdev->dev);
1429
1430         /* reset the hardware and block queue progress */
1431         spin_lock_irq(&as->lock);
1432         if (as->use_dma) {
1433                 atmel_spi_stop_dma(as);
1434                 atmel_spi_release_dma(as);
1435         }
1436
1437         spi_writel(as, CR, SPI_BIT(SWRST));
1438         spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
1439         spi_readl(as, SR);
1440         spin_unlock_irq(&as->lock);
1441
1442         dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
1443                         as->buffer_dma);
1444
1445         clk_disable_unprepare(as->clk);
1446
1447         pm_runtime_put_noidle(&pdev->dev);
1448         pm_runtime_disable(&pdev->dev);
1449
1450         return 0;
1451 }
1452
1453 #ifdef CONFIG_PM
1454 #ifdef CONFIG_PM_SLEEP
1455 static int atmel_spi_suspend(struct device *dev)
1456 {
1457         struct spi_master       *master = dev_get_drvdata(dev);
1458         struct atmel_spi        *as = spi_master_get_devdata(master);
1459         int ret;
1460
1461         /* Stop the queue running */
1462         ret = spi_master_suspend(master);
1463         if (ret) {
1464                 dev_warn(dev, "cannot suspend master\n");
1465                 return ret;
1466         }
1467
1468         if (!pm_runtime_suspended(dev)) {
1469                 clk_disable_unprepare(as->clk);
1470                 pinctrl_pm_select_sleep_state(dev);
1471         }
1472
1473         return 0;
1474 }
1475
1476 static int atmel_spi_resume(struct device *dev)
1477 {
1478         struct spi_master       *master = dev_get_drvdata(dev);
1479         struct atmel_spi        *as = spi_master_get_devdata(master);
1480         int ret;
1481
1482         if (!pm_runtime_suspended(dev)) {
1483                 pinctrl_pm_select_default_state(dev);
1484                 ret = clk_prepare_enable(as->clk);
1485                 if (ret)
1486                         return ret;
1487         }
1488
1489         /* Start the queue running */
1490         ret = spi_master_resume(master);
1491         if (ret)
1492                 dev_err(dev, "problem starting queue (%d)\n", ret);
1493
1494         return ret;
1495 }
1496 #endif
1497
1498 #ifdef CONFIG_PM_RUNTIME
1499 static int atmel_spi_runtime_suspend(struct device *dev)
1500 {
1501         struct spi_master *master = dev_get_drvdata(dev);
1502         struct atmel_spi *as = spi_master_get_devdata(master);
1503
1504         clk_disable_unprepare(as->clk);
1505         pinctrl_pm_select_sleep_state(dev);
1506
1507         return 0;
1508 }
1509
1510 static int atmel_spi_runtime_resume(struct device *dev)
1511 {
1512         struct spi_master *master = dev_get_drvdata(dev);
1513         struct atmel_spi *as = spi_master_get_devdata(master);
1514         int ret;
1515
1516         pinctrl_pm_select_default_state(dev);
1517
1518         ret = clk_prepare_enable(as->clk);
1519         if (ret)
1520                 return ret;
1521
1522         return 0;
1523 }
1524 #endif
1525
1526 static const struct dev_pm_ops atmel_spi_pm_ops = {
1527         SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
1528         SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
1529                            atmel_spi_runtime_resume, NULL)
1530 };
1531 #define ATMEL_SPI_PM_OPS        (&atmel_spi_pm_ops)
1532 #else
1533 #define ATMEL_SPI_PM_OPS        NULL
1534 #endif
1535
1536 #if defined(CONFIG_OF)
1537 static const struct of_device_id atmel_spi_dt_ids[] = {
1538         { .compatible = "atmel,at91rm9200-spi" },
1539         { /* sentinel */ }
1540 };
1541
1542 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
1543 #endif
1544
1545 static struct platform_driver atmel_spi_driver = {
1546         .driver         = {
1547                 .name   = "atmel_spi",
1548                 .owner  = THIS_MODULE,
1549                 .pm     = ATMEL_SPI_PM_OPS,
1550                 .of_match_table = of_match_ptr(atmel_spi_dt_ids),
1551         },
1552         .probe          = atmel_spi_probe,
1553         .remove         = atmel_spi_remove,
1554 };
1555 module_platform_driver(atmel_spi_driver);
1556
1557 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1558 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1559 MODULE_LICENSE("GPL");
1560 MODULE_ALIAS("platform:atmel_spi");