drivers/spi/spi-cavium.h

   1 #ifndef __SPI_CAVIUM_H
   2 #define __SPI_CAVIUM_H
   3
   4 #include <linux/clk.h>
   5
   6 #define OCTEON_SPI_MAX_BYTES 9
   7 #define OCTEON_SPI_MAX_CLOCK_HZ 16000000
   8
   9 struct octeon_spi_regs {
  10         int config;
  11         int status;
  12         int tx;
  13         int data;
  14 };
  15
  16 struct octeon_spi {
  17         void __iomem *register_base;
  18         u64 last_cfg;
  19         u64 cs_enax;
  20         int sys_freq;
  21         struct octeon_spi_regs regs;
  22         struct clk *clk;
  23 };
  24
  25 #define OCTEON_SPI_CFG(x)       (x->regs.config)
  26 #define OCTEON_SPI_STS(x)       (x->regs.status)
  27 #define OCTEON_SPI_TX(x)        (x->regs.tx)
  28 #define OCTEON_SPI_DAT0(x)      (x->regs.data)
  29
  30 int octeon_spi_transfer_one_message(struct spi_master *master,
  31                                     struct spi_message *msg);
  32
  33 /* MPI register descriptions */
  34
  35 #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
  36 #define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
  37 #define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
  38 #define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
  39
  40 union cvmx_mpi_cfg {
  41         uint64_t u64;
  42         struct cvmx_mpi_cfg_s {
  43 #ifdef __BIG_ENDIAN_BITFIELD
  44                 uint64_t reserved_29_63:35;
  45                 uint64_t clkdiv:13;
  46                 uint64_t csena3:1;
  47                 uint64_t csena2:1;
  48                 uint64_t csena1:1;
  49                 uint64_t csena0:1;
  50                 uint64_t cslate:1;
  51                 uint64_t tritx:1;
  52                 uint64_t idleclks:2;
  53                 uint64_t cshi:1;
  54                 uint64_t csena:1;
  55                 uint64_t int_ena:1;
  56                 uint64_t lsbfirst:1;
  57                 uint64_t wireor:1;
  58                 uint64_t clk_cont:1;
  59                 uint64_t idlelo:1;
  60                 uint64_t enable:1;
  61 #else
  62                 uint64_t enable:1;
  63                 uint64_t idlelo:1;
  64                 uint64_t clk_cont:1;
  65                 uint64_t wireor:1;
  66                 uint64_t lsbfirst:1;
  67                 uint64_t int_ena:1;
  68                 uint64_t csena:1;
  69                 uint64_t cshi:1;
  70                 uint64_t idleclks:2;
  71                 uint64_t tritx:1;
  72                 uint64_t cslate:1;
  73                 uint64_t csena0:1;
  74                 uint64_t csena1:1;
  75                 uint64_t csena2:1;
  76                 uint64_t csena3:1;
  77                 uint64_t clkdiv:13;
  78                 uint64_t reserved_29_63:35;
  79 #endif
  80         } s;
  81         struct cvmx_mpi_cfg_cn30xx {
  82 #ifdef __BIG_ENDIAN_BITFIELD
  83                 uint64_t reserved_29_63:35;
  84                 uint64_t clkdiv:13;
  85                 uint64_t reserved_12_15:4;
  86                 uint64_t cslate:1;
  87                 uint64_t tritx:1;
  88                 uint64_t idleclks:2;
  89                 uint64_t cshi:1;
  90                 uint64_t csena:1;
  91                 uint64_t int_ena:1;
  92                 uint64_t lsbfirst:1;
  93                 uint64_t wireor:1;
  94                 uint64_t clk_cont:1;
  95                 uint64_t idlelo:1;
  96                 uint64_t enable:1;
  97 #else
  98                 uint64_t enable:1;
  99                 uint64_t idlelo:1;
 100                 uint64_t clk_cont:1;
 101                 uint64_t wireor:1;
 102                 uint64_t lsbfirst:1;
 103                 uint64_t int_ena:1;
 104                 uint64_t csena:1;
 105                 uint64_t cshi:1;
 106                 uint64_t idleclks:2;
 107                 uint64_t tritx:1;
 108                 uint64_t cslate:1;
 109                 uint64_t reserved_12_15:4;
 110                 uint64_t clkdiv:13;
 111                 uint64_t reserved_29_63:35;
 112 #endif
 113         } cn30xx;
 114         struct cvmx_mpi_cfg_cn31xx {
 115 #ifdef __BIG_ENDIAN_BITFIELD
 116                 uint64_t reserved_29_63:35;
 117                 uint64_t clkdiv:13;
 118                 uint64_t reserved_11_15:5;
 119                 uint64_t tritx:1;
 120                 uint64_t idleclks:2;
 121                 uint64_t cshi:1;
 122                 uint64_t csena:1;
 123                 uint64_t int_ena:1;
 124                 uint64_t lsbfirst:1;
 125                 uint64_t wireor:1;
 126                 uint64_t clk_cont:1;
 127                 uint64_t idlelo:1;
 128                 uint64_t enable:1;
 129 #else
 130                 uint64_t enable:1;
 131                 uint64_t idlelo:1;
 132                 uint64_t clk_cont:1;
 133                 uint64_t wireor:1;
 134                 uint64_t lsbfirst:1;
 135                 uint64_t int_ena:1;
 136                 uint64_t csena:1;
 137                 uint64_t cshi:1;
 138                 uint64_t idleclks:2;
 139                 uint64_t tritx:1;
 140                 uint64_t reserved_11_15:5;
 141                 uint64_t clkdiv:13;
 142                 uint64_t reserved_29_63:35;
 143 #endif
 144         } cn31xx;
 145         struct cvmx_mpi_cfg_cn30xx cn50xx;
 146         struct cvmx_mpi_cfg_cn61xx {
 147 #ifdef __BIG_ENDIAN_BITFIELD
 148                 uint64_t reserved_29_63:35;
 149                 uint64_t clkdiv:13;
 150                 uint64_t reserved_14_15:2;
 151                 uint64_t csena1:1;
 152                 uint64_t csena0:1;
 153                 uint64_t cslate:1;
 154                 uint64_t tritx:1;
 155                 uint64_t idleclks:2;
 156                 uint64_t cshi:1;
 157                 uint64_t reserved_6_6:1;
 158                 uint64_t int_ena:1;
 159                 uint64_t lsbfirst:1;
 160                 uint64_t wireor:1;
 161                 uint64_t clk_cont:1;
 162                 uint64_t idlelo:1;
 163                 uint64_t enable:1;
 164 #else
 165                 uint64_t enable:1;
 166                 uint64_t idlelo:1;
 167                 uint64_t clk_cont:1;
 168                 uint64_t wireor:1;
 169                 uint64_t lsbfirst:1;
 170                 uint64_t int_ena:1;
 171                 uint64_t reserved_6_6:1;
 172                 uint64_t cshi:1;
 173                 uint64_t idleclks:2;
 174                 uint64_t tritx:1;
 175                 uint64_t cslate:1;
 176                 uint64_t csena0:1;
 177                 uint64_t csena1:1;
 178                 uint64_t reserved_14_15:2;
 179                 uint64_t clkdiv:13;
 180                 uint64_t reserved_29_63:35;
 181 #endif
 182         } cn61xx;
 183         struct cvmx_mpi_cfg_cn66xx {
 184 #ifdef __BIG_ENDIAN_BITFIELD
 185                 uint64_t reserved_29_63:35;
 186                 uint64_t clkdiv:13;
 187                 uint64_t csena3:1;
 188                 uint64_t csena2:1;
 189                 uint64_t reserved_12_13:2;
 190                 uint64_t cslate:1;
 191                 uint64_t tritx:1;
 192                 uint64_t idleclks:2;
 193                 uint64_t cshi:1;
 194                 uint64_t reserved_6_6:1;
 195                 uint64_t int_ena:1;
 196                 uint64_t lsbfirst:1;
 197                 uint64_t wireor:1;
 198                 uint64_t clk_cont:1;
 199                 uint64_t idlelo:1;
 200                 uint64_t enable:1;
 201 #else
 202                 uint64_t enable:1;
 203                 uint64_t idlelo:1;
 204                 uint64_t clk_cont:1;
 205                 uint64_t wireor:1;
 206                 uint64_t lsbfirst:1;
 207                 uint64_t int_ena:1;
 208                 uint64_t reserved_6_6:1;
 209                 uint64_t cshi:1;
 210                 uint64_t idleclks:2;
 211                 uint64_t tritx:1;
 212                 uint64_t cslate:1;
 213                 uint64_t reserved_12_13:2;
 214                 uint64_t csena2:1;
 215                 uint64_t csena3:1;
 216                 uint64_t clkdiv:13;
 217                 uint64_t reserved_29_63:35;
 218 #endif
 219         } cn66xx;
 220         struct cvmx_mpi_cfg_cn61xx cnf71xx;
 221 };
 222
 223 union cvmx_mpi_datx {
 224         uint64_t u64;
 225         struct cvmx_mpi_datx_s {
 226 #ifdef __BIG_ENDIAN_BITFIELD
 227                 uint64_t reserved_8_63:56;
 228                 uint64_t data:8;
 229 #else
 230                 uint64_t data:8;
 231                 uint64_t reserved_8_63:56;
 232 #endif
 233         } s;
 234         struct cvmx_mpi_datx_s cn30xx;
 235         struct cvmx_mpi_datx_s cn31xx;
 236         struct cvmx_mpi_datx_s cn50xx;
 237         struct cvmx_mpi_datx_s cn61xx;
 238         struct cvmx_mpi_datx_s cn66xx;
 239         struct cvmx_mpi_datx_s cnf71xx;
 240 };
 241
 242 union cvmx_mpi_sts {
 243         uint64_t u64;
 244         struct cvmx_mpi_sts_s {
 245 #ifdef __BIG_ENDIAN_BITFIELD
 246                 uint64_t reserved_13_63:51;
 247                 uint64_t rxnum:5;
 248                 uint64_t reserved_1_7:7;
 249                 uint64_t busy:1;
 250 #else
 251                 uint64_t busy:1;
 252                 uint64_t reserved_1_7:7;
 253                 uint64_t rxnum:5;
 254                 uint64_t reserved_13_63:51;
 255 #endif
 256         } s;
 257         struct cvmx_mpi_sts_s cn30xx;
 258         struct cvmx_mpi_sts_s cn31xx;
 259         struct cvmx_mpi_sts_s cn50xx;
 260         struct cvmx_mpi_sts_s cn61xx;
 261         struct cvmx_mpi_sts_s cn66xx;
 262         struct cvmx_mpi_sts_s cnf71xx;
 263 };
 264
 265 union cvmx_mpi_tx {
 266         uint64_t u64;
 267         struct cvmx_mpi_tx_s {
 268 #ifdef __BIG_ENDIAN_BITFIELD
 269                 uint64_t reserved_22_63:42;
 270                 uint64_t csid:2;
 271                 uint64_t reserved_17_19:3;
 272                 uint64_t leavecs:1;
 273                 uint64_t reserved_13_15:3;
 274                 uint64_t txnum:5;
 275                 uint64_t reserved_5_7:3;
 276                 uint64_t totnum:5;
 277 #else
 278                 uint64_t totnum:5;
 279                 uint64_t reserved_5_7:3;
 280                 uint64_t txnum:5;
 281                 uint64_t reserved_13_15:3;
 282                 uint64_t leavecs:1;
 283                 uint64_t reserved_17_19:3;
 284                 uint64_t csid:2;
 285                 uint64_t reserved_22_63:42;
 286 #endif
 287         } s;
 288         struct cvmx_mpi_tx_cn30xx {
 289 #ifdef __BIG_ENDIAN_BITFIELD
 290                 uint64_t reserved_17_63:47;
 291                 uint64_t leavecs:1;
 292                 uint64_t reserved_13_15:3;
 293                 uint64_t txnum:5;
 294                 uint64_t reserved_5_7:3;
 295                 uint64_t totnum:5;
 296 #else
 297                 uint64_t totnum:5;
 298                 uint64_t reserved_5_7:3;
 299                 uint64_t txnum:5;
 300                 uint64_t reserved_13_15:3;
 301                 uint64_t leavecs:1;
 302                 uint64_t reserved_17_63:47;
 303 #endif
 304         } cn30xx;
 305         struct cvmx_mpi_tx_cn30xx cn31xx;
 306         struct cvmx_mpi_tx_cn30xx cn50xx;
 307         struct cvmx_mpi_tx_cn61xx {
 308 #ifdef __BIG_ENDIAN_BITFIELD
 309                 uint64_t reserved_21_63:43;
 310                 uint64_t csid:1;
 311                 uint64_t reserved_17_19:3;
 312                 uint64_t leavecs:1;
 313                 uint64_t reserved_13_15:3;
 314                 uint64_t txnum:5;
 315                 uint64_t reserved_5_7:3;
 316                 uint64_t totnum:5;
 317 #else
 318                 uint64_t totnum:5;
 319                 uint64_t reserved_5_7:3;
 320                 uint64_t txnum:5;
 321                 uint64_t reserved_13_15:3;
 322                 uint64_t leavecs:1;
 323                 uint64_t reserved_17_19:3;
 324                 uint64_t csid:1;
 325                 uint64_t reserved_21_63:43;
 326 #endif
 327         } cn61xx;
 328         struct cvmx_mpi_tx_s cn66xx;
 329         struct cvmx_mpi_tx_cn61xx cnf71xx;
 330 };
 331
 332 #endif /* __SPI_CAVIUM_H */