drivers/spi/spi-cavium.h

   1 #ifndef __SPI_CAVIUM_H
   2 #define __SPI_CAVIUM_H
   3
   4 #define OCTEON_SPI_MAX_BYTES 9
   5 #define OCTEON_SPI_MAX_CLOCK_HZ 16000000
   6
   7 struct octeon_spi_regs {
   8         int config;
   9         int status;
  10         int tx;
  11         int data;
  12 };
  13
  14 struct octeon_spi {
  15         void __iomem *register_base;
  16         u64 last_cfg;
  17         u64 cs_enax;
  18         int sys_freq;
  19         struct octeon_spi_regs regs;
  20 };
  21
  22 #define OCTEON_SPI_CFG(x)       (x->regs.config)
  23 #define OCTEON_SPI_STS(x)       (x->regs.status)
  24 #define OCTEON_SPI_TX(x)        (x->regs.tx)
  25 #define OCTEON_SPI_DAT0(x)      (x->regs.data)
  26
  27 int octeon_spi_transfer_one_message(struct spi_master *master,
  28                                     struct spi_message *msg);
  29
  30 /* MPI register descriptions */
  31
  32 #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
  33 #define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
  34 #define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
  35 #define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
  36
  37 union cvmx_mpi_cfg {
  38         uint64_t u64;
  39         struct cvmx_mpi_cfg_s {
  40 #ifdef __BIG_ENDIAN_BITFIELD
  41                 uint64_t reserved_29_63:35;
  42                 uint64_t clkdiv:13;
  43                 uint64_t csena3:1;
  44                 uint64_t csena2:1;
  45                 uint64_t csena1:1;
  46                 uint64_t csena0:1;
  47                 uint64_t cslate:1;
  48                 uint64_t tritx:1;
  49                 uint64_t idleclks:2;
  50                 uint64_t cshi:1;
  51                 uint64_t csena:1;
  52                 uint64_t int_ena:1;
  53                 uint64_t lsbfirst:1;
  54                 uint64_t wireor:1;
  55                 uint64_t clk_cont:1;
  56                 uint64_t idlelo:1;
  57                 uint64_t enable:1;
  58 #else
  59                 uint64_t enable:1;
  60                 uint64_t idlelo:1;
  61                 uint64_t clk_cont:1;
  62                 uint64_t wireor:1;
  63                 uint64_t lsbfirst:1;
  64                 uint64_t int_ena:1;
  65                 uint64_t csena:1;
  66                 uint64_t cshi:1;
  67                 uint64_t idleclks:2;
  68                 uint64_t tritx:1;
  69                 uint64_t cslate:1;
  70                 uint64_t csena0:1;
  71                 uint64_t csena1:1;
  72                 uint64_t csena2:1;
  73                 uint64_t csena3:1;
  74                 uint64_t clkdiv:13;
  75                 uint64_t reserved_29_63:35;
  76 #endif
  77         } s;
  78         struct cvmx_mpi_cfg_cn30xx {
  79 #ifdef __BIG_ENDIAN_BITFIELD
  80                 uint64_t reserved_29_63:35;
  81                 uint64_t clkdiv:13;
  82                 uint64_t reserved_12_15:4;
  83                 uint64_t cslate:1;
  84                 uint64_t tritx:1;
  85                 uint64_t idleclks:2;
  86                 uint64_t cshi:1;
  87                 uint64_t csena:1;
  88                 uint64_t int_ena:1;
  89                 uint64_t lsbfirst:1;
  90                 uint64_t wireor:1;
  91                 uint64_t clk_cont:1;
  92                 uint64_t idlelo:1;
  93                 uint64_t enable:1;
  94 #else
  95                 uint64_t enable:1;
  96                 uint64_t idlelo:1;
  97                 uint64_t clk_cont:1;
  98                 uint64_t wireor:1;
  99                 uint64_t lsbfirst:1;
 100                 uint64_t int_ena:1;
 101                 uint64_t csena:1;
 102                 uint64_t cshi:1;
 103                 uint64_t idleclks:2;
 104                 uint64_t tritx:1;
 105                 uint64_t cslate:1;
 106                 uint64_t reserved_12_15:4;
 107                 uint64_t clkdiv:13;
 108                 uint64_t reserved_29_63:35;
 109 #endif
 110         } cn30xx;
 111         struct cvmx_mpi_cfg_cn31xx {
 112 #ifdef __BIG_ENDIAN_BITFIELD
 113                 uint64_t reserved_29_63:35;
 114                 uint64_t clkdiv:13;
 115                 uint64_t reserved_11_15:5;
 116                 uint64_t tritx:1;
 117                 uint64_t idleclks:2;
 118                 uint64_t cshi:1;
 119                 uint64_t csena:1;
 120                 uint64_t int_ena:1;
 121                 uint64_t lsbfirst:1;
 122                 uint64_t wireor:1;
 123                 uint64_t clk_cont:1;
 124                 uint64_t idlelo:1;
 125                 uint64_t enable:1;
 126 #else
 127                 uint64_t enable:1;
 128                 uint64_t idlelo:1;
 129                 uint64_t clk_cont:1;
 130                 uint64_t wireor:1;
 131                 uint64_t lsbfirst:1;
 132                 uint64_t int_ena:1;
 133                 uint64_t csena:1;
 134                 uint64_t cshi:1;
 135                 uint64_t idleclks:2;
 136                 uint64_t tritx:1;
 137                 uint64_t reserved_11_15:5;
 138                 uint64_t clkdiv:13;
 139                 uint64_t reserved_29_63:35;
 140 #endif
 141         } cn31xx;
 142         struct cvmx_mpi_cfg_cn30xx cn50xx;
 143         struct cvmx_mpi_cfg_cn61xx {
 144 #ifdef __BIG_ENDIAN_BITFIELD
 145                 uint64_t reserved_29_63:35;
 146                 uint64_t clkdiv:13;
 147                 uint64_t reserved_14_15:2;
 148                 uint64_t csena1:1;
 149                 uint64_t csena0:1;
 150                 uint64_t cslate:1;
 151                 uint64_t tritx:1;
 152                 uint64_t idleclks:2;
 153                 uint64_t cshi:1;
 154                 uint64_t reserved_6_6:1;
 155                 uint64_t int_ena:1;
 156                 uint64_t lsbfirst:1;
 157                 uint64_t wireor:1;
 158                 uint64_t clk_cont:1;
 159                 uint64_t idlelo:1;
 160                 uint64_t enable:1;
 161 #else
 162                 uint64_t enable:1;
 163                 uint64_t idlelo:1;
 164                 uint64_t clk_cont:1;
 165                 uint64_t wireor:1;
 166                 uint64_t lsbfirst:1;
 167                 uint64_t int_ena:1;
 168                 uint64_t reserved_6_6:1;
 169                 uint64_t cshi:1;
 170                 uint64_t idleclks:2;
 171                 uint64_t tritx:1;
 172                 uint64_t cslate:1;
 173                 uint64_t csena0:1;
 174                 uint64_t csena1:1;
 175                 uint64_t reserved_14_15:2;
 176                 uint64_t clkdiv:13;
 177                 uint64_t reserved_29_63:35;
 178 #endif
 179         } cn61xx;
 180         struct cvmx_mpi_cfg_cn66xx {
 181 #ifdef __BIG_ENDIAN_BITFIELD
 182                 uint64_t reserved_29_63:35;
 183                 uint64_t clkdiv:13;
 184                 uint64_t csena3:1;
 185                 uint64_t csena2:1;
 186                 uint64_t reserved_12_13:2;
 187                 uint64_t cslate:1;
 188                 uint64_t tritx:1;
 189                 uint64_t idleclks:2;
 190                 uint64_t cshi:1;
 191                 uint64_t reserved_6_6:1;
 192                 uint64_t int_ena:1;
 193                 uint64_t lsbfirst:1;
 194                 uint64_t wireor:1;
 195                 uint64_t clk_cont:1;
 196                 uint64_t idlelo:1;
 197                 uint64_t enable:1;
 198 #else
 199                 uint64_t enable:1;
 200                 uint64_t idlelo:1;
 201                 uint64_t clk_cont:1;
 202                 uint64_t wireor:1;
 203                 uint64_t lsbfirst:1;
 204                 uint64_t int_ena:1;
 205                 uint64_t reserved_6_6:1;
 206                 uint64_t cshi:1;
 207                 uint64_t idleclks:2;
 208                 uint64_t tritx:1;
 209                 uint64_t cslate:1;
 210                 uint64_t reserved_12_13:2;
 211                 uint64_t csena2:1;
 212                 uint64_t csena3:1;
 213                 uint64_t clkdiv:13;
 214                 uint64_t reserved_29_63:35;
 215 #endif
 216         } cn66xx;
 217         struct cvmx_mpi_cfg_cn61xx cnf71xx;
 218 };
 219
 220 union cvmx_mpi_datx {
 221         uint64_t u64;
 222         struct cvmx_mpi_datx_s {
 223 #ifdef __BIG_ENDIAN_BITFIELD
 224                 uint64_t reserved_8_63:56;
 225                 uint64_t data:8;
 226 #else
 227                 uint64_t data:8;
 228                 uint64_t reserved_8_63:56;
 229 #endif
 230         } s;
 231         struct cvmx_mpi_datx_s cn30xx;
 232         struct cvmx_mpi_datx_s cn31xx;
 233         struct cvmx_mpi_datx_s cn50xx;
 234         struct cvmx_mpi_datx_s cn61xx;
 235         struct cvmx_mpi_datx_s cn66xx;
 236         struct cvmx_mpi_datx_s cnf71xx;
 237 };
 238
 239 union cvmx_mpi_sts {
 240         uint64_t u64;
 241         struct cvmx_mpi_sts_s {
 242 #ifdef __BIG_ENDIAN_BITFIELD
 243                 uint64_t reserved_13_63:51;
 244                 uint64_t rxnum:5;
 245                 uint64_t reserved_1_7:7;
 246                 uint64_t busy:1;
 247 #else
 248                 uint64_t busy:1;
 249                 uint64_t reserved_1_7:7;
 250                 uint64_t rxnum:5;
 251                 uint64_t reserved_13_63:51;
 252 #endif
 253         } s;
 254         struct cvmx_mpi_sts_s cn30xx;
 255         struct cvmx_mpi_sts_s cn31xx;
 256         struct cvmx_mpi_sts_s cn50xx;
 257         struct cvmx_mpi_sts_s cn61xx;
 258         struct cvmx_mpi_sts_s cn66xx;
 259         struct cvmx_mpi_sts_s cnf71xx;
 260 };
 261
 262 union cvmx_mpi_tx {
 263         uint64_t u64;
 264         struct cvmx_mpi_tx_s {
 265 #ifdef __BIG_ENDIAN_BITFIELD
 266                 uint64_t reserved_22_63:42;
 267                 uint64_t csid:2;
 268                 uint64_t reserved_17_19:3;
 269                 uint64_t leavecs:1;
 270                 uint64_t reserved_13_15:3;
 271                 uint64_t txnum:5;
 272                 uint64_t reserved_5_7:3;
 273                 uint64_t totnum:5;
 274 #else
 275                 uint64_t totnum:5;
 276                 uint64_t reserved_5_7:3;
 277                 uint64_t txnum:5;
 278                 uint64_t reserved_13_15:3;
 279                 uint64_t leavecs:1;
 280                 uint64_t reserved_17_19:3;
 281                 uint64_t csid:2;
 282                 uint64_t reserved_22_63:42;
 283 #endif
 284         } s;
 285         struct cvmx_mpi_tx_cn30xx {
 286 #ifdef __BIG_ENDIAN_BITFIELD
 287                 uint64_t reserved_17_63:47;
 288                 uint64_t leavecs:1;
 289                 uint64_t reserved_13_15:3;
 290                 uint64_t txnum:5;
 291                 uint64_t reserved_5_7:3;
 292                 uint64_t totnum:5;
 293 #else
 294                 uint64_t totnum:5;
 295                 uint64_t reserved_5_7:3;
 296                 uint64_t txnum:5;
 297                 uint64_t reserved_13_15:3;
 298                 uint64_t leavecs:1;
 299                 uint64_t reserved_17_63:47;
 300 #endif
 301         } cn30xx;
 302         struct cvmx_mpi_tx_cn30xx cn31xx;
 303         struct cvmx_mpi_tx_cn30xx cn50xx;
 304         struct cvmx_mpi_tx_cn61xx {
 305 #ifdef __BIG_ENDIAN_BITFIELD
 306                 uint64_t reserved_21_63:43;
 307                 uint64_t csid:1;
 308                 uint64_t reserved_17_19:3;
 309                 uint64_t leavecs:1;
 310                 uint64_t reserved_13_15:3;
 311                 uint64_t txnum:5;
 312                 uint64_t reserved_5_7:3;
 313                 uint64_t totnum:5;
 314 #else
 315                 uint64_t totnum:5;
 316                 uint64_t reserved_5_7:3;
 317                 uint64_t txnum:5;
 318                 uint64_t reserved_13_15:3;
 319                 uint64_t leavecs:1;
 320                 uint64_t reserved_17_19:3;
 321                 uint64_t csid:1;
 322                 uint64_t reserved_21_63:43;
 323 #endif
 324         } cn61xx;
 325         struct cvmx_mpi_tx_s cn66xx;
 326         struct cvmx_mpi_tx_cn61xx cnf71xx;
 327 };
 328
 329 #endif /* __SPI_CAVIUM_H */