drivers/spi/spi-dw.c

   1 /*
   2  * Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/dma-mapping.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/highmem.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/gpio.h>
  24
  25 #include "spi-dw.h"
  26
  27 #ifdef CONFIG_DEBUG_FS
  28 #include <linux/debugfs.h>
  29 #endif
  30
  31 #define START_STATE     ((void *)0)
  32 #define RUNNING_STATE   ((void *)1)
  33 #define DONE_STATE      ((void *)2)
  34 #define ERROR_STATE     ((void *)-1)
  35
  36 /* Slave spi_dev related */
  37 struct chip_data {
  38         u16 cr0;
  39         u8 cs;                  /* chip select pin */
  40         u8 n_bytes;             /* current is a 1/2/4 byte op */
  41         u8 tmode;               /* TR/TO/RO/EEPROM */
  42         u8 type;                /* SPI/SSP/MicroWire */
  43
  44         u8 poll_mode;           /* 1 means use poll mode */
  45
  46         u32 dma_width;
  47         u32 rx_threshold;
  48         u32 tx_threshold;
  49         u8 enable_dma;
  50         u8 bits_per_word;
  51         u16 clk_div;            /* baud rate divider */
  52         u32 speed_hz;           /* baud rate */
  53         void (*cs_control)(u32 command);
  54 };
  55
  56 #ifdef CONFIG_DEBUG_FS
  57 #define SPI_REGS_BUFSIZE        1024
  58 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
  59                 size_t count, loff_t *ppos)
  60 {
  61         struct dw_spi *dws = file->private_data;
  62         char *buf;
  63         u32 len = 0;
  64         ssize_t ret;
  65
  66         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  67         if (!buf)
  68                 return 0;
  69
  70         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  71                         "%s registers:\n", dev_name(&dws->master->dev));
  72         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  73                         "=================================\n");
  74         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  75                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
  76         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  77                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
  78         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  79                         "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
  80         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  81                         "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
  82         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  83                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
  84         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  85                         "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
  86         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  87                         "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
  88         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  89                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
  90         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  91                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
  92         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  93                         "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
  94         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  95                         "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
  96         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  97                         "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
  98         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  99                         "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
 100         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 101                         "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
 102         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 103                         "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
 104         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 105                         "=================================\n");
 106
 107         ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
 108         kfree(buf);
 109         return ret;
 110 }
 111
 112 static const struct file_operations dw_spi_regs_ops = {
 113         .owner          = THIS_MODULE,
 114         .open           = simple_open,
 115         .read           = dw_spi_show_regs,
 116         .llseek         = default_llseek,
 117 };
 118
 119 static int dw_spi_debugfs_init(struct dw_spi *dws)
 120 {
 121         dws->debugfs = debugfs_create_dir("dw_spi", NULL);
 122         if (!dws->debugfs)
 123                 return -ENOMEM;
 124
 125         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 126                 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
 127         return 0;
 128 }
 129
 130 static void dw_spi_debugfs_remove(struct dw_spi *dws)
 131 {
 132         debugfs_remove_recursive(dws->debugfs);
 133 }
 134
 135 #else
 136 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
 137 {
 138         return 0;
 139 }
 140
 141 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
 142 {
 143 }
 144 #endif /* CONFIG_DEBUG_FS */
 145
 146 /* Return the max entries we can fill into tx fifo */
 147 static inline u32 tx_max(struct dw_spi *dws)
 148 {
 149         u32 tx_left, tx_room, rxtx_gap;
 150
 151         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 152         tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
 153
 154         /*
 155          * Another concern is about the tx/rx mismatch, we
 156          * though to use (dws->fifo_len - rxflr - txflr) as
 157          * one maximum value for tx, but it doesn't cover the
 158          * data which is out of tx/rx fifo and inside the
 159          * shift registers. So a control from sw point of
 160          * view is taken.
 161          */
 162         rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 163                         / dws->n_bytes;
 164
 165         return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
 166 }
 167
 168 /* Return the max entries we should read out of rx fifo */
 169 static inline u32 rx_max(struct dw_spi *dws)
 170 {
 171         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 172
 173         return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR));
 174 }
 175
 176 static void dw_writer(struct dw_spi *dws)
 177 {
 178         u32 max = tx_max(dws);
 179         u16 txw = 0;
 180
 181         while (max--) {
 182                 /* Set the tx word if the transfer's original "tx" is not null */
 183                 if (dws->tx_end - dws->len) {
 184                         if (dws->n_bytes == 1)
 185                                 txw = *(u8 *)(dws->tx);
 186                         else
 187                                 txw = *(u16 *)(dws->tx);
 188                 }
 189                 dw_writew(dws, DW_SPI_DR, txw);
 190                 dws->tx += dws->n_bytes;
 191         }
 192 }
 193
 194 static void dw_reader(struct dw_spi *dws)
 195 {
 196         u32 max = rx_max(dws);
 197         u16 rxw;
 198
 199         while (max--) {
 200                 rxw = dw_readw(dws, DW_SPI_DR);
 201                 /* Care rx only if the transfer's original "rx" is not null */
 202                 if (dws->rx_end - dws->len) {
 203                         if (dws->n_bytes == 1)
 204                                 *(u8 *)(dws->rx) = rxw;
 205                         else
 206                                 *(u16 *)(dws->rx) = rxw;
 207                 }
 208                 dws->rx += dws->n_bytes;
 209         }
 210 }
 211
 212 static void *next_transfer(struct dw_spi *dws)
 213 {
 214         struct spi_message *msg = dws->cur_msg;
 215         struct spi_transfer *trans = dws->cur_transfer;
 216
 217         /* Move to next transfer */
 218         if (trans->transfer_list.next != &msg->transfers) {
 219                 dws->cur_transfer =
 220                         list_entry(trans->transfer_list.next,
 221                                         struct spi_transfer,
 222                                         transfer_list);
 223                 return RUNNING_STATE;
 224         }
 225
 226         return DONE_STATE;
 227 }
 228
 229 /*
 230  * Note: first step is the protocol driver prepares
 231  * a dma-capable memory, and this func just need translate
 232  * the virt addr to physical
 233  */
 234 static int map_dma_buffers(struct dw_spi *dws)
 235 {
 236         if (!dws->cur_msg->is_dma_mapped
 237                 || !dws->dma_inited
 238                 || !dws->cur_chip->enable_dma
 239                 || !dws->dma_ops)
 240                 return 0;
 241
 242         if (dws->cur_transfer->tx_dma)
 243                 dws->tx_dma = dws->cur_transfer->tx_dma;
 244
 245         if (dws->cur_transfer->rx_dma)
 246                 dws->rx_dma = dws->cur_transfer->rx_dma;
 247
 248         return 1;
 249 }
 250
 251 /* Caller already set message->status; dma and pio irqs are blocked */
 252 static void giveback(struct dw_spi *dws)
 253 {
 254         struct spi_transfer *last_transfer;
 255         struct spi_message *msg;
 256
 257         msg = dws->cur_msg;
 258         dws->cur_msg = NULL;
 259         dws->cur_transfer = NULL;
 260         dws->prev_chip = dws->cur_chip;
 261         dws->cur_chip = NULL;
 262         dws->dma_mapped = 0;
 263
 264         last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
 265                                         transfer_list);
 266
 267         if (!last_transfer->cs_change)
 268                 spi_chip_sel(dws, msg->spi, 0);
 269
 270         spi_finalize_current_message(dws->master);
 271 }
 272
 273 static void int_error_stop(struct dw_spi *dws, const char *msg)
 274 {
 275         /* Stop the hw */
 276         spi_enable_chip(dws, 0);
 277
 278         dev_err(&dws->master->dev, "%s\n", msg);
 279         dws->cur_msg->state = ERROR_STATE;
 280         tasklet_schedule(&dws->pump_transfers);
 281 }
 282
 283 void dw_spi_xfer_done(struct dw_spi *dws)
 284 {
 285         /* Update total byte transferred return count actual bytes read */
 286         dws->cur_msg->actual_length += dws->len;
 287
 288         /* Move to next transfer */
 289         dws->cur_msg->state = next_transfer(dws);
 290
 291         /* Handle end of message */
 292         if (dws->cur_msg->state == DONE_STATE) {
 293                 dws->cur_msg->status = 0;
 294                 giveback(dws);
 295         } else
 296                 tasklet_schedule(&dws->pump_transfers);
 297 }
 298 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
 299
 300 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 301 {
 302         u16 irq_status = dw_readw(dws, DW_SPI_ISR);
 303
 304         /* Error handling */
 305         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 306                 dw_readw(dws, DW_SPI_TXOICR);
 307                 dw_readw(dws, DW_SPI_RXOICR);
 308                 dw_readw(dws, DW_SPI_RXUICR);
 309                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 310                 return IRQ_HANDLED;
 311         }
 312
 313         dw_reader(dws);
 314         if (dws->rx_end == dws->rx) {
 315                 spi_mask_intr(dws, SPI_INT_TXEI);
 316                 dw_spi_xfer_done(dws);
 317                 return IRQ_HANDLED;
 318         }
 319         if (irq_status & SPI_INT_TXEI) {
 320                 spi_mask_intr(dws, SPI_INT_TXEI);
 321                 dw_writer(dws);
 322                 /* Enable TX irq always, it will be disabled when RX finished */
 323                 spi_umask_intr(dws, SPI_INT_TXEI);
 324         }
 325
 326         return IRQ_HANDLED;
 327 }
 328
 329 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 330 {
 331         struct dw_spi *dws = dev_id;
 332         u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
 333
 334         if (!irq_status)
 335                 return IRQ_NONE;
 336
 337         if (!dws->cur_msg) {
 338                 spi_mask_intr(dws, SPI_INT_TXEI);
 339                 return IRQ_HANDLED;
 340         }
 341
 342         return dws->transfer_handler(dws);
 343 }
 344
 345 /* Must be called inside pump_transfers() */
 346 static void poll_transfer(struct dw_spi *dws)
 347 {
 348         do {
 349                 dw_writer(dws);
 350                 dw_reader(dws);
 351                 cpu_relax();
 352         } while (dws->rx_end > dws->rx);
 353
 354         dw_spi_xfer_done(dws);
 355 }
 356
 357 static void pump_transfers(unsigned long data)
 358 {
 359         struct dw_spi *dws = (struct dw_spi *)data;
 360         struct spi_message *message = NULL;
 361         struct spi_transfer *transfer = NULL;
 362         struct spi_transfer *previous = NULL;
 363         struct spi_device *spi = NULL;
 364         struct chip_data *chip = NULL;
 365         u8 bits = 0;
 366         u8 imask = 0;
 367         u8 cs_change = 0;
 368         u16 txint_level = 0;
 369         u16 clk_div = 0;
 370         u32 speed = 0;
 371         u32 cr0 = 0;
 372
 373         /* Get current state information */
 374         message = dws->cur_msg;
 375         transfer = dws->cur_transfer;
 376         chip = dws->cur_chip;
 377         spi = message->spi;
 378
 379         if (unlikely(!chip->clk_div))
 380                 chip->clk_div = dws->max_freq / chip->speed_hz;
 381
 382         if (message->state == ERROR_STATE) {
 383                 message->status = -EIO;
 384                 goto early_exit;
 385         }
 386
 387         /* Handle end of message */
 388         if (message->state == DONE_STATE) {
 389                 message->status = 0;
 390                 goto early_exit;
 391         }
 392
 393         /* Delay if requested at end of transfer */
 394         if (message->state == RUNNING_STATE) {
 395                 previous = list_entry(transfer->transfer_list.prev,
 396                                         struct spi_transfer,
 397                                         transfer_list);
 398                 if (previous->delay_usecs)
 399                         udelay(previous->delay_usecs);
 400         }
 401
 402         dws->n_bytes = chip->n_bytes;
 403         dws->dma_width = chip->dma_width;
 404         dws->cs_control = chip->cs_control;
 405
 406         dws->rx_dma = transfer->rx_dma;
 407         dws->tx_dma = transfer->tx_dma;
 408         dws->tx = (void *)transfer->tx_buf;
 409         dws->tx_end = dws->tx + transfer->len;
 410         dws->rx = transfer->rx_buf;
 411         dws->rx_end = dws->rx + transfer->len;
 412         dws->len = dws->cur_transfer->len;
 413         if (chip != dws->prev_chip)
 414                 cs_change = 1;
 415
 416         cr0 = chip->cr0;
 417
 418         /* Handle per transfer options for bpw and speed */
 419         if (transfer->speed_hz) {
 420                 speed = chip->speed_hz;
 421
 422                 if (transfer->speed_hz != speed) {
 423                         speed = transfer->speed_hz;
 424
 425                         /* clk_div doesn't support odd number */
 426                         clk_div = dws->max_freq / speed;
 427                         clk_div = (clk_div + 1) & 0xfffe;
 428
 429                         chip->speed_hz = speed;
 430                         chip->clk_div = clk_div;
 431                 }
 432         }
 433         if (transfer->bits_per_word) {
 434                 bits = transfer->bits_per_word;
 435                 dws->n_bytes = dws->dma_width = bits >> 3;
 436                 cr0 = (bits - 1)
 437                         | (chip->type << SPI_FRF_OFFSET)
 438                         | (spi->mode << SPI_MODE_OFFSET)
 439                         | (chip->tmode << SPI_TMOD_OFFSET);
 440         }
 441         message->state = RUNNING_STATE;
 442
 443         /*
 444          * Adjust transfer mode if necessary. Requires platform dependent
 445          * chipselect mechanism.
 446          */
 447         if (dws->cs_control) {
 448                 if (dws->rx && dws->tx)
 449                         chip->tmode = SPI_TMOD_TR;
 450                 else if (dws->rx)
 451                         chip->tmode = SPI_TMOD_RO;
 452                 else
 453                         chip->tmode = SPI_TMOD_TO;
 454
 455                 cr0 &= ~SPI_TMOD_MASK;
 456                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 457         }
 458
 459         /* Check if current transfer is a DMA transaction */
 460         dws->dma_mapped = map_dma_buffers(dws);
 461
 462         /*
 463          * Interrupt mode
 464          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 465          */
 466         if (!dws->dma_mapped && !chip->poll_mode) {
 467                 int templen = dws->len / dws->n_bytes;
 468
 469                 txint_level = dws->fifo_len / 2;
 470                 txint_level = (templen > txint_level) ? txint_level : templen;
 471
 472                 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
 473                          SPI_INT_RXUI | SPI_INT_RXOI;
 474                 dws->transfer_handler = interrupt_transfer;
 475         }
 476
 477         /*
 478          * Reprogram registers only if
 479          *      1. chip select changes
 480          *      2. clk_div is changed
 481          *      3. control value changes
 482          */
 483         if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
 484                 spi_enable_chip(dws, 0);
 485
 486                 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
 487                         dw_writew(dws, DW_SPI_CTRL0, cr0);
 488
 489                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 490                 spi_chip_sel(dws, spi, 1);
 491
 492                 /* Set the interrupt mask, for poll mode just disable all int */
 493                 spi_mask_intr(dws, 0xff);
 494                 if (imask)
 495                         spi_umask_intr(dws, imask);
 496                 if (txint_level)
 497                         dw_writew(dws, DW_SPI_TXFLTR, txint_level);
 498
 499                 spi_enable_chip(dws, 1);
 500                 if (cs_change)
 501                         dws->prev_chip = chip;
 502         }
 503
 504         if (dws->dma_mapped)
 505                 dws->dma_ops->dma_transfer(dws, cs_change);
 506
 507         if (chip->poll_mode)
 508                 poll_transfer(dws);
 509
 510         return;
 511
 512 early_exit:
 513         giveback(dws);
 514 }
 515
 516 static int dw_spi_transfer_one_message(struct spi_master *master,
 517                 struct spi_message *msg)
 518 {
 519         struct dw_spi *dws = spi_master_get_devdata(master);
 520
 521         dws->cur_msg = msg;
 522         /* Initial message state */
 523         dws->cur_msg->state = START_STATE;
 524         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 525                                                 struct spi_transfer,
 526                                                 transfer_list);
 527         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 528
 529         /* Launch transfers */
 530         tasklet_schedule(&dws->pump_transfers);
 531
 532         return 0;
 533 }
 534
 535 /* This may be called twice for each spi dev */
 536 static int dw_spi_setup(struct spi_device *spi)
 537 {
 538         struct dw_spi_chip *chip_info = NULL;
 539         struct chip_data *chip;
 540         int ret;
 541
 542         /* Only alloc on first setup */
 543         chip = spi_get_ctldata(spi);
 544         if (!chip) {
 545                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 546                 if (!chip)
 547                         return -ENOMEM;
 548                 spi_set_ctldata(spi, chip);
 549         }
 550
 551         /*
 552          * Protocol drivers may change the chip settings, so...
 553          * if chip_info exists, use it
 554          */
 555         chip_info = spi->controller_data;
 556
 557         /* chip_info doesn't always exist */
 558         if (chip_info) {
 559                 if (chip_info->cs_control)
 560                         chip->cs_control = chip_info->cs_control;
 561
 562                 chip->poll_mode = chip_info->poll_mode;
 563                 chip->type = chip_info->type;
 564
 565                 chip->rx_threshold = 0;
 566                 chip->tx_threshold = 0;
 567
 568                 chip->enable_dma = chip_info->enable_dma;
 569         }
 570
 571         if (spi->bits_per_word == 8) {
 572                 chip->n_bytes = 1;
 573                 chip->dma_width = 1;
 574         } else if (spi->bits_per_word == 16) {
 575                 chip->n_bytes = 2;
 576                 chip->dma_width = 2;
 577         }
 578         chip->bits_per_word = spi->bits_per_word;
 579
 580         if (!spi->max_speed_hz) {
 581                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 582                 return -EINVAL;
 583         }
 584         chip->speed_hz = spi->max_speed_hz;
 585
 586         chip->tmode = 0; /* Tx & Rx */
 587         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 588         chip->cr0 = (chip->bits_per_word - 1)
 589                         | (chip->type << SPI_FRF_OFFSET)
 590                         | (spi->mode  << SPI_MODE_OFFSET)
 591                         | (chip->tmode << SPI_TMOD_OFFSET);
 592
 593         if (spi->mode & SPI_LOOP)
 594                 chip->cr0 |= 1 << SPI_SRL_OFFSET;
 595
 596         if (gpio_is_valid(spi->cs_gpio)) {
 597                 ret = gpio_direction_output(spi->cs_gpio,
 598                                 !(spi->mode & SPI_CS_HIGH));
 599                 if (ret)
 600                         return ret;
 601         }
 602
 603         return 0;
 604 }
 605
 606 static void dw_spi_cleanup(struct spi_device *spi)
 607 {
 608         struct chip_data *chip = spi_get_ctldata(spi);
 609
 610         kfree(chip);
 611         spi_set_ctldata(spi, NULL);
 612 }
 613
 614 /* Restart the controller, disable all interrupts, clean rx fifo */
 615 static void spi_hw_init(struct dw_spi *dws)
 616 {
 617         spi_enable_chip(dws, 0);
 618         spi_mask_intr(dws, 0xff);
 619         spi_enable_chip(dws, 1);
 620
 621         /*
 622          * Try to detect the FIFO depth if not set by interface driver,
 623          * the depth could be from 2 to 256 from HW spec
 624          */
 625         if (!dws->fifo_len) {
 626                 u32 fifo;
 627
 628                 for (fifo = 2; fifo <= 257; fifo++) {
 629                         dw_writew(dws, DW_SPI_TXFLTR, fifo);
 630                         if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
 631                                 break;
 632                 }
 633
 634                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 635                 dw_writew(dws, DW_SPI_TXFLTR, 0);
 636         }
 637 }
 638
 639 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
 640 {
 641         struct spi_master *master;
 642         int ret;
 643
 644         BUG_ON(dws == NULL);
 645
 646         master = spi_alloc_master(dev, 0);
 647         if (!master)
 648                 return -ENOMEM;
 649
 650         dws->master = master;
 651         dws->type = SSI_MOTO_SPI;
 652         dws->prev_chip = NULL;
 653         dws->dma_inited = 0;
 654         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 655         snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
 656
 657         ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
 658                         dws->name, dws);
 659         if (ret < 0) {
 660                 dev_err(&master->dev, "can not get IRQ\n");
 661                 goto err_free_master;
 662         }
 663
 664         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 665         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 666         master->bus_num = dws->bus_num;
 667         master->num_chipselect = dws->num_cs;
 668         master->setup = dw_spi_setup;
 669         master->cleanup = dw_spi_cleanup;
 670         master->transfer_one_message = dw_spi_transfer_one_message;
 671         master->max_speed_hz = dws->max_freq;
 672         master->dev.of_node = dev->of_node;
 673
 674         /* Basic HW init */
 675         spi_hw_init(dws);
 676
 677         if (dws->dma_ops && dws->dma_ops->dma_init) {
 678                 ret = dws->dma_ops->dma_init(dws);
 679                 if (ret) {
 680                         dev_warn(&master->dev, "DMA init failed\n");
 681                         dws->dma_inited = 0;
 682                 }
 683         }
 684
 685         tasklet_init(&dws->pump_transfers, pump_transfers, (unsigned long)dws);
 686
 687         spi_master_set_devdata(master, dws);
 688         ret = devm_spi_register_master(dev, master);
 689         if (ret) {
 690                 dev_err(&master->dev, "problem registering spi master\n");
 691                 goto err_dma_exit;
 692         }
 693
 694         dw_spi_debugfs_init(dws);
 695         return 0;
 696
 697 err_dma_exit:
 698         if (dws->dma_ops && dws->dma_ops->dma_exit)
 699                 dws->dma_ops->dma_exit(dws);
 700         spi_enable_chip(dws, 0);
 701 err_free_master:
 702         spi_master_put(master);
 703         return ret;
 704 }
 705 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 706
 707 void dw_spi_remove_host(struct dw_spi *dws)
 708 {
 709         if (!dws)
 710                 return;
 711         dw_spi_debugfs_remove(dws);
 712
 713         if (dws->dma_ops && dws->dma_ops->dma_exit)
 714                 dws->dma_ops->dma_exit(dws);
 715         spi_enable_chip(dws, 0);
 716         /* Disable clk */
 717         spi_set_clk(dws, 0);
 718 }
 719 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 720
 721 int dw_spi_suspend_host(struct dw_spi *dws)
 722 {
 723         int ret = 0;
 724
 725         ret = spi_master_suspend(dws->master);
 726         if (ret)
 727                 return ret;
 728         spi_enable_chip(dws, 0);
 729         spi_set_clk(dws, 0);
 730         return ret;
 731 }
 732 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 733
 734 int dw_spi_resume_host(struct dw_spi *dws)
 735 {
 736         int ret;
 737
 738         spi_hw_init(dws);
 739         ret = spi_master_resume(dws->master);
 740         if (ret)
 741                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 742         return ret;
 743 }
 744 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 745
 746 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 747 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 748 MODULE_LICENSE("GPL v2");