2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/bitops.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/ioport.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/slab.h>
32 #include <linux/clk.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/acpi.h>
36 #include "spi-pxa2xx.h"
38 MODULE_AUTHOR("Stephen Street");
39 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
40 MODULE_LICENSE("GPL");
41 MODULE_ALIAS("platform:pxa2xx-spi");
43 #define TIMOUT_DFLT 1000
46 * for testing SSCR1 changes that require SSP restart, basically
47 * everything except the service and interrupt enables, the pxa270 developer
48 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
49 * list, but the PXA255 dev man says all bits without really meaning the
50 * service and interrupt enables
52 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
53 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
54 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
55 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
56 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
57 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
60 | QUARK_X1000_SSCR1_EFWR \
61 | QUARK_X1000_SSCR1_RFT \
62 | QUARK_X1000_SSCR1_TFT \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
65 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
67 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
68 #define LPSS_CAPS_CS_EN_SHIFT 9
69 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
72 /* LPSS offset from drv_data->ioaddr */
74 /* Register offsets from drv_data->lpss_base or -1 */
83 /* Chip select control */
84 unsigned cs_sel_shift;
89 /* Keep these sorted with enum pxa_ssp_type */
90 static const struct lpss_config lpss_platforms[] = {
96 .reg_capabilities = -1,
98 .tx_threshold_lo = 160,
99 .tx_threshold_hi = 224,
106 .reg_capabilities = -1,
108 .tx_threshold_lo = 160,
109 .tx_threshold_hi = 224,
116 .reg_capabilities = -1,
118 .tx_threshold_lo = 160,
119 .tx_threshold_hi = 224,
121 .cs_sel_mask = 1 << 2,
129 .reg_capabilities = -1,
131 .tx_threshold_lo = 32,
132 .tx_threshold_hi = 56,
139 .reg_capabilities = 0xfc,
141 .tx_threshold_lo = 16,
142 .tx_threshold_hi = 48,
144 .cs_sel_mask = 3 << 8,
148 static inline const struct lpss_config
149 *lpss_get_config(const struct driver_data *drv_data)
151 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
154 static bool is_lpss_ssp(const struct driver_data *drv_data)
156 switch (drv_data->ssp_type) {
168 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
170 return drv_data->ssp_type == QUARK_X1000_SSP;
173 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
175 switch (drv_data->ssp_type) {
176 case QUARK_X1000_SSP:
177 return QUARK_X1000_SSCR1_CHANGE_MASK;
179 return SSCR1_CHANGE_MASK;
184 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
186 switch (drv_data->ssp_type) {
187 case QUARK_X1000_SSP:
188 return RX_THRESH_QUARK_X1000_DFLT;
190 return RX_THRESH_DFLT;
194 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
198 switch (drv_data->ssp_type) {
199 case QUARK_X1000_SSP:
200 mask = QUARK_X1000_SSSR_TFL_MASK;
203 mask = SSSR_TFL_MASK;
207 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
210 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
215 switch (drv_data->ssp_type) {
216 case QUARK_X1000_SSP:
217 mask = QUARK_X1000_SSCR1_RFT;
226 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
227 u32 *sccr1_reg, u32 threshold)
229 switch (drv_data->ssp_type) {
230 case QUARK_X1000_SSP:
231 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
234 *sccr1_reg |= SSCR1_RxTresh(threshold);
239 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
240 u32 clk_div, u8 bits)
242 switch (drv_data->ssp_type) {
243 case QUARK_X1000_SSP:
245 | QUARK_X1000_SSCR0_Motorola
246 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
251 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
253 | (bits > 16 ? SSCR0_EDSS : 0);
258 * Read and write LPSS SSP private registers. Caller must first check that
259 * is_lpss_ssp() returns true before these can be called.
261 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
263 WARN_ON(!drv_data->lpss_base);
264 return readl(drv_data->lpss_base + offset);
267 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
268 unsigned offset, u32 value)
270 WARN_ON(!drv_data->lpss_base);
271 writel(value, drv_data->lpss_base + offset);
275 * lpss_ssp_setup - perform LPSS SSP specific setup
276 * @drv_data: pointer to the driver private data
278 * Perform LPSS SSP specific setup. This function must be called first if
279 * one is going to use LPSS SSP private registers.
281 static void lpss_ssp_setup(struct driver_data *drv_data)
283 const struct lpss_config *config;
286 config = lpss_get_config(drv_data);
287 drv_data->lpss_base = drv_data->ioaddr + config->offset;
289 /* Enable software chip select control */
290 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
291 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
292 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
293 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
295 /* Enable multiblock DMA transfers */
296 if (drv_data->master_info->enable_dma) {
297 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
299 if (config->reg_general >= 0) {
300 value = __lpss_ssp_read_priv(drv_data,
301 config->reg_general);
302 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
303 __lpss_ssp_write_priv(drv_data,
304 config->reg_general, value);
309 static void lpss_ssp_select_cs(struct driver_data *drv_data,
310 const struct lpss_config *config)
314 if (!config->cs_sel_mask)
317 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
319 cs = drv_data->master->cur_msg->spi->chip_select;
320 cs <<= config->cs_sel_shift;
321 if (cs != (value & config->cs_sel_mask)) {
323 * When switching another chip select output active the
324 * output must be selected first and wait 2 ssp_clk cycles
325 * before changing state to active. Otherwise a short
326 * glitch will occur on the previous chip select since
327 * output select is latched but state control is not.
329 value &= ~config->cs_sel_mask;
331 __lpss_ssp_write_priv(drv_data,
332 config->reg_cs_ctrl, value);
334 (drv_data->master->max_speed_hz / 2));
338 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
340 const struct lpss_config *config;
343 config = lpss_get_config(drv_data);
346 lpss_ssp_select_cs(drv_data, config);
348 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
350 value &= ~LPSS_CS_CONTROL_CS_HIGH;
352 value |= LPSS_CS_CONTROL_CS_HIGH;
353 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
356 static void cs_assert(struct driver_data *drv_data)
358 struct chip_data *chip =
359 spi_get_ctldata(drv_data->master->cur_msg->spi);
361 if (drv_data->ssp_type == CE4100_SSP) {
362 pxa2xx_spi_write(drv_data, SSSR, chip->frm);
366 if (chip->cs_control) {
367 chip->cs_control(PXA2XX_CS_ASSERT);
371 if (gpio_is_valid(chip->gpio_cs)) {
372 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
376 if (is_lpss_ssp(drv_data))
377 lpss_ssp_cs_control(drv_data, true);
380 static void cs_deassert(struct driver_data *drv_data)
382 struct chip_data *chip =
383 spi_get_ctldata(drv_data->master->cur_msg->spi);
385 if (drv_data->ssp_type == CE4100_SSP)
388 if (chip->cs_control) {
389 chip->cs_control(PXA2XX_CS_DEASSERT);
393 if (gpio_is_valid(chip->gpio_cs)) {
394 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
398 if (is_lpss_ssp(drv_data))
399 lpss_ssp_cs_control(drv_data, false);
402 int pxa2xx_spi_flush(struct driver_data *drv_data)
404 unsigned long limit = loops_per_jiffy << 1;
407 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
408 pxa2xx_spi_read(drv_data, SSDR);
409 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
410 write_SSSR_CS(drv_data, SSSR_ROR);
415 static int null_writer(struct driver_data *drv_data)
417 u8 n_bytes = drv_data->n_bytes;
419 if (pxa2xx_spi_txfifo_full(drv_data)
420 || (drv_data->tx == drv_data->tx_end))
423 pxa2xx_spi_write(drv_data, SSDR, 0);
424 drv_data->tx += n_bytes;
429 static int null_reader(struct driver_data *drv_data)
431 u8 n_bytes = drv_data->n_bytes;
433 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
434 && (drv_data->rx < drv_data->rx_end)) {
435 pxa2xx_spi_read(drv_data, SSDR);
436 drv_data->rx += n_bytes;
439 return drv_data->rx == drv_data->rx_end;
442 static int u8_writer(struct driver_data *drv_data)
444 if (pxa2xx_spi_txfifo_full(drv_data)
445 || (drv_data->tx == drv_data->tx_end))
448 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
454 static int u8_reader(struct driver_data *drv_data)
456 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
457 && (drv_data->rx < drv_data->rx_end)) {
458 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
462 return drv_data->rx == drv_data->rx_end;
465 static int u16_writer(struct driver_data *drv_data)
467 if (pxa2xx_spi_txfifo_full(drv_data)
468 || (drv_data->tx == drv_data->tx_end))
471 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
477 static int u16_reader(struct driver_data *drv_data)
479 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
480 && (drv_data->rx < drv_data->rx_end)) {
481 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
485 return drv_data->rx == drv_data->rx_end;
488 static int u32_writer(struct driver_data *drv_data)
490 if (pxa2xx_spi_txfifo_full(drv_data)
491 || (drv_data->tx == drv_data->tx_end))
494 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
500 static int u32_reader(struct driver_data *drv_data)
502 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
503 && (drv_data->rx < drv_data->rx_end)) {
504 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
508 return drv_data->rx == drv_data->rx_end;
511 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
513 struct spi_message *msg = drv_data->master->cur_msg;
514 struct spi_transfer *trans = drv_data->cur_transfer;
516 /* Move to next transfer */
517 if (trans->transfer_list.next != &msg->transfers) {
518 drv_data->cur_transfer =
519 list_entry(trans->transfer_list.next,
522 return RUNNING_STATE;
527 /* caller already set message->status; dma and pio irqs are blocked */
528 static void giveback(struct driver_data *drv_data)
530 struct spi_transfer* last_transfer;
531 struct spi_message *msg;
532 unsigned long timeout;
534 msg = drv_data->master->cur_msg;
535 drv_data->cur_transfer = NULL;
537 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
540 /* Delay if requested before any change in chip select */
541 if (last_transfer->delay_usecs)
542 udelay(last_transfer->delay_usecs);
544 /* Wait until SSP becomes idle before deasserting the CS */
545 timeout = jiffies + msecs_to_jiffies(10);
546 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
547 !time_after(jiffies, timeout))
550 /* Drop chip select UNLESS cs_change is true or we are returning
551 * a message with an error, or next message is for another chip
553 if (!last_transfer->cs_change)
554 cs_deassert(drv_data);
556 struct spi_message *next_msg;
558 /* Holding of cs was hinted, but we need to make sure
559 * the next message is for the same chip. Don't waste
560 * time with the following tests unless this was hinted.
562 * We cannot postpone this until pump_messages, because
563 * after calling msg->complete (below) the driver that
564 * sent the current message could be unloaded, which
565 * could invalidate the cs_control() callback...
568 /* get a pointer to the next message, if any */
569 next_msg = spi_get_next_queued_message(drv_data->master);
571 /* see if the next and current messages point
574 if ((next_msg && next_msg->spi != msg->spi) ||
575 msg->state == ERROR_STATE)
576 cs_deassert(drv_data);
579 spi_finalize_current_message(drv_data->master);
582 static void reset_sccr1(struct driver_data *drv_data)
584 struct chip_data *chip =
585 spi_get_ctldata(drv_data->master->cur_msg->spi);
588 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
589 switch (drv_data->ssp_type) {
590 case QUARK_X1000_SSP:
591 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
594 sccr1_reg &= ~SSCR1_RFT;
597 sccr1_reg |= chip->threshold;
598 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
601 static void int_error_stop(struct driver_data *drv_data, const char* msg)
603 /* Stop and reset SSP */
604 write_SSSR_CS(drv_data, drv_data->clear_sr);
605 reset_sccr1(drv_data);
606 if (!pxa25x_ssp_comp(drv_data))
607 pxa2xx_spi_write(drv_data, SSTO, 0);
608 pxa2xx_spi_flush(drv_data);
609 pxa2xx_spi_write(drv_data, SSCR0,
610 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
612 dev_err(&drv_data->pdev->dev, "%s\n", msg);
614 drv_data->master->cur_msg->state = ERROR_STATE;
615 tasklet_schedule(&drv_data->pump_transfers);
618 static void int_transfer_complete(struct driver_data *drv_data)
620 /* Clear and disable interrupts */
621 write_SSSR_CS(drv_data, drv_data->clear_sr);
622 reset_sccr1(drv_data);
623 if (!pxa25x_ssp_comp(drv_data))
624 pxa2xx_spi_write(drv_data, SSTO, 0);
626 /* Update total byte transferred return count actual bytes read */
627 drv_data->master->cur_msg->actual_length += drv_data->len -
628 (drv_data->rx_end - drv_data->rx);
630 /* Transfer delays and chip select release are
631 * handled in pump_transfers or giveback
634 /* Move to next transfer */
635 drv_data->master->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
637 /* Schedule transfer tasklet */
638 tasklet_schedule(&drv_data->pump_transfers);
641 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
643 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
644 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
646 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
648 if (irq_status & SSSR_ROR) {
649 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
653 if (irq_status & SSSR_TINT) {
654 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
655 if (drv_data->read(drv_data)) {
656 int_transfer_complete(drv_data);
661 /* Drain rx fifo, Fill tx fifo and prevent overruns */
663 if (drv_data->read(drv_data)) {
664 int_transfer_complete(drv_data);
667 } while (drv_data->write(drv_data));
669 if (drv_data->read(drv_data)) {
670 int_transfer_complete(drv_data);
674 if (drv_data->tx == drv_data->tx_end) {
678 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
679 sccr1_reg &= ~SSCR1_TIE;
682 * PXA25x_SSP has no timeout, set up rx threshould for the
683 * remaining RX bytes.
685 if (pxa25x_ssp_comp(drv_data)) {
688 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
690 bytes_left = drv_data->rx_end - drv_data->rx;
691 switch (drv_data->n_bytes) {
698 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
699 if (rx_thre > bytes_left)
700 rx_thre = bytes_left;
702 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
704 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
707 /* We did something */
711 static irqreturn_t ssp_int(int irq, void *dev_id)
713 struct driver_data *drv_data = dev_id;
715 u32 mask = drv_data->mask_sr;
719 * The IRQ might be shared with other peripherals so we must first
720 * check that are we RPM suspended or not. If we are we assume that
721 * the IRQ was not for us (we shouldn't be RPM suspended when the
722 * interrupt is enabled).
724 if (pm_runtime_suspended(&drv_data->pdev->dev))
728 * If the device is not yet in RPM suspended state and we get an
729 * interrupt that is meant for another device, check if status bits
730 * are all set to one. That means that the device is already
733 status = pxa2xx_spi_read(drv_data, SSSR);
737 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
739 /* Ignore possible writes if we don't need to write */
740 if (!(sccr1_reg & SSCR1_TIE))
743 /* Ignore RX timeout interrupt if it is disabled */
744 if (!(sccr1_reg & SSCR1_TINTE))
747 if (!(status & mask))
750 if (!drv_data->master->cur_msg) {
752 pxa2xx_spi_write(drv_data, SSCR0,
753 pxa2xx_spi_read(drv_data, SSCR0)
755 pxa2xx_spi_write(drv_data, SSCR1,
756 pxa2xx_spi_read(drv_data, SSCR1)
757 & ~drv_data->int_cr1);
758 if (!pxa25x_ssp_comp(drv_data))
759 pxa2xx_spi_write(drv_data, SSTO, 0);
760 write_SSSR_CS(drv_data, drv_data->clear_sr);
762 dev_err(&drv_data->pdev->dev,
763 "bad message state in interrupt handler\n");
769 return drv_data->transfer_handler(drv_data);
773 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
774 * input frequency by fractions of 2^24. It also has a divider by 5.
776 * There are formulas to get baud rate value for given input frequency and
777 * divider parameters, such as DDS_CLK_RATE and SCR:
781 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
782 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
784 * DDS_CLK_RATE either 2^n or 2^n / 5.
785 * SCR is in range 0 .. 255
787 * Divisor = 5^i * 2^j * 2 * k
788 * i = [0, 1] i = 1 iff j = 0 or j > 3
789 * j = [0, 23] j = 0 iff i = 1
791 * Special case: j = 0, i = 1: Divisor = 2 / 5
793 * Accordingly to the specification the recommended values for DDS_CLK_RATE
795 * Case 1: 2^n, n = [0, 23]
796 * Case 2: 2^24 * 2 / 5 (0x666666)
797 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
799 * In all cases the lowest possible value is better.
801 * The function calculates parameters for all cases and chooses the one closest
802 * to the asked baud rate.
804 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
806 unsigned long xtal = 200000000;
807 unsigned long fref = xtal / 2; /* mandatory division by 2,
810 unsigned long fref1 = fref / 2; /* case 1 */
811 unsigned long fref2 = fref * 2 / 5; /* case 2 */
813 unsigned long q, q1, q2;
819 /* Set initial value for DDS_CLK_RATE */
820 mul = (1 << 24) >> 1;
822 /* Calculate initial quot */
823 q1 = DIV_ROUND_UP(fref1, rate);
825 /* Scale q1 if it's too big */
827 /* Scale q1 to range [1, 512] */
828 scale = fls_long(q1 - 1);
834 /* Round the result if we have a remainder */
838 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
843 /* Get the remainder */
844 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
848 q2 = DIV_ROUND_UP(fref2, rate);
849 r2 = abs(fref2 / q2 - rate);
852 * Choose the best between two: less remainder we have the better. We
853 * can't go case 2 if q2 is greater than 256 since SCR register can
854 * hold only values 0 .. 255.
856 if (r2 >= r1 || q2 > 256) {
857 /* case 1 is better */
861 /* case 2 is better */
864 mul = (1 << 24) * 2 / 5;
867 /* Check case 3 only if the divisor is big enough */
868 if (fref / rate >= 80) {
872 /* Calculate initial quot */
873 q1 = DIV_ROUND_UP(fref, rate);
876 /* Get the remainder */
877 fssp = (u64)fref * m;
878 do_div(fssp, 1 << 24);
879 r1 = abs(fssp - rate);
881 /* Choose this one if it suits better */
883 /* case 3 is better */
893 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
895 unsigned long ssp_clk = drv_data->master->max_speed_hz;
896 const struct ssp_device *ssp = drv_data->ssp;
898 rate = min_t(int, ssp_clk, rate);
900 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
901 return (ssp_clk / (2 * rate) - 1) & 0xff;
903 return (ssp_clk / rate - 1) & 0xfff;
906 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
909 struct chip_data *chip =
910 spi_get_ctldata(drv_data->master->cur_msg->spi);
911 unsigned int clk_div;
913 switch (drv_data->ssp_type) {
914 case QUARK_X1000_SSP:
915 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
918 clk_div = ssp_get_clk_div(drv_data, rate);
924 static bool pxa2xx_spi_can_dma(struct spi_master *master,
925 struct spi_device *spi,
926 struct spi_transfer *xfer)
928 struct chip_data *chip = spi_get_ctldata(spi);
930 return chip->enable_dma &&
931 xfer->len <= MAX_DMA_LEN &&
932 xfer->len >= chip->dma_burst_size;
935 static void pump_transfers(unsigned long data)
937 struct driver_data *drv_data = (struct driver_data *)data;
938 struct spi_master *master = drv_data->master;
939 struct spi_message *message = master->cur_msg;
940 struct chip_data *chip = spi_get_ctldata(message->spi);
941 u32 dma_thresh = chip->dma_threshold;
942 u32 dma_burst = chip->dma_burst_size;
943 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
944 struct spi_transfer *transfer;
945 struct spi_transfer *previous;
954 /* Get current state information */
955 transfer = drv_data->cur_transfer;
957 /* Handle for abort */
958 if (message->state == ERROR_STATE) {
959 message->status = -EIO;
964 /* Handle end of message */
965 if (message->state == DONE_STATE) {
971 /* Delay if requested at end of transfer before CS change */
972 if (message->state == RUNNING_STATE) {
973 previous = list_entry(transfer->transfer_list.prev,
976 if (previous->delay_usecs)
977 udelay(previous->delay_usecs);
979 /* Drop chip select only if cs_change is requested */
980 if (previous->cs_change)
981 cs_deassert(drv_data);
984 /* Check if we can DMA this transfer */
985 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
987 /* reject already-mapped transfers; PIO won't always work */
988 if (message->is_dma_mapped
989 || transfer->rx_dma || transfer->tx_dma) {
990 dev_err(&drv_data->pdev->dev,
991 "pump_transfers: mapped transfer length of "
992 "%u is greater than %d\n",
993 transfer->len, MAX_DMA_LEN);
994 message->status = -EINVAL;
999 /* warn ... we force this to PIO mode */
1000 dev_warn_ratelimited(&message->spi->dev,
1001 "pump_transfers: DMA disabled for transfer length %ld "
1002 "greater than %d\n",
1003 (long)drv_data->len, MAX_DMA_LEN);
1006 /* Setup the transfer state based on the type of transfer */
1007 if (pxa2xx_spi_flush(drv_data) == 0) {
1008 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
1009 message->status = -EIO;
1013 drv_data->n_bytes = chip->n_bytes;
1014 drv_data->tx = (void *)transfer->tx_buf;
1015 drv_data->tx_end = drv_data->tx + transfer->len;
1016 drv_data->rx = transfer->rx_buf;
1017 drv_data->rx_end = drv_data->rx + transfer->len;
1018 drv_data->len = transfer->len;
1019 drv_data->write = drv_data->tx ? chip->write : null_writer;
1020 drv_data->read = drv_data->rx ? chip->read : null_reader;
1022 /* Change speed and bit per word on a per transfer */
1023 bits = transfer->bits_per_word;
1024 speed = transfer->speed_hz;
1026 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1029 drv_data->n_bytes = 1;
1030 drv_data->read = drv_data->read != null_reader ?
1031 u8_reader : null_reader;
1032 drv_data->write = drv_data->write != null_writer ?
1033 u8_writer : null_writer;
1034 } else if (bits <= 16) {
1035 drv_data->n_bytes = 2;
1036 drv_data->read = drv_data->read != null_reader ?
1037 u16_reader : null_reader;
1038 drv_data->write = drv_data->write != null_writer ?
1039 u16_writer : null_writer;
1040 } else if (bits <= 32) {
1041 drv_data->n_bytes = 4;
1042 drv_data->read = drv_data->read != null_reader ?
1043 u32_reader : null_reader;
1044 drv_data->write = drv_data->write != null_writer ?
1045 u32_writer : null_writer;
1048 * if bits/word is changed in dma mode, then must check the
1049 * thresholds and burst also
1051 if (chip->enable_dma) {
1052 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1056 dev_warn_ratelimited(&message->spi->dev,
1057 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1060 message->state = RUNNING_STATE;
1062 dma_mapped = master->can_dma &&
1063 master->can_dma(master, message->spi, transfer) &&
1064 master->cur_msg_mapped;
1067 /* Ensure we have the correct interrupt handler */
1068 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1070 err = pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1072 message->status = err;
1077 /* Clear status and start DMA engine */
1078 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1079 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1081 pxa2xx_spi_dma_start(drv_data);
1083 /* Ensure we have the correct interrupt handler */
1084 drv_data->transfer_handler = interrupt_transfer;
1087 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1088 write_SSSR_CS(drv_data, drv_data->clear_sr);
1091 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1092 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1093 if (!pxa25x_ssp_comp(drv_data))
1094 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1095 master->max_speed_hz
1096 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1097 dma_mapped ? "DMA" : "PIO");
1099 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1100 master->max_speed_hz / 2
1101 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1102 dma_mapped ? "DMA" : "PIO");
1104 if (is_lpss_ssp(drv_data)) {
1105 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1106 != chip->lpss_rx_threshold)
1107 pxa2xx_spi_write(drv_data, SSIRF,
1108 chip->lpss_rx_threshold);
1109 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1110 != chip->lpss_tx_threshold)
1111 pxa2xx_spi_write(drv_data, SSITF,
1112 chip->lpss_tx_threshold);
1115 if (is_quark_x1000_ssp(drv_data) &&
1116 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1117 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1119 /* see if we need to reload the config registers */
1120 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1121 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1122 != (cr1 & change_mask)) {
1123 /* stop the SSP, and update the other bits */
1124 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1125 if (!pxa25x_ssp_comp(drv_data))
1126 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1127 /* first set CR1 without interrupt and service enables */
1128 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1129 /* restart the SSP */
1130 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1133 if (!pxa25x_ssp_comp(drv_data))
1134 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1137 cs_assert(drv_data);
1139 /* after chip select, release the data by enabling service
1140 * requests and interrupts, without changing any mode bits */
1141 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1144 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1145 struct spi_message *msg)
1147 struct driver_data *drv_data = spi_master_get_devdata(master);
1149 /* Initial message state*/
1150 msg->state = START_STATE;
1151 drv_data->cur_transfer = list_entry(msg->transfers.next,
1152 struct spi_transfer,
1155 /* Mark as busy and launch transfers */
1156 tasklet_schedule(&drv_data->pump_transfers);
1160 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1162 struct driver_data *drv_data = spi_master_get_devdata(master);
1164 /* Disable the SSP now */
1165 pxa2xx_spi_write(drv_data, SSCR0,
1166 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1171 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1172 struct pxa2xx_spi_chip *chip_info)
1176 if (chip == NULL || chip_info == NULL)
1179 /* NOTE: setup() can be called multiple times, possibly with
1180 * different chip_info, release previously requested GPIO
1182 if (gpio_is_valid(chip->gpio_cs))
1183 gpio_free(chip->gpio_cs);
1185 /* If (*cs_control) is provided, ignore GPIO chip select */
1186 if (chip_info->cs_control) {
1187 chip->cs_control = chip_info->cs_control;
1191 if (gpio_is_valid(chip_info->gpio_cs)) {
1192 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1194 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1195 chip_info->gpio_cs);
1199 chip->gpio_cs = chip_info->gpio_cs;
1200 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1202 err = gpio_direction_output(chip->gpio_cs,
1203 !chip->gpio_cs_inverted);
1209 static int setup(struct spi_device *spi)
1211 struct pxa2xx_spi_chip *chip_info;
1212 struct chip_data *chip;
1213 const struct lpss_config *config;
1214 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1215 uint tx_thres, tx_hi_thres, rx_thres;
1217 switch (drv_data->ssp_type) {
1218 case QUARK_X1000_SSP:
1219 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1221 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1228 config = lpss_get_config(drv_data);
1229 tx_thres = config->tx_threshold_lo;
1230 tx_hi_thres = config->tx_threshold_hi;
1231 rx_thres = config->rx_threshold;
1234 tx_thres = TX_THRESH_DFLT;
1236 rx_thres = RX_THRESH_DFLT;
1240 /* Only alloc on first setup */
1241 chip = spi_get_ctldata(spi);
1243 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1247 if (drv_data->ssp_type == CE4100_SSP) {
1248 if (spi->chip_select > 4) {
1250 "failed setup: cs number must not be > 4.\n");
1255 chip->frm = spi->chip_select;
1258 chip->enable_dma = drv_data->master_info->enable_dma;
1259 chip->timeout = TIMOUT_DFLT;
1262 /* protocol drivers may change the chip settings, so...
1263 * if chip_info exists, use it */
1264 chip_info = spi->controller_data;
1266 /* chip_info isn't always needed */
1269 if (chip_info->timeout)
1270 chip->timeout = chip_info->timeout;
1271 if (chip_info->tx_threshold)
1272 tx_thres = chip_info->tx_threshold;
1273 if (chip_info->tx_hi_threshold)
1274 tx_hi_thres = chip_info->tx_hi_threshold;
1275 if (chip_info->rx_threshold)
1276 rx_thres = chip_info->rx_threshold;
1277 chip->dma_threshold = 0;
1278 if (chip_info->enable_loopback)
1279 chip->cr1 = SSCR1_LBM;
1282 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1283 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1284 | SSITF_TxHiThresh(tx_hi_thres);
1286 /* set dma burst and threshold outside of chip_info path so that if
1287 * chip_info goes away after setting chip->enable_dma, the
1288 * burst and threshold can still respond to changes in bits_per_word */
1289 if (chip->enable_dma) {
1290 /* set up legal burst and threshold for dma */
1291 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1293 &chip->dma_burst_size,
1294 &chip->dma_threshold)) {
1296 "in setup: DMA burst size reduced to match bits_per_word\n");
1300 switch (drv_data->ssp_type) {
1301 case QUARK_X1000_SSP:
1302 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1303 & QUARK_X1000_SSCR1_RFT)
1304 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1305 & QUARK_X1000_SSCR1_TFT);
1308 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1309 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1313 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1314 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1315 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1317 if (spi->mode & SPI_LOOP)
1318 chip->cr1 |= SSCR1_LBM;
1320 if (spi->bits_per_word <= 8) {
1322 chip->read = u8_reader;
1323 chip->write = u8_writer;
1324 } else if (spi->bits_per_word <= 16) {
1326 chip->read = u16_reader;
1327 chip->write = u16_writer;
1328 } else if (spi->bits_per_word <= 32) {
1330 chip->read = u32_reader;
1331 chip->write = u32_writer;
1334 spi_set_ctldata(spi, chip);
1336 if (drv_data->ssp_type == CE4100_SSP)
1339 return setup_cs(spi, chip, chip_info);
1342 static void cleanup(struct spi_device *spi)
1344 struct chip_data *chip = spi_get_ctldata(spi);
1345 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1350 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1351 gpio_free(chip->gpio_cs);
1359 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1360 { "INT33C0", LPSS_LPT_SSP },
1361 { "INT33C1", LPSS_LPT_SSP },
1362 { "INT3430", LPSS_LPT_SSP },
1363 { "INT3431", LPSS_LPT_SSP },
1364 { "80860F0E", LPSS_BYT_SSP },
1365 { "8086228E", LPSS_BSW_SSP },
1368 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1370 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1375 if (adev && adev->pnp.unique_id &&
1376 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1380 #else /* !CONFIG_ACPI */
1381 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1388 * PCI IDs of compound devices that integrate both host controller and private
1389 * integrated DMA engine. Please note these are not used in module
1390 * autoloading and probing in this module but matching the LPSS SSP type.
1392 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1394 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1395 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1397 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1398 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1400 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1401 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1403 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1404 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1405 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1407 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1408 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1409 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1411 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1412 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1413 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1417 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1419 struct device *dev = param;
1421 if (dev != chan->device->dev->parent)
1427 static struct pxa2xx_spi_master *
1428 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1430 struct pxa2xx_spi_master *pdata;
1431 struct acpi_device *adev;
1432 struct ssp_device *ssp;
1433 struct resource *res;
1434 const struct acpi_device_id *adev_id = NULL;
1435 const struct pci_device_id *pcidev_id = NULL;
1438 adev = ACPI_COMPANION(&pdev->dev);
1440 if (dev_is_pci(pdev->dev.parent))
1441 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1442 to_pci_dev(pdev->dev.parent));
1444 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1450 type = (int)adev_id->driver_data;
1452 type = (int)pcidev_id->driver_data;
1456 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1460 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1466 ssp->phys_base = res->start;
1467 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1468 if (IS_ERR(ssp->mmio_base))
1472 pdata->tx_param = pdev->dev.parent;
1473 pdata->rx_param = pdev->dev.parent;
1474 pdata->dma_filter = pxa2xx_spi_idma_filter;
1477 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1478 ssp->irq = platform_get_irq(pdev, 0);
1481 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1483 pdata->num_chipselect = 1;
1484 pdata->enable_dma = true;
1489 #else /* !CONFIG_PCI */
1490 static inline struct pxa2xx_spi_master *
1491 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1497 static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs)
1499 struct driver_data *drv_data = spi_master_get_devdata(master);
1501 if (has_acpi_companion(&drv_data->pdev->dev)) {
1502 switch (drv_data->ssp_type) {
1504 * For Atoms the ACPI DeviceSelection used by the Windows
1505 * driver starts from 1 instead of 0 so translate it here
1506 * to match what Linux expects.
1520 static int pxa2xx_spi_probe(struct platform_device *pdev)
1522 struct device *dev = &pdev->dev;
1523 struct pxa2xx_spi_master *platform_info;
1524 struct spi_master *master;
1525 struct driver_data *drv_data;
1526 struct ssp_device *ssp;
1527 const struct lpss_config *config;
1531 platform_info = dev_get_platdata(dev);
1532 if (!platform_info) {
1533 platform_info = pxa2xx_spi_init_pdata(pdev);
1534 if (!platform_info) {
1535 dev_err(&pdev->dev, "missing platform data\n");
1540 ssp = pxa_ssp_request(pdev->id, pdev->name);
1542 ssp = &platform_info->ssp;
1544 if (!ssp->mmio_base) {
1545 dev_err(&pdev->dev, "failed to get ssp\n");
1549 master = spi_alloc_master(dev, sizeof(struct driver_data));
1551 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1555 drv_data = spi_master_get_devdata(master);
1556 drv_data->master = master;
1557 drv_data->master_info = platform_info;
1558 drv_data->pdev = pdev;
1559 drv_data->ssp = ssp;
1561 master->dev.of_node = pdev->dev.of_node;
1562 /* the spi->mode bits understood by this driver: */
1563 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1565 master->bus_num = ssp->port_id;
1566 master->dma_alignment = DMA_ALIGNMENT;
1567 master->cleanup = cleanup;
1568 master->setup = setup;
1569 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1570 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1571 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1572 master->auto_runtime_pm = true;
1573 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
1575 drv_data->ssp_type = ssp->type;
1577 drv_data->ioaddr = ssp->mmio_base;
1578 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1579 if (pxa25x_ssp_comp(drv_data)) {
1580 switch (drv_data->ssp_type) {
1581 case QUARK_X1000_SSP:
1582 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1585 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1589 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1590 drv_data->dma_cr1 = 0;
1591 drv_data->clear_sr = SSSR_ROR;
1592 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1594 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1595 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1596 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1597 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1598 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1601 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1604 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1605 goto out_error_master_alloc;
1608 /* Setup DMA if requested */
1609 if (platform_info->enable_dma) {
1610 status = pxa2xx_spi_dma_setup(drv_data);
1612 dev_dbg(dev, "no DMA channels available, using PIO\n");
1613 platform_info->enable_dma = false;
1615 master->can_dma = pxa2xx_spi_can_dma;
1619 /* Enable SOC clock */
1620 clk_prepare_enable(ssp->clk);
1622 master->max_speed_hz = clk_get_rate(ssp->clk);
1624 /* Load default SSP configuration */
1625 pxa2xx_spi_write(drv_data, SSCR0, 0);
1626 switch (drv_data->ssp_type) {
1627 case QUARK_X1000_SSP:
1628 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1629 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1630 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1632 /* using the Motorola SPI protocol and use 8 bit frame */
1633 pxa2xx_spi_write(drv_data, SSCR0,
1634 QUARK_X1000_SSCR0_Motorola
1635 | QUARK_X1000_SSCR0_DataSize(8));
1638 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1639 SSCR1_TxTresh(TX_THRESH_DFLT);
1640 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1641 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1642 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1646 if (!pxa25x_ssp_comp(drv_data))
1647 pxa2xx_spi_write(drv_data, SSTO, 0);
1649 if (!is_quark_x1000_ssp(drv_data))
1650 pxa2xx_spi_write(drv_data, SSPSP, 0);
1652 if (is_lpss_ssp(drv_data)) {
1653 lpss_ssp_setup(drv_data);
1654 config = lpss_get_config(drv_data);
1655 if (config->reg_capabilities >= 0) {
1656 tmp = __lpss_ssp_read_priv(drv_data,
1657 config->reg_capabilities);
1658 tmp &= LPSS_CAPS_CS_EN_MASK;
1659 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1660 platform_info->num_chipselect = ffz(tmp);
1661 } else if (config->cs_num) {
1662 platform_info->num_chipselect = config->cs_num;
1665 master->num_chipselect = platform_info->num_chipselect;
1667 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1668 (unsigned long)drv_data);
1670 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1671 pm_runtime_use_autosuspend(&pdev->dev);
1672 pm_runtime_set_active(&pdev->dev);
1673 pm_runtime_enable(&pdev->dev);
1675 /* Register with the SPI framework */
1676 platform_set_drvdata(pdev, drv_data);
1677 status = devm_spi_register_master(&pdev->dev, master);
1679 dev_err(&pdev->dev, "problem registering spi master\n");
1680 goto out_error_clock_enabled;
1685 out_error_clock_enabled:
1686 clk_disable_unprepare(ssp->clk);
1687 pxa2xx_spi_dma_release(drv_data);
1688 free_irq(ssp->irq, drv_data);
1690 out_error_master_alloc:
1691 spi_master_put(master);
1696 static int pxa2xx_spi_remove(struct platform_device *pdev)
1698 struct driver_data *drv_data = platform_get_drvdata(pdev);
1699 struct ssp_device *ssp;
1703 ssp = drv_data->ssp;
1705 pm_runtime_get_sync(&pdev->dev);
1707 /* Disable the SSP at the peripheral and SOC level */
1708 pxa2xx_spi_write(drv_data, SSCR0, 0);
1709 clk_disable_unprepare(ssp->clk);
1712 if (drv_data->master_info->enable_dma)
1713 pxa2xx_spi_dma_release(drv_data);
1715 pm_runtime_put_noidle(&pdev->dev);
1716 pm_runtime_disable(&pdev->dev);
1719 free_irq(ssp->irq, drv_data);
1727 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1731 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1732 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1735 #ifdef CONFIG_PM_SLEEP
1736 static int pxa2xx_spi_suspend(struct device *dev)
1738 struct driver_data *drv_data = dev_get_drvdata(dev);
1739 struct ssp_device *ssp = drv_data->ssp;
1742 status = spi_master_suspend(drv_data->master);
1745 pxa2xx_spi_write(drv_data, SSCR0, 0);
1747 if (!pm_runtime_suspended(dev))
1748 clk_disable_unprepare(ssp->clk);
1753 static int pxa2xx_spi_resume(struct device *dev)
1755 struct driver_data *drv_data = dev_get_drvdata(dev);
1756 struct ssp_device *ssp = drv_data->ssp;
1759 /* Enable the SSP clock */
1760 if (!pm_runtime_suspended(dev))
1761 clk_prepare_enable(ssp->clk);
1763 /* Restore LPSS private register bits */
1764 if (is_lpss_ssp(drv_data))
1765 lpss_ssp_setup(drv_data);
1767 /* Start the queue running */
1768 status = spi_master_resume(drv_data->master);
1770 dev_err(dev, "problem starting queue (%d)\n", status);
1779 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1781 struct driver_data *drv_data = dev_get_drvdata(dev);
1783 clk_disable_unprepare(drv_data->ssp->clk);
1787 static int pxa2xx_spi_runtime_resume(struct device *dev)
1789 struct driver_data *drv_data = dev_get_drvdata(dev);
1791 clk_prepare_enable(drv_data->ssp->clk);
1796 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1797 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1798 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1799 pxa2xx_spi_runtime_resume, NULL)
1802 static struct platform_driver driver = {
1804 .name = "pxa2xx-spi",
1805 .pm = &pxa2xx_spi_pm_ops,
1806 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1808 .probe = pxa2xx_spi_probe,
1809 .remove = pxa2xx_spi_remove,
1810 .shutdown = pxa2xx_spi_shutdown,
1813 static int __init pxa2xx_spi_init(void)
1815 return platform_driver_register(&driver);
1817 subsys_initcall(pxa2xx_spi_init);
1819 static void __exit pxa2xx_spi_exit(void)
1821 platform_driver_unregister(&driver);
1823 module_exit(pxa2xx_spi_exit);