drivers/spi/spi-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Addy Ke <addy.ke@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/clk.h>
  19 #include <linux/err.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/slab.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/of.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/io.h>
  29 #include <linux/dmaengine.h>
  30
  31 #define DRIVER_NAME "rockchip-spi"
  32
  33 /* SPI register offsets */
  34 #define ROCKCHIP_SPI_CTRLR0                     0x0000
  35 #define ROCKCHIP_SPI_CTRLR1                     0x0004
  36 #define ROCKCHIP_SPI_SSIENR                     0x0008
  37 #define ROCKCHIP_SPI_SER                        0x000c
  38 #define ROCKCHIP_SPI_BAUDR                      0x0010
  39 #define ROCKCHIP_SPI_TXFTLR                     0x0014
  40 #define ROCKCHIP_SPI_RXFTLR                     0x0018
  41 #define ROCKCHIP_SPI_TXFLR                      0x001c
  42 #define ROCKCHIP_SPI_RXFLR                      0x0020
  43 #define ROCKCHIP_SPI_SR                         0x0024
  44 #define ROCKCHIP_SPI_IPR                        0x0028
  45 #define ROCKCHIP_SPI_IMR                        0x002c
  46 #define ROCKCHIP_SPI_ISR                        0x0030
  47 #define ROCKCHIP_SPI_RISR                       0x0034
  48 #define ROCKCHIP_SPI_ICR                        0x0038
  49 #define ROCKCHIP_SPI_DMACR                      0x003c
  50 #define ROCKCHIP_SPI_DMATDLR            0x0040
  51 #define ROCKCHIP_SPI_DMARDLR            0x0044
  52 #define ROCKCHIP_SPI_TXDR                       0x0400
  53 #define ROCKCHIP_SPI_RXDR                       0x0800
  54
  55 /* Bit fields in CTRLR0 */
  56 #define CR0_DFS_OFFSET                          0
  57
  58 #define CR0_CFS_OFFSET                          2
  59
  60 #define CR0_SCPH_OFFSET                         6
  61
  62 #define CR0_SCPOL_OFFSET                        7
  63
  64 #define CR0_CSM_OFFSET                          8
  65 #define CR0_CSM_KEEP                            0x0
  66 /* ss_n be high for half sclk_out cycles */
  67 #define CR0_CSM_HALF                            0X1
  68 /* ss_n be high for one sclk_out cycle */
  69 #define CR0_CSM_ONE                                     0x2
  70
  71 /* ss_n to sclk_out delay */
  72 #define CR0_SSD_OFFSET                          10
  73 /*
  74  * The period between ss_n active and
  75  * sclk_out active is half sclk_out cycles
  76  */
  77 #define CR0_SSD_HALF                            0x0
  78 /*
  79  * The period between ss_n active and
  80  * sclk_out active is one sclk_out cycle
  81  */
  82 #define CR0_SSD_ONE                                     0x1
  83
  84 #define CR0_EM_OFFSET                           11
  85 #define CR0_EM_LITTLE                           0x0
  86 #define CR0_EM_BIG                                      0x1
  87
  88 #define CR0_FBM_OFFSET                          12
  89 #define CR0_FBM_MSB                                     0x0
  90 #define CR0_FBM_LSB                                     0x1
  91
  92 #define CR0_BHT_OFFSET                          13
  93 #define CR0_BHT_16BIT                           0x0
  94 #define CR0_BHT_8BIT                            0x1
  95
  96 #define CR0_RSD_OFFSET                          14
  97
  98 #define CR0_FRF_OFFSET                          16
  99 #define CR0_FRF_SPI                                     0x0
 100 #define CR0_FRF_SSP                                     0x1
 101 #define CR0_FRF_MICROWIRE                       0x2
 102
 103 #define CR0_XFM_OFFSET                          18
 104 #define CR0_XFM_MASK                            (0x03 << SPI_XFM_OFFSET)
 105 #define CR0_XFM_TR                                      0x0
 106 #define CR0_XFM_TO                                      0x1
 107 #define CR0_XFM_RO                                      0x2
 108
 109 #define CR0_OPM_OFFSET                          20
 110 #define CR0_OPM_MASTER                          0x0
 111 #define CR0_OPM_SLAVE                           0x1
 112
 113 #define CR0_MTM_OFFSET                          0x21
 114
 115 /* Bit fields in SER, 2bit */
 116 #define SER_MASK                                        0x3
 117
 118 /* Bit fields in SR, 5bit */
 119 #define SR_MASK                                         0x1f
 120 #define SR_BUSY                                         (1 << 0)
 121 #define SR_TF_FULL                                      (1 << 1)
 122 #define SR_TF_EMPTY                                     (1 << 2)
 123 #define SR_RF_EMPTY                                     (1 << 3)
 124 #define SR_RF_FULL                                      (1 << 4)
 125
 126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
 127 #define INT_MASK                                        0x1f
 128 #define INT_TF_EMPTY                            (1 << 0)
 129 #define INT_TF_OVERFLOW                         (1 << 1)
 130 #define INT_RF_UNDERFLOW                        (1 << 2)
 131 #define INT_RF_OVERFLOW                         (1 << 3)
 132 #define INT_RF_FULL                                     (1 << 4)
 133
 134 /* Bit fields in ICR, 4bit */
 135 #define ICR_MASK                                        0x0f
 136 #define ICR_ALL                                         (1 << 0)
 137 #define ICR_RF_UNDERFLOW                        (1 << 1)
 138 #define ICR_RF_OVERFLOW                         (1 << 2)
 139 #define ICR_TF_OVERFLOW                         (1 << 3)
 140
 141 /* Bit fields in DMACR */
 142 #define RF_DMA_EN                                       (1 << 0)
 143 #define TF_DMA_EN                                       (1 << 1)
 144
 145 #define RXBUSY                                          (1 << 0)
 146 #define TXBUSY                                          (1 << 1)
 147
 148 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 149 #define MAX_SCLK_OUT            50000000
 150
 151 enum rockchip_ssi_type {
 152         SSI_MOTO_SPI = 0,
 153         SSI_TI_SSP,
 154         SSI_NS_MICROWIRE,
 155 };
 156
 157 struct rockchip_spi_dma_data {
 158         struct dma_chan *ch;
 159         enum dma_transfer_direction direction;
 160         dma_addr_t addr;
 161 };
 162
 163 struct rockchip_spi {
 164         struct device *dev;
 165         struct spi_master *master;
 166
 167         struct clk *spiclk;
 168         struct clk *apb_pclk;
 169
 170         void __iomem *regs;
 171         /*depth of the FIFO buffer */
 172         u32 fifo_len;
 173         /* max bus freq supported */
 174         u32 max_freq;
 175         /* supported slave numbers */
 176         enum rockchip_ssi_type type;
 177
 178         u16 mode;
 179         u8 tmode;
 180         u8 bpw;
 181         u8 n_bytes;
 182         u8 rsd_nsecs;
 183         unsigned len;
 184         u32 speed;
 185
 186         const void *tx;
 187         const void *tx_end;
 188         void *rx;
 189         void *rx_end;
 190
 191         u32 state;
 192         /* protect state */
 193         spinlock_t lock;
 194
 195         struct completion xfer_completion;
 196
 197         u32 use_dma;
 198         struct sg_table tx_sg;
 199         struct sg_table rx_sg;
 200         struct rockchip_spi_dma_data dma_rx;
 201         struct rockchip_spi_dma_data dma_tx;
 202         struct dma_slave_caps dma_caps;
 203 };
 204
 205 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
 206 {
 207         writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
 208 }
 209
 210 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
 211 {
 212         writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
 213 }
 214
 215 static inline void flush_fifo(struct rockchip_spi *rs)
 216 {
 217         while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
 218                 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 219 }
 220
 221 static inline void wait_for_idle(struct rockchip_spi *rs)
 222 {
 223         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 224
 225         do {
 226                 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
 227                         return;
 228         } while (!time_after(jiffies, timeout));
 229
 230         dev_warn(rs->dev, "spi controller is in busy state!\n");
 231 }
 232
 233 static u32 get_fifo_len(struct rockchip_spi *rs)
 234 {
 235         u32 fifo;
 236
 237         for (fifo = 2; fifo < 32; fifo++) {
 238                 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
 239                 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
 240                         break;
 241         }
 242
 243         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
 244
 245         return (fifo == 31) ? 0 : fifo;
 246 }
 247
 248 static inline u32 tx_max(struct rockchip_spi *rs)
 249 {
 250         u32 tx_left, tx_room;
 251
 252         tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
 253         tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
 254
 255         return min(tx_left, tx_room);
 256 }
 257
 258 static inline u32 rx_max(struct rockchip_spi *rs)
 259 {
 260         u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
 261         u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
 262
 263         return min(rx_left, rx_room);
 264 }
 265
 266 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
 267 {
 268         u32 ser;
 269         struct rockchip_spi *rs = spi_master_get_devdata(spi->master);
 270
 271         ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
 272
 273         /*
 274          * drivers/spi/spi.c:
 275          * static void spi_set_cs(struct spi_device *spi, bool enable)
 276          * {
 277          *              if (spi->mode & SPI_CS_HIGH)
 278          *                      enable = !enable;
 279          *
 280          *              if (spi->cs_gpio >= 0)
 281          *                      gpio_set_value(spi->cs_gpio, !enable);
 282          *              else if (spi->master->set_cs)
 283          *              spi->master->set_cs(spi, !enable);
 284          * }
 285          *
 286          * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
 287          */
 288         if (!enable)
 289                 ser |= 1 << spi->chip_select;
 290         else
 291                 ser &= ~(1 << spi->chip_select);
 292
 293         writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
 294 }
 295
 296 static int rockchip_spi_prepare_message(struct spi_master *master,
 297                                         struct spi_message *msg)
 298 {
 299         struct rockchip_spi *rs = spi_master_get_devdata(master);
 300         struct spi_device *spi = msg->spi;
 301
 302         rs->mode = spi->mode;
 303
 304         return 0;
 305 }
 306
 307 static void rockchip_spi_handle_err(struct spi_master *master,
 308                                     struct spi_message *msg)
 309 {
 310         unsigned long flags;
 311         struct rockchip_spi *rs = spi_master_get_devdata(master);
 312
 313         spin_lock_irqsave(&rs->lock, flags);
 314
 315         /*
 316          * For DMA mode, we need terminate DMA channel and flush
 317          * fifo for the next transfer if DMA thansfer timeout.
 318          * handle_err() was called by core if transfer failed.
 319          * Maybe it is reasonable for error handling here.
 320          */
 321         if (rs->use_dma) {
 322                 if (rs->state & RXBUSY) {
 323                         dmaengine_terminate_all(rs->dma_rx.ch);
 324                         flush_fifo(rs);
 325                 }
 326
 327                 if (rs->state & TXBUSY)
 328                         dmaengine_terminate_all(rs->dma_tx.ch);
 329         }
 330
 331         spin_unlock_irqrestore(&rs->lock, flags);
 332 }
 333
 334 static int rockchip_spi_unprepare_message(struct spi_master *master,
 335                                           struct spi_message *msg)
 336 {
 337         struct rockchip_spi *rs = spi_master_get_devdata(master);
 338
 339         spi_enable_chip(rs, 0);
 340
 341         return 0;
 342 }
 343
 344 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
 345 {
 346         u32 max = tx_max(rs);
 347         u32 txw = 0;
 348
 349         while (max--) {
 350                 if (rs->n_bytes == 1)
 351                         txw = *(u8 *)(rs->tx);
 352                 else
 353                         txw = *(u16 *)(rs->tx);
 354
 355                 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
 356                 rs->tx += rs->n_bytes;
 357         }
 358 }
 359
 360 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
 361 {
 362         u32 max = rx_max(rs);
 363         u32 rxw;
 364
 365         while (max--) {
 366                 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
 367                 if (rs->n_bytes == 1)
 368                         *(u8 *)(rs->rx) = (u8)rxw;
 369                 else
 370                         *(u16 *)(rs->rx) = (u16)rxw;
 371                 rs->rx += rs->n_bytes;
 372         }
 373 }
 374
 375 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
 376 {
 377         int remain = 0;
 378
 379         do {
 380                 if (rs->tx) {
 381                         remain = rs->tx_end - rs->tx;
 382                         rockchip_spi_pio_writer(rs);
 383                 }
 384
 385                 if (rs->rx) {
 386                         remain = rs->rx_end - rs->rx;
 387                         rockchip_spi_pio_reader(rs);
 388                 }
 389
 390                 cpu_relax();
 391         } while (remain);
 392
 393         /* If tx, wait until the FIFO data completely. */
 394         if (rs->tx)
 395                 wait_for_idle(rs);
 396
 397         spi_enable_chip(rs, 0);
 398
 399         return 0;
 400 }
 401
 402 static void rockchip_spi_dma_rxcb(void *data)
 403 {
 404         unsigned long flags;
 405         struct rockchip_spi *rs = data;
 406
 407         spin_lock_irqsave(&rs->lock, flags);
 408
 409         rs->state &= ~RXBUSY;
 410         if (!(rs->state & TXBUSY)) {
 411                 spi_enable_chip(rs, 0);
 412                 spi_finalize_current_transfer(rs->master);
 413         }
 414
 415         spin_unlock_irqrestore(&rs->lock, flags);
 416 }
 417
 418 static void rockchip_spi_dma_txcb(void *data)
 419 {
 420         unsigned long flags;
 421         struct rockchip_spi *rs = data;
 422
 423         /* Wait until the FIFO data completely. */
 424         wait_for_idle(rs);
 425
 426         spin_lock_irqsave(&rs->lock, flags);
 427
 428         rs->state &= ~TXBUSY;
 429         if (!(rs->state & RXBUSY)) {
 430                 spi_enable_chip(rs, 0);
 431                 spi_finalize_current_transfer(rs->master);
 432         }
 433
 434         spin_unlock_irqrestore(&rs->lock, flags);
 435 }
 436
 437 static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
 438 {
 439         unsigned long flags;
 440         struct dma_slave_config rxconf, txconf;
 441         struct dma_async_tx_descriptor *rxdesc, *txdesc;
 442
 443         spin_lock_irqsave(&rs->lock, flags);
 444         rs->state &= ~RXBUSY;
 445         rs->state &= ~TXBUSY;
 446         spin_unlock_irqrestore(&rs->lock, flags);
 447
 448         rxdesc = NULL;
 449         if (rs->rx) {
 450                 rxconf.direction = rs->dma_rx.direction;
 451                 rxconf.src_addr = rs->dma_rx.addr;
 452                 rxconf.src_addr_width = rs->n_bytes;
 453                 if (rs->dma_caps.max_burst > 4)
 454                         rxconf.src_maxburst = 4;
 455                 else
 456                         rxconf.src_maxburst = 1;
 457                 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
 458
 459                 rxdesc = dmaengine_prep_slave_sg(
 460                                 rs->dma_rx.ch,
 461                                 rs->rx_sg.sgl, rs->rx_sg.nents,
 462                                 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
 463
 464                 rxdesc->callback = rockchip_spi_dma_rxcb;
 465                 rxdesc->callback_param = rs;
 466         }
 467
 468         txdesc = NULL;
 469         if (rs->tx) {
 470                 txconf.direction = rs->dma_tx.direction;
 471                 txconf.dst_addr = rs->dma_tx.addr;
 472                 txconf.dst_addr_width = rs->n_bytes;
 473                 if (rs->dma_caps.max_burst > 4)
 474                         txconf.dst_maxburst = 4;
 475                 else
 476                         txconf.dst_maxburst = 1;
 477                 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
 478
 479                 txdesc = dmaengine_prep_slave_sg(
 480                                 rs->dma_tx.ch,
 481                                 rs->tx_sg.sgl, rs->tx_sg.nents,
 482                                 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
 483
 484                 txdesc->callback = rockchip_spi_dma_txcb;
 485                 txdesc->callback_param = rs;
 486         }
 487
 488         /* rx must be started before tx due to spi instinct */
 489         if (rxdesc) {
 490                 spin_lock_irqsave(&rs->lock, flags);
 491                 rs->state |= RXBUSY;
 492                 spin_unlock_irqrestore(&rs->lock, flags);
 493                 dmaengine_submit(rxdesc);
 494                 dma_async_issue_pending(rs->dma_rx.ch);
 495         }
 496
 497         if (txdesc) {
 498                 spin_lock_irqsave(&rs->lock, flags);
 499                 rs->state |= TXBUSY;
 500                 spin_unlock_irqrestore(&rs->lock, flags);
 501                 dmaengine_submit(txdesc);
 502                 dma_async_issue_pending(rs->dma_tx.ch);
 503         }
 504 }
 505
 506 static void rockchip_spi_config(struct rockchip_spi *rs)
 507 {
 508         u32 div = 0;
 509         u32 dmacr = 0;
 510         int rsd = 0;
 511
 512         u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
 513                 | (CR0_SSD_ONE << CR0_SSD_OFFSET);
 514
 515         cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
 516         cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
 517         cr0 |= (rs->tmode << CR0_XFM_OFFSET);
 518         cr0 |= (rs->type << CR0_FRF_OFFSET);
 519
 520         if (rs->use_dma) {
 521                 if (rs->tx)
 522                         dmacr |= TF_DMA_EN;
 523                 if (rs->rx)
 524                         dmacr |= RF_DMA_EN;
 525         }
 526
 527         if (WARN_ON(rs->speed > MAX_SCLK_OUT))
 528                 rs->speed = MAX_SCLK_OUT;
 529
 530         /* the minimum divsor is 2 */
 531         if (rs->max_freq < 2 * rs->speed) {
 532                 clk_set_rate(rs->spiclk, 2 * rs->speed);
 533                 rs->max_freq = clk_get_rate(rs->spiclk);
 534         }
 535
 536         /* div doesn't support odd number */
 537         div = DIV_ROUND_UP(rs->max_freq, rs->speed);
 538         div = (div + 1) & 0xfffe;
 539
 540         /* Rx sample delay is expressed in parent clock cycles (max 3) */
 541         rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
 542                                 1000000000 >> 8);
 543         if (!rsd && rs->rsd_nsecs) {
 544                 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
 545                              rs->max_freq, rs->rsd_nsecs);
 546         } else if (rsd > 3) {
 547                 rsd = 3;
 548                 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
 549                              rs->max_freq, rs->rsd_nsecs,
 550                              rsd * 1000000000U / rs->max_freq);
 551         }
 552         cr0 |= rsd << CR0_RSD_OFFSET;
 553
 554         writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
 555
 556         writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
 557         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
 558         writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
 559
 560         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
 561         writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
 562         writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
 563
 564         spi_set_clk(rs, div);
 565
 566         dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
 567 }
 568
 569 static int rockchip_spi_transfer_one(
 570                 struct spi_master *master,
 571                 struct spi_device *spi,
 572                 struct spi_transfer *xfer)
 573 {
 574         int ret = 1;
 575         struct rockchip_spi *rs = spi_master_get_devdata(master);
 576
 577         WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
 578                 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
 579
 580         if (!xfer->tx_buf && !xfer->rx_buf) {
 581                 dev_err(rs->dev, "No buffer for transfer\n");
 582                 return -EINVAL;
 583         }
 584
 585         rs->speed = xfer->speed_hz;
 586         rs->bpw = xfer->bits_per_word;
 587         rs->n_bytes = rs->bpw >> 3;
 588
 589         rs->tx = xfer->tx_buf;
 590         rs->tx_end = rs->tx + xfer->len;
 591         rs->rx = xfer->rx_buf;
 592         rs->rx_end = rs->rx + xfer->len;
 593         rs->len = xfer->len;
 594
 595         rs->tx_sg = xfer->tx_sg;
 596         rs->rx_sg = xfer->rx_sg;
 597
 598         if (rs->tx && rs->rx)
 599                 rs->tmode = CR0_XFM_TR;
 600         else if (rs->tx)
 601                 rs->tmode = CR0_XFM_TO;
 602         else if (rs->rx)
 603                 rs->tmode = CR0_XFM_RO;
 604
 605         /* we need prepare dma before spi was enabled */
 606         if (master->can_dma && master->can_dma(master, spi, xfer))
 607                 rs->use_dma = 1;
 608         else
 609                 rs->use_dma = 0;
 610
 611         rockchip_spi_config(rs);
 612
 613         if (rs->use_dma) {
 614                 if (rs->tmode == CR0_XFM_RO) {
 615                         /* rx: dma must be prepared first */
 616                         rockchip_spi_prepare_dma(rs);
 617                         spi_enable_chip(rs, 1);
 618                 } else {
 619                         /* tx or tr: spi must be enabled first */
 620                         spi_enable_chip(rs, 1);
 621                         rockchip_spi_prepare_dma(rs);
 622                 }
 623         } else {
 624                 spi_enable_chip(rs, 1);
 625                 ret = rockchip_spi_pio_transfer(rs);
 626         }
 627
 628         return ret;
 629 }
 630
 631 static bool rockchip_spi_can_dma(struct spi_master *master,
 632                                  struct spi_device *spi,
 633                                  struct spi_transfer *xfer)
 634 {
 635         struct rockchip_spi *rs = spi_master_get_devdata(master);
 636
 637         return (xfer->len > rs->fifo_len);
 638 }
 639
 640 static int rockchip_spi_probe(struct platform_device *pdev)
 641 {
 642         int ret = 0;
 643         struct rockchip_spi *rs;
 644         struct spi_master *master;
 645         struct resource *mem;
 646         u32 rsd_nsecs;
 647
 648         master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
 649         if (!master)
 650                 return -ENOMEM;
 651
 652         platform_set_drvdata(pdev, master);
 653
 654         rs = spi_master_get_devdata(master);
 655
 656         /* Get basic io resource and map it */
 657         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 658         rs->regs = devm_ioremap_resource(&pdev->dev, mem);
 659         if (IS_ERR(rs->regs)) {
 660                 ret =  PTR_ERR(rs->regs);
 661                 goto err_ioremap_resource;
 662         }
 663
 664         rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 665         if (IS_ERR(rs->apb_pclk)) {
 666                 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
 667                 ret = PTR_ERR(rs->apb_pclk);
 668                 goto err_ioremap_resource;
 669         }
 670
 671         rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
 672         if (IS_ERR(rs->spiclk)) {
 673                 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
 674                 ret = PTR_ERR(rs->spiclk);
 675                 goto err_ioremap_resource;
 676         }
 677
 678         ret = clk_prepare_enable(rs->apb_pclk);
 679         if (ret) {
 680                 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
 681                 goto err_ioremap_resource;
 682         }
 683
 684         ret = clk_prepare_enable(rs->spiclk);
 685         if (ret) {
 686                 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
 687                 goto err_spiclk_enable;
 688         }
 689
 690         spi_enable_chip(rs, 0);
 691
 692         rs->type = SSI_MOTO_SPI;
 693         rs->master = master;
 694         rs->dev = &pdev->dev;
 695         rs->max_freq = clk_get_rate(rs->spiclk);
 696
 697         if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
 698                                   &rsd_nsecs))
 699                 rs->rsd_nsecs = rsd_nsecs;
 700
 701         rs->fifo_len = get_fifo_len(rs);
 702         if (!rs->fifo_len) {
 703                 dev_err(&pdev->dev, "Failed to get fifo length\n");
 704                 ret = -EINVAL;
 705                 goto err_get_fifo_len;
 706         }
 707
 708         spin_lock_init(&rs->lock);
 709
 710         pm_runtime_set_active(&pdev->dev);
 711         pm_runtime_enable(&pdev->dev);
 712
 713         master->auto_runtime_pm = true;
 714         master->bus_num = pdev->id;
 715         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
 716         master->num_chipselect = 2;
 717         master->dev.of_node = pdev->dev.of_node;
 718         master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
 719
 720         master->set_cs = rockchip_spi_set_cs;
 721         master->prepare_message = rockchip_spi_prepare_message;
 722         master->unprepare_message = rockchip_spi_unprepare_message;
 723         master->transfer_one = rockchip_spi_transfer_one;
 724         master->handle_err = rockchip_spi_handle_err;
 725
 726         rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
 727         if (!rs->dma_tx.ch)
 728                 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
 729
 730         rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
 731         if (!rs->dma_rx.ch) {
 732                 if (rs->dma_tx.ch) {
 733                         dma_release_channel(rs->dma_tx.ch);
 734                         rs->dma_tx.ch = NULL;
 735                 }
 736                 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
 737         }
 738
 739         if (rs->dma_tx.ch && rs->dma_rx.ch) {
 740                 dma_get_slave_caps(rs->dma_rx.ch, &(rs->dma_caps));
 741                 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
 742                 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
 743                 rs->dma_tx.direction = DMA_MEM_TO_DEV;
 744                 rs->dma_rx.direction = DMA_DEV_TO_MEM;
 745
 746                 master->can_dma = rockchip_spi_can_dma;
 747                 master->dma_tx = rs->dma_tx.ch;
 748                 master->dma_rx = rs->dma_rx.ch;
 749         }
 750
 751         ret = devm_spi_register_master(&pdev->dev, master);
 752         if (ret) {
 753                 dev_err(&pdev->dev, "Failed to register master\n");
 754                 goto err_register_master;
 755         }
 756
 757         return 0;
 758
 759 err_register_master:
 760         if (rs->dma_tx.ch)
 761                 dma_release_channel(rs->dma_tx.ch);
 762         if (rs->dma_rx.ch)
 763                 dma_release_channel(rs->dma_rx.ch);
 764 err_get_fifo_len:
 765         clk_disable_unprepare(rs->spiclk);
 766 err_spiclk_enable:
 767         clk_disable_unprepare(rs->apb_pclk);
 768 err_ioremap_resource:
 769         spi_master_put(master);
 770
 771         return ret;
 772 }
 773
 774 static int rockchip_spi_remove(struct platform_device *pdev)
 775 {
 776         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 777         struct rockchip_spi *rs = spi_master_get_devdata(master);
 778
 779         pm_runtime_disable(&pdev->dev);
 780
 781         clk_disable_unprepare(rs->spiclk);
 782         clk_disable_unprepare(rs->apb_pclk);
 783
 784         if (rs->dma_tx.ch)
 785                 dma_release_channel(rs->dma_tx.ch);
 786         if (rs->dma_rx.ch)
 787                 dma_release_channel(rs->dma_rx.ch);
 788
 789         return 0;
 790 }
 791
 792 #ifdef CONFIG_PM_SLEEP
 793 static int rockchip_spi_suspend(struct device *dev)
 794 {
 795         int ret = 0;
 796         struct spi_master *master = dev_get_drvdata(dev);
 797         struct rockchip_spi *rs = spi_master_get_devdata(master);
 798
 799         ret = spi_master_suspend(rs->master);
 800         if (ret)
 801                 return ret;
 802
 803         if (!pm_runtime_suspended(dev)) {
 804                 clk_disable_unprepare(rs->spiclk);
 805                 clk_disable_unprepare(rs->apb_pclk);
 806         }
 807
 808         return ret;
 809 }
 810
 811 static int rockchip_spi_resume(struct device *dev)
 812 {
 813         int ret = 0;
 814         struct spi_master *master = dev_get_drvdata(dev);
 815         struct rockchip_spi *rs = spi_master_get_devdata(master);
 816
 817         if (!pm_runtime_suspended(dev)) {
 818                 ret = clk_prepare_enable(rs->apb_pclk);
 819                 if (ret < 0)
 820                         return ret;
 821
 822                 ret = clk_prepare_enable(rs->spiclk);
 823                 if (ret < 0) {
 824                         clk_disable_unprepare(rs->apb_pclk);
 825                         return ret;
 826                 }
 827         }
 828
 829         ret = spi_master_resume(rs->master);
 830         if (ret < 0) {
 831                 clk_disable_unprepare(rs->spiclk);
 832                 clk_disable_unprepare(rs->apb_pclk);
 833         }
 834
 835         return ret;
 836 }
 837 #endif /* CONFIG_PM_SLEEP */
 838
 839 #ifdef CONFIG_PM
 840 static int rockchip_spi_runtime_suspend(struct device *dev)
 841 {
 842         struct spi_master *master = dev_get_drvdata(dev);
 843         struct rockchip_spi *rs = spi_master_get_devdata(master);
 844
 845         clk_disable_unprepare(rs->spiclk);
 846         clk_disable_unprepare(rs->apb_pclk);
 847
 848         return 0;
 849 }
 850
 851 static int rockchip_spi_runtime_resume(struct device *dev)
 852 {
 853         int ret;
 854         struct spi_master *master = dev_get_drvdata(dev);
 855         struct rockchip_spi *rs = spi_master_get_devdata(master);
 856
 857         ret = clk_prepare_enable(rs->apb_pclk);
 858         if (ret)
 859                 return ret;
 860
 861         ret = clk_prepare_enable(rs->spiclk);
 862         if (ret)
 863                 clk_disable_unprepare(rs->apb_pclk);
 864
 865         return ret;
 866 }
 867 #endif /* CONFIG_PM */
 868
 869 static const struct dev_pm_ops rockchip_spi_pm = {
 870         SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
 871         SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
 872                            rockchip_spi_runtime_resume, NULL)
 873 };
 874
 875 static const struct of_device_id rockchip_spi_dt_match[] = {
 876         { .compatible = "rockchip,rk3066-spi", },
 877         { .compatible = "rockchip,rk3188-spi", },
 878         { .compatible = "rockchip,rk3288-spi", },
 879         { },
 880 };
 881 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
 882
 883 static struct platform_driver rockchip_spi_driver = {
 884         .driver = {
 885                 .name   = DRIVER_NAME,
 886                 .pm = &rockchip_spi_pm,
 887                 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
 888         },
 889         .probe = rockchip_spi_probe,
 890         .remove = rockchip_spi_remove,
 891 };
 892
 893 module_platform_driver(rockchip_spi_driver);
 894
 895 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 896 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
 897 MODULE_LICENSE("GPL v2");