drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/delay.h>
  20 #include <linux/clk.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/gpio.h>
  27 #include <linux/of.h>
  28 #include <linux/of_gpio.h>
  29
  30 #include <linux/platform_data/spi-s3c64xx.h>
  31
  32 #define MAX_SPI_PORTS           6
  33 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  34 #define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
  35 #define AUTOSUSPEND_TIMEOUT     2000
  36
  37 /* Registers and bit-fields */
  38
  39 #define S3C64XX_SPI_CH_CFG              0x00
  40 #define S3C64XX_SPI_CLK_CFG             0x04
  41 #define S3C64XX_SPI_MODE_CFG    0x08
  42 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  43 #define S3C64XX_SPI_INT_EN              0x10
  44 #define S3C64XX_SPI_STATUS              0x14
  45 #define S3C64XX_SPI_TX_DATA             0x18
  46 #define S3C64XX_SPI_RX_DATA             0x1C
  47 #define S3C64XX_SPI_PACKET_CNT  0x20
  48 #define S3C64XX_SPI_PENDING_CLR 0x24
  49 #define S3C64XX_SPI_SWAP_CFG    0x28
  50 #define S3C64XX_SPI_FB_CLK              0x2C
  51
  52 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  53 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  54 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  55 #define S3C64XX_SPI_CPOL_L              (1<<3)
  56 #define S3C64XX_SPI_CPHA_B              (1<<2)
  57 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  58 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  59
  60 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  61 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  62 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  63 #define S3C64XX_SPI_PSR_MASK            0xff
  64
  65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  73 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  74 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  75 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  76
  77 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  78 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2             (2<<4)
  80
  81 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  88
  89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  93 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  94 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  95
  96 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  97
  98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
  99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 102 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 103
 104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 105 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 106 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 107 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 109 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 110 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 111 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 112
 113 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 114
 115 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 116 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 117                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 118 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 119 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 120                                         FIFO_LVL_MASK(i))
 121
 122 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 123 #define S3C64XX_SPI_TRAILCNT_OFF        19
 124
 125 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 126
 127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 128 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 129
 130 #define RXBUSY    (1<<2)
 131 #define TXBUSY    (1<<3)
 132
 133 struct s3c64xx_spi_dma_data {
 134         struct dma_chan *ch;
 135         enum dma_transfer_direction direction;
 136 };
 137
 138 /**
 139  * struct s3c64xx_spi_info - SPI Controller hardware info
 140  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 141  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 142  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 143  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 144  * @clk_from_cmu: True, if the controller does not include a clock mux and
 145  *      prescaler unit.
 146  *
 147  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 148  * differ in some aspects such as the size of the fifo and spi bus clock
 149  * setup. Such differences are specified to the driver using this structure
 150  * which is provided as driver data to the driver.
 151  */
 152 struct s3c64xx_spi_port_config {
 153         int     fifo_lvl_mask[MAX_SPI_PORTS];
 154         int     rx_lvl_offset;
 155         int     tx_st_done;
 156         int     quirks;
 157         bool    high_speed;
 158         bool    clk_from_cmu;
 159 };
 160
 161 /**
 162  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 163  * @clk: Pointer to the spi clock.
 164  * @src_clk: Pointer to the clock used to generate SPI signals.
 165  * @master: Pointer to the SPI Protocol master.
 166  * @cntrlr_info: Platform specific data for the controller this driver manages.
 167  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 168  * @lock: Controller specific lock.
 169  * @state: Set of FLAGS to indicate status.
 170  * @rx_dmach: Controller's DMA channel for Rx.
 171  * @tx_dmach: Controller's DMA channel for Tx.
 172  * @sfr_start: BUS address of SPI controller regs.
 173  * @regs: Pointer to ioremap'ed controller registers.
 174  * @irq: interrupt
 175  * @xfer_completion: To indicate completion of xfer task.
 176  * @cur_mode: Stores the active configuration of the controller.
 177  * @cur_bpw: Stores the active bits per word settings.
 178  * @cur_speed: Stores the active xfer clock speed.
 179  */
 180 struct s3c64xx_spi_driver_data {
 181         void __iomem                    *regs;
 182         struct clk                      *clk;
 183         struct clk                      *src_clk;
 184         struct platform_device          *pdev;
 185         struct spi_master               *master;
 186         struct s3c64xx_spi_info  *cntrlr_info;
 187         struct spi_device               *tgl_spi;
 188         spinlock_t                      lock;
 189         unsigned long                   sfr_start;
 190         struct completion               xfer_completion;
 191         unsigned                        state;
 192         unsigned                        cur_mode, cur_bpw;
 193         unsigned                        cur_speed;
 194         struct s3c64xx_spi_dma_data     rx_dma;
 195         struct s3c64xx_spi_dma_data     tx_dma;
 196         struct s3c64xx_spi_port_config  *port_conf;
 197         unsigned int                    port_id;
 198 };
 199
 200 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 201 {
 202         void __iomem *regs = sdd->regs;
 203         unsigned long loops;
 204         u32 val;
 205
 206         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 207
 208         val = readl(regs + S3C64XX_SPI_CH_CFG);
 209         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 210         writel(val, regs + S3C64XX_SPI_CH_CFG);
 211
 212         val = readl(regs + S3C64XX_SPI_CH_CFG);
 213         val |= S3C64XX_SPI_CH_SW_RST;
 214         val &= ~S3C64XX_SPI_CH_HS_EN;
 215         writel(val, regs + S3C64XX_SPI_CH_CFG);
 216
 217         /* Flush TxFIFO*/
 218         loops = msecs_to_loops(1);
 219         do {
 220                 val = readl(regs + S3C64XX_SPI_STATUS);
 221         } while (TX_FIFO_LVL(val, sdd) && loops--);
 222
 223         if (loops == 0)
 224                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 225
 226         /* Flush RxFIFO*/
 227         loops = msecs_to_loops(1);
 228         do {
 229                 val = readl(regs + S3C64XX_SPI_STATUS);
 230                 if (RX_FIFO_LVL(val, sdd))
 231                         readl(regs + S3C64XX_SPI_RX_DATA);
 232                 else
 233                         break;
 234         } while (loops--);
 235
 236         if (loops == 0)
 237                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 238
 239         val = readl(regs + S3C64XX_SPI_CH_CFG);
 240         val &= ~S3C64XX_SPI_CH_SW_RST;
 241         writel(val, regs + S3C64XX_SPI_CH_CFG);
 242
 243         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 244         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 245         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 246 }
 247
 248 static void s3c64xx_spi_dmacb(void *data)
 249 {
 250         struct s3c64xx_spi_driver_data *sdd;
 251         struct s3c64xx_spi_dma_data *dma = data;
 252         unsigned long flags;
 253
 254         if (dma->direction == DMA_DEV_TO_MEM)
 255                 sdd = container_of(data,
 256                         struct s3c64xx_spi_driver_data, rx_dma);
 257         else
 258                 sdd = container_of(data,
 259                         struct s3c64xx_spi_driver_data, tx_dma);
 260
 261         spin_lock_irqsave(&sdd->lock, flags);
 262
 263         if (dma->direction == DMA_DEV_TO_MEM) {
 264                 sdd->state &= ~RXBUSY;
 265                 if (!(sdd->state & TXBUSY))
 266                         complete(&sdd->xfer_completion);
 267         } else {
 268                 sdd->state &= ~TXBUSY;
 269                 if (!(sdd->state & RXBUSY))
 270                         complete(&sdd->xfer_completion);
 271         }
 272
 273         spin_unlock_irqrestore(&sdd->lock, flags);
 274 }
 275
 276 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 277                         struct sg_table *sgt)
 278 {
 279         struct s3c64xx_spi_driver_data *sdd;
 280         struct dma_slave_config config;
 281         struct dma_async_tx_descriptor *desc;
 282
 283         memset(&config, 0, sizeof(config));
 284
 285         if (dma->direction == DMA_DEV_TO_MEM) {
 286                 sdd = container_of((void *)dma,
 287                         struct s3c64xx_spi_driver_data, rx_dma);
 288                 config.direction = dma->direction;
 289                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 290                 config.src_addr_width = sdd->cur_bpw / 8;
 291                 config.src_maxburst = 1;
 292                 dmaengine_slave_config(dma->ch, &config);
 293         } else {
 294                 sdd = container_of((void *)dma,
 295                         struct s3c64xx_spi_driver_data, tx_dma);
 296                 config.direction = dma->direction;
 297                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 298                 config.dst_addr_width = sdd->cur_bpw / 8;
 299                 config.dst_maxburst = 1;
 300                 dmaengine_slave_config(dma->ch, &config);
 301         }
 302
 303         desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
 304                                        dma->direction, DMA_PREP_INTERRUPT);
 305
 306         desc->callback = s3c64xx_spi_dmacb;
 307         desc->callback_param = dma;
 308
 309         dmaengine_submit(desc);
 310         dma_async_issue_pending(dma->ch);
 311 }
 312
 313 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
 314 {
 315         struct s3c64xx_spi_driver_data *sdd =
 316                                         spi_master_get_devdata(spi->master);
 317
 318         if (sdd->cntrlr_info->no_cs)
 319                 return;
 320
 321         if (enable) {
 322                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
 323                         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 324                 } else {
 325                         u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 326
 327                         ssel |= (S3C64XX_SPI_SLAVE_AUTO |
 328                                                 S3C64XX_SPI_SLAVE_NSC_CNT_2);
 329                         writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 330                 }
 331         } else {
 332                 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 333                         writel(S3C64XX_SPI_SLAVE_SIG_INACT,
 334                                sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 335         }
 336 }
 337
 338 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 339 {
 340         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 341         dma_filter_fn filter = sdd->cntrlr_info->filter;
 342         struct device *dev = &sdd->pdev->dev;
 343         dma_cap_mask_t mask;
 344
 345         if (is_polling(sdd))
 346                 return 0;
 347
 348         dma_cap_zero(mask);
 349         dma_cap_set(DMA_SLAVE, mask);
 350
 351         /* Acquire DMA channels */
 352         sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 353                            sdd->cntrlr_info->dma_rx, dev, "rx");
 354         if (!sdd->rx_dma.ch) {
 355                 dev_err(dev, "Failed to get RX DMA channel\n");
 356                 return -EBUSY;
 357         }
 358         spi->dma_rx = sdd->rx_dma.ch;
 359
 360         sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 361                            sdd->cntrlr_info->dma_tx, dev, "tx");
 362         if (!sdd->tx_dma.ch) {
 363                 dev_err(dev, "Failed to get TX DMA channel\n");
 364                 dma_release_channel(sdd->rx_dma.ch);
 365                 return -EBUSY;
 366         }
 367         spi->dma_tx = sdd->tx_dma.ch;
 368
 369         return 0;
 370 }
 371
 372 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 373 {
 374         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 375
 376         /* Free DMA channels */
 377         if (!is_polling(sdd)) {
 378                 dma_release_channel(sdd->rx_dma.ch);
 379                 dma_release_channel(sdd->tx_dma.ch);
 380         }
 381
 382         return 0;
 383 }
 384
 385 static bool s3c64xx_spi_can_dma(struct spi_master *master,
 386                                 struct spi_device *spi,
 387                                 struct spi_transfer *xfer)
 388 {
 389         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 390
 391         return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
 392 }
 393
 394 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 395                                 struct spi_device *spi,
 396                                 struct spi_transfer *xfer, int dma_mode)
 397 {
 398         void __iomem *regs = sdd->regs;
 399         u32 modecfg, chcfg;
 400
 401         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 402         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 403
 404         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 405         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 406
 407         if (dma_mode) {
 408                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 409         } else {
 410                 /* Always shift in data in FIFO, even if xfer is Tx only,
 411                  * this helps setting PCKT_CNT value for generating clocks
 412                  * as exactly needed.
 413                  */
 414                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 415                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 416                                         | S3C64XX_SPI_PACKET_CNT_EN,
 417                                         regs + S3C64XX_SPI_PACKET_CNT);
 418         }
 419
 420         if (xfer->tx_buf != NULL) {
 421                 sdd->state |= TXBUSY;
 422                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 423                 if (dma_mode) {
 424                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 425                         prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
 426                 } else {
 427                         switch (sdd->cur_bpw) {
 428                         case 32:
 429                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 430                                         xfer->tx_buf, xfer->len / 4);
 431                                 break;
 432                         case 16:
 433                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 434                                         xfer->tx_buf, xfer->len / 2);
 435                                 break;
 436                         default:
 437                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 438                                         xfer->tx_buf, xfer->len);
 439                                 break;
 440                         }
 441                 }
 442         }
 443
 444         if (xfer->rx_buf != NULL) {
 445                 sdd->state |= RXBUSY;
 446
 447                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 448                                         && !(sdd->cur_mode & SPI_CPHA))
 449                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 450
 451                 if (dma_mode) {
 452                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 453                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 454                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 455                                         | S3C64XX_SPI_PACKET_CNT_EN,
 456                                         regs + S3C64XX_SPI_PACKET_CNT);
 457                         prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
 458                 }
 459         }
 460
 461         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 462         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 463 }
 464
 465 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 466                                         int timeout_ms)
 467 {
 468         void __iomem *regs = sdd->regs;
 469         unsigned long val = 1;
 470         u32 status;
 471
 472         /* max fifo depth available */
 473         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 474
 475         if (timeout_ms)
 476                 val = msecs_to_loops(timeout_ms);
 477
 478         do {
 479                 status = readl(regs + S3C64XX_SPI_STATUS);
 480         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 481
 482         /* return the actual received data length */
 483         return RX_FIFO_LVL(status, sdd);
 484 }
 485
 486 static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
 487                         struct spi_transfer *xfer)
 488 {
 489         void __iomem *regs = sdd->regs;
 490         unsigned long val;
 491         u32 status;
 492         int ms;
 493
 494         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 495         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 496         ms += 10; /* some tolerance */
 497
 498         val = msecs_to_jiffies(ms) + 10;
 499         val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 500
 501         /*
 502          * If the previous xfer was completed within timeout, then
 503          * proceed further else return -EIO.
 504          * DmaTx returns after simply writing data in the FIFO,
 505          * w/o waiting for real transmission on the bus to finish.
 506          * DmaRx returns only after Dma read data from FIFO which
 507          * needs bus transmission to finish, so we don't worry if
 508          * Xfer involved Rx(with or without Tx).
 509          */
 510         if (val && !xfer->rx_buf) {
 511                 val = msecs_to_loops(10);
 512                 status = readl(regs + S3C64XX_SPI_STATUS);
 513                 while ((TX_FIFO_LVL(status, sdd)
 514                         || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 515                        && --val) {
 516                         cpu_relax();
 517                         status = readl(regs + S3C64XX_SPI_STATUS);
 518                 }
 519
 520         }
 521
 522         /* If timed out while checking rx/tx status return error */
 523         if (!val)
 524                 return -EIO;
 525
 526         return 0;
 527 }
 528
 529 static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
 530                         struct spi_transfer *xfer)
 531 {
 532         void __iomem *regs = sdd->regs;
 533         unsigned long val;
 534         u32 status;
 535         int loops;
 536         u32 cpy_len;
 537         u8 *buf;
 538         int ms;
 539
 540         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 541         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 542         ms += 10; /* some tolerance */
 543
 544         val = msecs_to_loops(ms);
 545         do {
 546                 status = readl(regs + S3C64XX_SPI_STATUS);
 547         } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 548
 549
 550         /* If it was only Tx */
 551         if (!xfer->rx_buf) {
 552                 sdd->state &= ~TXBUSY;
 553                 return 0;
 554         }
 555
 556         /*
 557          * If the receive length is bigger than the controller fifo
 558          * size, calculate the loops and read the fifo as many times.
 559          * loops = length / max fifo size (calculated by using the
 560          * fifo mask).
 561          * For any size less than the fifo size the below code is
 562          * executed atleast once.
 563          */
 564         loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 565         buf = xfer->rx_buf;
 566         do {
 567                 /* wait for data to be received in the fifo */
 568                 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 569                                                        (loops ? ms : 0));
 570
 571                 switch (sdd->cur_bpw) {
 572                 case 32:
 573                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 574                                      buf, cpy_len / 4);
 575                         break;
 576                 case 16:
 577                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 578                                      buf, cpy_len / 2);
 579                         break;
 580                 default:
 581                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 582                                     buf, cpy_len);
 583                         break;
 584                 }
 585
 586                 buf = buf + cpy_len;
 587         } while (loops--);
 588         sdd->state &= ~RXBUSY;
 589
 590         return 0;
 591 }
 592
 593 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 594 {
 595         void __iomem *regs = sdd->regs;
 596         u32 val;
 597
 598         /* Disable Clock */
 599         if (sdd->port_conf->clk_from_cmu) {
 600                 clk_disable_unprepare(sdd->src_clk);
 601         } else {
 602                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 603                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 604                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 605         }
 606
 607         /* Set Polarity and Phase */
 608         val = readl(regs + S3C64XX_SPI_CH_CFG);
 609         val &= ~(S3C64XX_SPI_CH_SLAVE |
 610                         S3C64XX_SPI_CPOL_L |
 611                         S3C64XX_SPI_CPHA_B);
 612
 613         if (sdd->cur_mode & SPI_CPOL)
 614                 val |= S3C64XX_SPI_CPOL_L;
 615
 616         if (sdd->cur_mode & SPI_CPHA)
 617                 val |= S3C64XX_SPI_CPHA_B;
 618
 619         writel(val, regs + S3C64XX_SPI_CH_CFG);
 620
 621         /* Set Channel & DMA Mode */
 622         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 623         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 624                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 625
 626         switch (sdd->cur_bpw) {
 627         case 32:
 628                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 629                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 630                 break;
 631         case 16:
 632                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 633                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 634                 break;
 635         default:
 636                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 637                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 638                 break;
 639         }
 640
 641         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 642
 643         if (sdd->port_conf->clk_from_cmu) {
 644                 /* Configure Clock */
 645                 /* There is half-multiplier before the SPI */
 646                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 647                 /* Enable Clock */
 648                 clk_prepare_enable(sdd->src_clk);
 649         } else {
 650                 /* Configure Clock */
 651                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 652                 val &= ~S3C64XX_SPI_PSR_MASK;
 653                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 654                                 & S3C64XX_SPI_PSR_MASK);
 655                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 656
 657                 /* Enable Clock */
 658                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 659                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 660                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 661         }
 662 }
 663
 664 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 665
 666 static int s3c64xx_spi_prepare_message(struct spi_master *master,
 667                                        struct spi_message *msg)
 668 {
 669         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 670         struct spi_device *spi = msg->spi;
 671         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 672
 673         /* Configure feedback delay */
 674         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 675
 676         return 0;
 677 }
 678
 679 static int s3c64xx_spi_transfer_one(struct spi_master *master,
 680                                     struct spi_device *spi,
 681                                     struct spi_transfer *xfer)
 682 {
 683         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 684         int status;
 685         u32 speed;
 686         u8 bpw;
 687         unsigned long flags;
 688         int use_dma;
 689
 690         reinit_completion(&sdd->xfer_completion);
 691
 692         /* Only BPW and Speed may change across transfers */
 693         bpw = xfer->bits_per_word;
 694         speed = xfer->speed_hz;
 695
 696         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 697                 sdd->cur_bpw = bpw;
 698                 sdd->cur_speed = speed;
 699                 sdd->cur_mode = spi->mode;
 700                 s3c64xx_spi_config(sdd);
 701         }
 702
 703         /* Polling method for xfers not bigger than FIFO capacity */
 704         use_dma = 0;
 705         if (!is_polling(sdd) &&
 706             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
 707              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
 708                 use_dma = 1;
 709
 710         spin_lock_irqsave(&sdd->lock, flags);
 711
 712         /* Pending only which is to be done */
 713         sdd->state &= ~RXBUSY;
 714         sdd->state &= ~TXBUSY;
 715
 716         enable_datapath(sdd, spi, xfer, use_dma);
 717
 718         /* Start the signals */
 719         s3c64xx_spi_set_cs(spi, true);
 720
 721         spin_unlock_irqrestore(&sdd->lock, flags);
 722
 723         if (use_dma)
 724                 status = wait_for_dma(sdd, xfer);
 725         else
 726                 status = wait_for_pio(sdd, xfer);
 727
 728         if (status) {
 729                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 730                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 731                         (sdd->state & RXBUSY) ? 'f' : 'p',
 732                         (sdd->state & TXBUSY) ? 'f' : 'p',
 733                         xfer->len);
 734
 735                 if (use_dma) {
 736                         if (xfer->tx_buf != NULL
 737                             && (sdd->state & TXBUSY))
 738                                 dmaengine_terminate_all(sdd->tx_dma.ch);
 739                         if (xfer->rx_buf != NULL
 740                             && (sdd->state & RXBUSY))
 741                                 dmaengine_terminate_all(sdd->rx_dma.ch);
 742                 }
 743         } else {
 744                 flush_fifo(sdd);
 745         }
 746
 747         return status;
 748 }
 749
 750 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 751                                 struct spi_device *spi)
 752 {
 753         struct s3c64xx_spi_csinfo *cs;
 754         struct device_node *slave_np, *data_np = NULL;
 755         u32 fb_delay = 0;
 756
 757         slave_np = spi->dev.of_node;
 758         if (!slave_np) {
 759                 dev_err(&spi->dev, "device node not found\n");
 760                 return ERR_PTR(-EINVAL);
 761         }
 762
 763         data_np = of_get_child_by_name(slave_np, "controller-data");
 764         if (!data_np) {
 765                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 766                 return ERR_PTR(-EINVAL);
 767         }
 768
 769         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 770         if (!cs) {
 771                 of_node_put(data_np);
 772                 return ERR_PTR(-ENOMEM);
 773         }
 774
 775         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 776         cs->fb_delay = fb_delay;
 777         of_node_put(data_np);
 778         return cs;
 779 }
 780
 781 /*
 782  * Here we only check the validity of requested configuration
 783  * and save the configuration in a local data-structure.
 784  * The controller is actually configured only just before we
 785  * get a message to transfer.
 786  */
 787 static int s3c64xx_spi_setup(struct spi_device *spi)
 788 {
 789         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 790         struct s3c64xx_spi_driver_data *sdd;
 791         struct s3c64xx_spi_info *sci;
 792         int err;
 793
 794         sdd = spi_master_get_devdata(spi->master);
 795         if (spi->dev.of_node) {
 796                 cs = s3c64xx_get_slave_ctrldata(spi);
 797                 spi->controller_data = cs;
 798         } else if (cs) {
 799                 /* On non-DT platforms the SPI core will set spi->cs_gpio
 800                  * to -ENOENT. The GPIO pin used to drive the chip select
 801                  * is defined by using platform data so spi->cs_gpio value
 802                  * has to be override to have the proper GPIO pin number.
 803                  */
 804                 spi->cs_gpio = cs->line;
 805         }
 806
 807         if (IS_ERR_OR_NULL(cs)) {
 808                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 809                 return -ENODEV;
 810         }
 811
 812         if (!spi_get_ctldata(spi)) {
 813                 if (gpio_is_valid(spi->cs_gpio)) {
 814                         err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
 815                                                dev_name(&spi->dev));
 816                         if (err) {
 817                                 dev_err(&spi->dev,
 818                                         "Failed to get /CS gpio [%d]: %d\n",
 819                                         spi->cs_gpio, err);
 820                                 goto err_gpio_req;
 821                         }
 822                 }
 823
 824                 spi_set_ctldata(spi, cs);
 825         }
 826
 827         sci = sdd->cntrlr_info;
 828
 829         pm_runtime_get_sync(&sdd->pdev->dev);
 830
 831         /* Check if we can provide the requested rate */
 832         if (!sdd->port_conf->clk_from_cmu) {
 833                 u32 psr, speed;
 834
 835                 /* Max possible */
 836                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 837
 838                 if (spi->max_speed_hz > speed)
 839                         spi->max_speed_hz = speed;
 840
 841                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 842                 psr &= S3C64XX_SPI_PSR_MASK;
 843                 if (psr == S3C64XX_SPI_PSR_MASK)
 844                         psr--;
 845
 846                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 847                 if (spi->max_speed_hz < speed) {
 848                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 849                                 psr++;
 850                         } else {
 851                                 err = -EINVAL;
 852                                 goto setup_exit;
 853                         }
 854                 }
 855
 856                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 857                 if (spi->max_speed_hz >= speed) {
 858                         spi->max_speed_hz = speed;
 859                 } else {
 860                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
 861                                 spi->max_speed_hz);
 862                         err = -EINVAL;
 863                         goto setup_exit;
 864                 }
 865         }
 866
 867         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 868         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 869         s3c64xx_spi_set_cs(spi, false);
 870
 871         return 0;
 872
 873 setup_exit:
 874         pm_runtime_mark_last_busy(&sdd->pdev->dev);
 875         pm_runtime_put_autosuspend(&sdd->pdev->dev);
 876         /* setup() returns with device de-selected */
 877         s3c64xx_spi_set_cs(spi, false);
 878
 879         if (gpio_is_valid(spi->cs_gpio))
 880                 gpio_free(spi->cs_gpio);
 881         spi_set_ctldata(spi, NULL);
 882
 883 err_gpio_req:
 884         if (spi->dev.of_node)
 885                 kfree(cs);
 886
 887         return err;
 888 }
 889
 890 static void s3c64xx_spi_cleanup(struct spi_device *spi)
 891 {
 892         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 893
 894         if (gpio_is_valid(spi->cs_gpio)) {
 895                 gpio_free(spi->cs_gpio);
 896                 if (spi->dev.of_node)
 897                         kfree(cs);
 898                 else {
 899                         /* On non-DT platforms, the SPI core sets
 900                          * spi->cs_gpio to -ENOENT and .setup()
 901                          * overrides it with the GPIO pin value
 902                          * passed using platform data.
 903                          */
 904                         spi->cs_gpio = -ENOENT;
 905                 }
 906         }
 907
 908         spi_set_ctldata(spi, NULL);
 909 }
 910
 911 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 912 {
 913         struct s3c64xx_spi_driver_data *sdd = data;
 914         struct spi_master *spi = sdd->master;
 915         unsigned int val, clr = 0;
 916
 917         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
 918
 919         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
 920                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
 921                 dev_err(&spi->dev, "RX overrun\n");
 922         }
 923         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
 924                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
 925                 dev_err(&spi->dev, "RX underrun\n");
 926         }
 927         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
 928                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
 929                 dev_err(&spi->dev, "TX overrun\n");
 930         }
 931         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
 932                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 933                 dev_err(&spi->dev, "TX underrun\n");
 934         }
 935
 936         /* Clear the pending irq by setting and then clearing it */
 937         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 938         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 939
 940         return IRQ_HANDLED;
 941 }
 942
 943 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
 944 {
 945         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 946         void __iomem *regs = sdd->regs;
 947         unsigned int val;
 948
 949         sdd->cur_speed = 0;
 950
 951         if (sci->no_cs)
 952                 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 953         else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 954                 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 955
 956         /* Disable Interrupts - we use Polling if not DMA mode */
 957         writel(0, regs + S3C64XX_SPI_INT_EN);
 958
 959         if (!sdd->port_conf->clk_from_cmu)
 960                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 961                                 regs + S3C64XX_SPI_CLK_CFG);
 962         writel(0, regs + S3C64XX_SPI_MODE_CFG);
 963         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 964
 965         /* Clear any irq pending bits, should set and clear the bits */
 966         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
 967                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
 968                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
 969                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 970         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
 971         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
 972
 973         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
 974
 975         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 976         val &= ~S3C64XX_SPI_MODE_4BURST;
 977         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 978         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 979         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 980
 981         flush_fifo(sdd);
 982 }
 983
 984 #ifdef CONFIG_OF
 985 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
 986 {
 987         struct s3c64xx_spi_info *sci;
 988         u32 temp;
 989
 990         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
 991         if (!sci)
 992                 return ERR_PTR(-ENOMEM);
 993
 994         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
 995                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
 996                 sci->src_clk_nr = 0;
 997         } else {
 998                 sci->src_clk_nr = temp;
 999         }
1000
1001         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1002                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1003                 sci->num_cs = 1;
1004         } else {
1005                 sci->num_cs = temp;
1006         }
1007
1008         sci->no_cs = of_property_read_bool(dev->of_node, "broken-cs");
1009
1010         return sci;
1011 }
1012 #else
1013 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1014 {
1015         return dev_get_platdata(dev);
1016 }
1017 #endif
1018
1019 static const struct of_device_id s3c64xx_spi_dt_match[];
1020
1021 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1022                                                 struct platform_device *pdev)
1023 {
1024 #ifdef CONFIG_OF
1025         if (pdev->dev.of_node) {
1026                 const struct of_device_id *match;
1027                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1028                 return (struct s3c64xx_spi_port_config *)match->data;
1029         }
1030 #endif
1031         return (struct s3c64xx_spi_port_config *)
1032                          platform_get_device_id(pdev)->driver_data;
1033 }
1034
1035 static int s3c64xx_spi_probe(struct platform_device *pdev)
1036 {
1037         struct resource *mem_res;
1038         struct s3c64xx_spi_driver_data *sdd;
1039         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1040         struct spi_master *master;
1041         int ret, irq;
1042         char clk_name[16];
1043
1044         if (!sci && pdev->dev.of_node) {
1045                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1046                 if (IS_ERR(sci))
1047                         return PTR_ERR(sci);
1048         }
1049
1050         if (!sci) {
1051                 dev_err(&pdev->dev, "platform_data missing!\n");
1052                 return -ENODEV;
1053         }
1054
1055         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1056         if (mem_res == NULL) {
1057                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1058                 return -ENXIO;
1059         }
1060
1061         irq = platform_get_irq(pdev, 0);
1062         if (irq < 0) {
1063                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1064                 return irq;
1065         }
1066
1067         master = spi_alloc_master(&pdev->dev,
1068                                 sizeof(struct s3c64xx_spi_driver_data));
1069         if (master == NULL) {
1070                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1071                 return -ENOMEM;
1072         }
1073
1074         platform_set_drvdata(pdev, master);
1075
1076         sdd = spi_master_get_devdata(master);
1077         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1078         sdd->master = master;
1079         sdd->cntrlr_info = sci;
1080         sdd->pdev = pdev;
1081         sdd->sfr_start = mem_res->start;
1082         if (pdev->dev.of_node) {
1083                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1084                 if (ret < 0) {
1085                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1086                                 ret);
1087                         goto err0;
1088                 }
1089                 sdd->port_id = ret;
1090         } else {
1091                 sdd->port_id = pdev->id;
1092         }
1093
1094         sdd->cur_bpw = 8;
1095
1096         if (!sdd->pdev->dev.of_node && (!sci->dma_tx || !sci->dma_rx)) {
1097                 dev_warn(&pdev->dev, "Unable to get SPI tx/rx DMA data. Switching to poll mode\n");
1098                 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1099         }
1100
1101         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1102         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1103
1104         master->dev.of_node = pdev->dev.of_node;
1105         master->bus_num = sdd->port_id;
1106         master->setup = s3c64xx_spi_setup;
1107         master->cleanup = s3c64xx_spi_cleanup;
1108         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1109         master->prepare_message = s3c64xx_spi_prepare_message;
1110         master->transfer_one = s3c64xx_spi_transfer_one;
1111         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1112         master->num_chipselect = sci->num_cs;
1113         master->dma_alignment = 8;
1114         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1115                                         SPI_BPW_MASK(8);
1116         /* the spi->mode bits understood by this driver: */
1117         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1118         master->auto_runtime_pm = true;
1119         if (!is_polling(sdd))
1120                 master->can_dma = s3c64xx_spi_can_dma;
1121
1122         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1123         if (IS_ERR(sdd->regs)) {
1124                 ret = PTR_ERR(sdd->regs);
1125                 goto err0;
1126         }
1127
1128         if (sci->cfg_gpio && sci->cfg_gpio()) {
1129                 dev_err(&pdev->dev, "Unable to config gpio\n");
1130                 ret = -EBUSY;
1131                 goto err0;
1132         }
1133
1134         /* Setup clocks */
1135         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1136         if (IS_ERR(sdd->clk)) {
1137                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1138                 ret = PTR_ERR(sdd->clk);
1139                 goto err0;
1140         }
1141
1142         if (clk_prepare_enable(sdd->clk)) {
1143                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1144                 ret = -EBUSY;
1145                 goto err0;
1146         }
1147
1148         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1149         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1150         if (IS_ERR(sdd->src_clk)) {
1151                 dev_err(&pdev->dev,
1152                         "Unable to acquire clock '%s'\n", clk_name);
1153                 ret = PTR_ERR(sdd->src_clk);
1154                 goto err2;
1155         }
1156
1157         if (clk_prepare_enable(sdd->src_clk)) {
1158                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1159                 ret = -EBUSY;
1160                 goto err2;
1161         }
1162
1163         pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1164         pm_runtime_use_autosuspend(&pdev->dev);
1165         pm_runtime_set_active(&pdev->dev);
1166         pm_runtime_enable(&pdev->dev);
1167         pm_runtime_get_sync(&pdev->dev);
1168
1169         /* Setup Deufult Mode */
1170         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1171
1172         spin_lock_init(&sdd->lock);
1173         init_completion(&sdd->xfer_completion);
1174
1175         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1176                                 "spi-s3c64xx", sdd);
1177         if (ret != 0) {
1178                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1179                         irq, ret);
1180                 goto err3;
1181         }
1182
1183         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1184                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1185                sdd->regs + S3C64XX_SPI_INT_EN);
1186
1187         ret = devm_spi_register_master(&pdev->dev, master);
1188         if (ret != 0) {
1189                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1190                 goto err3;
1191         }
1192
1193         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1194                                         sdd->port_id, master->num_chipselect);
1195         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%p, Tx-%p]\n",
1196                                         mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1,
1197                                         sci->dma_rx, sci->dma_tx);
1198
1199         pm_runtime_mark_last_busy(&pdev->dev);
1200         pm_runtime_put_autosuspend(&pdev->dev);
1201
1202         return 0;
1203
1204 err3:
1205         pm_runtime_put_noidle(&pdev->dev);
1206         pm_runtime_disable(&pdev->dev);
1207         pm_runtime_set_suspended(&pdev->dev);
1208
1209         clk_disable_unprepare(sdd->src_clk);
1210 err2:
1211         clk_disable_unprepare(sdd->clk);
1212 err0:
1213         spi_master_put(master);
1214
1215         return ret;
1216 }
1217
1218 static int s3c64xx_spi_remove(struct platform_device *pdev)
1219 {
1220         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1221         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1222
1223         pm_runtime_get_sync(&pdev->dev);
1224
1225         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1226
1227         clk_disable_unprepare(sdd->src_clk);
1228
1229         clk_disable_unprepare(sdd->clk);
1230
1231         pm_runtime_put_noidle(&pdev->dev);
1232         pm_runtime_disable(&pdev->dev);
1233         pm_runtime_set_suspended(&pdev->dev);
1234
1235         return 0;
1236 }
1237
1238 #ifdef CONFIG_PM_SLEEP
1239 static int s3c64xx_spi_suspend(struct device *dev)
1240 {
1241         struct spi_master *master = dev_get_drvdata(dev);
1242         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1243
1244         int ret = spi_master_suspend(master);
1245         if (ret)
1246                 return ret;
1247
1248         ret = pm_runtime_force_suspend(dev);
1249         if (ret < 0)
1250                 return ret;
1251
1252         sdd->cur_speed = 0; /* Output Clock is stopped */
1253
1254         return 0;
1255 }
1256
1257 static int s3c64xx_spi_resume(struct device *dev)
1258 {
1259         struct spi_master *master = dev_get_drvdata(dev);
1260         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1261         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1262         int ret;
1263
1264         if (sci->cfg_gpio)
1265                 sci->cfg_gpio();
1266
1267         ret = pm_runtime_force_resume(dev);
1268         if (ret < 0)
1269                 return ret;
1270
1271         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1272
1273         return spi_master_resume(master);
1274 }
1275 #endif /* CONFIG_PM_SLEEP */
1276
1277 #ifdef CONFIG_PM
1278 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1279 {
1280         struct spi_master *master = dev_get_drvdata(dev);
1281         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1282
1283         clk_disable_unprepare(sdd->clk);
1284         clk_disable_unprepare(sdd->src_clk);
1285
1286         return 0;
1287 }
1288
1289 static int s3c64xx_spi_runtime_resume(struct device *dev)
1290 {
1291         struct spi_master *master = dev_get_drvdata(dev);
1292         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1293         int ret;
1294
1295         ret = clk_prepare_enable(sdd->src_clk);
1296         if (ret != 0)
1297                 return ret;
1298
1299         ret = clk_prepare_enable(sdd->clk);
1300         if (ret != 0) {
1301                 clk_disable_unprepare(sdd->src_clk);
1302                 return ret;
1303         }
1304
1305         return 0;
1306 }
1307 #endif /* CONFIG_PM */
1308
1309 static const struct dev_pm_ops s3c64xx_spi_pm = {
1310         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1311         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1312                            s3c64xx_spi_runtime_resume, NULL)
1313 };
1314
1315 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1316         .fifo_lvl_mask  = { 0x7f },
1317         .rx_lvl_offset  = 13,
1318         .tx_st_done     = 21,
1319         .high_speed     = true,
1320 };
1321
1322 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1323         .fifo_lvl_mask  = { 0x7f, 0x7F },
1324         .rx_lvl_offset  = 13,
1325         .tx_st_done     = 21,
1326 };
1327
1328 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1329         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1330         .rx_lvl_offset  = 15,
1331         .tx_st_done     = 25,
1332         .high_speed     = true,
1333 };
1334
1335 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1336         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1337         .rx_lvl_offset  = 15,
1338         .tx_st_done     = 25,
1339         .high_speed     = true,
1340         .clk_from_cmu   = true,
1341 };
1342
1343 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1344         .fifo_lvl_mask  = { 0x1ff },
1345         .rx_lvl_offset  = 15,
1346         .tx_st_done     = 25,
1347         .high_speed     = true,
1348         .clk_from_cmu   = true,
1349         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1350 };
1351
1352 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1353         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1354         .rx_lvl_offset  = 15,
1355         .tx_st_done     = 25,
1356         .high_speed     = true,
1357         .clk_from_cmu   = true,
1358         .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1359 };
1360
1361 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1362         {
1363                 .name           = "s3c2443-spi",
1364                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1365         }, {
1366                 .name           = "s3c6410-spi",
1367                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1368         },
1369         { },
1370 };
1371
1372 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1373         { .compatible = "samsung,s3c2443-spi",
1374                         .data = (void *)&s3c2443_spi_port_config,
1375         },
1376         { .compatible = "samsung,s3c6410-spi",
1377                         .data = (void *)&s3c6410_spi_port_config,
1378         },
1379         { .compatible = "samsung,s5pv210-spi",
1380                         .data = (void *)&s5pv210_spi_port_config,
1381         },
1382         { .compatible = "samsung,exynos4210-spi",
1383                         .data = (void *)&exynos4_spi_port_config,
1384         },
1385         { .compatible = "samsung,exynos5440-spi",
1386                         .data = (void *)&exynos5440_spi_port_config,
1387         },
1388         { .compatible = "samsung,exynos7-spi",
1389                         .data = (void *)&exynos7_spi_port_config,
1390         },
1391         { },
1392 };
1393 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1394
1395 static struct platform_driver s3c64xx_spi_driver = {
1396         .driver = {
1397                 .name   = "s3c64xx-spi",
1398                 .pm = &s3c64xx_spi_pm,
1399                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1400         },
1401         .probe = s3c64xx_spi_probe,
1402         .remove = s3c64xx_spi_remove,
1403         .id_table = s3c64xx_spi_driver_ids,
1404 };
1405 MODULE_ALIAS("platform:s3c64xx-spi");
1406
1407 module_platform_driver(s3c64xx_spi_driver);
1408
1409 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1410 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1411 MODULE_LICENSE("GPL");