2 * SuperH MSIOF SPI Master Interface
4 * Copyright (c) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/bitmap.h>
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/spi/sh_msiof.h>
27 #include <linux/spi/spi.h>
28 #include <linux/spi/spi_bitbang.h>
30 #include <asm/unaligned.h>
32 struct sh_msiof_spi_priv {
33 struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */
34 void __iomem *mapbase;
36 struct platform_device *pdev;
37 struct sh_msiof_spi_info *info;
38 struct completion done;
63 #define CTR_TSCKE (1 << 15)
64 #define CTR_TFSE (1 << 14)
65 #define CTR_TXE (1 << 9)
66 #define CTR_RXE (1 << 8)
68 #define STR_TEOF (1 << 23)
69 #define STR_REOF (1 << 7)
71 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
76 return ioread16(p->mapbase + reg_offs);
78 return ioread32(p->mapbase + reg_offs);
82 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
88 iowrite16(value, p->mapbase + reg_offs);
91 iowrite32(value, p->mapbase + reg_offs);
96 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
103 data = sh_msiof_read(p, CTR);
106 sh_msiof_write(p, CTR, data);
108 for (k = 100; k > 0; k--) {
109 if ((sh_msiof_read(p, CTR) & mask) == set)
115 return k > 0 ? 0 : -ETIMEDOUT;
118 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
120 struct sh_msiof_spi_priv *p = data;
122 /* just disable the interrupt and wake up */
123 sh_msiof_write(p, IER, 0);
132 } const sh_msiof_spi_clk_table[] = {
146 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
147 unsigned long parent_rate,
148 unsigned long spi_hz)
150 unsigned long div = 1024;
153 if (!WARN_ON(!spi_hz || !parent_rate))
154 div = DIV_ROUND_UP(parent_rate, spi_hz);
156 /* TODO: make more fine grained */
158 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
159 if (sh_msiof_spi_clk_table[k].div >= div)
163 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
165 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
166 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
169 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
171 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
177 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
183 sh_msiof_write(p, FCTR, 0);
186 tmp |= !cs_high << 25;
187 tmp |= lsb_first << 24;
188 sh_msiof_write(p, TMDR1, 0xe0000005 | tmp);
189 sh_msiof_write(p, RMDR1, 0x20000005 | tmp);
192 tmp |= cpol << 30; /* TSCKIZ */
193 tmp |= cpol << 28; /* RSCKIZ */
197 tmp |= edge << 27; /* TEDG */
198 tmp |= edge << 26; /* REDG */
199 tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */
200 sh_msiof_write(p, CTR, tmp);
203 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
204 const void *tx_buf, void *rx_buf,
207 u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16);
210 sh_msiof_write(p, TMDR2, dr2);
212 sh_msiof_write(p, TMDR2, dr2 | 1);
215 sh_msiof_write(p, RMDR2, dr2);
217 sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
220 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
222 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
225 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
226 const void *tx_buf, int words, int fs)
228 const u8 *buf_8 = tx_buf;
231 for (k = 0; k < words; k++)
232 sh_msiof_write(p, TFDR, buf_8[k] << fs);
235 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
236 const void *tx_buf, int words, int fs)
238 const u16 *buf_16 = tx_buf;
241 for (k = 0; k < words; k++)
242 sh_msiof_write(p, TFDR, buf_16[k] << fs);
245 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
246 const void *tx_buf, int words, int fs)
248 const u16 *buf_16 = tx_buf;
251 for (k = 0; k < words; k++)
252 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
255 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
256 const void *tx_buf, int words, int fs)
258 const u32 *buf_32 = tx_buf;
261 for (k = 0; k < words; k++)
262 sh_msiof_write(p, TFDR, buf_32[k] << fs);
265 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
266 const void *tx_buf, int words, int fs)
268 const u32 *buf_32 = tx_buf;
271 for (k = 0; k < words; k++)
272 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
275 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
276 const void *tx_buf, int words, int fs)
278 const u32 *buf_32 = tx_buf;
281 for (k = 0; k < words; k++)
282 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
285 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
286 const void *tx_buf, int words, int fs)
288 const u32 *buf_32 = tx_buf;
291 for (k = 0; k < words; k++)
292 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
295 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
296 void *rx_buf, int words, int fs)
301 for (k = 0; k < words; k++)
302 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
305 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
306 void *rx_buf, int words, int fs)
308 u16 *buf_16 = rx_buf;
311 for (k = 0; k < words; k++)
312 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
315 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
316 void *rx_buf, int words, int fs)
318 u16 *buf_16 = rx_buf;
321 for (k = 0; k < words; k++)
322 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
325 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
326 void *rx_buf, int words, int fs)
328 u32 *buf_32 = rx_buf;
331 for (k = 0; k < words; k++)
332 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
335 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
336 void *rx_buf, int words, int fs)
338 u32 *buf_32 = rx_buf;
341 for (k = 0; k < words; k++)
342 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
345 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
346 void *rx_buf, int words, int fs)
348 u32 *buf_32 = rx_buf;
351 for (k = 0; k < words; k++)
352 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
355 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
356 void *rx_buf, int words, int fs)
358 u32 *buf_32 = rx_buf;
361 for (k = 0; k < words; k++)
362 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
365 static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t)
369 bits = t ? t->bits_per_word : 0;
371 bits = spi->bits_per_word;
375 static unsigned long sh_msiof_spi_hz(struct spi_device *spi,
376 struct spi_transfer *t)
380 hz = t ? t->speed_hz : 0;
382 hz = spi->max_speed_hz;
386 static int sh_msiof_spi_setup_transfer(struct spi_device *spi,
387 struct spi_transfer *t)
391 /* noting to check hz values against since parent clock is disabled */
393 bits = sh_msiof_spi_bits(spi, t);
399 return spi_bitbang_setup_transfer(spi, t);
402 static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
404 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
407 /* chip select is active low unless SPI_CS_HIGH is set */
408 if (spi->mode & SPI_CS_HIGH)
409 value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0;
411 value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1;
413 if (is_on == BITBANG_CS_ACTIVE) {
414 if (!test_and_set_bit(0, &p->flags)) {
415 pm_runtime_get_sync(&p->pdev->dev);
419 /* Configure pins before asserting CS */
420 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
421 !!(spi->mode & SPI_CPHA),
422 !!(spi->mode & SPI_3WIRE),
423 !!(spi->mode & SPI_LSB_FIRST),
424 !!(spi->mode & SPI_CS_HIGH));
427 /* use spi->controller data for CS (same strategy as spi_gpio) */
428 gpio_set_value((uintptr_t)spi->controller_data, value);
430 if (is_on == BITBANG_CS_INACTIVE) {
431 if (test_and_clear_bit(0, &p->flags)) {
433 pm_runtime_put(&p->pdev->dev);
438 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
439 void (*tx_fifo)(struct sh_msiof_spi_priv *,
440 const void *, int, int),
441 void (*rx_fifo)(struct sh_msiof_spi_priv *,
443 const void *tx_buf, void *rx_buf,
449 /* limit maximum word transfer to rx/tx fifo size */
451 words = min_t(int, words, p->tx_fifo_size);
453 words = min_t(int, words, p->rx_fifo_size);
455 /* the fifo contents need shifting */
456 fifo_shift = 32 - bits;
458 /* setup msiof transfer mode registers */
459 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
463 tx_fifo(p, tx_buf, words, fifo_shift);
465 /* setup clock and rx/tx signals */
466 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
468 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
469 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
471 /* start by setting frame bit */
472 reinit_completion(&p->done);
473 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
475 dev_err(&p->pdev->dev, "failed to start hardware\n");
479 /* wait for tx fifo to be emptied / rx fifo to be filled */
480 wait_for_completion(&p->done);
484 rx_fifo(p, rx_buf, words, fifo_shift);
486 /* clear status bits */
487 sh_msiof_reset_str(p);
489 /* shut down frame, tx/tx and clock signals */
490 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
491 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
493 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
494 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
496 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
503 sh_msiof_write(p, IER, 0);
507 static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
509 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
510 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
511 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
519 bits = sh_msiof_spi_bits(spi, t);
521 if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
528 /* setup bytes per word and fifo read/write functions */
531 tx_fifo = sh_msiof_spi_write_fifo_8;
532 rx_fifo = sh_msiof_spi_read_fifo_8;
533 } else if (bits <= 16) {
535 if ((unsigned long)t->tx_buf & 0x01)
536 tx_fifo = sh_msiof_spi_write_fifo_16u;
538 tx_fifo = sh_msiof_spi_write_fifo_16;
540 if ((unsigned long)t->rx_buf & 0x01)
541 rx_fifo = sh_msiof_spi_read_fifo_16u;
543 rx_fifo = sh_msiof_spi_read_fifo_16;
546 if ((unsigned long)t->tx_buf & 0x03)
547 tx_fifo = sh_msiof_spi_write_fifo_s32u;
549 tx_fifo = sh_msiof_spi_write_fifo_s32;
551 if ((unsigned long)t->rx_buf & 0x03)
552 rx_fifo = sh_msiof_spi_read_fifo_s32u;
554 rx_fifo = sh_msiof_spi_read_fifo_s32;
557 if ((unsigned long)t->tx_buf & 0x03)
558 tx_fifo = sh_msiof_spi_write_fifo_32u;
560 tx_fifo = sh_msiof_spi_write_fifo_32;
562 if ((unsigned long)t->rx_buf & 0x03)
563 rx_fifo = sh_msiof_spi_read_fifo_32u;
565 rx_fifo = sh_msiof_spi_read_fifo_32;
568 /* setup clocks (clock already enabled in chipselect()) */
569 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk),
570 sh_msiof_spi_hz(spi, t));
572 /* transfer in fifo sized chunks */
573 words = t->len / bytes_per_word;
576 while (bytes_done < t->len) {
577 void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL;
578 const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL;
579 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
586 bytes_done += n * bytes_per_word;
593 static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
596 BUG(); /* unused but needed by bitbang code */
601 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
603 struct sh_msiof_spi_info *info;
604 struct device_node *np = dev->of_node;
607 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
609 dev_err(dev, "failed to allocate setup data\n");
613 /* Parse the MSIOF properties */
614 of_property_read_u32(np, "num-cs", &num_cs);
615 of_property_read_u32(np, "renesas,tx-fifo-size",
616 &info->tx_fifo_override);
617 of_property_read_u32(np, "renesas,rx-fifo-size",
618 &info->rx_fifo_override);
620 info->num_chipselect = num_cs;
625 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
631 static int sh_msiof_spi_probe(struct platform_device *pdev)
634 struct spi_master *master;
635 struct sh_msiof_spi_priv *p;
639 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
640 if (master == NULL) {
641 dev_err(&pdev->dev, "failed to allocate spi master\n");
645 p = spi_master_get_devdata(master);
647 platform_set_drvdata(pdev, p);
648 if (pdev->dev.of_node)
649 p->info = sh_msiof_spi_parse_dt(&pdev->dev);
651 p->info = dev_get_platdata(&pdev->dev);
654 dev_err(&pdev->dev, "failed to obtain device info\n");
659 init_completion(&p->done);
661 p->clk = devm_clk_get(&pdev->dev, NULL);
662 if (IS_ERR(p->clk)) {
663 dev_err(&pdev->dev, "cannot get clock\n");
664 ret = PTR_ERR(p->clk);
668 i = platform_get_irq(pdev, 0);
670 dev_err(&pdev->dev, "cannot get platform IRQ\n");
675 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
676 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
677 if (IS_ERR(p->mapbase)) {
678 ret = PTR_ERR(p->mapbase);
682 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
683 dev_name(&pdev->dev), p);
685 dev_err(&pdev->dev, "unable to request irq\n");
689 ret = clk_prepare(p->clk);
691 dev_err(&pdev->dev, "unable to prepare clock\n");
696 pm_runtime_enable(&pdev->dev);
698 /* The standard version of MSIOF use 64 word FIFOs */
699 p->tx_fifo_size = 64;
700 p->rx_fifo_size = 64;
702 /* Platform data may override FIFO sizes */
703 if (p->info->tx_fifo_override)
704 p->tx_fifo_size = p->info->tx_fifo_override;
705 if (p->info->rx_fifo_override)
706 p->rx_fifo_size = p->info->rx_fifo_override;
708 /* init master and bitbang code */
709 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
710 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
712 master->bus_num = pdev->id;
713 master->num_chipselect = p->info->num_chipselect;
714 master->setup = spi_bitbang_setup;
715 master->cleanup = spi_bitbang_cleanup;
717 p->bitbang.master = master;
718 p->bitbang.chipselect = sh_msiof_spi_chipselect;
719 p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer;
720 p->bitbang.txrx_bufs = sh_msiof_spi_txrx;
721 p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word;
722 p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word;
723 p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word;
724 p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word;
726 ret = spi_bitbang_start(&p->bitbang);
730 pm_runtime_disable(&pdev->dev);
731 clk_unprepare(p->clk);
733 spi_master_put(master);
737 static int sh_msiof_spi_remove(struct platform_device *pdev)
739 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
742 ret = spi_bitbang_stop(&p->bitbang);
744 pm_runtime_disable(&pdev->dev);
745 clk_unprepare(p->clk);
746 spi_master_put(p->bitbang.master);
752 static const struct of_device_id sh_msiof_match[] = {
753 { .compatible = "renesas,sh-msiof", },
754 { .compatible = "renesas,sh-mobile-msiof", },
757 MODULE_DEVICE_TABLE(of, sh_msiof_match);
760 static struct platform_driver sh_msiof_spi_drv = {
761 .probe = sh_msiof_spi_probe,
762 .remove = sh_msiof_spi_remove,
764 .name = "spi_sh_msiof",
765 .owner = THIS_MODULE,
766 .of_match_table = of_match_ptr(sh_msiof_match),
769 module_platform_driver(sh_msiof_spi_drv);
771 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
772 MODULE_AUTHOR("Magnus Damm");
773 MODULE_LICENSE("GPL v2");
774 MODULE_ALIAS("platform:spi_sh_msiof");