drivers/spi/spi-sh.c

   1 /*
   2  * SH SPI bus driver
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  *
   6  * Based on pxa2xx_spi.c:
   7  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/sched.h>
  22 #include <linux/errno.h>
  23 #include <linux/timer.h>
  24 #include <linux/delay.h>
  25 #include <linux/list.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/io.h>
  30 #include <linux/spi/spi.h>
  31
  32 #define SPI_SH_TBR              0x00
  33 #define SPI_SH_RBR              0x00
  34 #define SPI_SH_CR1              0x08
  35 #define SPI_SH_CR2              0x10
  36 #define SPI_SH_CR3              0x18
  37 #define SPI_SH_CR4              0x20
  38 #define SPI_SH_CR5              0x28
  39
  40 /* CR1 */
  41 #define SPI_SH_TBE              0x80
  42 #define SPI_SH_TBF              0x40
  43 #define SPI_SH_RBE              0x20
  44 #define SPI_SH_RBF              0x10
  45 #define SPI_SH_PFONRD           0x08
  46 #define SPI_SH_SSDB             0x04
  47 #define SPI_SH_SSD              0x02
  48 #define SPI_SH_SSA              0x01
  49
  50 /* CR2 */
  51 #define SPI_SH_RSTF             0x80
  52 #define SPI_SH_LOOPBK           0x40
  53 #define SPI_SH_CPOL             0x20
  54 #define SPI_SH_CPHA             0x10
  55 #define SPI_SH_L1M0             0x08
  56
  57 /* CR3 */
  58 #define SPI_SH_MAX_BYTE         0xFF
  59
  60 /* CR4 */
  61 #define SPI_SH_TBEI             0x80
  62 #define SPI_SH_TBFI             0x40
  63 #define SPI_SH_RBEI             0x20
  64 #define SPI_SH_RBFI             0x10
  65 #define SPI_SH_WPABRT           0x04
  66 #define SPI_SH_SSS              0x01
  67
  68 /* CR8 */
  69 #define SPI_SH_P1L0             0x80
  70 #define SPI_SH_PP1L0            0x40
  71 #define SPI_SH_MUXI             0x20
  72 #define SPI_SH_MUXIRQ           0x10
  73
  74 #define SPI_SH_FIFO_SIZE        32
  75 #define SPI_SH_SEND_TIMEOUT     (3 * HZ)
  76 #define SPI_SH_RECEIVE_TIMEOUT  (HZ >> 3)
  77
  78 #undef DEBUG
  79
  80 struct spi_sh_data {
  81         void __iomem *addr;
  82         int irq;
  83         struct spi_master *master;
  84         struct list_head queue;
  85         struct work_struct ws;
  86         unsigned long cr1;
  87         wait_queue_head_t wait;
  88         spinlock_t lock;
  89         int width;
  90 };
  91
  92 static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
  93                              unsigned long offset)
  94 {
  95         if (ss->width == 8)
  96                 iowrite8(data, ss->addr + (offset >> 2));
  97         else if (ss->width == 32)
  98                 iowrite32(data, ss->addr + offset);
  99 }
 100
 101 static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
 102 {
 103         if (ss->width == 8)
 104                 return ioread8(ss->addr + (offset >> 2));
 105         else if (ss->width == 32)
 106                 return ioread32(ss->addr + offset);
 107         else
 108                 return 0;
 109 }
 110
 111 static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
 112                                 unsigned long offset)
 113 {
 114         unsigned long tmp;
 115
 116         tmp = spi_sh_read(ss, offset);
 117         tmp |= val;
 118         spi_sh_write(ss, tmp, offset);
 119 }
 120
 121 static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
 122                                 unsigned long offset)
 123 {
 124         unsigned long tmp;
 125
 126         tmp = spi_sh_read(ss, offset);
 127         tmp &= ~val;
 128         spi_sh_write(ss, tmp, offset);
 129 }
 130
 131 static void clear_fifo(struct spi_sh_data *ss)
 132 {
 133         spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
 134         spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
 135 }
 136
 137 static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
 138 {
 139         int timeout = 100000;
 140
 141         while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
 142                 udelay(10);
 143                 if (timeout-- < 0)
 144                         return -ETIMEDOUT;
 145         }
 146         return 0;
 147 }
 148
 149 static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
 150 {
 151         int timeout = 100000;
 152
 153         while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
 154                 udelay(10);
 155                 if (timeout-- < 0)
 156                         return -ETIMEDOUT;
 157         }
 158         return 0;
 159 }
 160
 161 static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
 162                         struct spi_transfer *t)
 163 {
 164         int i, retval = 0;
 165         int remain = t->len;
 166         int cur_len;
 167         unsigned char *data;
 168         long ret;
 169
 170         if (t->len)
 171                 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
 172
 173         data = (unsigned char *)t->tx_buf;
 174         while (remain > 0) {
 175                 cur_len = min(SPI_SH_FIFO_SIZE, remain);
 176                 for (i = 0; i < cur_len &&
 177                                 !(spi_sh_read(ss, SPI_SH_CR4) &
 178                                                         SPI_SH_WPABRT) &&
 179                                 !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
 180                                 i++)
 181                         spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
 182
 183                 if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
 184                         /* Abort SPI operation */
 185                         spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
 186                         retval = -EIO;
 187                         break;
 188                 }
 189
 190                 cur_len = i;
 191
 192                 remain -= cur_len;
 193                 data += cur_len;
 194
 195                 if (remain > 0) {
 196                         ss->cr1 &= ~SPI_SH_TBE;
 197                         spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
 198                         ret = wait_event_interruptible_timeout(ss->wait,
 199                                                  ss->cr1 & SPI_SH_TBE,
 200                                                  SPI_SH_SEND_TIMEOUT);
 201                         if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
 202                                 printk(KERN_ERR "%s: timeout\n", __func__);
 203                                 return -ETIMEDOUT;
 204                         }
 205                 }
 206         }
 207
 208         if (list_is_last(&t->transfer_list, &mesg->transfers)) {
 209                 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
 210                 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
 211
 212                 ss->cr1 &= ~SPI_SH_TBE;
 213                 spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
 214                 ret = wait_event_interruptible_timeout(ss->wait,
 215                                          ss->cr1 & SPI_SH_TBE,
 216                                          SPI_SH_SEND_TIMEOUT);
 217                 if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
 218                         printk(KERN_ERR "%s: timeout\n", __func__);
 219                         return -ETIMEDOUT;
 220                 }
 221         }
 222
 223         return retval;
 224 }
 225
 226 static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
 227                           struct spi_transfer *t)
 228 {
 229         int i;
 230         int remain = t->len;
 231         int cur_len;
 232         unsigned char *data;
 233         long ret;
 234
 235         if (t->len > SPI_SH_MAX_BYTE)
 236                 spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
 237         else
 238                 spi_sh_write(ss, t->len, SPI_SH_CR3);
 239
 240         spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1);
 241         spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
 242
 243         spi_sh_wait_write_buffer_empty(ss);
 244
 245         data = (unsigned char *)t->rx_buf;
 246         while (remain > 0) {
 247                 if (remain >= SPI_SH_FIFO_SIZE) {
 248                         ss->cr1 &= ~SPI_SH_RBF;
 249                         spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
 250                         ret = wait_event_interruptible_timeout(ss->wait,
 251                                                  ss->cr1 & SPI_SH_RBF,
 252                                                  SPI_SH_RECEIVE_TIMEOUT);
 253                         if (ret == 0 &&
 254                             spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
 255                                 printk(KERN_ERR "%s: timeout\n", __func__);
 256                                 return -ETIMEDOUT;
 257                         }
 258                 }
 259
 260                 cur_len = min(SPI_SH_FIFO_SIZE, remain);
 261                 for (i = 0; i < cur_len; i++) {
 262                         if (spi_sh_wait_receive_buffer(ss))
 263                                 break;
 264                         data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
 265                 }
 266
 267                 remain -= cur_len;
 268                 data += cur_len;
 269         }
 270
 271         /* deassert CS when SPI is receiving. */
 272         if (t->len > SPI_SH_MAX_BYTE) {
 273                 clear_fifo(ss);
 274                 spi_sh_write(ss, 1, SPI_SH_CR3);
 275         } else {
 276                 spi_sh_write(ss, 0, SPI_SH_CR3);
 277         }
 278
 279         return 0;
 280 }
 281
 282 static void spi_sh_work(struct work_struct *work)
 283 {
 284         struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws);
 285         struct spi_message *mesg;
 286         struct spi_transfer *t;
 287         unsigned long flags;
 288         int ret;
 289
 290         pr_debug("%s: enter\n", __func__);
 291
 292         spin_lock_irqsave(&ss->lock, flags);
 293         while (!list_empty(&ss->queue)) {
 294                 mesg = list_entry(ss->queue.next, struct spi_message, queue);
 295                 list_del_init(&mesg->queue);
 296
 297                 spin_unlock_irqrestore(&ss->lock, flags);
 298                 list_for_each_entry(t, &mesg->transfers, transfer_list) {
 299                         pr_debug("tx_buf = %p, rx_buf = %p\n",
 300                                         t->tx_buf, t->rx_buf);
 301                         pr_debug("len = %d, delay_usecs = %d\n",
 302                                         t->len, t->delay_usecs);
 303
 304                         if (t->tx_buf) {
 305                                 ret = spi_sh_send(ss, mesg, t);
 306                                 if (ret < 0)
 307                                         goto error;
 308                         }
 309                         if (t->rx_buf) {
 310                                 ret = spi_sh_receive(ss, mesg, t);
 311                                 if (ret < 0)
 312                                         goto error;
 313                         }
 314                         mesg->actual_length += t->len;
 315                 }
 316                 spin_lock_irqsave(&ss->lock, flags);
 317
 318                 mesg->status = 0;
 319                 if (mesg->complete)
 320                         mesg->complete(mesg->context);
 321         }
 322
 323         clear_fifo(ss);
 324         spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
 325         udelay(100);
 326
 327         spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
 328                          SPI_SH_CR1);
 329
 330         clear_fifo(ss);
 331
 332         spin_unlock_irqrestore(&ss->lock, flags);
 333
 334         return;
 335
 336  error:
 337         mesg->status = ret;
 338         if (mesg->complete)
 339                 mesg->complete(mesg->context);
 340
 341         spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
 342                          SPI_SH_CR1);
 343         clear_fifo(ss);
 344
 345 }
 346
 347 static int spi_sh_setup(struct spi_device *spi)
 348 {
 349         struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
 350
 351         pr_debug("%s: enter\n", __func__);
 352
 353         spi_sh_write(ss, 0xfe, SPI_SH_CR1);     /* SPI sycle stop */
 354         spi_sh_write(ss, 0x00, SPI_SH_CR1);     /* CR1 init */
 355         spi_sh_write(ss, 0x00, SPI_SH_CR3);     /* CR3 init */
 356
 357         clear_fifo(ss);
 358
 359         /* 1/8 clock */
 360         spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
 361         udelay(10);
 362
 363         return 0;
 364 }
 365
 366 static int spi_sh_transfer(struct spi_device *spi, struct spi_message *mesg)
 367 {
 368         struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
 369         unsigned long flags;
 370
 371         pr_debug("%s: enter\n", __func__);
 372         pr_debug("\tmode = %02x\n", spi->mode);
 373
 374         spin_lock_irqsave(&ss->lock, flags);
 375
 376         mesg->actual_length = 0;
 377         mesg->status = -EINPROGRESS;
 378
 379         spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
 380
 381         list_add_tail(&mesg->queue, &ss->queue);
 382         schedule_work(&ss->ws);
 383
 384         spin_unlock_irqrestore(&ss->lock, flags);
 385
 386         return 0;
 387 }
 388
 389 static void spi_sh_cleanup(struct spi_device *spi)
 390 {
 391         struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
 392
 393         pr_debug("%s: enter\n", __func__);
 394
 395         spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
 396                          SPI_SH_CR1);
 397 }
 398
 399 static irqreturn_t spi_sh_irq(int irq, void *_ss)
 400 {
 401         struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
 402         unsigned long cr1;
 403
 404         cr1 = spi_sh_read(ss, SPI_SH_CR1);
 405         if (cr1 & SPI_SH_TBE)
 406                 ss->cr1 |= SPI_SH_TBE;
 407         if (cr1 & SPI_SH_TBF)
 408                 ss->cr1 |= SPI_SH_TBF;
 409         if (cr1 & SPI_SH_RBE)
 410                 ss->cr1 |= SPI_SH_RBE;
 411         if (cr1 & SPI_SH_RBF)
 412                 ss->cr1 |= SPI_SH_RBF;
 413
 414         if (ss->cr1) {
 415                 spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
 416                 wake_up(&ss->wait);
 417         }
 418
 419         return IRQ_HANDLED;
 420 }
 421
 422 static int spi_sh_remove(struct platform_device *pdev)
 423 {
 424         struct spi_sh_data *ss = platform_get_drvdata(pdev);
 425
 426         spi_unregister_master(ss->master);
 427         flush_work(&ss->ws);
 428         free_irq(ss->irq, ss);
 429
 430         return 0;
 431 }
 432
 433 static int spi_sh_probe(struct platform_device *pdev)
 434 {
 435         struct resource *res;
 436         struct spi_master *master;
 437         struct spi_sh_data *ss;
 438         int ret, irq;
 439
 440         /* get base addr */
 441         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 442         if (unlikely(res == NULL)) {
 443                 dev_err(&pdev->dev, "invalid resource\n");
 444                 return -EINVAL;
 445         }
 446
 447         irq = platform_get_irq(pdev, 0);
 448         if (irq < 0) {
 449                 dev_err(&pdev->dev, "platform_get_irq error\n");
 450                 return -ENODEV;
 451         }
 452
 453         master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
 454         if (master == NULL) {
 455                 dev_err(&pdev->dev, "spi_alloc_master error.\n");
 456                 return -ENOMEM;
 457         }
 458
 459         ss = spi_master_get_devdata(master);
 460         platform_set_drvdata(pdev, ss);
 461
 462         switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
 463         case IORESOURCE_MEM_8BIT:
 464                 ss->width = 8;
 465                 break;
 466         case IORESOURCE_MEM_32BIT:
 467                 ss->width = 32;
 468                 break;
 469         default:
 470                 dev_err(&pdev->dev, "No support width\n");
 471                 ret = -ENODEV;
 472                 goto error1;
 473         }
 474         ss->irq = irq;
 475         ss->master = master;
 476         ss->addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 477         if (ss->addr == NULL) {
 478                 dev_err(&pdev->dev, "ioremap error.\n");
 479                 ret = -ENOMEM;
 480                 goto error1;
 481         }
 482         INIT_LIST_HEAD(&ss->queue);
 483         spin_lock_init(&ss->lock);
 484         INIT_WORK(&ss->ws, spi_sh_work);
 485         init_waitqueue_head(&ss->wait);
 486
 487         ret = request_irq(irq, spi_sh_irq, 0, "spi_sh", ss);
 488         if (ret < 0) {
 489                 dev_err(&pdev->dev, "request_irq error\n");
 490                 goto error1;
 491         }
 492
 493         master->num_chipselect = 2;
 494         master->bus_num = pdev->id;
 495         master->setup = spi_sh_setup;
 496         master->transfer = spi_sh_transfer;
 497         master->cleanup = spi_sh_cleanup;
 498
 499         ret = spi_register_master(master);
 500         if (ret < 0) {
 501                 printk(KERN_ERR "spi_register_master error.\n");
 502                 goto error3;
 503         }
 504
 505         return 0;
 506
 507  error3:
 508         free_irq(irq, ss);
 509  error1:
 510         spi_master_put(master);
 511
 512         return ret;
 513 }
 514
 515 static struct platform_driver spi_sh_driver = {
 516         .probe = spi_sh_probe,
 517         .remove = spi_sh_remove,
 518         .driver = {
 519                 .name = "sh_spi",
 520         },
 521 };
 522 module_platform_driver(spi_sh_driver);
 523
 524 MODULE_DESCRIPTION("SH SPI bus driver");
 525 MODULE_LICENSE("GPL");
 526 MODULE_AUTHOR("Yoshihiro Shimoda");
 527 MODULE_ALIAS("platform:sh_spi");