drivers/spmi/spmi-pmic-arb.c

   1 /*
   2  * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13 #include <linux/bitmap.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/irqchip/chained_irq.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/irq.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/spmi.h>
  27
  28 /* PMIC Arbiter configuration registers */
  29 #define PMIC_ARB_VERSION                0x0000
  30 #define PMIC_ARB_VERSION_V2_MIN         0x20010000
  31 #define PMIC_ARB_INT_EN                 0x0004
  32
  33 /* PMIC Arbiter channel registers offsets */
  34 #define PMIC_ARB_CMD                    0x00
  35 #define PMIC_ARB_CONFIG                 0x04
  36 #define PMIC_ARB_STATUS                 0x08
  37 #define PMIC_ARB_WDATA0                 0x10
  38 #define PMIC_ARB_WDATA1                 0x14
  39 #define PMIC_ARB_RDATA0                 0x18
  40 #define PMIC_ARB_RDATA1                 0x1C
  41 #define PMIC_ARB_REG_CHNL(N)            (0x800 + 0x4 * (N))
  42
  43 /* Mapping Table */
  44 #define SPMI_MAPPING_TABLE_REG(N)       (0x0B00 + (4 * (N)))
  45 #define SPMI_MAPPING_BIT_INDEX(X)       (((X) >> 18) & 0xF)
  46 #define SPMI_MAPPING_BIT_IS_0_FLAG(X)   (((X) >> 17) & 0x1)
  47 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
  48 #define SPMI_MAPPING_BIT_IS_1_FLAG(X)   (((X) >> 8) & 0x1)
  49 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
  50
  51 #define SPMI_MAPPING_TABLE_TREE_DEPTH   16      /* Maximum of 16-bits */
  52 #define PMIC_ARB_MAX_PPID               BIT(12) /* PPID is 12bit */
  53 #define PMIC_ARB_CHAN_VALID             BIT(15)
  54
  55 /* Ownership Table */
  56 #define SPMI_OWNERSHIP_TABLE_REG(N)     (0x0700 + (4 * (N)))
  57 #define SPMI_OWNERSHIP_PERIPH2OWNER(X)  ((X) & 0x7)
  58
  59 /* Channel Status fields */
  60 enum pmic_arb_chnl_status {
  61         PMIC_ARB_STATUS_DONE    = (1 << 0),
  62         PMIC_ARB_STATUS_FAILURE = (1 << 1),
  63         PMIC_ARB_STATUS_DENIED  = (1 << 2),
  64         PMIC_ARB_STATUS_DROPPED = (1 << 3),
  65 };
  66
  67 /* Command register fields */
  68 #define PMIC_ARB_CMD_MAX_BYTE_COUNT     8
  69
  70 /* Command Opcodes */
  71 enum pmic_arb_cmd_op_code {
  72         PMIC_ARB_OP_EXT_WRITEL = 0,
  73         PMIC_ARB_OP_EXT_READL = 1,
  74         PMIC_ARB_OP_EXT_WRITE = 2,
  75         PMIC_ARB_OP_RESET = 3,
  76         PMIC_ARB_OP_SLEEP = 4,
  77         PMIC_ARB_OP_SHUTDOWN = 5,
  78         PMIC_ARB_OP_WAKEUP = 6,
  79         PMIC_ARB_OP_AUTHENTICATE = 7,
  80         PMIC_ARB_OP_MSTR_READ = 8,
  81         PMIC_ARB_OP_MSTR_WRITE = 9,
  82         PMIC_ARB_OP_EXT_READ = 13,
  83         PMIC_ARB_OP_WRITE = 14,
  84         PMIC_ARB_OP_READ = 15,
  85         PMIC_ARB_OP_ZERO_WRITE = 16,
  86 };
  87
  88 /* Maximum number of support PMIC peripherals */
  89 #define PMIC_ARB_MAX_PERIPHS            512
  90 #define PMIC_ARB_TIMEOUT_US             100
  91 #define PMIC_ARB_MAX_TRANS_BYTES        (8)
  92
  93 #define PMIC_ARB_APID_MASK              0xFF
  94 #define PMIC_ARB_PPID_MASK              0xFFF
  95
  96 /* interrupt enable bit */
  97 #define SPMI_PIC_ACC_ENABLE_BIT         BIT(0)
  98
  99 struct pmic_arb_ver_ops;
 100
 101 /**
 102  * spmi_pmic_arb_dev - SPMI PMIC Arbiter object
 103  *
 104  * @rd_base:            on v1 "core", on v2 "observer" register base off DT.
 105  * @wr_base:            on v1 "core", on v2 "chnls"    register base off DT.
 106  * @intr:               address of the SPMI interrupt control registers.
 107  * @cnfg:               address of the PMIC Arbiter configuration registers.
 108  * @lock:               lock to synchronize accesses.
 109  * @channel:            execution environment channel to use for accesses.
 110  * @irq:                PMIC ARB interrupt.
 111  * @ee:                 the current Execution Environment
 112  * @min_apid:           minimum APID (used for bounding IRQ search)
 113  * @max_apid:           maximum APID
 114  * @mapping_table:      in-memory copy of PPID -> APID mapping table.
 115  * @domain:             irq domain object for PMIC IRQ domain
 116  * @spmic:              SPMI controller object
 117  * @apid_to_ppid:       in-memory copy of APID -> PPID mapping table.
 118  * @ver_ops:            version dependent operations.
 119  * @ppid_to_chan        in-memory copy of PPID -> channel (APID) mapping table.
 120  *                      v2 only.
 121  */
 122 struct spmi_pmic_arb_dev {
 123         void __iomem            *rd_base;
 124         void __iomem            *wr_base;
 125         void __iomem            *intr;
 126         void __iomem            *cnfg;
 127         void __iomem            *core;
 128         resource_size_t         core_size;
 129         raw_spinlock_t          lock;
 130         u8                      channel;
 131         int                     irq;
 132         u8                      ee;
 133         u16                     min_apid;
 134         u16                     max_apid;
 135         u32                     *mapping_table;
 136         DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
 137         struct irq_domain       *domain;
 138         struct spmi_controller  *spmic;
 139         u16                     *apid_to_ppid;
 140         const struct pmic_arb_ver_ops *ver_ops;
 141         u16                     *ppid_to_chan;
 142         u16                     last_channel;
 143 };
 144
 145 /**
 146  * pmic_arb_ver: version dependent functionality.
 147  *
 148  * @non_data_cmd:       on v1 issues an spmi non-data command.
 149  *                      on v2 no HW support, returns -EOPNOTSUPP.
 150  * @offset:             on v1 offset of per-ee channel.
 151  *                      on v2 offset of per-ee and per-ppid channel.
 152  * @fmt_cmd:            formats a GENI/SPMI command.
 153  * @owner_acc_status:   on v1 offset of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
 154  *                      on v2 offset of SPMI_PIC_OWNERm_ACC_STATUSn.
 155  * @acc_enable:         on v1 offset of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
 156  *                      on v2 offset of SPMI_PIC_ACC_ENABLEn.
 157  * @irq_status:         on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
 158  *                      on v2 offset of SPMI_PIC_IRQ_STATUSn.
 159  * @irq_clear:          on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
 160  *                      on v2 offset of SPMI_PIC_IRQ_CLEARn.
 161  */
 162 struct pmic_arb_ver_ops {
 163         /* spmi commands (read_cmd, write_cmd, cmd) functionality */
 164         int (*offset)(struct spmi_pmic_arb_dev *dev, u8 sid, u16 addr,
 165                       u32 *offset);
 166         u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
 167         int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
 168         /* Interrupts controller functionality (offset of PIC registers) */
 169         u32 (*owner_acc_status)(u8 m, u8 n);
 170         u32 (*acc_enable)(u8 n);
 171         u32 (*irq_status)(u8 n);
 172         u32 (*irq_clear)(u8 n);
 173 };
 174
 175 static inline void pmic_arb_base_write(struct spmi_pmic_arb_dev *dev,
 176                                        u32 offset, u32 val)
 177 {
 178         writel_relaxed(val, dev->wr_base + offset);
 179 }
 180
 181 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb_dev *dev,
 182                                        u32 offset, u32 val)
 183 {
 184         writel_relaxed(val, dev->rd_base + offset);
 185 }
 186
 187 /**
 188  * pa_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
 189  * @bc:         byte count -1. range: 0..3
 190  * @reg:        register's address
 191  * @buf:        output parameter, length must be bc + 1
 192  */
 193 static void pa_read_data(struct spmi_pmic_arb_dev *dev, u8 *buf, u32 reg, u8 bc)
 194 {
 195         u32 data = __raw_readl(dev->rd_base + reg);
 196         memcpy(buf, &data, (bc & 3) + 1);
 197 }
 198
 199 /**
 200  * pa_write_data: write 1..4 bytes from buf to pmic-arb's register
 201  * @bc:         byte-count -1. range: 0..3.
 202  * @reg:        register's address.
 203  * @buf:        buffer to write. length must be bc + 1.
 204  */
 205 static void
 206 pa_write_data(struct spmi_pmic_arb_dev *dev, const u8 *buf, u32 reg, u8 bc)
 207 {
 208         u32 data = 0;
 209         memcpy(&data, buf, (bc & 3) + 1);
 210         __raw_writel(data, dev->wr_base + reg);
 211 }
 212
 213 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
 214                                   void __iomem *base, u8 sid, u16 addr)
 215 {
 216         struct spmi_pmic_arb_dev *dev = spmi_controller_get_drvdata(ctrl);
 217         u32 status = 0;
 218         u32 timeout = PMIC_ARB_TIMEOUT_US;
 219         u32 offset;
 220         int rc;
 221
 222         rc = dev->ver_ops->offset(dev, sid, addr, &offset);
 223         if (rc)
 224                 return rc;
 225
 226         offset += PMIC_ARB_STATUS;
 227
 228         while (timeout--) {
 229                 status = readl_relaxed(base + offset);
 230
 231                 if (status & PMIC_ARB_STATUS_DONE) {
 232                         if (status & PMIC_ARB_STATUS_DENIED) {
 233                                 dev_err(&ctrl->dev,
 234                                         "%s: transaction denied (0x%x)\n",
 235                                         __func__, status);
 236                                 return -EPERM;
 237                         }
 238
 239                         if (status & PMIC_ARB_STATUS_FAILURE) {
 240                                 dev_err(&ctrl->dev,
 241                                         "%s: transaction failed (0x%x)\n",
 242                                         __func__, status);
 243                                 return -EIO;
 244                         }
 245
 246                         if (status & PMIC_ARB_STATUS_DROPPED) {
 247                                 dev_err(&ctrl->dev,
 248                                         "%s: transaction dropped (0x%x)\n",
 249                                         __func__, status);
 250                                 return -EIO;
 251                         }
 252
 253                         return 0;
 254                 }
 255                 udelay(1);
 256         }
 257
 258         dev_err(&ctrl->dev,
 259                 "%s: timeout, status 0x%x\n",
 260                 __func__, status);
 261         return -ETIMEDOUT;
 262 }
 263
 264 static int
 265 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
 266 {
 267         struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl);
 268         unsigned long flags;
 269         u32 cmd;
 270         int rc;
 271         u32 offset;
 272
 273         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, &offset);
 274         if (rc)
 275                 return rc;
 276
 277         cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
 278
 279         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 280         pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 281         rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0);
 282         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 283
 284         return rc;
 285 }
 286
 287 static int
 288 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
 289 {
 290         return -EOPNOTSUPP;
 291 }
 292
 293 /* Non-data command */
 294 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
 295 {
 296         struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl);
 297
 298         dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
 299
 300         /* Check for valid non-data command */
 301         if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
 302                 return -EINVAL;
 303
 304         return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
 305 }
 306
 307 static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
 308                              u16 addr, u8 *buf, size_t len)
 309 {
 310         struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl);
 311         unsigned long flags;
 312         u8 bc = len - 1;
 313         u32 cmd;
 314         int rc;
 315         u32 offset;
 316
 317         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, &offset);
 318         if (rc)
 319                 return rc;
 320
 321         if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
 322                 dev_err(&ctrl->dev,
 323                         "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
 324                         PMIC_ARB_MAX_TRANS_BYTES, len);
 325                 return  -EINVAL;
 326         }
 327
 328         /* Check the opcode */
 329         if (opc >= 0x60 && opc <= 0x7F)
 330                 opc = PMIC_ARB_OP_READ;
 331         else if (opc >= 0x20 && opc <= 0x2F)
 332                 opc = PMIC_ARB_OP_EXT_READ;
 333         else if (opc >= 0x38 && opc <= 0x3F)
 334                 opc = PMIC_ARB_OP_EXT_READL;
 335         else
 336                 return -EINVAL;
 337
 338         cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
 339
 340         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 341         pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 342         rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr);
 343         if (rc)
 344                 goto done;
 345
 346         pa_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
 347                      min_t(u8, bc, 3));
 348
 349         if (bc > 3)
 350                 pa_read_data(pmic_arb, buf + 4,
 351                                 offset + PMIC_ARB_RDATA1, bc - 4);
 352
 353 done:
 354         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 355         return rc;
 356 }
 357
 358 static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
 359                               u16 addr, const u8 *buf, size_t len)
 360 {
 361         struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl);
 362         unsigned long flags;
 363         u8 bc = len - 1;
 364         u32 cmd;
 365         int rc;
 366         u32 offset;
 367
 368         rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, &offset);
 369         if (rc)
 370                 return rc;
 371
 372         if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
 373                 dev_err(&ctrl->dev,
 374                         "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
 375                         PMIC_ARB_MAX_TRANS_BYTES, len);
 376                 return  -EINVAL;
 377         }
 378
 379         /* Check the opcode */
 380         if (opc >= 0x40 && opc <= 0x5F)
 381                 opc = PMIC_ARB_OP_WRITE;
 382         else if (opc >= 0x00 && opc <= 0x0F)
 383                 opc = PMIC_ARB_OP_EXT_WRITE;
 384         else if (opc >= 0x30 && opc <= 0x37)
 385                 opc = PMIC_ARB_OP_EXT_WRITEL;
 386         else if (opc >= 0x80)
 387                 opc = PMIC_ARB_OP_ZERO_WRITE;
 388         else
 389                 return -EINVAL;
 390
 391         cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
 392
 393         /* Write data to FIFOs */
 394         raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 395         pa_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
 396                       min_t(u8, bc, 3));
 397         if (bc > 3)
 398                 pa_write_data(pmic_arb, buf + 4,
 399                                 offset + PMIC_ARB_WDATA1, bc - 4);
 400
 401         /* Start the transaction */
 402         pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 403         rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr);
 404         raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 405
 406         return rc;
 407 }
 408
 409 enum qpnpint_regs {
 410         QPNPINT_REG_RT_STS              = 0x10,
 411         QPNPINT_REG_SET_TYPE            = 0x11,
 412         QPNPINT_REG_POLARITY_HIGH       = 0x12,
 413         QPNPINT_REG_POLARITY_LOW        = 0x13,
 414         QPNPINT_REG_LATCHED_CLR         = 0x14,
 415         QPNPINT_REG_EN_SET              = 0x15,
 416         QPNPINT_REG_EN_CLR              = 0x16,
 417         QPNPINT_REG_LATCHED_STS         = 0x18,
 418 };
 419
 420 struct spmi_pmic_arb_qpnpint_type {
 421         u8 type; /* 1 -> edge */
 422         u8 polarity_high;
 423         u8 polarity_low;
 424 } __packed;
 425
 426 /* Simplified accessor functions for irqchip callbacks */
 427 static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
 428                                size_t len)
 429 {
 430         struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 431         u8 sid = d->hwirq >> 24;
 432         u8 per = d->hwirq >> 16;
 433
 434         if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid,
 435                                (per << 8) + reg, buf, len))
 436                 dev_err_ratelimited(&pa->spmic->dev,
 437                                 "failed irqchip transaction on %x\n",
 438                                     d->irq);
 439 }
 440
 441 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
 442 {
 443         struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 444         u8 sid = d->hwirq >> 24;
 445         u8 per = d->hwirq >> 16;
 446
 447         if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid,
 448                               (per << 8) + reg, buf, len))
 449                 dev_err_ratelimited(&pa->spmic->dev,
 450                                 "failed irqchip transaction on %x\n",
 451                                     d->irq);
 452 }
 453
 454 static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid)
 455 {
 456         unsigned int irq;
 457         u32 status;
 458         int id;
 459
 460         status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid));
 461         while (status) {
 462                 id = ffs(status) - 1;
 463                 status &= ~(1 << id);
 464                 irq = irq_find_mapping(pa->domain,
 465                                        pa->apid_to_ppid[apid] << 16
 466                                      | id << 8
 467                                      | apid);
 468                 generic_handle_irq(irq);
 469         }
 470 }
 471
 472 static void pmic_arb_chained_irq(struct irq_desc *desc)
 473 {
 474         struct spmi_pmic_arb_dev *pa = irq_desc_get_handler_data(desc);
 475         struct irq_chip *chip = irq_desc_get_chip(desc);
 476         void __iomem *intr = pa->intr;
 477         int first = pa->min_apid >> 5;
 478         int last = pa->max_apid >> 5;
 479         u32 status;
 480         int i, id;
 481
 482         chained_irq_enter(chip, desc);
 483
 484         for (i = first; i <= last; ++i) {
 485                 status = readl_relaxed(intr +
 486                                       pa->ver_ops->owner_acc_status(pa->ee, i));
 487                 while (status) {
 488                         id = ffs(status) - 1;
 489                         status &= ~(1 << id);
 490                         periph_interrupt(pa, id + i * 32);
 491                 }
 492         }
 493
 494         chained_irq_exit(chip, desc);
 495 }
 496
 497 static void qpnpint_irq_ack(struct irq_data *d)
 498 {
 499         struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 500         u8 irq  = d->hwirq >> 8;
 501         u8 apid = d->hwirq;
 502         unsigned long flags;
 503         u8 data;
 504
 505         raw_spin_lock_irqsave(&pa->lock, flags);
 506         writel_relaxed(1 << irq, pa->intr + pa->ver_ops->irq_clear(apid));
 507         raw_spin_unlock_irqrestore(&pa->lock, flags);
 508
 509         data = 1 << irq;
 510         qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
 511 }
 512
 513 static void qpnpint_irq_mask(struct irq_data *d)
 514 {
 515         struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 516         u8 irq  = d->hwirq >> 8;
 517         u8 apid = d->hwirq;
 518         unsigned long flags;
 519         u32 status;
 520         u8 data;
 521
 522         raw_spin_lock_irqsave(&pa->lock, flags);
 523         status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid));
 524         if (status & SPMI_PIC_ACC_ENABLE_BIT) {
 525                 status = status & ~SPMI_PIC_ACC_ENABLE_BIT;
 526                 writel_relaxed(status, pa->intr +
 527                                pa->ver_ops->acc_enable(apid));
 528         }
 529         raw_spin_unlock_irqrestore(&pa->lock, flags);
 530
 531         data = 1 << irq;
 532         qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
 533 }
 534
 535 static void qpnpint_irq_unmask(struct irq_data *d)
 536 {
 537         struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d);
 538         u8 irq  = d->hwirq >> 8;
 539         u8 apid = d->hwirq;
 540         unsigned long flags;
 541         u32 status;
 542         u8 data;
 543
 544         raw_spin_lock_irqsave(&pa->lock, flags);
 545         status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid));
 546         if (!(status & SPMI_PIC_ACC_ENABLE_BIT)) {
 547                 writel_relaxed(status | SPMI_PIC_ACC_ENABLE_BIT,
 548                                 pa->intr + pa->ver_ops->acc_enable(apid));
 549         }
 550         raw_spin_unlock_irqrestore(&pa->lock, flags);
 551
 552         data = 1 << irq;
 553         qpnpint_spmi_write(d, QPNPINT_REG_EN_SET, &data, 1);
 554 }
 555
 556 static void qpnpint_irq_enable(struct irq_data *d)
 557 {
 558         u8 irq  = d->hwirq >> 8;
 559         u8 data;
 560
 561         qpnpint_irq_unmask(d);
 562
 563         data = 1 << irq;
 564         qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
 565 }
 566
 567 static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
 568 {
 569         struct spmi_pmic_arb_qpnpint_type type;
 570         u8 irq = d->hwirq >> 8;
 571
 572         qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
 573
 574         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
 575                 type.type |= 1 << irq;
 576                 if (flow_type & IRQF_TRIGGER_RISING)
 577                         type.polarity_high |= 1 << irq;
 578                 if (flow_type & IRQF_TRIGGER_FALLING)
 579                         type.polarity_low  |= 1 << irq;
 580         } else {
 581                 if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
 582                     (flow_type & (IRQF_TRIGGER_LOW)))
 583                         return -EINVAL;
 584
 585                 type.type &= ~(1 << irq); /* level trig */
 586                 if (flow_type & IRQF_TRIGGER_HIGH)
 587                         type.polarity_high |= 1 << irq;
 588                 else
 589                         type.polarity_low  |= 1 << irq;
 590         }
 591
 592         qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
 593         return 0;
 594 }
 595
 596 static int qpnpint_get_irqchip_state(struct irq_data *d,
 597                                      enum irqchip_irq_state which,
 598                                      bool *state)
 599 {
 600         u8 irq = d->hwirq >> 8;
 601         u8 status = 0;
 602
 603         if (which != IRQCHIP_STATE_LINE_LEVEL)
 604                 return -EINVAL;
 605
 606         qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
 607         *state = !!(status & BIT(irq));
 608
 609         return 0;
 610 }
 611
 612 static struct irq_chip pmic_arb_irqchip = {
 613         .name           = "pmic_arb",
 614         .irq_enable     = qpnpint_irq_enable,
 615         .irq_ack        = qpnpint_irq_ack,
 616         .irq_mask       = qpnpint_irq_mask,
 617         .irq_unmask     = qpnpint_irq_unmask,
 618         .irq_set_type   = qpnpint_irq_set_type,
 619         .irq_get_irqchip_state  = qpnpint_get_irqchip_state,
 620         .flags          = IRQCHIP_MASK_ON_SUSPEND
 621                         | IRQCHIP_SKIP_SET_WAKE,
 622 };
 623
 624 struct spmi_pmic_arb_irq_spec {
 625         unsigned slave:4;
 626         unsigned per:8;
 627         unsigned irq:3;
 628 };
 629
 630 static int search_mapping_table(struct spmi_pmic_arb_dev *pa,
 631                                 struct spmi_pmic_arb_irq_spec *spec,
 632                                 u8 *apid)
 633 {
 634         u16 ppid = spec->slave << 8 | spec->per;
 635         u32 *mapping_table = pa->mapping_table;
 636         int index = 0, i;
 637         u32 data;
 638
 639         for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
 640                 if (!test_and_set_bit(index, pa->mapping_table_valid))
 641                         mapping_table[index] = readl_relaxed(pa->cnfg +
 642                                                 SPMI_MAPPING_TABLE_REG(index));
 643
 644                 data = mapping_table[index];
 645
 646                 if (ppid & (1 << SPMI_MAPPING_BIT_INDEX(data))) {
 647                         if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
 648                                 index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 649                         } else {
 650                                 *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 651                                 return 0;
 652                         }
 653                 } else {
 654                         if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
 655                                 index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 656                         } else {
 657                                 *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 658                                 return 0;
 659                         }
 660                 }
 661         }
 662
 663         return -ENODEV;
 664 }
 665
 666 static int qpnpint_irq_domain_dt_translate(struct irq_domain *d,
 667                                            struct device_node *controller,
 668                                            const u32 *intspec,
 669                                            unsigned int intsize,
 670                                            unsigned long *out_hwirq,
 671                                            unsigned int *out_type)
 672 {
 673         struct spmi_pmic_arb_dev *pa = d->host_data;
 674         struct spmi_pmic_arb_irq_spec spec;
 675         int err;
 676         u8 apid;
 677
 678         dev_dbg(&pa->spmic->dev,
 679                 "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
 680                 intspec[0], intspec[1], intspec[2]);
 681
 682         if (irq_domain_get_of_node(d) != controller)
 683                 return -EINVAL;
 684         if (intsize != 4)
 685                 return -EINVAL;
 686         if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
 687                 return -EINVAL;
 688
 689         spec.slave = intspec[0];
 690         spec.per   = intspec[1];
 691         spec.irq   = intspec[2];
 692
 693         err = search_mapping_table(pa, &spec, &apid);
 694         if (err)
 695                 return err;
 696
 697         pa->apid_to_ppid[apid] = spec.slave << 8 | spec.per;
 698
 699         /* Keep track of {max,min}_apid for bounding search during interrupt */
 700         if (apid > pa->max_apid)
 701                 pa->max_apid = apid;
 702         if (apid < pa->min_apid)
 703                 pa->min_apid = apid;
 704
 705         *out_hwirq = spec.slave << 24
 706                    | spec.per   << 16
 707                    | spec.irq   << 8
 708                    | apid;
 709         *out_type  = intspec[3] & IRQ_TYPE_SENSE_MASK;
 710
 711         dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
 712
 713         return 0;
 714 }
 715
 716 static int qpnpint_irq_domain_map(struct irq_domain *d,
 717                                   unsigned int virq,
 718                                   irq_hw_number_t hwirq)
 719 {
 720         struct spmi_pmic_arb_dev *pa = d->host_data;
 721
 722         dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq);
 723
 724         irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq);
 725         irq_set_chip_data(virq, d->host_data);
 726         irq_set_noprobe(virq);
 727         return 0;
 728 }
 729
 730 /* v1 offset per ee */
 731 static int
 732 pmic_arb_offset_v1(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr, u32 *offset)
 733 {
 734         *offset = 0x800 + 0x80 * pa->channel;
 735         return 0;
 736 }
 737
 738 static u16 pmic_arb_find_chan(struct spmi_pmic_arb_dev *pa, u16 ppid)
 739 {
 740         u32 regval, offset;
 741         u16 chan;
 742         u16 id;
 743
 744         /*
 745          * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid.
 746          * ppid_to_chan is an in-memory invert of that table.
 747          */
 748         for (chan = pa->last_channel; ; chan++) {
 749                 offset = PMIC_ARB_REG_CHNL(chan);
 750                 if (offset >= pa->core_size)
 751                         break;
 752
 753                 regval = readl_relaxed(pa->core + offset);
 754                 if (!regval)
 755                         continue;
 756
 757                 id = (regval >> 8) & PMIC_ARB_PPID_MASK;
 758                 pa->ppid_to_chan[id] = chan | PMIC_ARB_CHAN_VALID;
 759                 if (id == ppid) {
 760                         chan |= PMIC_ARB_CHAN_VALID;
 761                         break;
 762                 }
 763         }
 764         pa->last_channel = chan & ~PMIC_ARB_CHAN_VALID;
 765
 766         return chan;
 767 }
 768
 769
 770 /* v2 offset per ppid (chan) and per ee */
 771 static int
 772 pmic_arb_offset_v2(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr, u32 *offset)
 773 {
 774         u16 ppid = (sid << 8) | (addr >> 8);
 775         u16 chan;
 776
 777         chan = pa->ppid_to_chan[ppid];
 778         if (!(chan & PMIC_ARB_CHAN_VALID))
 779                 chan = pmic_arb_find_chan(pa, ppid);
 780         if (!(chan & PMIC_ARB_CHAN_VALID))
 781                 return -ENODEV;
 782         chan &= ~PMIC_ARB_CHAN_VALID;
 783
 784         *offset = 0x1000 * pa->ee + 0x8000 * chan;
 785         return 0;
 786 }
 787
 788 static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
 789 {
 790         return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
 791 }
 792
 793 static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
 794 {
 795         return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
 796 }
 797
 798 static u32 pmic_arb_owner_acc_status_v1(u8 m, u8 n)
 799 {
 800         return 0x20 * m + 0x4 * n;
 801 }
 802
 803 static u32 pmic_arb_owner_acc_status_v2(u8 m, u8 n)
 804 {
 805         return 0x100000 + 0x1000 * m + 0x4 * n;
 806 }
 807
 808 static u32 pmic_arb_acc_enable_v1(u8 n)
 809 {
 810         return 0x200 + 0x4 * n;
 811 }
 812
 813 static u32 pmic_arb_acc_enable_v2(u8 n)
 814 {
 815         return 0x1000 * n;
 816 }
 817
 818 static u32 pmic_arb_irq_status_v1(u8 n)
 819 {
 820         return 0x600 + 0x4 * n;
 821 }
 822
 823 static u32 pmic_arb_irq_status_v2(u8 n)
 824 {
 825         return 0x4 + 0x1000 * n;
 826 }
 827
 828 static u32 pmic_arb_irq_clear_v1(u8 n)
 829 {
 830         return 0xA00 + 0x4 * n;
 831 }
 832
 833 static u32 pmic_arb_irq_clear_v2(u8 n)
 834 {
 835         return 0x8 + 0x1000 * n;
 836 }
 837
 838 static const struct pmic_arb_ver_ops pmic_arb_v1 = {
 839         .non_data_cmd           = pmic_arb_non_data_cmd_v1,
 840         .offset                 = pmic_arb_offset_v1,
 841         .fmt_cmd                = pmic_arb_fmt_cmd_v1,
 842         .owner_acc_status       = pmic_arb_owner_acc_status_v1,
 843         .acc_enable             = pmic_arb_acc_enable_v1,
 844         .irq_status             = pmic_arb_irq_status_v1,
 845         .irq_clear              = pmic_arb_irq_clear_v1,
 846 };
 847
 848 static const struct pmic_arb_ver_ops pmic_arb_v2 = {
 849         .non_data_cmd           = pmic_arb_non_data_cmd_v2,
 850         .offset                 = pmic_arb_offset_v2,
 851         .fmt_cmd                = pmic_arb_fmt_cmd_v2,
 852         .owner_acc_status       = pmic_arb_owner_acc_status_v2,
 853         .acc_enable             = pmic_arb_acc_enable_v2,
 854         .irq_status             = pmic_arb_irq_status_v2,
 855         .irq_clear              = pmic_arb_irq_clear_v2,
 856 };
 857
 858 static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
 859         .map    = qpnpint_irq_domain_map,
 860         .xlate  = qpnpint_irq_domain_dt_translate,
 861 };
 862
 863 static int spmi_pmic_arb_probe(struct platform_device *pdev)
 864 {
 865         struct spmi_pmic_arb_dev *pa;
 866         struct spmi_controller *ctrl;
 867         struct resource *res;
 868         void __iomem *core;
 869         u32 channel, ee, hw_ver;
 870         int err;
 871         bool is_v1;
 872
 873         ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa));
 874         if (!ctrl)
 875                 return -ENOMEM;
 876
 877         pa = spmi_controller_get_drvdata(ctrl);
 878         pa->spmic = ctrl;
 879
 880         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
 881         pa->core_size = resource_size(res);
 882         core = devm_ioremap_resource(&ctrl->dev, res);
 883         if (IS_ERR(core)) {
 884                 err = PTR_ERR(core);
 885                 goto err_put_ctrl;
 886         }
 887
 888         hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
 889         is_v1  = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
 890
 891         dev_info(&ctrl->dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2),
 892                 hw_ver);
 893
 894         if (is_v1) {
 895                 pa->ver_ops = &pmic_arb_v1;
 896                 pa->wr_base = core;
 897                 pa->rd_base = core;
 898         } else {
 899                 pa->core = core;
 900                 pa->ver_ops = &pmic_arb_v2;
 901
 902                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 903                                                    "obsrvr");
 904                 pa->rd_base = devm_ioremap_resource(&ctrl->dev, res);
 905                 if (IS_ERR(pa->rd_base)) {
 906                         err = PTR_ERR(pa->rd_base);
 907                         goto err_put_ctrl;
 908                 }
 909
 910                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 911                                                    "chnls");
 912                 pa->wr_base = devm_ioremap_resource(&ctrl->dev, res);
 913                 if (IS_ERR(pa->wr_base)) {
 914                         err = PTR_ERR(pa->wr_base);
 915                         goto err_put_ctrl;
 916                 }
 917
 918                 pa->ppid_to_chan = devm_kcalloc(&ctrl->dev,
 919                                                 PMIC_ARB_MAX_PPID,
 920                                                 sizeof(*pa->ppid_to_chan),
 921                                                 GFP_KERNEL);
 922                 if (!pa->ppid_to_chan) {
 923                         err = -ENOMEM;
 924                         goto err_put_ctrl;
 925                 }
 926         }
 927
 928         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
 929         pa->intr = devm_ioremap_resource(&ctrl->dev, res);
 930         if (IS_ERR(pa->intr)) {
 931                 err = PTR_ERR(pa->intr);
 932                 goto err_put_ctrl;
 933         }
 934
 935         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
 936         pa->cnfg = devm_ioremap_resource(&ctrl->dev, res);
 937         if (IS_ERR(pa->cnfg)) {
 938                 err = PTR_ERR(pa->cnfg);
 939                 goto err_put_ctrl;
 940         }
 941
 942         pa->irq = platform_get_irq_byname(pdev, "periph_irq");
 943         if (pa->irq < 0) {
 944                 err = pa->irq;
 945                 goto err_put_ctrl;
 946         }
 947
 948         err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
 949         if (err) {
 950                 dev_err(&pdev->dev, "channel unspecified.\n");
 951                 goto err_put_ctrl;
 952         }
 953
 954         if (channel > 5) {
 955                 dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
 956                         channel);
 957                 goto err_put_ctrl;
 958         }
 959
 960         pa->channel = channel;
 961
 962         err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
 963         if (err) {
 964                 dev_err(&pdev->dev, "EE unspecified.\n");
 965                 goto err_put_ctrl;
 966         }
 967
 968         if (ee > 5) {
 969                 dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
 970                 err = -EINVAL;
 971                 goto err_put_ctrl;
 972         }
 973
 974         pa->ee = ee;
 975
 976         pa->apid_to_ppid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
 977                                             sizeof(*pa->apid_to_ppid),
 978                                             GFP_KERNEL);
 979         if (!pa->apid_to_ppid) {
 980                 err = -ENOMEM;
 981                 goto err_put_ctrl;
 982         }
 983
 984         pa->mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS - 1,
 985                                         sizeof(*pa->mapping_table), GFP_KERNEL);
 986         if (!pa->mapping_table) {
 987                 err = -ENOMEM;
 988                 goto err_put_ctrl;
 989         }
 990
 991         /* Initialize max_apid/min_apid to the opposite bounds, during
 992          * the irq domain translation, we are sure to update these */
 993         pa->max_apid = 0;
 994         pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
 995
 996         platform_set_drvdata(pdev, ctrl);
 997         raw_spin_lock_init(&pa->lock);
 998
 999         ctrl->cmd = pmic_arb_cmd;
1000         ctrl->read_cmd = pmic_arb_read_cmd;
1001         ctrl->write_cmd = pmic_arb_write_cmd;
1002
1003         dev_dbg(&pdev->dev, "adding irq domain\n");
1004         pa->domain = irq_domain_add_tree(pdev->dev.of_node,
1005                                          &pmic_arb_irq_domain_ops, pa);
1006         if (!pa->domain) {
1007                 dev_err(&pdev->dev, "unable to create irq_domain\n");
1008                 err = -ENOMEM;
1009                 goto err_put_ctrl;
1010         }
1011
1012         irq_set_chained_handler_and_data(pa->irq, pmic_arb_chained_irq, pa);
1013
1014         err = spmi_controller_add(ctrl);
1015         if (err)
1016                 goto err_domain_remove;
1017
1018         return 0;
1019
1020 err_domain_remove:
1021         irq_set_chained_handler_and_data(pa->irq, NULL, NULL);
1022         irq_domain_remove(pa->domain);
1023 err_put_ctrl:
1024         spmi_controller_put(ctrl);
1025         return err;
1026 }
1027
1028 static int spmi_pmic_arb_remove(struct platform_device *pdev)
1029 {
1030         struct spmi_controller *ctrl = platform_get_drvdata(pdev);
1031         struct spmi_pmic_arb_dev *pa = spmi_controller_get_drvdata(ctrl);
1032         spmi_controller_remove(ctrl);
1033         irq_set_chained_handler_and_data(pa->irq, NULL, NULL);
1034         irq_domain_remove(pa->domain);
1035         spmi_controller_put(ctrl);
1036         return 0;
1037 }
1038
1039 static const struct of_device_id spmi_pmic_arb_match_table[] = {
1040         { .compatible = "qcom,spmi-pmic-arb", },
1041         {},
1042 };
1043 MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
1044
1045 static struct platform_driver spmi_pmic_arb_driver = {
1046         .probe          = spmi_pmic_arb_probe,
1047         .remove         = spmi_pmic_arb_remove,
1048         .driver         = {
1049                 .name   = "spmi_pmic_arb",
1050                 .of_match_table = spmi_pmic_arb_match_table,
1051         },
1052 };
1053 module_platform_driver(spmi_pmic_arb_driver);
1054
1055 MODULE_LICENSE("GPL v2");
1056 MODULE_ALIAS("platform:spmi_pmic_arb");