drivers/staging/cxt1e1/comet.c

   1 /* Copyright (C) 2003-2005  SBE, Inc.
   2  *
   3  *   This program is free software; you can redistribute it and/or modify
   4  *   it under the terms of the GNU General Public License as published by
   5  *   the Free Software Foundation; either version 2 of the License, or
   6  *   (at your option) any later version.
   7  *
   8  *   This program is distributed in the hope that it will be useful,
   9  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *   GNU General Public License for more details.
  12  */
  13
  14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15
  16 #include <linux/io.h>
  17 #include <linux/hdlc.h>
  18 #include "pmcc4_sysdep.h"
  19 #include "sbecom_inline_linux.h"
  20 #include "libsbew.h"
  21 #include "pmcc4.h"
  22 #include "comet.h"
  23 #include "comet_tables.h"
  24
  25
  26 #define COMET_NUM_SAMPLES   24  /* Number of entries in the waveform table */
  27 #define COMET_NUM_UNITS     5   /* Number of points per entry in table */
  28
  29 /* forward references */
  30 static void SetPwrLevel(struct s_comet_reg *comet);
  31 static void WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet,
  32                                 u_int32_t *table);
  33 static void WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
  34                                 u_int8_t table[COMET_NUM_SAMPLES]
  35                                 [COMET_NUM_UNITS]);
  36
  37
  38 static void *TWV_table[12] = {
  39         TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
  40         TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
  41         TWVShortHaul4, TWVShortHaul5,
  42         /** PORT POINT - 75 Ohm not supported **/
  43         TWV_E1_75Ohm,
  44         TWV_E1_120Ohm
  45 };
  46
  47
  48 static int
  49 lbo_tbl_lkup(int t1, int lbo) {
  50         /* error switches to default */
  51         if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
  52                 if (t1)
  53                         /* default T1 waveform table */
  54                         lbo = CFG_LBO_LH0;
  55
  56                 else
  57                         /* default E1 waveform table */
  58                         lbo = CFG_LBO_E120;
  59         }
  60         /* make index ZERO relative */
  61         return lbo - 1;
  62 }
  63
  64 void init_comet(void *ci, struct s_comet_reg *comet, u_int32_t port_mode,
  65                 int clockmaster, u_int8_t moreParams)
  66 {
  67         u_int8_t isT1mode;
  68         /* T1 default */
  69         u_int8_t    tix = CFG_LBO_LH0;
  70         isT1mode = IS_FRAME_ANY_T1(port_mode);
  71         /* T1 or E1 */
  72         if (isT1mode) {
  73                 /* Select T1 Mode & PIO output enabled */
  74                 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
  75                 /* default T1 waveform table */
  76                 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
  77         } else {
  78                 /* Select E1 Mode & PIO output enabled */
  79                 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
  80                 /* default E1 waveform table */
  81                 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
  82         }
  83
  84         if (moreParams & CFG_LBO_MASK)
  85                 /* dial-in requested waveform table */
  86                 tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
  87         /* Tx line Intfc cfg Set for analog & no special patterns */
  88         /* Transmit Line Interface Config. */
  89         pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
  90         /* master test Ignore Test settings for now */
  91         /* making sure it's Default value */
  92         pci_write_32((u_int32_t *) &comet->mtest, 0x00);
  93         /* Turn on Center (CENT) and everything else off */
  94         /* RJAT cfg */
  95         pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
  96         /* Set Jitter Attenuation to recommend T1 values */
  97         if (isT1mode) {
  98                 /* RJAT Divider N1 Control */
  99                 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
 100                 /* RJAT Divider N2 Control */
 101                 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
 102         } else {
 103                 /* RJAT Divider N1 Control */
 104                 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
 105                 /* RJAT Divider N2 Control */
 106                 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
 107         }
 108
 109         /* Turn on Center (CENT) and everything else off */
 110         /* TJAT Config. */
 111         pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
 112
 113         /* Do not bypass jitter attenuation and bypass elastic store */
 114         /* rx opts */
 115         pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
 116
 117         /* TJAT ctrl & TJAT divider ctrl */
 118         /* Set Jitter Attenuation to recommended T1 values */
 119         if (isT1mode) {
 120                 /* TJAT Divider N1 Control */
 121                 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
 122                 /* TJAT Divider N2  Control */
 123                 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
 124         } else {
 125                 /* TJAT Divider N1 Control */
 126                 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
 127                 /* TJAT Divider N2 Control */
 128                 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
 129         }
 130
 131         /* 1c: rx ELST cfg   20: tx ELST cfg  28&38: rx&tx data link ctrl */
 132
 133         /* Select 193-bit frame format */
 134         if (isT1mode) {
 135                 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
 136                 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
 137         } else {
 138                 /* Select 256-bit frame format */
 139                 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
 140                 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
 141                 /* disable T1 data link receive */
 142                 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
 143                 /* disable T1 data link transmit */
 144                 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
 145         }
 146
 147     /* the following is a default value */
 148     /* Enable 8 out of 10 validation */
 149          /* t1RBOC enable(BOC:BitOriented Code) */
 150         pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
 151         if (isT1mode) {
 152                 /* IBCD cfg: aka Inband Code Detection ** loopback code length
 153                  * set to
 154                  */
 155                 /* 6 bit down, 5 bit up (assert) */
 156                 pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
 157                 /* line loopback activate pattern */
 158                 pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
 159                 /* deactivate code pattern (i.e.001) */
 160                 pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
 161         }
 162     /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg  */
 163     /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg  */
 164     /* 60: t1 ALMI cfg */
 165     /* Configure Line Coding */
 166
 167         switch (port_mode) {
 168         /* 1 - T1 B8ZS */
 169         case CFG_FRAME_SF:
 170                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 171                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
 172                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 173                 /* 5:B8ZS */
 174                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
 175                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
 176                 break;
 177         /* 2 - T1 B8ZS */
 178         case CFG_FRAME_ESF:
 179                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 180                 /* Bit 5: T1 DataLink Enable */
 181                 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
 182                 /* 5: T1 DataLink Enable */
 183                 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
 184                 /* 4:ESF  5:ESFFA */
 185                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
 186                 /* 2:ESF */
 187                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
 188                 /* 4:ESF  5:B8ZS */
 189                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
 190                 /* 4:ESF */
 191                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
 192                 break;
 193         /* 3 - HDB3 */
 194         case CFG_FRAME_E1PLAIN:
 195                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 196                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 197                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
 198                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 199                 break;
 200         /* 4 - HDB3 */
 201         case CFG_FRAME_E1CAS:
 202                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 203                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 204                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
 205                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
 206                 break;
 207         /* 5 - HDB3 */
 208         case CFG_FRAME_E1CRC:
 209                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 210                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 211                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
 212                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 213                 break;
 214         /* 6 - HDB3 */
 215         case CFG_FRAME_E1CRC_CAS:
 216                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 217                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 218                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
 219                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 220                 break;
 221         /* 7 - T1 AMI */
 222         case CFG_FRAME_SF_AMI:
 223                 /* Enable AMI Line Decoding */
 224                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 225                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
 226                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
 227                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
 228                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 229                 break;
 230         /* 8 - T1 AMI */
 231         case CFG_FRAME_ESF_AMI:
 232                 /* Enable AMI Line Decoding */
 233                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 234                 /* 5: T1 DataLink Enable */
 235                 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
 236                 /* 5: T1 DataLink Enable */
 237                 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
 238                 /* Bit 4:ESF  5:ESFFA */
 239                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
 240                 /* 2:ESF */
 241                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
 242                 /* 4:ESF */
 243                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
 244                 /* 4:ESF */
 245                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
 246                 break;
 247         /* 9 - AMI */
 248         case CFG_FRAME_E1PLAIN_AMI:
 249                 /* Enable AMI Line Decoding */
 250                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 251                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 252                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
 253                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 254                 break;
 255         /* 10 - AMI */
 256         case CFG_FRAME_E1CAS_AMI:
 257                 /* Enable AMI Line Decoding */
 258                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 259                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 260                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
 261                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
 262                 break;
 263         /* 11 - AMI */
 264         case CFG_FRAME_E1CRC_AMI:
 265                 /* Enable AMI Line Decoding */
 266                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 267                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 268                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
 269                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 270                 break;
 271         /* 12 - AMI */
 272         case CFG_FRAME_E1CRC_CAS_AMI:
 273                 /* Enable AMI Line Decoding */
 274                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 275                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 276                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
 277                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 278                 break;
 279         }       /* end switch */
 280
 281     /***
 282      * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
 283      * CMODE=1: Clock slave mode with BRCLK as an input,
 284      * DE=0: Use falling edge of BRCLK for data,
 285      * FE=0: Use falling edge of BRCLK for frame,
 286      * CMS=0: Use backplane freq,
 287      * RATE[1:0]=0,0: T1
 288      ***/
 289
 290
 291     /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
 292     /* note "rate bits can only be set once after reset" */
 293         if (clockmaster) {
 294                 /* CMODE == clockMode, 0=clock master
 295                  * (so all 3 others should be slave)
 296                  */
 297                 /* rate = 1.544 Mb/s */
 298                 if (isT1mode)
 299                         /* Comet 0 Master Mode(CMODE=0) */
 300                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
 301                 /* rate = 2.048 Mb/s */
 302                 else
 303                         /* Comet 0 Master Mode(CMODE=0) */
 304                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
 305
 306                 /* 31: BRIF frame pulse cfg  06: tx timing options */
 307
 308                 /* Master Mode i.e.FPMODE=0 (@0x20) */
 309                 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
 310                 if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
 311                         if (cxt1e1_log_level >= LOG_SBEBUG12)
 312                                 pr_info(">> %s: clockmaster internal clock\n",
 313                                         __func__);
 314                         /* internal oscillator */
 315                         pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
 316                 } else {
 317                         /* external clock source */
 318                         if (cxt1e1_log_level >= LOG_SBEBUG12)
 319                                 pr_info(">> %s: clockmaster external clock\n",
 320                                         __func__);
 321                         /* loop timing(external) */
 322                         pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
 323                 }
 324
 325         } else  {
 326                 /* slave */
 327                 if (isT1mode)
 328                         /* Slave Mode(CMODE=1, see above) */
 329                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
 330                 else
 331                         /* Slave Mode(CMODE=1)*/
 332                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
 333                 /* Slave Mode i.e. FPMODE=1 (@0x20) */
 334                 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
 335         if (cxt1e1_log_level >= LOG_SBEBUG12)
 336                 pr_info(">> %s: clockslave internal clock\n", __func__);
 337         /* oscillator timing */
 338         pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
 339         }
 340
 341         /* 32: BRIF parity F-bit cfg */
 342         /* Totem-pole operation */
 343         /* Receive Backplane Parity/F-bit */
 344         pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
 345
 346     /* dc: RLPS equalizer V ref */
 347     /* Configuration */
 348         if (isT1mode)
 349                 /* RLPS Equalizer Voltage  */
 350                 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
 351         else
 352                 /* RLPS Equalizer Voltage  */
 353                 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
 354
 355     /* Reserved bit set and SQUELCH enabled */
 356     /* f8: RLPS cfg & status  f9: RLPS ALOS detect/clear threshold */
 357         /* RLPS Configuration Status */
 358         pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
 359         if (isT1mode)
 360                 /* ? */
 361                 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
 362         else
 363                 /* ? */
 364                 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
 365
 366
 367     /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
 368     /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
 369     /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
 370     /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
 371     /***    Transmit side is always an Input, Slave Clock*/
 372     /* 40: BTIF cfg  41: loop timing(external) */
 373         /*BTIF frame pulse cfg */
 374         if (isT1mode)
 375                 /* BTIF Configuration  Reg. */
 376                 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
 377         else
 378                 /* BTIF Configuration  Reg. */
 379                 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
 380         /* BTIF Frame Pulse Config. */
 381         pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
 382
 383     /* 0a: master diag  06: tx timing options */
 384     /* if set Comet to loop back */
 385
 386     /* Comets set to normal */
 387         pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
 388
 389     /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted  */
 390     /* Store is enabled. */
 391
 392         WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
 393         if (isT1mode)
 394                 WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
 395         else
 396                 WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
 397         SetPwrLevel(comet);
 398 }
 399
 400 /*
 401 ** Name:        WrtXmtWaveform
 402 ** Description: Formulate the Data for the Pulse Waveform Storage
 403 **                Write register, (F2), from the sample and unit inputs.
 404 **                Write the data to the Pulse Waveform Storage Data register.
 405 ** Returns:     Nothing
 406 */
 407 static void
 408 WrtXmtWaveform(ci_t *ci, struct s_comet_reg *comet, u_int32_t sample,
 409                 u_int32_t unit, u_int8_t data)
 410 {
 411         u_int8_t    WaveformAddr;
 412
 413         WaveformAddr = (sample << 3) + (unit & 7);
 414         pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
 415         /* for write order preservation when Optimizing driver */
 416         pci_flush_write(ci);
 417         pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
 418 }
 419
 420 /*
 421 ** Name:        WrtXmtWaveformTbl
 422 ** Description: Fill in the Transmit Waveform Values
 423 **                for driving the transmitter DAC.
 424 ** Returns:     Nothing
 425 */
 426 static void
 427 WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
 428                   u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
 429 {
 430         u_int32_t sample, unit;
 431
 432         for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
 433                 for (unit = 0; unit < COMET_NUM_UNITS; unit++)
 434                         WrtXmtWaveform(ci, comet, sample, unit,
 435                                         table[sample][unit]);
 436                 }
 437
 438     /* Enable transmitter and set output amplitude */
 439         pci_write_32((u_int32_t *) &comet->xlpg_cfg,
 440                         table[COMET_NUM_SAMPLES][0]);
 441 }
 442
 443
 444 /*
 445 ** Name:        WrtXmtWaveform
 446 ** Description: Fill in the Receive Equalizer RAM from the desired
 447 **                table.
 448 ** Returns:     Nothing
 449 **
 450 ** Remarks:  Per PM4351 Device Errata, Receive Equalizer RAM Initialization
 451 **           is coded with early setup of indirect address.
 452 */
 453
 454 static void
 455 WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table)
 456 {
 457         u_int32_t   ramaddr;
 458         u_int32_t value;
 459
 460         for (ramaddr = 0; ramaddr < 256; ramaddr++) {
 461                 /*** the following lines are per Errata 7, 2.5 ***/
 462                 {
 463                 /* Set up for a read operation */
 464                 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
 465                 /* for write order preservation when Optimizing driver */
 466                 pci_flush_write(ci);
 467                 /* write the addr, initiate a read */
 468                 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
 469                                 (u_int8_t) ramaddr);
 470                 /* for write order preservation when Optimizing driver */
 471                 pci_flush_write(ci);
 472                 /*
 473                 * wait 3 line rate clock cycles to ensure address bits are
 474                 * captured by T1/E1 clock
 475                 */
 476
 477                 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
 478                 OS_uwait(4, "wret");
 479         }
 480
 481         value = *table++;
 482         pci_write_32((u_int32_t *) &comet->rlps_idata3,
 483                         (u_int8_t) (value >> 24));
 484         pci_write_32((u_int32_t *) &comet->rlps_idata2,
 485                         (u_int8_t) (value >> 16));
 486         pci_write_32((u_int32_t *) &comet->rlps_idata1,
 487                         (u_int8_t) (value >> 8));
 488         pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
 489          /* for write order preservation when Optimizing driver */
 490         pci_flush_write(ci);
 491
 492         /* Storing RAM address, causes RAM to be updated */
 493
 494                 /* Set up for a write operation */
 495                 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
 496                 /* for write order preservation when optimizing driver */
 497                 pci_flush_write(ci);
 498                 /* write the addr, initiate a read */
 499                 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
 500                                 (u_int8_t) ramaddr);
 501                  /* for write order preservation when optimizing driver */
 502                 pci_flush_write(ci);
 503
 504         /*
 505         * wait 3 line rate clock cycles to ensure address bits are captured
 506         * by T1/E1 clock
 507         */
 508                 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
 509                 OS_uwait(4, "wret");
 510         }
 511
 512         /* Enable Equalizer & set it to use 256 periods */
 513         pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
 514 }
 515
 516
 517 /*
 518 ** Name:        SetPwrLevel
 519 ** Description: Implement power level setting algorithm described below
 520 ** Returns:     Nothing
 521 */
 522
 523 static void
 524 SetPwrLevel(struct s_comet_reg *comet)
 525 {
 526         u_int32_t temp;
 527
 528 /*
 529 **    Algorithm to Balance the Power Distribution of Ttip Tring
 530 **
 531 **    Zero register F6
 532 **    Write 0x01 to register F4
 533 **    Write another 0x01 to register F4
 534 **    Read register F4
 535 **    Remove the 0x01 bit by Anding register F4 with 0xFE
 536 **    Write the resultant value to register F4
 537 **    Repeat these steps for register F5
 538 **    Write 0x01 to register F6
 539 */
 540         /* XLPG Fuse Data Select */
 541         pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
 542         /* XLPG Analog Test Positive control */
 543         pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
 544         pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
 545         temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
 546         pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
 547         pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
 548         pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
 549         /* XLPG Analog Test Negative control */
 550         temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
 551         pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
 552         /* XLPG */
 553         pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
 554 }
 555
 556
 557 /*
 558 ** Name:        SetCometOps
 559 ** Description: Set up the selected Comet's clock edge drive for both
 560 **                the transmit out the analog side and receive to the
 561 **                backplane side.
 562 ** Returns:     Nothing
 563 */
 564 #if 0
 565 static void
 566 SetCometOps(struct s_comet_reg *comet)
 567 {
 568         u_int8_t rd_value;
 569
 570         if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
 571                 /* read the BRIF Configuration */
 572                 rd_value = (u_int8_t) pci_read_32((u_int32_t *)
 573                                 &comet->brif_cfg);
 574                 rd_value &= ~0x20;
 575                 pci_write_32((u_int32_t *) &comet->brif_cfg,
 576                                 (u_int32_t) rd_value);
 577                 /* read the BRIF Frame Pulse Configuration */
 578                 rd_value = (u_int8_t) pci_read_32((u_int32_t *)
 579                                 &comet->brif_fpcfg);
 580                 rd_value &= ~0x20;
 581                 pci_write_32((u_int32_t *) &comet->brif_fpcfg,
 582                                 (u_int8_t) rd_value);
 583         } else {
 584         /* read the BRIF Configuration */
 585         rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
 586         rd_value |= 0x20;
 587         pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
 588         /* read the BRIF Frame Pulse Configuration */
 589         rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
 590         rd_value |= 0x20;
 591         pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
 592         }
 593 }
 594 #endif
 595
 596 /***  End-of-File  ***/