2 * AD5933 AD5934 Impedance Converter, Network Analyzer
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/sysfs.h>
13 #include <linux/i2c.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/slab.h>
16 #include <linux/types.h>
17 #include <linux/err.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
20 #include <asm/div64.h>
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/kfifo_buf.h>
29 /* AD5933/AD5934 Registers */
30 #define AD5933_REG_CONTROL_HB 0x80 /* R/W, 2 bytes */
31 #define AD5933_REG_CONTROL_LB 0x81 /* R/W, 2 bytes */
32 #define AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */
33 #define AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */
34 #define AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */
35 #define AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */
36 #define AD5933_REG_STATUS 0x8F /* R, 1 byte */
37 #define AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/
38 #define AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/
39 #define AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/
41 /* AD5933_REG_CONTROL_HB Bits */
42 #define AD5933_CTRL_INIT_START_FREQ (0x1 << 4)
43 #define AD5933_CTRL_START_SWEEP (0x2 << 4)
44 #define AD5933_CTRL_INC_FREQ (0x3 << 4)
45 #define AD5933_CTRL_REPEAT_FREQ (0x4 << 4)
46 #define AD5933_CTRL_MEASURE_TEMP (0x9 << 4)
47 #define AD5933_CTRL_POWER_DOWN (0xA << 4)
48 #define AD5933_CTRL_STANDBY (0xB << 4)
50 #define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
51 #define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
52 #define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
53 #define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
54 #define AD5933_CTRL_RANGE(x) ((x) << 1)
56 #define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0)
57 #define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0)
59 /* AD5933_REG_CONTROL_LB Bits */
60 #define AD5933_CTRL_RESET (0x1 << 4)
61 #define AD5933_CTRL_INT_SYSCLK (0x0 << 3)
62 #define AD5933_CTRL_EXT_SYSCLK (0x1 << 3)
64 /* AD5933_REG_STATUS Bits */
65 #define AD5933_STAT_TEMP_VALID (0x1 << 0)
66 #define AD5933_STAT_DATA_VALID (0x1 << 1)
67 #define AD5933_STAT_SWEEP_DONE (0x1 << 2)
69 /* I2C Block Commands */
70 #define AD5933_I2C_BLOCK_WRITE 0xA0
71 #define AD5933_I2C_BLOCK_READ 0xA1
72 #define AD5933_I2C_ADDR_POINTER 0xB0
75 #define AD5933_INT_OSC_FREQ_Hz 16776000
76 #define AD5933_MAX_OUTPUT_FREQ_Hz 100000
77 #define AD5933_MAX_RETRIES 100
79 #define AD5933_OUT_RANGE 1
80 #define AD5933_OUT_RANGE_AVAIL 2
81 #define AD5933_OUT_SETTLING_CYCLES 3
82 #define AD5933_IN_PGA_GAIN 4
83 #define AD5933_IN_PGA_GAIN_AVAIL 5
84 #define AD5933_FREQ_POINTS 6
86 #define AD5933_POLL_TIME_ms 10
87 #define AD5933_INIT_EXCITATION_TIME_ms 100
90 struct i2c_client *client;
91 struct regulator *reg;
92 struct ad5933_platform_data *pdata;
93 struct delayed_work work;
94 unsigned long mclk_hz;
95 unsigned char ctrl_hb;
96 unsigned char ctrl_lb;
97 unsigned range_avail[4];
98 unsigned short vref_mv;
99 unsigned short settling_cycles;
100 unsigned short freq_points;
104 unsigned poll_time_jiffies;
107 static struct ad5933_platform_data ad5933_default_pdata = {
111 static const struct iio_chan_spec ad5933_channels[] = {
116 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
117 .address = AD5933_REG_TEMP_DATA,
123 }, { /* Ring Channels */
127 .extend_name = "real_raw",
128 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
129 BIT(IIO_CHAN_INFO_SCALE),
130 .address = AD5933_REG_REAL_DATA,
141 .extend_name = "imag_raw",
142 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
143 BIT(IIO_CHAN_INFO_SCALE),
144 .address = AD5933_REG_IMAG_DATA,
154 static int ad5933_i2c_write(struct i2c_client *client,
155 u8 reg, u8 len, u8 *data)
160 ret = i2c_smbus_write_byte_data(client, reg++, *data++);
162 dev_err(&client->dev, "I2C write error\n");
169 static int ad5933_i2c_read(struct i2c_client *client,
170 u8 reg, u8 len, u8 *data)
175 ret = i2c_smbus_read_byte_data(client, reg++);
177 dev_err(&client->dev, "I2C read error\n");
185 static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd)
187 unsigned char dat = st->ctrl_hb | cmd;
189 return ad5933_i2c_write(st->client,
190 AD5933_REG_CONTROL_HB, 1, &dat);
193 static int ad5933_reset(struct ad5933_state *st)
195 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET;
197 return ad5933_i2c_write(st->client,
198 AD5933_REG_CONTROL_LB, 1, &dat);
201 static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event)
203 unsigned char val, timeout = AD5933_MAX_RETRIES;
207 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val);
219 static int ad5933_set_freq(struct ad5933_state *st,
220 unsigned reg, unsigned long freq)
222 unsigned long long freqreg;
228 freqreg = (u64) freq * (u64) (1 << 27);
229 do_div(freqreg, st->mclk_hz / 4);
232 case AD5933_REG_FREQ_START:
233 st->freq_start = freq;
235 case AD5933_REG_FREQ_INC:
242 dat.d32 = cpu_to_be32(freqreg);
243 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]);
246 static int ad5933_setup(struct ad5933_state *st)
251 ret = ad5933_reset(st);
255 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
259 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
263 st->settling_cycles = 10;
264 dat = cpu_to_be16(st->settling_cycles);
266 ret = ad5933_i2c_write(st->client,
267 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
271 st->freq_points = 100;
272 dat = cpu_to_be16(st->freq_points);
274 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat);
277 static void ad5933_calc_out_ranges(struct ad5933_state *st)
280 unsigned normalized_3v3[4] = {1980, 198, 383, 970};
282 for (i = 0; i < 4; i++)
283 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300;
288 * handles: AD5933_REG_FREQ_START and AD5933_REG_FREQ_INC
291 static ssize_t ad5933_show_frequency(struct device *dev,
292 struct device_attribute *attr,
295 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
296 struct ad5933_state *st = iio_priv(indio_dev);
297 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
299 unsigned long long freqreg;
305 mutex_lock(&indio_dev->mlock);
306 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]);
307 mutex_unlock(&indio_dev->mlock);
311 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF;
313 freqreg = (u64) freqreg * (u64) (st->mclk_hz / 4);
314 do_div(freqreg, 1 << 27);
316 return sprintf(buf, "%d\n", (int) freqreg);
319 static ssize_t ad5933_store_frequency(struct device *dev,
320 struct device_attribute *attr,
324 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
325 struct ad5933_state *st = iio_priv(indio_dev);
326 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
330 ret = kstrtoul(buf, 10, &val);
334 if (val > AD5933_MAX_OUTPUT_FREQ_Hz)
337 mutex_lock(&indio_dev->mlock);
338 ret = ad5933_set_freq(st, this_attr->address, val);
339 mutex_unlock(&indio_dev->mlock);
341 return ret ? ret : len;
344 static IIO_DEVICE_ATTR(out_voltage0_freq_start, S_IRUGO | S_IWUSR,
345 ad5933_show_frequency,
346 ad5933_store_frequency,
347 AD5933_REG_FREQ_START);
349 static IIO_DEVICE_ATTR(out_voltage0_freq_increment, S_IRUGO | S_IWUSR,
350 ad5933_show_frequency,
351 ad5933_store_frequency,
352 AD5933_REG_FREQ_INC);
354 static ssize_t ad5933_show(struct device *dev,
355 struct device_attribute *attr,
358 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
359 struct ad5933_state *st = iio_priv(indio_dev);
360 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
361 int ret = 0, len = 0;
363 mutex_lock(&indio_dev->mlock);
364 switch ((u32) this_attr->address) {
365 case AD5933_OUT_RANGE:
366 len = sprintf(buf, "%d\n",
367 st->range_avail[(st->ctrl_hb >> 1) & 0x3]);
369 case AD5933_OUT_RANGE_AVAIL:
370 len = sprintf(buf, "%d %d %d %d\n", st->range_avail[0],
371 st->range_avail[3], st->range_avail[2],
374 case AD5933_OUT_SETTLING_CYCLES:
375 len = sprintf(buf, "%d\n", st->settling_cycles);
377 case AD5933_IN_PGA_GAIN:
378 len = sprintf(buf, "%s\n",
379 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ?
382 case AD5933_IN_PGA_GAIN_AVAIL:
383 len = sprintf(buf, "1 0.2\n");
385 case AD5933_FREQ_POINTS:
386 len = sprintf(buf, "%d\n", st->freq_points);
392 mutex_unlock(&indio_dev->mlock);
393 return ret ? ret : len;
396 static ssize_t ad5933_store(struct device *dev,
397 struct device_attribute *attr,
401 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
402 struct ad5933_state *st = iio_priv(indio_dev);
403 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
408 if (this_attr->address != AD5933_IN_PGA_GAIN) {
409 ret = kstrtou16(buf, 10, &val);
414 mutex_lock(&indio_dev->mlock);
415 switch ((u32) this_attr->address) {
416 case AD5933_OUT_RANGE:
417 for (i = 0; i < 4; i++)
418 if (val == st->range_avail[i]) {
419 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3);
420 st->ctrl_hb |= AD5933_CTRL_RANGE(i);
421 ret = ad5933_cmd(st, 0);
426 case AD5933_IN_PGA_GAIN:
427 if (sysfs_streq(buf, "1")) {
428 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1;
429 } else if (sysfs_streq(buf, "0.2")) {
430 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1;
435 ret = ad5933_cmd(st, 0);
437 case AD5933_OUT_SETTLING_CYCLES:
438 val = clamp(val, (u16)0, (u16)0x7FF);
439 st->settling_cycles = val;
441 /* 2x, 4x handling, see datasheet */
443 val = (val >> 1) | (1 << 9);
445 val = (val >> 2) | (3 << 9);
447 dat = cpu_to_be16(val);
448 ret = ad5933_i2c_write(st->client,
449 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
451 case AD5933_FREQ_POINTS:
452 val = clamp(val, (u16)0, (u16)511);
453 st->freq_points = val;
455 dat = cpu_to_be16(val);
456 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2,
463 mutex_unlock(&indio_dev->mlock);
464 return ret ? ret : len;
467 static IIO_DEVICE_ATTR(out_voltage0_scale, S_IRUGO | S_IWUSR,
472 static IIO_DEVICE_ATTR(out_voltage0_scale_available, S_IRUGO,
475 AD5933_OUT_RANGE_AVAIL);
477 static IIO_DEVICE_ATTR(in_voltage0_scale, S_IRUGO | S_IWUSR,
482 static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO,
485 AD5933_IN_PGA_GAIN_AVAIL);
487 static IIO_DEVICE_ATTR(out_voltage0_freq_points, S_IRUGO | S_IWUSR,
492 static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, S_IRUGO | S_IWUSR,
495 AD5933_OUT_SETTLING_CYCLES);
498 * ideally we would handle the scale attributes via the iio_info
499 * (read|write)_raw methods, however this part is a untypical since we
500 * don't create dedicated sysfs channel attributes for out0 and in0.
502 static struct attribute *ad5933_attributes[] = {
503 &iio_dev_attr_out_voltage0_scale.dev_attr.attr,
504 &iio_dev_attr_out_voltage0_scale_available.dev_attr.attr,
505 &iio_dev_attr_out_voltage0_freq_start.dev_attr.attr,
506 &iio_dev_attr_out_voltage0_freq_increment.dev_attr.attr,
507 &iio_dev_attr_out_voltage0_freq_points.dev_attr.attr,
508 &iio_dev_attr_out_voltage0_settling_cycles.dev_attr.attr,
509 &iio_dev_attr_in_voltage0_scale.dev_attr.attr,
510 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
514 static const struct attribute_group ad5933_attribute_group = {
515 .attrs = ad5933_attributes,
518 static int ad5933_read_raw(struct iio_dev *indio_dev,
519 struct iio_chan_spec const *chan,
524 struct ad5933_state *st = iio_priv(indio_dev);
528 mutex_lock(&indio_dev->mlock);
530 case IIO_CHAN_INFO_RAW:
531 case IIO_CHAN_INFO_PROCESSED:
532 if (iio_buffer_enabled(indio_dev)) {
536 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP);
539 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID);
543 ret = ad5933_i2c_read(st->client,
544 AD5933_REG_TEMP_DATA, 2,
548 mutex_unlock(&indio_dev->mlock);
549 ret = be16_to_cpu(dat);
550 /* Temp in Milli degrees Celsius */
552 *val = ret * 1000 / 32;
554 *val = (ret - 16384) * 1000 / 32;
560 mutex_unlock(&indio_dev->mlock);
564 static const struct iio_info ad5933_info = {
565 .read_raw = &ad5933_read_raw,
566 .attrs = &ad5933_attribute_group,
567 .driver_module = THIS_MODULE,
570 static int ad5933_ring_preenable(struct iio_dev *indio_dev)
572 struct ad5933_state *st = iio_priv(indio_dev);
575 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
578 ret = ad5933_reset(st);
582 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
586 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
590 st->state = AD5933_CTRL_INIT_START_FREQ;
595 static int ad5933_ring_postenable(struct iio_dev *indio_dev)
597 struct ad5933_state *st = iio_priv(indio_dev);
599 /* AD5933_CTRL_INIT_START_FREQ:
600 * High Q complex circuits require a long time to reach steady state.
601 * To facilitate the measurement of such impedances, this mode allows
602 * the user full control of the settling time requirement before
603 * entering start frequency sweep mode where the impedance measurement
604 * takes place. In this mode the impedance is excited with the
605 * programmed start frequency (ad5933_ring_preenable),
606 * but no measurement takes place.
609 schedule_delayed_work(&st->work,
610 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms));
614 static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
616 struct ad5933_state *st = iio_priv(indio_dev);
618 cancel_delayed_work_sync(&st->work);
619 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
622 static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = {
623 .preenable = &ad5933_ring_preenable,
624 .postenable = &ad5933_ring_postenable,
625 .postdisable = &ad5933_ring_postdisable,
628 static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
630 struct iio_buffer *buffer;
632 buffer = iio_kfifo_allocate(indio_dev);
636 iio_device_attach_buffer(indio_dev, buffer);
638 /* Ring buffer functions - here trigger setup related */
639 indio_dev->setup_ops = &ad5933_ring_setup_ops;
641 indio_dev->modes |= INDIO_BUFFER_HARDWARE;
646 static void ad5933_work(struct work_struct *work)
648 struct ad5933_state *st = container_of(work,
649 struct ad5933_state, work.work);
650 struct iio_dev *indio_dev = i2c_get_clientdata(st->client);
652 unsigned char status;
654 mutex_lock(&indio_dev->mlock);
655 if (st->state == AD5933_CTRL_INIT_START_FREQ) {
657 ad5933_cmd(st, AD5933_CTRL_START_SWEEP);
658 st->state = AD5933_CTRL_START_SWEEP;
659 schedule_delayed_work(&st->work, st->poll_time_jiffies);
660 mutex_unlock(&indio_dev->mlock);
664 ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status);
666 if (status & AD5933_STAT_DATA_VALID) {
667 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
668 indio_dev->masklength);
669 ad5933_i2c_read(st->client,
670 test_bit(1, indio_dev->active_scan_mask) ?
671 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA,
672 scan_count * 2, (u8 *)buf);
674 if (scan_count == 2) {
675 buf[0] = be16_to_cpu(buf[0]);
676 buf[1] = be16_to_cpu(buf[1]);
678 buf[0] = be16_to_cpu(buf[0]);
680 iio_push_to_buffers(indio_dev, buf);
682 /* no data available - try again later */
683 schedule_delayed_work(&st->work, st->poll_time_jiffies);
684 mutex_unlock(&indio_dev->mlock);
688 if (status & AD5933_STAT_SWEEP_DONE) {
689 /* last sample received - power down do nothing until
690 * the ring enable is toggled */
691 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
693 /* we just received a valid datum, move on to the next */
694 ad5933_cmd(st, AD5933_CTRL_INC_FREQ);
695 schedule_delayed_work(&st->work, st->poll_time_jiffies);
698 mutex_unlock(&indio_dev->mlock);
701 static int ad5933_probe(struct i2c_client *client,
702 const struct i2c_device_id *id)
704 int ret, voltage_uv = 0;
705 struct ad5933_platform_data *pdata = client->dev.platform_data;
706 struct ad5933_state *st;
707 struct iio_dev *indio_dev;
709 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
710 if (indio_dev == NULL)
713 st = iio_priv(indio_dev);
714 i2c_set_clientdata(client, indio_dev);
718 st->pdata = &ad5933_default_pdata;
722 st->reg = devm_regulator_get(&client->dev, "vcc");
723 if (!IS_ERR(st->reg)) {
724 ret = regulator_enable(st->reg);
727 voltage_uv = regulator_get_voltage(st->reg);
731 st->vref_mv = voltage_uv / 1000;
733 st->vref_mv = st->pdata->vref_mv;
735 if (st->pdata->ext_clk_Hz) {
736 st->mclk_hz = st->pdata->ext_clk_Hz;
737 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK;
739 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz;
740 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK;
743 ad5933_calc_out_ranges(st);
744 INIT_DELAYED_WORK(&st->work, ad5933_work);
745 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms);
747 indio_dev->dev.parent = &client->dev;
748 indio_dev->info = &ad5933_info;
749 indio_dev->name = id->name;
750 indio_dev->modes = INDIO_DIRECT_MODE;
751 indio_dev->channels = ad5933_channels;
752 indio_dev->num_channels = 1; /* only register temp0_input */
754 ret = ad5933_register_ring_funcs_and_init(indio_dev);
756 goto error_disable_reg;
758 /* skip temp0_input, register in0_(real|imag)_raw */
759 ret = iio_buffer_register(indio_dev, &ad5933_channels[1], 2);
761 goto error_unreg_ring;
763 /* enable both REAL and IMAG channels by default */
764 iio_scan_mask_set(indio_dev, indio_dev->buffer, 0);
765 iio_scan_mask_set(indio_dev, indio_dev->buffer, 1);
767 ret = ad5933_setup(st);
769 goto error_uninitialize_ring;
771 ret = iio_device_register(indio_dev);
773 goto error_uninitialize_ring;
777 error_uninitialize_ring:
778 iio_buffer_unregister(indio_dev);
780 iio_kfifo_free(indio_dev->buffer);
782 if (!IS_ERR(st->reg))
783 regulator_disable(st->reg);
788 static int ad5933_remove(struct i2c_client *client)
790 struct iio_dev *indio_dev = i2c_get_clientdata(client);
791 struct ad5933_state *st = iio_priv(indio_dev);
793 iio_device_unregister(indio_dev);
794 iio_buffer_unregister(indio_dev);
795 iio_kfifo_free(indio_dev->buffer);
796 if (!IS_ERR(st->reg))
797 regulator_disable(st->reg);
802 static const struct i2c_device_id ad5933_id[] = {
808 MODULE_DEVICE_TABLE(i2c, ad5933_id);
810 static struct i2c_driver ad5933_driver = {
814 .probe = ad5933_probe,
815 .remove = ad5933_remove,
816 .id_table = ad5933_id,
818 module_i2c_driver(ad5933_driver);
820 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
821 MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer");
822 MODULE_LICENSE("GPL v2");