drivers/staging/rtl8188eu/hal/HalPwrSeqCmd.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 /*++
  21 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
  22
  23 Module Name:
  24         HalPwrSeqCmd.c
  25
  26 Abstract:
  27         Implement HW Power sequence configuration CMD handling routine for Realtek devices.
  28
  29 Major Change History:
  30         When       Who               What
  31         ---------- ---------------   -------------------------------
  32         2011-10-26 Lucas            Modify to be compatible with SD4-CE driver.
  33         2011-07-07 Roger            Create.
  34
  35 --*/
  36
  37 #include <HalPwrSeqCmd.h>
  38
  39 /*      Description: */
  40 /*              This routine deals with the Power Configuration CMDs parsing
  41  *              for RTL8723/RTL8188E Series IC.
  42  *      Assumption:
  43  *              We should follow specific format which was released from HW SD.
  44  */
  45 u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers,
  46                        u8 ifacetype, struct wl_pwr_cfg pwrseqcmd[])
  47 {
  48         struct wl_pwr_cfg pwrcfgcmd = {0};
  49         u8 poll_bit = false;
  50         u32 aryidx = 0;
  51         u8 value = 0;
  52         u32 offset = 0;
  53         u32 poll_count = 0; /*  polling autoload done. */
  54         u32 max_poll_count = 5000;
  55
  56         do {
  57                 pwrcfgcmd = pwrseqcmd[aryidx];
  58
  59                 RT_TRACE(_module_hal_init_c_ , _drv_info_,
  60                          ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
  61                          GET_PWR_CFG_OFFSET(pwrcfgcmd),
  62                          GET_PWR_CFG_CUT_MASK(pwrcfgcmd),
  63                          GET_PWR_CFG_FAB_MASK(pwrcfgcmd),
  64                          GET_PWR_CFG_INTF_MASK(pwrcfgcmd),
  65                          GET_PWR_CFG_BASE(pwrcfgcmd),
  66                          GET_PWR_CFG_CMD(pwrcfgcmd),
  67                          GET_PWR_CFG_MASK(pwrcfgcmd),
  68                          GET_PWR_CFG_VALUE(pwrcfgcmd)));
  69
  70                 /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
  71                 if ((GET_PWR_CFG_FAB_MASK(pwrcfgcmd) & fab_vers) &&
  72                     (GET_PWR_CFG_CUT_MASK(pwrcfgcmd) & cut_vers) &&
  73                     (GET_PWR_CFG_INTF_MASK(pwrcfgcmd) & ifacetype)) {
  74                         switch (GET_PWR_CFG_CMD(pwrcfgcmd)) {
  75                         case PWR_CMD_READ:
  76                                 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
  77                                 break;
  78                         case PWR_CMD_WRITE:
  79                                 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
  80                                 offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
  81
  82                                 /*  Read the value from system register */
  83                                 value = rtw_read8(padapter, offset);
  84
  85                                 value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd));
  86                                 value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd));
  87
  88                                 /*  Write the value back to system register */
  89                                 rtw_write8(padapter, offset, value);
  90                                 break;
  91                         case PWR_CMD_POLLING:
  92                                 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
  93
  94                                 poll_bit = false;
  95                                 offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
  96                                 do {
  97                                                 value = rtw_read8(padapter, offset);
  98
  99                                         value &= GET_PWR_CFG_MASK(pwrcfgcmd);
 100                                         if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd)))
 101                                                 poll_bit = true;
 102                                         else
 103                                                 rtw_udelay_os(10);
 104
 105                                         if (poll_count++ > max_poll_count) {
 106                                                 DBG_88E("Fail to polling Offset[%#x]\n", offset);
 107                                                 return false;
 108                                         }
 109                                 } while (!poll_bit);
 110                                 break;
 111                         case PWR_CMD_DELAY:
 112                                 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
 113                                 if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US)
 114                                         rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd));
 115                                 else
 116                                         rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000);
 117                                 break;
 118                         case PWR_CMD_END:
 119                                 /*  When this command is parsed, end the process */
 120                                 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
 121                                 return true;
 122                                 break;
 123                         default:
 124                                 RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
 125                                 break;
 126                         }
 127                 }
 128
 129                 aryidx++;/* Add Array Index */
 130         } while (1);
 131         return true;
 132 }