1 /******************************************************************************
3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
17 #include <linux/firmware.h>
18 #include <drv_types.h>
19 #include <rtw_efuse.h>
21 #include <rtl8723a_hal.h>
22 #include <usb_ops_linux.h>
24 static void _FWDownloadEnable(struct rtw_adapter *padapter, bool enable)
30 tmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
31 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
33 /* MCU firmware download enable. */
34 tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
35 rtl8723au_write8(padapter, REG_MCUFWDL, tmp | 0x01);
38 tmp = rtl8723au_read8(padapter, REG_MCUFWDL + 2);
39 rtl8723au_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
41 /* MCU firmware download disable. */
42 tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
43 rtl8723au_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
45 /* Reserved for fw extension. */
46 rtl8723au_write8(padapter, REG_MCUFWDL + 1, 0x00);
51 _PageWrite(struct rtw_adapter *padapter, u32 page, void *buffer, u32 size)
54 u8 u8Page = (u8) (page & 0x07);
56 if (size > MAX_PAGE_SIZE)
59 value8 = (rtl8723au_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page;
60 rtl8723au_write8(padapter, REG_MCUFWDL + 2, value8);
62 return rtl8723au_writeN(padapter, FW_8723A_START_ADDRESS, size, buffer);
65 static int _WriteFW(struct rtw_adapter *padapter, void *buffer, u32 size)
67 /* Since we need dynamic decide method of dwonload fw, so we
68 call this function to get chip version. */
69 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
71 u32 pageNums, remainSize;
73 u8 *bufferPtr = (u8 *) buffer;
75 pageNums = size / MAX_PAGE_SIZE;
76 /* RT_ASSERT((pageNums <= 4),
77 ("Page numbers should not greater then 4 \n")); */
78 remainSize = size % MAX_PAGE_SIZE;
80 for (page = 0; page < pageNums; page++) {
81 offset = page * MAX_PAGE_SIZE;
82 ret = _PageWrite(padapter, page, bufferPtr + offset,
89 offset = pageNums * MAX_PAGE_SIZE;
91 ret = _PageWrite(padapter, page, bufferPtr + offset,
97 RT_TRACE(_module_hal_init_c_, _drv_info_,
98 ("_WriteFW Done- for Normal chip.\n"));
104 static int _FWFreeToGo(struct rtw_adapter *padapter)
109 /* polling CheckSum report */
111 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
112 if (value32 & FWDL_ChkSum_rpt)
114 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
116 if (counter >= POLLING_READY_TIMEOUT_COUNT) {
117 RT_TRACE(_module_hal_init_c_, _drv_err_,
118 ("%s: chksum report fail! REG_MCUFWDL:0x%08x\n",
122 RT_TRACE(_module_hal_init_c_, _drv_info_,
123 ("%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __func__,
126 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
127 value32 |= MCUFWDL_RDY;
128 value32 &= ~WINTINI_RDY;
129 rtl8723au_write32(padapter, REG_MCUFWDL, value32);
131 /* polling for FW ready */
134 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
135 if (value32 & WINTINI_RDY) {
136 RT_TRACE(_module_hal_init_c_, _drv_info_,
137 ("%s: Polling FW ready success!! "
138 "REG_MCUFWDL:0x%08x\n",
143 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
145 RT_TRACE(_module_hal_init_c_, _drv_err_,
146 ("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n",
151 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
153 void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter)
155 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
159 if (!(IS_FW_81xxC(padapter) &&
160 ((pHalData->FirmwareVersion < 0x21) ||
161 (pHalData->FirmwareVersion == 0x21 &&
162 pHalData->FirmwareSubVersion < 0x01)))) {
163 /* after 88C Fw v33.1 */
164 /* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
165 rtl8723au_write8(padapter, REG_HMETFR + 3, 0x20);
167 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
168 while (u1bTmp & BIT(2)) {
173 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
175 RT_TRACE(_module_hal_init_c_, _drv_info_,
176 ("-%s: 8051 reset success (%d)\n", __func__,
180 /* force firmware reset */
181 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
182 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1,
190 /* Download 8192C firmware code. */
193 int rtl8723a_FirmwareDownload(struct rtw_adapter *padapter)
195 int rtStatus = _SUCCESS;
196 u8 writeFW_retry = 0;
197 unsigned long fwdl_start_time;
198 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
199 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
200 struct device *device = dvobj_to_dev(dvobj);
201 struct rt_8723a_firmware_hdr *pFwHdr = NULL;
202 const struct firmware *fw;
204 u8 *firmware_buf = NULL;
207 static int log_version;
209 RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__));
211 if (IS_8723A_A_CUT(pHalData->VersionID)) {
212 fw_name = "rtlwifi/rtl8723aufw_A.bin";
213 RT_TRACE(_module_hal_init_c_, _drv_info_,
214 ("rtl8723a_FirmwareDownload: R8723FwImageArray_UMC "
215 "for RTL8723A A CUT\n"));
216 } else if (IS_8723A_B_CUT(pHalData->VersionID)) {
218 if (padapter->registrypriv.wifi_spec == 1) {
219 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
220 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithoutBT for "
223 if (rtl8723a_BT_coexist(padapter)) {
224 fw_name = "rtlwifi/rtl8723aufw_B.bin";
225 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithBT "
226 "for RTL8723A B CUT\n");
228 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
229 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithout "
230 "BT for RTL8723A B CUT\n");
234 /* <Roger_TODO> We should download proper RAM Code here
235 to match the ROM code. */
236 RT_TRACE(_module_hal_init_c_, _drv_err_,
237 ("%s: unknow version!\n", __func__));
242 pr_info("rtl8723au: Loading firmware %s\n", fw_name);
243 if (request_firmware(&fw, fw_name, device)) {
244 pr_err("rtl8723au: request_firmware load failed\n");
249 pr_err("rtl8723au: Firmware %s not available\n", fw_name);
253 firmware_buf = kmemdup(fw->data, fw->size, GFP_KERNEL);
260 release_firmware(fw);
262 /* To Check Fw header. Added by tynli. 2009.12.04. */
263 pFwHdr = (struct rt_8723a_firmware_hdr *)firmware_buf;
265 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
266 pHalData->FirmwareSubVersion = pFwHdr->Subversion;
267 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
269 DBG_8723A("%s: fw_ver =%d fw_subver =%d sig = 0x%x\n",
270 __func__, pHalData->FirmwareVersion,
271 pHalData->FirmwareSubVersion, pHalData->FirmwareSignature);
274 pr_info("%sFirmware Version %d, SubVersion %d, Signature "
275 "0x%x\n", DRIVER_PREFIX, pHalData->FirmwareVersion,
276 pHalData->FirmwareSubVersion,
277 pHalData->FirmwareSignature);
279 if (IS_FW_HEADER_EXIST(pFwHdr)) {
280 /* Shift 32 bytes for FW header */
282 fw_size = fw_size - 32;
285 /* Suggested by Filen. If 8051 is running in RAM code, driver should
286 inform Fw to reset by itself, */
287 /* or it will cause download Fw fail. 2010.02.01. by tynli. */
288 if (rtl8723au_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
290 rtl8723a_FirmwareSelfReset(padapter);
291 rtl8723au_write8(padapter, REG_MCUFWDL, 0x00);
294 _FWDownloadEnable(padapter, true);
295 fwdl_start_time = jiffies;
297 /* reset the FWDL chksum */
298 rtl8723au_write8(padapter, REG_MCUFWDL,
299 rtl8723au_read8(padapter, REG_MCUFWDL) |
302 rtStatus = _WriteFW(padapter, buf, fw_size);
304 if (rtStatus == _SUCCESS ||
305 (jiffies_to_msecs(jiffies - fwdl_start_time) > 500 &&
306 writeFW_retry++ >= 3))
309 DBG_8723A("%s writeFW_retry:%u, time after fwdl_start_time:"
310 "%ums\n", __func__, writeFW_retry,
311 jiffies_to_msecs(jiffies - fwdl_start_time));
313 _FWDownloadEnable(padapter, false);
314 if (_SUCCESS != rtStatus) {
315 DBG_8723A("DL Firmware failed!\n");
319 rtStatus = _FWFreeToGo(padapter);
320 if (_SUCCESS != rtStatus) {
321 RT_TRACE(_module_hal_init_c_, _drv_err_,
322 ("DL Firmware failed!\n"));
325 RT_TRACE(_module_hal_init_c_, _drv_info_,
326 ("Firmware is ready to run!\n"));
333 void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter)
335 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
337 /* Init Fw LPS related. */
338 padapter->pwrctrlpriv.bFwCurrentInPSMode = false;
340 /* Init H2C counter. by tynli. 2009.12.09. */
341 pHalData->LastHMEBoxNum = 0;
345 /* Efuse related code */
348 hal_EfuseSwitchToBank(struct rtw_adapter *padapter, u8 bank)
353 DBG_8723A("%s: Efuse switch bank to %d\n", __func__, bank);
354 value32 = rtl8723au_read32(padapter, EFUSE_TEST);
358 value32 = (value32 & ~EFUSE_SEL_MASK) |
359 EFUSE_SEL(EFUSE_WIFI_SEL_0);
362 value32 = (value32 & ~EFUSE_SEL_MASK) |
363 EFUSE_SEL(EFUSE_BT_SEL_0);
366 value32 = (value32 & ~EFUSE_SEL_MASK) |
367 EFUSE_SEL(EFUSE_BT_SEL_1);
370 value32 = (value32 & ~EFUSE_SEL_MASK) |
371 EFUSE_SEL(EFUSE_BT_SEL_2);
374 value32 = (value32 & ~EFUSE_SEL_MASK) |
375 EFUSE_SEL(EFUSE_WIFI_SEL_0);
379 rtl8723au_write32(padapter, EFUSE_TEST, value32);
385 hal_ReadEFuse_WiFi(struct rtw_adapter *padapter,
386 u16 _offset, u16 _size_byte, u8 *pbuf)
391 u8 efuseHeader, efuseExtHdr, efuseData;
393 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
395 /* Do NOT excess total size of EFuse table.
396 Added by Roger, 2008.11.10. */
397 if ((_offset + _size_byte) > EFUSE_MAP_LEN_8723A) {
398 DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
399 __func__, _offset, _size_byte);
403 efuseTbl = kmalloc(EFUSE_MAP_LEN_8723A, GFP_KERNEL);
404 if (efuseTbl == NULL) {
405 DBG_8723A("%s: alloc efuseTbl fail!\n", __func__);
408 /* 0xff will be efuse default value instead of 0x00. */
409 memset(efuseTbl, 0xFF, EFUSE_MAP_LEN_8723A);
411 /* switch bank back to bank 0 for later BT and wifi use. */
412 hal_EfuseSwitchToBank(padapter, 0);
414 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
415 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
416 if (efuseHeader == 0xFF) {
417 DBG_8723A("%s: data end at address =%#x\n", __func__,
422 /* Check PG header for section num. */
423 if (EXT_HEADER(efuseHeader)) { /* extended header */
424 offset = GET_HDR_OFFSET_2_0(efuseHeader);
426 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseExtHdr);
427 if (ALL_WORDS_DISABLED(efuseExtHdr)) {
431 offset |= ((efuseExtHdr & 0xF0) >> 1);
432 wden = (efuseExtHdr & 0x0F);
434 offset = ((efuseHeader >> 4) & 0x0f);
435 wden = (efuseHeader & 0x0f);
438 if (offset < EFUSE_MAX_SECTION_8723A) {
440 /* Get word enable value from PG header */
442 addr = offset * PGPKT_DATA_SIZE;
443 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
444 /* Check word enable condition in the section */
445 if (!(wden & (0x01 << i))) {
446 ReadEFuseByte23a(padapter, eFuse_Addr++,
448 efuseTbl[addr] = efuseData;
450 ReadEFuseByte23a(padapter, eFuse_Addr++,
452 efuseTbl[addr + 1] = efuseData;
457 DBG_8723A(KERN_ERR "%s: offset(%d) is illegal!!\n",
459 eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
463 /* Copy from Efuse map to output pointer memory!!! */
464 for (i = 0; i < _size_byte; i++)
465 pbuf[i] = efuseTbl[_offset + i];
467 /* Calculate Efuse utilization */
468 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI,
469 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
470 used = eFuse_Addr - 1;
471 pHalData->EfuseUsedBytes = used;
477 hal_ReadEFuse_BT(struct rtw_adapter *padapter,
478 u16 _offset, u16 _size_byte, u8 *pbuf)
483 u8 efuseHeader, efuseExtHdr, efuseData;
486 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
488 /* Do NOT excess total size of EFuse table.
489 Added by Roger, 2008.11.10. */
490 if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
491 DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
492 __func__, _offset, _size_byte);
496 efuseTbl = kmalloc(EFUSE_BT_MAP_LEN, GFP_KERNEL);
497 if (efuseTbl == NULL) {
498 DBG_8723A("%s: efuseTbl malloc fail!\n", __func__);
501 /* 0xff will be efuse default value instead of 0x00. */
502 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
504 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
505 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total);
507 for (bank = 1; bank < EFUSE_MAX_BANK; bank++) {
508 if (hal_EfuseSwitchToBank(padapter, bank) == false) {
509 DBG_8723A("%s: hal_EfuseSwitchToBank Fail!!\n",
516 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
517 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
518 if (efuseHeader == 0xFF)
521 /* Check PG header for section num. */
522 if (EXT_HEADER(efuseHeader)) { /* extended header */
523 offset = GET_HDR_OFFSET_2_0(efuseHeader);
525 ReadEFuseByte23a(padapter, eFuse_Addr++,
527 if (ALL_WORDS_DISABLED(efuseExtHdr)) {
531 offset |= ((efuseExtHdr & 0xF0) >> 1);
532 wden = (efuseExtHdr & 0x0F);
534 offset = ((efuseHeader >> 4) & 0x0f);
535 wden = (efuseHeader & 0x0f);
538 if (offset < EFUSE_BT_MAX_SECTION) {
541 /* Get word enable value from PG header */
543 addr = offset * PGPKT_DATA_SIZE;
544 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
545 /* Check word enable condition in
547 if (!(wden & (0x01 << i))) {
548 ReadEFuseByte23a(padapter,
551 efuseTbl[addr] = efuseData;
553 ReadEFuseByte23a(padapter,
556 efuseTbl[addr + 1] = efuseData;
562 "%s: offset(%d) is illegal!!\n",
564 eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
568 if ((eFuse_Addr - 1) < total) {
569 DBG_8723A("%s: bank(%d) data end at %#x\n",
570 __func__, bank, eFuse_Addr - 1);
575 /* switch bank back to bank 0 for later BT and wifi use. */
576 hal_EfuseSwitchToBank(padapter, 0);
578 /* Copy from Efuse map to output pointer memory!!! */
579 for (i = 0; i < _size_byte; i++)
580 pbuf[i] = efuseTbl[_offset + i];
583 /* Calculate Efuse utilization. */
585 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
586 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
587 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1;
588 pHalData->BTEfuseUsedBytes = used;
595 rtl8723a_readefuse(struct rtw_adapter *padapter,
596 u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf)
598 if (efuseType == EFUSE_WIFI)
599 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf);
601 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf);
604 u16 rtl8723a_EfuseGetCurrentSize_WiFi(struct rtw_adapter *padapter)
607 u8 hoffset = 0, hworden = 0;
608 u8 efuse_data, word_cnts = 0;
609 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
611 efuse_addr = pHalData->EfuseUsedBytes;
613 DBG_8723A("%s: start_efuse_addr = 0x%X\n", __func__, efuse_addr);
615 /* switch bank back to bank 0 for later BT and wifi use. */
616 hal_EfuseSwitchToBank(padapter, 0);
618 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
619 if (efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data) ==
621 DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail! "
622 "addr = 0x%X !!\n", __func__, efuse_addr);
626 if (efuse_data == 0xFF)
629 if (EXT_HEADER(efuse_data)) {
630 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
632 efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data);
633 if (ALL_WORDS_DISABLED(efuse_data)) {
637 hoffset |= ((efuse_data & 0xF0) >> 1);
638 hworden = efuse_data & 0x0F;
640 hoffset = (efuse_data >> 4) & 0x0F;
641 hworden = efuse_data & 0x0F;
644 word_cnts = Efuse_CalculateWordCnts23a(hworden);
645 efuse_addr += (word_cnts * 2) + 1;
648 pHalData->EfuseUsedBytes = efuse_addr;
650 DBG_8723A("%s: CurrentSize =%d\n", __func__, efuse_addr);
655 u16 rtl8723a_EfuseGetCurrentSize_BT(struct rtw_adapter *padapter)
660 u8 hoffset = 0, hworden = 0;
661 u8 efuse_data, word_cnts = 0;
663 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
665 btusedbytes = pHalData->BTEfuseUsedBytes;
667 efuse_addr = (u16) ((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
668 startBank = (u8) (1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
670 DBG_8723A("%s: start from bank =%d addr = 0x%X\n", __func__, startBank,
673 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
674 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2);
676 for (bank = startBank; bank < EFUSE_MAX_BANK; bank++) {
677 if (hal_EfuseSwitchToBank(padapter, bank) == false) {
678 DBG_8723A(KERN_ERR "%s: switch bank(%d) Fail!!\n",
680 bank = EFUSE_MAX_BANK;
684 /* only when bank is switched we have to reset
686 if (bank != startBank)
689 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
690 if (efuse_OneByteRead23a(padapter, efuse_addr,
691 &efuse_data) == _FAIL) {
692 DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail!"
694 __func__, efuse_addr);
695 bank = EFUSE_MAX_BANK;
699 if (efuse_data == 0xFF)
702 if (EXT_HEADER(efuse_data)) {
703 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
705 efuse_OneByteRead23a(padapter, efuse_addr,
707 if (ALL_WORDS_DISABLED(efuse_data)) {
712 hoffset |= ((efuse_data & 0xF0) >> 1);
713 hworden = efuse_data & 0x0F;
715 hoffset = (efuse_data >> 4) & 0x0F;
716 hworden = efuse_data & 0x0F;
718 word_cnts = Efuse_CalculateWordCnts23a(hworden);
719 /* read next header */
720 efuse_addr += (word_cnts * 2) + 1;
723 /* Check if we need to check next bank efuse */
724 if (efuse_addr < retU2) {
725 break; /* don't need to check next bank. */
729 retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
730 pHalData->BTEfuseUsedBytes = retU2;
732 DBG_8723A("%s: CurrentSize =%d\n", __func__, retU2);
736 void rtl8723a_read_chip_version(struct rtw_adapter *padapter)
739 struct hal_version ChipVersion;
740 struct hal_data_8723a *pHalData;
742 pHalData = GET_HAL_DATA(padapter);
744 value32 = rtl8723au_read32(padapter, REG_SYS_CFG);
745 ChipVersion.ICType = CHIP_8723A;
746 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
747 ChipVersion.RFType = RF_TYPE_1T1R;
748 ChipVersion.VendorType =
749 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
750 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
752 /* For regulator mode. by tynli. 2011.01.14 */
753 pHalData->RegulatorMode = ((value32 & SPS_SEL) ?
754 RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
756 value32 = rtl8723au_read32(padapter, REG_GPIO_OUTSTS);
757 /* ROM code version. */
758 ChipVersion.ROMVer = ((value32 & RF_RL_ID) >> 20);
760 /* For multi-function consideration. Added by Roger, 2010.10.06. */
761 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
762 value32 = rtl8723au_read32(padapter, REG_MULTI_FUNC_CTRL);
763 pHalData->MultiFunc |=
764 ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
765 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
766 pHalData->MultiFunc |=
767 ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
768 pHalData->PolarityCtl =
769 ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT :
770 RT_POLARITY_LOW_ACT);
771 dump_chip_info23a(ChipVersion);
772 pHalData->VersionID = ChipVersion;
774 if (IS_1T2R(ChipVersion))
775 pHalData->rf_type = RF_1T2R;
776 else if (IS_2T2R(ChipVersion))
777 pHalData->rf_type = RF_2T2R;
779 pHalData->rf_type = RF_1T1R;
781 MSG_8723A("RF_Type is %x!!\n", pHalData->rf_type);
786 /* 20100209 Joseph: */
787 /* This function is used only for 92C to set REG_BCN_CTRL(0x550) register. */
788 /* We just reserve the value of the register in variable
789 pHalData->RegBcnCtrlVal and then operate */
790 /* the value of the register via atomic operation. */
791 /* This prevents from race condition when setting this register. */
792 /* The value of pHalData->RegBcnCtrlVal is initialized in
793 HwConfigureRTL8192CE() function. */
795 void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits)
799 val8 = rtl8723au_read8(padapter, REG_BCN_CTRL);
803 rtl8723au_write8(padapter, REG_BCN_CTRL, val8);
806 void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter)
808 rtl8723au_write16(padapter, REG_BCN_CTRL, 0x1010);
810 /* TODO: Remove these magic number */
811 rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0x6404); /* ms */
812 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
813 /* so don't set this register on STA mode. */
814 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
815 rtl8723au_write8(padapter, REG_DRVERLYINT,
816 DRIVER_EARLY_INT_TIME);
818 rtl8723au_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
820 /* Suggested by designer timchen. Change beacon AIFS to the
821 largest number beacause test chip does not contension before
822 sending beacon. by tynli. 2009.11.03 */
823 rtl8723au_write16(padapter, REG_BCNTCFG, 0x660F);
826 static void ResumeTxBeacon(struct rtw_adapter *padapter)
828 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
830 /* 2010.03.01. Marked by tynli. No need to call workitem beacause
831 we record the value */
832 /* which should be read from register to a global variable. */
834 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n"));
836 pHalData->RegFwHwTxQCtrl |= BIT(6);
837 rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
838 pHalData->RegFwHwTxQCtrl);
839 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff);
840 pHalData->RegReg542 |= BIT(0);
841 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
844 static void StopTxBeacon(struct rtw_adapter *padapter)
846 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
848 /* 2010.03.01. Marked by tynli. No need to call workitem beacause
849 we record the value */
850 /* which should be read from register to a global variable. */
852 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n"));
854 pHalData->RegFwHwTxQCtrl &= ~BIT(6);
855 rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
856 pHalData->RegFwHwTxQCtrl);
857 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64);
858 pHalData->RegReg542 &= ~BIT(0);
859 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
862 static void _BeaconFunctionEnable(struct rtw_adapter *padapter, u8 Enable,
865 SetBcnCtrlReg23a(padapter, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB,
867 rtl8723au_write8(padapter, REG_RD_CTRL + 1, 0x6F);
870 void rtl8723a_SetBeaconRelatedRegisters(struct rtw_adapter *padapter)
873 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
874 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
876 /* reset TSF, enable update TSF, correcting TSF On Beacon */
878 /* REG_BCN_INTERVAL */
881 /* REG_TBTT_PROHIBIT */
883 /* REG_BCN_MAX_ERR */
884 /* REG_BCNTCFG (0x510) */
885 /* REG_DUAL_TSF_RST */
886 /* REG_BCN_CTRL (0x550) */
891 rtl8723au_write16(padapter, REG_ATIMWND, 2);
894 /* Beacon interval (in unit of TU). */
896 rtl8723au_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
898 rtl8723a_InitBeaconParameters(padapter);
900 rtl8723au_write8(padapter, REG_SLOT, 0x09);
903 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
905 value32 = rtl8723au_read32(padapter, REG_TCR);
907 rtl8723au_write32(padapter, REG_TCR, value32);
910 rtl8723au_write32(padapter, REG_TCR, value32);
912 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
913 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE |
914 WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == true) {
915 rtl8723au_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
916 rtl8723au_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
919 _BeaconFunctionEnable(padapter, true, true);
921 ResumeTxBeacon(padapter);
922 SetBcnCtrlReg23a(padapter, DIS_BCNQ_SUB, 0);
925 void rtl8723a_SetHalODMVar(struct rtw_adapter *Adapter,
926 enum hal_odm_variable eVariable,
927 void *pValue1, bool bSet)
929 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
930 struct dm_odm_t *podmpriv = &pHalData->odmpriv;
932 case HAL_ODM_STA_INFO:
934 struct sta_info *psta = (struct sta_info *)pValue1;
937 DBG_8723A("Set STA_(%d) info\n", psta->mac_id);
938 ODM_CmnInfoPtrArrayHook23a(podmpriv,
939 ODM_CMNINFO_STA_STATUS,
942 DBG_8723A("Clean STA_(%d) info\n", psta->mac_id);
943 ODM_CmnInfoPtrArrayHook23a(podmpriv,
944 ODM_CMNINFO_STA_STATUS,
949 case HAL_ODM_P2P_STATE:
950 ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
952 case HAL_ODM_WIFI_DISPLAY_STATE:
953 ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
960 void rtl8723a_notch_filter(struct rtw_adapter *adapter, bool enable)
963 DBG_8723A("Enable notch filter\n");
964 rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
965 rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) |
968 DBG_8723A("Disable notch filter\n");
969 rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
970 rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) &
975 bool c2h_id_filter_ccx_8723a(u8 id)
978 if (id == C2H_CCX_TX_RPT)
984 int c2h_handler_8723a(struct rtw_adapter *padapter, struct c2h_evt_hdr *c2h_evt)
989 if (c2h_evt == NULL) {
990 DBG_8723A("%s c2h_evt is NULL\n", __func__);
995 switch (c2h_evt->id) {
997 RT_TRACE(_module_hal_init_c_, _drv_info_,
998 ("C2HCommandHandler: %s\n", c2h_evt->payload));
1001 case C2H_CCX_TX_RPT:
1002 handle_txrpt_ccx_8723a(padapter, c2h_evt->payload);
1004 case C2H_EXT_RA_RPT:
1006 case C2H_HW_INFO_EXCH:
1007 RT_TRACE(_module_hal_init_c_, _drv_info_,
1008 ("[BT], C2H_HW_INFO_EXCH\n"));
1009 for (i = 0; i < c2h_evt->plen; i++) {
1010 RT_TRACE(_module_hal_init_c_, _drv_info_,
1011 ("[BT], tmpBuf[%d]= 0x%x\n", i,
1012 c2h_evt->payload[i]));
1016 case C2H_C2H_H2C_TEST:
1017 RT_TRACE(_module_hal_init_c_, _drv_info_,
1018 ("[BT], C2H_H2C_TEST\n"));
1019 RT_TRACE(_module_hal_init_c_, _drv_info_,
1020 ("[BT], tmpBuf[0]/[1]/[2]/[3]/[4]= 0x%x/ 0x%x/ "
1021 "0x%x/ 0x%x/ 0x%x\n", c2h_evt->payload[0],
1022 c2h_evt->payload[1], c2h_evt->payload[2],
1023 c2h_evt->payload[3], c2h_evt->payload[4]));
1027 DBG_8723A("%s , Got C2H_BT_INFO \n", __func__);
1028 rtl8723a_fw_c2h_BT_info(padapter,
1029 c2h_evt->payload, c2h_evt->plen);
1041 void handle_txrpt_ccx_8723a(struct rtw_adapter *adapter, void *buf)
1043 struct txrpt_ccx_8723a *txrpt_ccx = buf;
1044 struct submit_ctx *pack_tx_ops = &adapter->xmitpriv.ack_tx_ops;
1046 if (txrpt_ccx->int_ccx && adapter->xmitpriv.ack_tx) {
1047 if (txrpt_ccx->pkt_ok)
1048 rtw23a_sctx_done_err(&pack_tx_ops,
1049 RTW_SCTX_DONE_SUCCESS);
1051 rtw23a_sctx_done_err(&pack_tx_ops,
1052 RTW_SCTX_DONE_CCX_PKT_FAIL);
1056 void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter)
1060 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1061 /* Let 8051 take control antenna settting */
1062 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1063 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1066 void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter)
1070 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1071 /* Let 8051 take control antenna settting */
1072 if (!(val & BIT(7))) {
1073 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1074 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1078 void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter)
1082 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1083 /* Let 8051 take control antenna settting */
1084 val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */
1085 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1088 void rtl8723a_init_default_value(struct rtw_adapter *padapter)
1090 struct hal_data_8723a *pHalData;
1091 struct dm_priv *pdmpriv;
1094 pHalData = GET_HAL_DATA(padapter);
1095 pdmpriv = &pHalData->dmpriv;
1097 /* init default value */
1098 pHalData->fw_ractrl = false;
1099 pHalData->bIQKInitialized = false;
1100 if (!padapter->pwrctrlpriv.bkeepfwalive)
1101 pHalData->LastHMEBoxNum = 0;
1103 pHalData->bIQKInitialized = false;
1105 /* init dm default value */
1106 pdmpriv->TM_Trigger = 0; /* for IQK */
1107 /* pdmpriv->binitialized = false; */
1108 /* pdmpriv->prv_traffic_idx = 3; */
1109 /* pdmpriv->initialize = 0; */
1111 pdmpriv->ThermalValue_HP_index = 0;
1112 for (i = 0; i < HP_THERMAL_NUM; i++)
1113 pdmpriv->ThermalValue_HP[i] = 0;
1115 /* init Efuse variables */
1116 pHalData->EfuseUsedBytes = 0;
1117 pHalData->BTEfuseUsedBytes = 0;
1120 u8 GetEEPROMSize8723A(struct rtw_adapter *padapter)
1125 cr = rtl8723au_read16(padapter, REG_9346CR);
1126 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
1127 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
1129 MSG_8723A("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
1136 /* LLT R/W/Init function */
1139 static int _LLTWrite(struct rtw_adapter *padapter, u32 address, u32 data)
1141 int status = _SUCCESS;
1143 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
1144 _LLT_OP(_LLT_WRITE_ACCESS);
1145 u16 LLTReg = REG_LLT_INIT;
1147 rtl8723au_write32(padapter, LLTReg, value);
1151 value = rtl8723au_read32(padapter, LLTReg);
1152 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) {
1156 if (count > POLLING_LLT_THRESHOLD) {
1157 RT_TRACE(_module_hal_init_c_, _drv_err_,
1158 ("Failed to polling write LLT done at "
1159 "address %d!\n", address));
1168 int InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary)
1170 int status = _SUCCESS;
1172 u32 txpktbuf_bndy = boundary;
1173 u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1175 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
1176 status = _LLTWrite(padapter, i, i + 1);
1177 if (status != _SUCCESS) {
1183 status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
1184 if (status != _SUCCESS) {
1188 /* Make the other pages as ring buffer */
1189 /* This ring buffer is used as beacon buffer if we config this
1190 MAC as two MAC transfer. */
1191 /* Otherwise used as local loopback buffer. */
1192 for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
1193 status = _LLTWrite(padapter, i, (i + 1));
1194 if (_SUCCESS != status) {
1199 /* Let last entry point to the start entry of ring buffer */
1200 status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
1201 if (status != _SUCCESS) {
1208 static void _DisableGPIO(struct rtw_adapter *padapter)
1210 /***************************************
1211 j. GPIO_PIN_CTRL 0x44[31:0]= 0x000
1212 k.Value = GPIO_PIN_CTRL[7:0]
1213 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write external PIN level
1214 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1215 n. LEDCFG 0x4C[15:0] = 0x8080
1216 ***************************************/
1220 /* 1. Disable GPIO[7:0] */
1221 rtl8723au_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
1222 value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1223 u4bTmp = value32 & 0x000000FF;
1224 value32 |= ((u4bTmp << 8) | 0x00FF0000);
1225 rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL, value32);
1228 /* <Roger_Notes> For RTL8723u multi-function configuration which
1229 was autoload from Efuse offset 0x0a and 0x0b, */
1230 /* WLAN HW GPIO[9], GPS HW GPIO[10] and BT HW GPIO[11]. */
1231 /* Added by Roger, 2010.10.07. */
1233 /* 2. Disable GPIO[8] and GPIO[12] */
1235 /* Configure all pins as input mode. */
1236 rtl8723au_write16(padapter, REG_GPIO_IO_SEL_2, 0x0000);
1237 value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL_2) & 0xFFFF001F;
1238 u4bTmp = value32 & 0x0000001F;
1239 /* Set pin 8, 10, 11 and pin 12 to output mode. */
1240 value32 |= ((u4bTmp << 8) | 0x001D0000);
1241 rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL_2, value32);
1243 /* 3. Disable LED0 & 1 */
1244 rtl8723au_write16(padapter, REG_LEDCFG0, 0x8080);
1245 } /* end of _DisableGPIO() */
1247 static void _DisableRFAFEAndResetBB8192C(struct rtw_adapter *padapter)
1249 /**************************************
1250 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1251 b. RF path 0 offset 0x00 = 0x00 disable RF
1252 c. APSD_CTRL 0x600[7:0] = 0x40
1253 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1254 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1255 ***************************************/
1258 rtl8723au_write8(padapter, REG_TXPAUSE, 0xFF);
1260 PHY_SetRFReg(padapter, RF_PATH_A, 0x0, bMaskByte0, 0x0);
1263 rtl8723au_write8(padapter, REG_APSD_CTRL, value8); /* 0x40 */
1265 /* Set BB reset at first */
1266 value8 = FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn;
1267 rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x16 */
1269 /* Set global reset. */
1270 value8 &= ~FEN_BB_GLB_RSTn;
1271 rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x14 */
1273 /* 2010/08/12 MH We need to set BB/GLBAL reset to save power
1276 /* RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n")); */
1279 static void _ResetDigitalProcedure1_92C(struct rtw_adapter *padapter,
1282 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1284 if (IS_FW_81xxC(padapter) && (pHalData->FirmwareVersion <= 0x20)) {
1285 /*****************************
1286 f. MCUFWDL 0x80[7:0]= 0 reset MCU ready status
1287 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU register, (8051 reset)
1288 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC register, DCORE
1289 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU register,
1291 ******************************/
1293 rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1295 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1296 /* reset MCU , 8051 */
1297 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1298 valu16 & ~FEN_CPUEN);
1300 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
1302 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1303 valu16 | FEN_HWPDN | FEN_ELDR);
1305 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1306 /* enable MCU , 8051 */
1307 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1308 valu16 | FEN_CPUEN);
1313 val8 = rtl8723au_read8(padapter, REG_MCUFWDL);
1315 /* 2010/08/12 MH For USB SS, we can not stop 8051 when we
1316 are trying to enter IPS/HW&SW radio off. For
1317 S3/S4/S5/Disable, we can stop 8051 because */
1318 /* we will init FW when power on again. */
1319 /* If we want to SS mode, we can not reset 8051. */
1320 if ((val8 & BIT(1)) && padapter->bFWReady) {
1321 /* IF fw in RAM code, do reset */
1322 /* 2010/08/25 MH Accordign to RD alfred's
1323 suggestion, we need to disable other */
1324 /* HRCV INT to influence 8051 reset. */
1325 rtl8723au_write8(padapter, REG_FWIMR, 0x20);
1326 /* 2011/02/15 MH According to Alex's
1327 suggestion, close mask to prevent
1328 incorrect FW write operation. */
1329 rtl8723au_write8(padapter, REG_FTIMR, 0x00);
1330 rtl8723au_write8(padapter, REG_FSIMR, 0x00);
1332 /* 8051 reset by self */
1333 rtl8723au_write8(padapter, REG_HMETFR + 3, 0x20);
1335 while ((retry_cnts++ < 100) &&
1336 (rtl8723au_read16(padapter, REG_SYS_FUNC_EN) &
1338 udelay(50); /* us */
1341 if (retry_cnts >= 100) {
1342 /* Reset MAC and Enable 8051 */
1343 rtl8723au_write8(padapter,
1344 REG_SYS_FUNC_EN + 1, 0x50);
1348 /* Reset MAC and Enable 8051 */
1349 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
1350 rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1354 /*****************************
1355 Without HW auto state machine
1356 g. SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1357 h. AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1358 i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1359 j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1360 ******************************/
1361 /* modify to 0x70A3 by Scott. */
1362 rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70A3);
1363 rtl8723au_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
1364 rtl8723au_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
1365 rtl8723au_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
1367 /* Disable all RF/BB power */
1368 rtl8723au_write8(padapter, REG_RF_CTRL, 0x00);
1372 static void _ResetDigitalProcedure2(struct rtw_adapter *padapter)
1374 /*****************************
1375 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1376 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1377 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1378 ******************************/
1379 /* modify to 0x70a3 by Scott. */
1380 rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70a3);
1381 /* modify to 0x82 by Scott. */
1382 rtl8723au_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82);
1385 static void _DisableAnalog(struct rtw_adapter *padapter, bool bWithoutHWSM)
1387 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1392 /*****************************
1393 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1394 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1395 r. When driver call disable, the ASIC will turn off remaining
1397 ******************************/
1399 rtl8723au_write8(padapter, REG_LDOA15_CTRL, 0x04);
1400 /* rtl8723au_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
1402 value8 = rtl8723au_read8(padapter, REG_LDOV12D_CTRL);
1403 value8 &= ~LDV12_EN;
1404 rtl8723au_write8(padapter, REG_LDOV12D_CTRL, value8);
1405 /* RT_TRACE(COMP_INIT, DBG_LOUD,
1406 (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n", value8)); */
1409 /*****************************
1410 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1411 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1412 ******************************/
1414 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
1417 rtl8723au_write8(padapter, REG_SPS0_CTRL, value8);
1420 /* value16 |= (APDM_HOST | FSM_HSUS |/PFM_ALDN); */
1421 /* 2010/08/31 According to Filen description, we need to
1422 use HW to shut down 8051 automatically. */
1423 /* Becasue suspend operatione need the asistance of 8051
1425 value16 = APDM_HOST | AFSM_HSUS | PFM_ALDN;
1427 value16 = APDM_HOST | AFSM_HSUS | PFM_ALDN;
1430 rtl8723au_write16(padapter, REG_APS_FSMCO, value16); /* 0x4802 */
1432 rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0e);
1435 /* HW Auto state machine */
1436 int CardDisableHWSM(struct rtw_adapter *padapter, u8 resetMCU)
1438 if (padapter->bSurpriseRemoved) {
1441 /* RF Off Sequence ==== */
1442 _DisableRFAFEAndResetBB8192C(padapter);
1444 /* ==== Reset digital sequence ====== */
1445 _ResetDigitalProcedure1_92C(padapter, false);
1447 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1448 _DisableGPIO(padapter);
1450 /* ==== Disable analog sequence === */
1451 _DisableAnalog(padapter, false);
1453 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1454 ("======> Card disable finished.\n"));
1459 /* without HW Auto state machine */
1460 int CardDisableWithoutHWSM(struct rtw_adapter *padapter)
1462 if (padapter->bSurpriseRemoved) {
1466 /* RF Off Sequence ==== */
1467 _DisableRFAFEAndResetBB8192C(padapter);
1469 /* ==== Reset digital sequence ====== */
1470 _ResetDigitalProcedure1_92C(padapter, true);
1472 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1473 _DisableGPIO(padapter);
1475 /* ==== Reset digital sequence ====== */
1476 _ResetDigitalProcedure2(padapter);
1478 /* ==== Disable analog sequence === */
1479 _DisableAnalog(padapter, true);
1481 /* RT_TRACE(COMP_INIT, DBG_LOUD,
1482 ("<====== Card Disable Without HWSM .\n")); */
1486 void Hal_InitPGData(struct rtw_adapter *padapter, u8 *PROMContent)
1488 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1490 if (false == pEEPROM->bautoload_fail_flag) { /* autoload OK. */
1491 if (!pEEPROM->EepromOrEfuse) {
1492 /* Read EFUSE real map to shadow. */
1493 EFUSE_ShadowMapUpdate23a(padapter, EFUSE_WIFI);
1494 memcpy((void *)PROMContent,
1495 (void *)pEEPROM->efuse_eeprom_data,
1498 } else { /* autoload fail */
1499 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1500 ("AutoLoad Fail reported from CR9346!!\n"));
1501 /* pHalData->AutoloadFailFlag = true; */
1502 /* update to default value 0xFF */
1503 if (false == pEEPROM->EepromOrEfuse)
1504 EFUSE_ShadowMapUpdate23a(padapter, EFUSE_WIFI);
1505 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data,
1510 void Hal_EfuseParseIDCode(struct rtw_adapter *padapter, u8 *hwinfo)
1512 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1513 /* struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); */
1516 /* Checl 0x8129 again for making sure autoload status!! */
1517 EEPROMId = le16_to_cpu(*((u16 *) hwinfo));
1518 if (EEPROMId != RTL_EEPROM_ID) {
1519 DBG_8723A("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
1520 pEEPROM->bautoload_fail_flag = true;
1522 pEEPROM->bautoload_fail_flag = false;
1525 RT_TRACE(_module_hal_init_c_, _drv_info_,
1526 ("EEPROM ID = 0x%04x\n", EEPROMId));
1529 static void Hal_EEValueCheck(u8 EEType, void *pInValue, void *pOutValue)
1535 pIn = (u8 *) pInValue;
1536 pOut = (u8 *) pOutValue;
1540 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
1541 ("EETYPE_TX_PWR, value =%d is invalid, set "
1542 "to default = 0x%x\n",
1543 *pIn, EEPROM_Default_TxPowerLevel));
1544 *pOut = EEPROM_Default_TxPowerLevel;
1554 Hal_ReadPowerValueFromPROM_8723A(struct txpowerinfo *pwrInfo,
1555 u8 *PROMContent, bool AutoLoadFail)
1557 u32 rfPath, eeAddr, group, rfPathMax = 1;
1559 memset(pwrInfo, 0, sizeof(*pwrInfo));
1562 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1563 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1564 pwrInfo->CCKIndex[rfPath][group] =
1565 EEPROM_Default_TxPowerLevel;
1566 pwrInfo->HT40_1SIndex[rfPath][group] =
1567 EEPROM_Default_TxPowerLevel;
1568 pwrInfo->HT40_2SIndexDiff[rfPath][group] =
1569 EEPROM_Default_HT40_2SDiff;
1570 pwrInfo->HT20IndexDiff[rfPath][group] =
1571 EEPROM_Default_HT20_Diff;
1572 pwrInfo->OFDMIndexDiff[rfPath][group] =
1573 EEPROM_Default_LegacyHTTxPowerDiff;
1574 pwrInfo->HT40MaxOffset[rfPath][group] =
1575 EEPROM_Default_HT40_PwrMaxOffset;
1576 pwrInfo->HT20MaxOffset[rfPath][group] =
1577 EEPROM_Default_HT20_PwrMaxOffset;
1580 pwrInfo->TSSI_A[0] = EEPROM_Default_TSSI;
1584 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1585 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1587 EEPROM_CCK_TX_PWR_INX_8723A + (rfPath * 3) + group;
1588 /* pwrInfo->CCKIndex[rfPath][group] =
1589 PROMContent[eeAddr]; */
1590 Hal_EEValueCheck(EETYPE_TX_PWR, &PROMContent[eeAddr],
1591 &pwrInfo->CCKIndex[rfPath][group]);
1592 eeAddr = EEPROM_HT40_1S_TX_PWR_INX_8723A +
1593 (rfPath * 3) + group;
1594 /* pwrInfo->HT40_1SIndex[rfPath][group] =
1595 PROMContent[eeAddr]; */
1596 Hal_EEValueCheck(EETYPE_TX_PWR, &PROMContent[eeAddr],
1597 &pwrInfo->HT40_1SIndex[rfPath][group]);
1601 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1602 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1603 pwrInfo->HT40_2SIndexDiff[rfPath][group] = 0;
1604 pwrInfo->HT20IndexDiff[rfPath][group] =
1606 [EEPROM_HT20_TX_PWR_INX_DIFF_8723A +
1607 group] >> (rfPath * 4)) & 0xF;
1608 /* 4bit sign number to 8 bit sign number */
1609 if (pwrInfo->HT20IndexDiff[rfPath][group] & BIT(3))
1610 pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0;
1612 pwrInfo->OFDMIndexDiff[rfPath][group] =
1613 (PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF_8723A +
1614 group] >> (rfPath * 4)) & 0xF;
1616 pwrInfo->HT40MaxOffset[rfPath][group] =
1617 (PROMContent[EEPROM_HT40_MAX_PWR_OFFSET_8723A +
1618 group] >> (rfPath * 4)) & 0xF;
1620 pwrInfo->HT20MaxOffset[rfPath][group] =
1621 (PROMContent[EEPROM_HT20_MAX_PWR_OFFSET_8723A +
1622 group] >> (rfPath * 4)) & 0xF;
1626 pwrInfo->TSSI_A[0] = PROMContent[EEPROM_TSSI_A_8723A];
1629 static u8 Hal_GetChnlGroup(u8 chnl)
1633 if (chnl < 3) /* Cjanel 1-3 */
1635 else if (chnl < 9) /* Channel 4-9 */
1637 else /* Channel 10-14 */
1644 Hal_EfuseParsetxpowerinfo_8723A(struct rtw_adapter *padapter,
1645 u8 *PROMContent, bool AutoLoadFail)
1647 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1648 struct txpowerinfo pwrInfo;
1649 u8 rfPath, ch, group, rfPathMax = 1;
1652 Hal_ReadPowerValueFromPROM_8723A(&pwrInfo, PROMContent, AutoLoadFail);
1653 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1654 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1655 group = Hal_GetChnlGroup(ch);
1657 pHalData->TxPwrLevelCck[rfPath][ch] =
1658 pwrInfo.CCKIndex[rfPath][group];
1659 pHalData->TxPwrLevelHT40_1S[rfPath][ch] =
1660 pwrInfo.HT40_1SIndex[rfPath][group];
1662 pHalData->TxPwrHt20Diff[rfPath][ch] =
1663 pwrInfo.HT20IndexDiff[rfPath][group];
1664 pHalData->TxPwrLegacyHtDiff[rfPath][ch] =
1665 pwrInfo.OFDMIndexDiff[rfPath][group];
1666 pHalData->PwrGroupHT20[rfPath][ch] =
1667 pwrInfo.HT20MaxOffset[rfPath][group];
1668 pHalData->PwrGroupHT40[rfPath][ch] =
1669 pwrInfo.HT40MaxOffset[rfPath][group];
1671 pwr = pwrInfo.HT40_1SIndex[rfPath][group];
1672 diff = pwrInfo.HT40_2SIndexDiff[rfPath][group];
1674 pHalData->TxPwrLevelHT40_2S[rfPath][ch] =
1675 (pwr > diff) ? (pwr - diff) : 0;
1678 for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) {
1679 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1680 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1681 ("RF(%u)-Ch(%u) [CCK / HT40_1S / HT40_2S] = "
1682 "[0x%x / 0x%x / 0x%x]\n",
1684 pHalData->TxPwrLevelCck[rfPath][ch],
1685 pHalData->TxPwrLevelHT40_1S[rfPath][ch],
1686 pHalData->TxPwrLevelHT40_2S[rfPath][ch]));
1690 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1691 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1692 ("RF-A Ht20 to HT40 Diff[%u] = 0x%x(%d)\n", ch,
1693 pHalData->TxPwrHt20Diff[RF_PATH_A][ch],
1694 pHalData->TxPwrHt20Diff[RF_PATH_A][ch]));
1696 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++)
1697 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1698 ("RF-A Legacy to Ht40 Diff[%u] = 0x%x\n", ch,
1699 pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch]));
1700 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1701 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1702 ("RF-B Ht20 to HT40 Diff[%u] = 0x%x(%d)\n", ch,
1703 pHalData->TxPwrHt20Diff[RF_PATH_B][ch],
1704 pHalData->TxPwrHt20Diff[RF_PATH_B][ch]));
1706 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++)
1707 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1708 ("RF-B Legacy to HT40 Diff[%u] = 0x%x\n", ch,
1709 pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch]));
1710 if (!AutoLoadFail) {
1711 struct registry_priv *registry_par = &padapter->registrypriv;
1712 if (registry_par->regulatory_tid == 0xff) {
1713 if (PROMContent[RF_OPTION1_8723A] == 0xff)
1714 pHalData->EEPROMRegulatory = 0;
1716 pHalData->EEPROMRegulatory =
1717 PROMContent[RF_OPTION1_8723A] & 0x7;
1719 pHalData->EEPROMRegulatory =
1720 registry_par->regulatory_tid;
1723 pHalData->EEPROMRegulatory = 0;
1725 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1726 ("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory));
1729 pHalData->bTXPowerDataReadFromEEPORM = true;
1733 Hal_EfuseParseBTCoexistInfo_8723A(struct rtw_adapter *padapter,
1734 u8 *hwinfo, bool AutoLoadFail)
1736 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1740 if (!AutoLoadFail) {
1741 tmpu4 = rtl8723au_read32(padapter, REG_MULTI_FUNC_CTRL);
1742 if (tmpu4 & BT_FUNC_EN)
1743 pHalData->EEPROMBluetoothCoexist = 1;
1745 pHalData->EEPROMBluetoothCoexist = 0;
1746 pHalData->EEPROMBluetoothType = BT_RTL8723A;
1748 /* The following need to be checked with newer version of */
1750 tempval = hwinfo[RF_OPTION4_8723A];
1751 pHalData->EEPROMBluetoothAntNum = (tempval & 0x1);
1752 pHalData->EEPROMBluetoothAntIsolation = ((tempval & 0x10) >> 4);
1753 pHalData->EEPROMBluetoothRadioShared = ((tempval & 0x20) >> 5);
1755 pHalData->EEPROMBluetoothCoexist = 0;
1756 pHalData->EEPROMBluetoothType = BT_RTL8723A;
1757 pHalData->EEPROMBluetoothAntNum = Ant_x2;
1758 pHalData->EEPROMBluetoothAntIsolation = 0;
1759 pHalData->EEPROMBluetoothRadioShared = BT_Radio_Shared;
1762 rtl8723a_BT_init_hal_vars(padapter);
1766 Hal_EfuseParseEEPROMVer(struct rtw_adapter *padapter,
1767 u8 *hwinfo, bool AutoLoadFail)
1769 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1772 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723A];
1774 pHalData->EEPROMVersion = 1;
1775 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1776 ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
1777 pHalData->EEPROMVersion));
1781 rtl8723a_EfuseParseChnlPlan(struct rtw_adapter *padapter,
1782 u8 *hwinfo, bool AutoLoadFail)
1784 padapter->mlmepriv.ChannelPlan =
1785 hal_com_get_channel_plan23a(padapter, hwinfo ?
1786 hwinfo[EEPROM_ChannelPlan_8723A]:0xFF,
1787 padapter->registrypriv.channel_plan,
1788 RT_CHANNEL_DOMAIN_WORLD_WIDE_13,
1791 DBG_8723A("mlmepriv.ChannelPlan = 0x%02x\n",
1792 padapter->mlmepriv.ChannelPlan);
1796 Hal_EfuseParseCustomerID(struct rtw_adapter *padapter,
1797 u8 *hwinfo, bool AutoLoadFail)
1799 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1801 if (!AutoLoadFail) {
1802 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723A];
1803 pHalData->EEPROMSubCustomerID =
1804 hwinfo[EEPROM_SubCustomID_8723A];
1806 pHalData->EEPROMCustomerID = 0;
1807 pHalData->EEPROMSubCustomerID = 0;
1809 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1810 ("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID));
1811 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1812 ("EEPROM SubCustomer ID: 0x%02x\n",
1813 pHalData->EEPROMSubCustomerID));
1817 Hal_EfuseParseAntennaDiversity(struct rtw_adapter *padapter,
1818 u8 *hwinfo, bool AutoLoadFail)
1823 Hal_EfuseParseRateIndicationOption(struct rtw_adapter *padapter,
1824 u8 *hwinfo, bool AutoLoadFail)
1829 Hal_EfuseParseXtal_8723A(struct rtw_adapter *pAdapter,
1830 u8 *hwinfo, u8 AutoLoadFail)
1832 struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1834 if (!AutoLoadFail) {
1835 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_K_8723A];
1836 if (pHalData->CrystalCap == 0xFF)
1837 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723A;
1839 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723A;
1841 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1842 ("%s: CrystalCap = 0x%2x\n", __func__,
1843 pHalData->CrystalCap));
1847 Hal_EfuseParseThermalMeter_8723A(struct rtw_adapter *padapter,
1848 u8 *PROMContent, bool AutoloadFail)
1850 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1853 /* ThermalMeter from EEPROM */
1856 pHalData->EEPROMThermalMeter =
1857 PROMContent[EEPROM_THERMAL_METER_8723A];
1859 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
1861 if ((pHalData->EEPROMThermalMeter == 0xff) || AutoloadFail) {
1862 pHalData->bAPKThermalMeterIgnore = true;
1863 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
1866 DBG_8723A("%s: ThermalMeter = 0x%x\n", __func__,
1867 pHalData->EEPROMThermalMeter);
1870 static void rtl8723a_cal_txdesc_chksum(struct tx_desc *ptxdesc)
1872 u16 *usPtr = (u16 *) ptxdesc;
1873 u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
1878 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
1880 for (index = 0; index < count; index++) {
1881 checksum ^= le16_to_cpu(*(usPtr + index));
1884 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
1888 * Description: In normal chip, we should send some packet to Hw which
1889 * will be used by Fw in FW LPS mode. The function is to fill the Tx
1890 * descriptor of this packets, then
1892 /* Fw can tell Hw to send these packet derectly. */
1893 /* Added by tynli. 2009.10.15. */
1895 void rtl8723a_fill_fake_txdesc(struct rtw_adapter *padapter, u8 *pDesc,
1896 u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull)
1898 struct tx_desc *ptxdesc;
1900 /* Clear all status */
1901 ptxdesc = (struct tx_desc *)pDesc;
1902 memset(pDesc, 0, TXDESC_SIZE);
1905 /* own, bFirstSeg, bLastSeg; */
1906 ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
1908 /* 32 bytes for TX Desc */
1909 ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) <<
1910 OFFSET_SHT) & 0x00ff0000);
1912 /* Buffer size + command header */
1913 ptxdesc->txdw0 |= cpu_to_le32(BufferLen & 0x0000ffff);
1916 /* Fixed queue of Mgnt queue */
1917 ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT << QSEL_SHT) & 0x00001f00);
1919 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed
1920 to error vlaue by Hw. */
1922 ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
1924 /* Hw set sequence number */
1925 ptxdesc->txdw4 |= cpu_to_le32(BIT(7));
1926 /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
1927 ptxdesc->txdw3 |= cpu_to_le32((8 << 28));
1930 if (true == IsBTQosNull) {
1931 ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
1935 ptxdesc->txdw4 |= cpu_to_le32(BIT(8)); /* driver uses rate */
1937 /* USB interface drop packet if the checksum of descriptor isn't
1939 /* Using this checksum can let hardware recovery from packet bulk
1940 out error (e.g. Cancel URC, Bulk out error.). */
1941 rtl8723a_cal_txdesc_chksum(ptxdesc);
1944 void hw_var_set_opmode(struct rtw_adapter *padapter, u8 mode)
1948 if (mode == MSR_INFRA || mode == MSR_NOLINK) {
1949 StopTxBeacon(padapter);
1951 /* disable atim wnd */
1952 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM;
1953 SetBcnCtrlReg23a(padapter, val8, ~val8);
1954 } else if (mode == MSR_ADHOC) {
1955 ResumeTxBeacon(padapter);
1957 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB;
1958 SetBcnCtrlReg23a(padapter, val8, ~val8);
1959 } else if (mode == MSR_AP) {
1960 /* add NULL Data and BT NULL Data Packets to FW RSVD Page */
1961 rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(padapter);
1963 ResumeTxBeacon(padapter);
1965 val8 = DIS_TSF_UDT | DIS_BCNQ_SUB;
1966 SetBcnCtrlReg23a(padapter, val8, ~val8);
1969 /* rtl8723au_write32(padapter, REG_RCR, 0x70002a8e);
1970 CBSSID_DATA must set to 0 */
1971 /* CBSSID_DATA must set to 0 */
1972 rtl8723au_write32(padapter, REG_RCR, 0x7000228e);
1973 /* enable to rx data frame */
1974 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
1975 /* enable to rx ps-poll */
1976 rtl8723au_write16(padapter, REG_RXFLTMAP1, 0x0400);
1978 /* Beacon Control related register for first time */
1980 rtl8723au_write8(padapter, REG_BCNDMATIM, 0x02);
1982 rtl8723au_write8(padapter, REG_DRVERLYINT, 0x05);
1983 /* 10ms for port0 */
1984 rtl8723au_write8(padapter, REG_ATIMWND, 0x0a);
1985 rtl8723au_write16(padapter, REG_BCNTCFG, 0x00);
1986 rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
1987 /* +32767 (~32ms) */
1988 rtl8723au_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
1991 rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
1993 /* enable BCN Function */
1994 /* don't enable update TSF (due to TSF update when
1995 beacon/probe rsp are received) */
1996 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION |
1997 EN_TXBCN_RPT | DIS_BCNQ_SUB;
1998 SetBcnCtrlReg23a(padapter, val8, ~val8);
2001 val8 = rtl8723au_read8(padapter, MSR);
2002 val8 = (val8 & 0xC) | mode;
2003 rtl8723au_write8(padapter, MSR, val8);
2006 void hw_var_set_macaddr(struct rtw_adapter *padapter, u8 *val)
2011 reg_macid = REG_MACID;
2013 for (idx = 0; idx < 6; idx++)
2014 rtl8723au_write8(padapter, (reg_macid + idx), val[idx]);
2017 void hw_var_set_bssid(struct rtw_adapter *padapter, u8 *val)
2022 reg_bssid = REG_BSSID;
2024 for (idx = 0; idx < 6; idx++)
2025 rtl8723au_write8(padapter, (reg_bssid + idx), val[idx]);
2028 void hw_var_set_correct_tsf(struct rtw_adapter *padapter)
2032 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2033 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2035 /* tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue %
2036 (pmlmeinfo->bcn_interval*1024)) - 1024; us */
2037 tsf = pmlmeext->TSFValue -
2038 do_div(pmlmeext->TSFValue,
2039 (pmlmeinfo->bcn_interval * 1024)) - 1024; /* us */
2041 if (((pmlmeinfo->state & 0x03) == MSR_ADHOC) ||
2042 ((pmlmeinfo->state & 0x03) == MSR_AP)) {
2043 /* pHalData->RegTxPause |= STOP_BCNQ;BIT(6) */
2044 /* rtl8723au_write8(padapter, REG_TXPAUSE,
2045 (rtl8723au_read8(Adapter, REG_TXPAUSE)|BIT(6))); */
2046 StopTxBeacon(padapter);
2049 reg_tsftr = REG_TSFTR;
2051 /* disable related TSF function */
2052 SetBcnCtrlReg23a(padapter, 0, EN_BCN_FUNCTION);
2054 rtl8723au_write32(padapter, reg_tsftr, tsf);
2055 rtl8723au_write32(padapter, reg_tsftr + 4, tsf >> 32);
2057 /* enable related TSF function */
2058 SetBcnCtrlReg23a(padapter, EN_BCN_FUNCTION, 0);
2060 if (((pmlmeinfo->state & 0x03) == MSR_ADHOC) ||
2061 ((pmlmeinfo->state & 0x03) == MSR_AP))
2062 ResumeTxBeacon(padapter);
2065 void hw_var_set_mlme_disconnect(struct rtw_adapter *padapter)
2067 /* reject all data frames */
2068 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
2071 rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
2073 /* disable update TSF */
2074 SetBcnCtrlReg23a(padapter, DIS_TSF_UDT, 0);
2077 void hw_var_set_mlme_join(struct rtw_adapter *padapter, u8 type)
2079 u8 RetryLimit = 0x30;
2081 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
2082 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
2084 if (type == 0) { /* prepare to join */
2087 /* enable to rx data frame.Accept all data frame */
2088 /* rtl8723au_write32(padapter, REG_RCR,
2089 rtl8723au_read32(padapter, REG_RCR)|RCR_ADF); */
2090 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2092 v32 = rtl8723au_read32(padapter, REG_RCR);
2093 v32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN;
2094 rtl8723au_write32(padapter, REG_RCR, v32);
2096 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
2098 (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
2099 else /* Ad-hoc Mode */
2101 } else if (type == 1) { /* joinbss_event callback when join res < 0 */
2102 /* config RCR to receive different BSSID & not to
2103 receive data frame during linking */
2104 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
2105 } else if (type == 2) { /* sta add event callback */
2106 /* enable update TSF */
2107 SetBcnCtrlReg23a(padapter, 0, DIS_TSF_UDT);
2109 if (check_fwstate(pmlmepriv,
2110 WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
2111 /* fixed beacon issue for 8191su........... */
2112 rtl8723au_write8(padapter, 0x542, 0x02);
2117 rtl8723au_write16(padapter, REG_RL,
2118 RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit <<
2119 RETRY_LIMIT_LONG_SHIFT);
2123 /* prepare to join */
2124 rtl8723a_BT_wifiassociate_notify(padapter, true);
2127 /* joinbss_event callback when join res < 0 */
2128 rtl8723a_BT_wifiassociate_notify(padapter, false);
2131 /* sta add event callback */
2132 /* BT_WifiMediaStatusNotify(padapter, RT_MEDIA_CONNECT); */