1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL8821AE_REG_H__
31 #define __RTL8821AE_REG_H__
33 #define TXPKT_BUF_SELECT 0x69
34 #define RXPKT_BUF_SELECT 0xA5
35 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
37 #define REG_SYS_ISO_CTRL 0x0000
38 #define REG_SYS_FUNC_EN 0x0002
39 #define REG_APS_FSMCO 0x0004
40 #define REG_SYS_CLKR 0x0008
41 #define REG_9346CR 0x000A
42 #define REG_EE_VPD 0x000C
43 #define REG_AFE_MISC 0x0010
44 #define REG_SPS0_CTRL 0x0011
45 #define REG_SPS_OCP_CFG 0x0018
46 #define REG_RSV_CTRL 0x001C
47 #define REG_RF_CTRL 0x001F
48 #define REG_LDOA15_CTRL 0x0020
49 #define REG_LDOV12D_CTRL 0x0021
50 #define REG_LDOHCI12_CTRL 0x0022
51 #define REG_LPLDO_CTRL 0x0023
52 #define REG_AFE_XTAL_CTRL 0x0024
53 #define REG_AFE_LDO_CTRL 0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */
54 #define REG_AFE_PLL_CTRL 0x0028
55 #define REG_MAC_PHY_CTRL 0x002c
56 #define REG_EFUSE_CTRL 0x0030
57 #define REG_EFUSE_TEST 0x0034
58 #define REG_PWR_DATA 0x0038
59 #define REG_CAL_TIMER 0x003C
60 #define REG_ACLK_MON 0x003E
61 #define REG_GPIO_MUXCFG 0x0040
62 #define REG_GPIO_IO_SEL 0x0042
63 #define REG_MAC_PINMUX_CFG 0x0043
64 #define REG_GPIO_PIN_CTRL 0x0044
65 #define REG_GPIO_INTM 0x0048
66 #define REG_LEDCFG0 0x004C
67 #define REG_LEDCFG1 0x004D
68 #define REG_LEDCFG2 0x004E
69 #define REG_LEDCFG3 0x004F
70 #define REG_FSIMR 0x0050
71 #define REG_FSISR 0x0054
72 #define REG_HSIMR 0x0058
73 #define REG_HSISR 0x005c
74 #define REG_GPIO_PIN_CTRL_2 0x0060
75 #define REG_GPIO_IO_SEL_2 0x0062
76 #define REG_MULTI_FUNC_CTRL 0x0068
77 #define REG_GPIO_OUTPUT 0x006c
78 #define REG_OPT_CTRL 0x0074
79 #define REG_AFE_XTAL_CTRL_EXT 0x0078
80 #define REG_XCK_OUT_CTRL 0x007c
81 #define REG_MCUFWDL 0x0080
82 #define REG_WOL_EVENT 0x0081
83 #define REG_MCUTSTCFG 0x0084
86 #define REG_HIMR 0x00B0
87 #define REG_HISR 0x00B4
88 #define REG_HIMRE 0x00B8
89 #define REG_HISRE 0x00BC
91 #define REG_PMC_DBG_CTRL2 0x00CC
93 #define REG_EFUSE_ACCESS 0x00CF
95 #define REG_BIST_SCAN 0x00D0
96 #define REG_BIST_RPT 0x00D4
97 #define REG_BIST_ROM_RPT 0x00D8
98 #define REG_USB_SIE_INTF 0x00E0
99 #define REG_PCIE_MIO_INTF 0x00E4
100 #define REG_PCIE_MIO_INTD 0x00E8
101 #define REG_HPON_FSM 0x00EC
102 #define REG_SYS_CFG 0x00F0
103 #define REG_GPIO_OUTSTS 0x00F4
104 #define REG_SYS_CFG1 0x00FC
105 #define REG_ROM_VERSION 0x00FD
107 #define REG_CR 0x0100
108 #define REG_PBP 0x0104
109 #define REG_PKT_BUFF_ACCESS_CTRL 0x0106
110 #define REG_TRXDMA_CTRL 0x010C
111 #define REG_TRXFF_BNDY 0x0114
112 #define REG_TRXFF_STATUS 0x0118
113 #define REG_RXFF_PTR 0x011C
115 #define REG_CPWM 0x012F
116 #define REG_FWIMR 0x0130
117 #define REG_FWISR 0x0134
118 #define REG_PKTBUF_DBG_CTRL 0x0140
119 #define REG_PKTBUF_DBG_DATA_L 0x0144
120 #define REG_PKTBUF_DBG_DATA_H 0x0148
121 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2)
123 #define REG_TC0_CTRL 0x0150
124 #define REG_TC1_CTRL 0x0154
125 #define REG_TC2_CTRL 0x0158
126 #define REG_TC3_CTRL 0x015C
127 #define REG_TC4_CTRL 0x0160
128 #define REG_TCUNIT_BASE 0x0164
129 #define REG_MBIST_START 0x0174
130 #define REG_MBIST_DONE 0x0178
131 #define REG_MBIST_FAIL 0x017C
132 #define REG_32K_CTRL 0x0194
133 #define REG_C2HEVT_MSG_NORMAL 0x01A0
134 #define REG_C2HEVT_CLEAR 0x01AF
135 #define REG_C2HEVT_MSG_TEST 0x01B8
136 #define REG_MCUTST_1 0x01c0
137 #define REG_FMETHR 0x01C8
138 #define REG_HMETFR 0x01CC
139 #define REG_HMEBOX_0 0x01D0
140 #define REG_HMEBOX_1 0x01D4
141 #define REG_HMEBOX_2 0x01D8
142 #define REG_HMEBOX_3 0x01DC
144 #define REG_LLT_INIT 0x01E0
145 #define REG_BB_ACCEESS_CTRL 0x01E8
146 #define REG_BB_ACCESS_DATA 0x01EC
148 #define REG_HMEBOX_EXT_0 0x01F0
149 #define REG_HMEBOX_EXT_1 0x01F4
150 #define REG_HMEBOX_EXT_2 0x01F8
151 #define REG_HMEBOX_EXT_3 0x01FC
153 #define REG_RQPN 0x0200
154 #define REG_FIFOPAGE 0x0204
155 #define REG_TDECTRL 0x0208
156 #define REG_TXDMA_OFFSET_CHK 0x020C
157 #define REG_TXDMA_STATUS 0x0210
158 #define REG_RQPN_NPQ 0x0214
160 #define REG_RXDMA_AGG_PG_TH 0x0280
161 #define REG_FW_UPD_RDPTR 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
162 #define REG_RXDMA_CONTROL 0x0286 /* Control the RX DMA.*/
163 #define REG_RXPKT_NUM 0x0287 /* The number of packets in RXPKTBUF. */
165 #define REG_PCIE_CTRL_REG 0x0300
166 #define REG_INT_MIG 0x0304
167 #define REG_BCNQ_DESA 0x0308
168 #define REG_HQ_DESA 0x0310
169 #define REG_MGQ_DESA 0x0318
170 #define REG_VOQ_DESA 0x0320
171 #define REG_VIQ_DESA 0x0328
172 #define REG_BEQ_DESA 0x0330
173 #define REG_BKQ_DESA 0x0338
174 #define REG_RX_DESA 0x0340
176 #define REG_DBI_WDATA 0x0348
177 #define REG_DBI_RDATA 0x034C
178 #define REG_DBI_ADDR 0x0350
179 #define REG_DBI_FLAG 0x0352
180 #define REG_MDIO_WDATA 0x0354
181 #define REG_MDIO_RDATA 0x0356
182 #define REG_MDIO_CTL 0x0358
183 #define REG_DBG_SEL 0x0360
184 #define REG_PCIE_HRPWM 0x0361
185 #define REG_PCIE_HCPWM 0x0363
186 #define REG_UART_CTRL 0x0364
187 #define REG_WATCH_DOG 0x0368
188 #define REG_UART_TX_DESA 0x0370
189 #define REG_UART_RX_DESA 0x0378
192 #define REG_HDAQ_DESA_NODEF 0x0000
193 #define REG_CMDQ_DESA_NODEF 0x0000
195 #define REG_VOQ_INFORMATION 0x0400
196 #define REG_VIQ_INFORMATION 0x0404
197 #define REG_BEQ_INFORMATION 0x0408
198 #define REG_BKQ_INFORMATION 0x040C
199 #define REG_MGQ_INFORMATION 0x0410
200 #define REG_HGQ_INFORMATION 0x0414
201 #define REG_BCNQ_INFORMATION 0x0418
202 #define REG_TXPKT_EMPTY 0x041A
205 #define REG_CPU_MGQ_INFORMATION 0x041C
206 #define REG_FWHW_TXQ_CTRL 0x0420
207 #define REG_HWSEQ_CTRL 0x0423
208 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424
209 #define REG_TXPKTBUF_MGQ_BDNY 0x0425
210 #define REG_MULTI_BCNQ_EN 0x0426
211 #define REG_MULTI_BCNQ_OFFSET 0x0427
212 #define REG_SPEC_SIFS 0x0428
213 #define REG_RL 0x042A
214 #define REG_DARFRC 0x0430
215 #define REG_RARFRC 0x0438
216 #define REG_RRSR 0x0440
217 #define REG_ARFR0 0x0444
218 #define REG_ARFR1 0x044C
219 #define REG_CCK_CHECK 0x0454
220 #define REG_AMPDU_MAX_TIME 0x0456
221 #define REG_AGGLEN_LMT 0x0458
222 #define REG_AMPDU_MIN_SPACE 0x045C
223 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
224 #define REG_FAST_EDCA_CTRL 0x0460
225 #define REG_RD_RESP_PKT_TH 0x0463
226 #define REG_INIRTS_RATE_SEL 0x0480
227 #define REG_INIDATA_RATE_SEL 0x0484
228 #define REG_ARFR2 0x048C
229 #define REG_ARFR3 0x0494
230 #define REG_POWER_STATUS 0x04A4
231 #define REG_POWER_STAGE1 0x04B4
232 #define REG_POWER_STAGE2 0x04B8
233 #define REG_PKT_LIFE_TIME 0x04C0
234 #define REG_STBC_SETTING 0x04C4
235 #define REG_HT_SINGLE_AMPDU 0x04C7
236 #define REG_PROT_MODE_CTRL 0x04C8
237 #define REG_MAX_AGGR_NUM 0x04CA
238 #define REG_BAR_MODE_CTRL 0x04CC
239 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF
240 #define REG_EARLY_MODE_CONTROL 0x04D0
241 #define REG_NQOS_SEQ 0x04DC
242 #define REG_QOS_SEQ 0x04DE
243 #define REG_NEED_CPU_HANDLE 0x04E0
244 #define REG_PKT_LOSE_RPT 0x04E1
245 #define REG_PTCL_ERR_STATUS 0x04E2
246 #define REG_TX_RPT_CTRL 0x04EC
247 #define REG_TX_RPT_TIME 0x04F0
248 #define REG_DUMMY 0x04FC
250 #define REG_EDCA_VO_PARAM 0x0500
251 #define REG_EDCA_VI_PARAM 0x0504
252 #define REG_EDCA_BE_PARAM 0x0508
253 #define REG_EDCA_BK_PARAM 0x050C
254 #define REG_BCNTCFG 0x0510
255 #define REG_PIFS 0x0512
256 #define REG_RDG_PIFS 0x0513
257 #define REG_SIFS_CTX 0x0514
258 #define REG_SIFS_TRX 0x0516
259 #define REG_AGGR_BREAK_TIME 0x051A
260 #define REG_SLOT 0x051B
261 #define REG_TX_PTCL_CTRL 0x0520
262 #define REG_TXPAUSE 0x0522
263 #define REG_DIS_TXREQ_CLR 0x0523
264 #define REG_RD_CTRL 0x0524
265 #define REG_TBTT_PROHIBIT 0x0540
266 #define REG_RD_NAV_NXT 0x0544
267 #define REG_NAV_PROT_LEN 0x0546
268 #define REG_BCN_CTRL 0x0550
269 #define REG_USTIME_TSF 0x0551
270 #define REG_MBID_NUM 0x0552
271 #define REG_DUAL_TSF_RST 0x0553
272 #define REG_BCN_INTERVAL 0x0554
273 #define REG_MBSSID_BCN_SPACE 0x0554
274 #define REG_DRVERLYINT 0x0558
275 #define REG_BCNDMATIM 0x0559
276 #define REG_ATIMWND 0x055A
277 #define REG_BCN_MAX_ERR 0x055D
278 #define REG_RXTSF_OFFSET_CCK 0x055E
279 #define REG_RXTSF_OFFSET_OFDM 0x055F
280 #define REG_TSFTR 0x0560
281 #define REG_INIT_TSFTR 0x0564
282 #define REG_SECONDARY_CCA_CTRL 0x0577
283 #define REG_PSTIMER 0x0580
284 #define REG_TIMER0 0x0584
285 #define REG_TIMER1 0x0588
286 #define REG_ACMHWCTRL 0x05C0
287 #define REG_ACMRSTCTRL 0x05C1
288 #define REG_ACMAVG 0x05C2
289 #define REG_VO_ADMTIME 0x05C4
290 #define REG_VI_ADMTIME 0x05C6
291 #define REG_BE_ADMTIME 0x05C8
292 #define REG_EDCA_RANDOM_GEN 0x05CC
293 #define REG_NOA_DESC_SEL 0x05CF
294 #define REG_NOA_DESC_DURATION 0x05E0
295 #define REG_NOA_DESC_INTERVAL 0x05E4
296 #define REG_NOA_DESC_START 0x05E8
297 #define REG_NOA_DESC_COUNT 0x05EC
298 #define REG_SCH_TX_CMD 0x05F8
300 #define REG_APSD_CTRL 0x0600
301 #define REG_BWOPMODE 0x0603
302 #define REG_TCR 0x0604
303 #define REG_RCR 0x0608
304 #define REG_RX_PKT_LIMIT 0x060C
305 #define REG_RX_DLK_TIME 0x060D
306 #define REG_RX_DRVINFO_SZ 0x060F
308 #define REG_MACID 0x0610
309 #define REG_BSSID 0x0618
310 #define REG_MAR 0x0620
311 #define REG_MBIDCAMCFG 0x0628
313 #define REG_USTIME_EDCA 0x0638
314 #define REG_MAC_SPEC_SIFS 0x063A
315 #define REG_RESP_SIFS_CCK 0x063C
316 #define REG_RESP_SIFS_OFDM 0x063E
317 #define REG_ACKTO 0x0640
318 #define REG_CTS2TO 0x0641
319 #define REG_EIFS 0x0642
321 #define REG_NAV_CTRL 0x0650
322 #define REG_NAV_UPPER 0x0652
323 #define REG_BACAMCMD 0x0654
324 #define REG_BACAMCONTENT 0x0658
325 #define REG_LBDLY 0x0660
326 #define REG_FWDLY 0x0661
327 #define REG_RXERR_RPT 0x0664
328 #define REG_TRXPTCL_CTL 0x0668
330 #define REG_CAMCMD 0x0670
331 #define REG_CAMWRITE 0x0674
332 #define REG_CAMREAD 0x0678
333 #define REG_CAMDBG 0x067C
334 #define REG_SECCFG 0x0680
336 #define REG_WOW_CTRL 0x0690
337 #define REG_PSSTATUS 0x0691
338 #define REG_PS_RX_INFO 0x0692
339 #define REG_UAPSD_TID 0x0693
340 #define REG_LPNAV_CTRL 0x0694
341 #define REG_WKFMCAM_NUM 0x0698
342 #define REG_WKFMCAM_RWD 0x069C
343 #define REG_RXFLTMAP0 0x06A0
344 #define REG_RXFLTMAP1 0x06A2
345 #define REG_RXFLTMAP2 0x06A4
346 #define REG_BCN_PSR_RPT 0x06A8
347 #define REG_CALB32K_CTRL 0x06AC
348 #define REG_PKT_MON_CTRL 0x06B4
349 #define REG_BT_COEX_TABLE 0x06C0
350 #define REG_WMAC_RESP_TXINFO 0x06D8
352 #define REG_USB_INFO 0xFE17
353 #define REG_USB_SPECIAL_OPTION 0xFE55
354 #define REG_USB_DMA_AGG_TO 0xFE5B
355 #define REG_USB_AGG_TO 0xFE5C
356 #define REG_USB_AGG_TH 0xFE5D
358 #define REG_TEST_USB_TXQS 0xFE48
359 #define REG_TEST_SIE_VID 0xFE60
360 #define REG_TEST_SIE_PID 0xFE62
361 #define REG_TEST_SIE_OPTIONAL 0xFE64
362 #define REG_TEST_SIE_CHIRP_K 0xFE65
363 #define REG_TEST_SIE_PHY 0xFE66
364 #define REG_TEST_SIE_MAC_ADDR 0xFE70
365 #define REG_TEST_SIE_STRING 0xFE80
367 #define REG_NORMAL_SIE_VID 0xFE60
368 #define REG_NORMAL_SIE_PID 0xFE62
369 #define REG_NORMAL_SIE_OPTIONAL 0xFE64
370 #define REG_NORMAL_SIE_EP 0xFE65
371 #define REG_NORMAL_SIE_PHY 0xFE68
372 #define REG_NORMAL_SIE_MAC_ADDR 0xFE70
373 #define REG_NORMAL_SIE_STRING 0xFE80
375 #define CR9346 REG_9346CR
376 #define MSR (REG_CR + 2)
378 #define TSFR REG_TSFTR
380 #define MACIDR0 REG_MACID
381 #define MACIDR4 (REG_MACID + 4)
388 #define UNUSED_REGISTER 0x1BF
389 #define DCAM UNUSED_REGISTER
390 #define PSR UNUSED_REGISTER
391 #define BBADDR UNUSED_REGISTER
392 #define PHYDATAR UNUSED_REGISTER
394 #define INVALID_BBRF_VALUE 0x12345678
396 #define MAX_MSS_DENSITY_2T 0x13
397 #define MAX_MSS_DENSITY_1T 0x0A
399 #define CMDEEPROM_EN BIT(5)
400 #define CMDEEPROM_SEL BIT(4)
401 #define CMD9346CR_9356SEL BIT(4)
402 #define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)
403 #define AUTOLOAD_EFUSE CMDEEPROM_EN
405 #define GPIOSEL_GPIO 0
406 #define GPIOSEL_ENBT BIT(5)
408 #define GPIO_IN REG_GPIO_PIN_CTRL
409 #define GPIO_OUT (REG_GPIO_PIN_CTRL+1)
410 #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)
411 #define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
413 /* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
414 #define HSIMR_GPIO12_0_INT_EN BIT(0)
415 #define HSIMR_SPS_OCP_INT_EN BIT(5)
416 #define HSIMR_RON_INT_EN BIT(6)
417 #define HSIMR_PDN_INT_EN BIT(7)
418 #define HSIMR_GPIO9_INT_EN BIT(25)
422 * 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte)
424 #define HSISR_GPIO12_0_INT BIT(0)
425 #define HSISR_SPS_OCP_INT BIT(5)
426 #define HSISR_RON_INT_EN BIT(6)
427 #define HSISR_PDNINT BIT(7)
428 #define HSISR_GPIO9_INT BIT(25)
430 #define MSR_NOLINK 0x00
431 #define MSR_ADHOC 0x01
432 #define MSR_INFRA 0x02
435 #define RRSR_RSC_OFFSET 21
436 #define RRSR_SHORT_OFFSET 23
437 #define RRSR_RSC_BW_40M 0x600000
438 #define RRSR_RSC_UPSUBCHNL 0x400000
439 #define RRSR_RSC_LOWSUBCHNL 0x200000
440 #define RRSR_SHORT 0x800000
441 #define RRSR_1M BIT(0)
442 #define RRSR_2M BIT(1)
443 #define RRSR_5_5M BIT(2)
444 #define RRSR_11M BIT(3)
445 #define RRSR_6M BIT(4)
446 #define RRSR_9M BIT(5)
447 #define RRSR_12M BIT(6)
448 #define RRSR_18M BIT(7)
449 #define RRSR_24M BIT(8)
450 #define RRSR_36M BIT(9)
451 #define RRSR_48M BIT(10)
452 #define RRSR_54M BIT(11)
453 #define RRSR_MCS0 BIT(12)
454 #define RRSR_MCS1 BIT(13)
455 #define RRSR_MCS2 BIT(14)
456 #define RRSR_MCS3 BIT(15)
457 #define RRSR_MCS4 BIT(16)
458 #define RRSR_MCS5 BIT(17)
459 #define RRSR_MCS6 BIT(18)
460 #define RRSR_MCS7 BIT(19)
461 #define BRSR_ACKSHORTPMB BIT(23)
463 #define RATR_1M 0x00000001
464 #define RATR_2M 0x00000002
465 #define RATR_55M 0x00000004
466 #define RATR_11M 0x00000008
467 #define RATR_6M 0x00000010
468 #define RATR_9M 0x00000020
469 #define RATR_12M 0x00000040
470 #define RATR_18M 0x00000080
471 #define RATR_24M 0x00000100
472 #define RATR_36M 0x00000200
473 #define RATR_48M 0x00000400
474 #define RATR_54M 0x00000800
475 #define RATR_MCS0 0x00001000
476 #define RATR_MCS1 0x00002000
477 #define RATR_MCS2 0x00004000
478 #define RATR_MCS3 0x00008000
479 #define RATR_MCS4 0x00010000
480 #define RATR_MCS5 0x00020000
481 #define RATR_MCS6 0x00040000
482 #define RATR_MCS7 0x00080000
483 #define RATR_MCS8 0x00100000
484 #define RATR_MCS9 0x00200000
485 #define RATR_MCS10 0x00400000
486 #define RATR_MCS11 0x00800000
487 #define RATR_MCS12 0x01000000
488 #define RATR_MCS13 0x02000000
489 #define RATR_MCS14 0x04000000
490 #define RATR_MCS15 0x08000000
492 #define RATE_1M BIT(0)
493 #define RATE_2M BIT(1)
494 #define RATE_5_5M BIT(2)
495 #define RATE_11M BIT(3)
496 #define RATE_6M BIT(4)
497 #define RATE_9M BIT(5)
498 #define RATE_12M BIT(6)
499 #define RATE_18M BIT(7)
500 #define RATE_24M BIT(8)
501 #define RATE_36M BIT(9)
502 #define RATE_48M BIT(10)
503 #define RATE_54M BIT(11)
504 #define RATE_MCS0 BIT(12)
505 #define RATE_MCS1 BIT(13)
506 #define RATE_MCS2 BIT(14)
507 #define RATE_MCS3 BIT(15)
508 #define RATE_MCS4 BIT(16)
509 #define RATE_MCS5 BIT(17)
510 #define RATE_MCS6 BIT(18)
511 #define RATE_MCS7 BIT(19)
512 #define RATE_MCS8 BIT(20)
513 #define RATE_MCS9 BIT(21)
514 #define RATE_MCS10 BIT(22)
515 #define RATE_MCS11 BIT(23)
516 #define RATE_MCS12 BIT(24)
517 #define RATE_MCS13 BIT(25)
518 #define RATE_MCS14 BIT(26)
519 #define RATE_MCS15 BIT(27)
521 #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
522 #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\
523 RATR_24M| RATR_36M | RATR_48M | RATR_54M)
524 #define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\
525 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\
526 RATR_MCS6 | RATR_MCS7)
527 #define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\
528 RATR_MCS11| RATR_MCS12 | RATR_MCS13 |\
529 RATR_MCS14 | RATR_MCS15)
531 #define BW_OPMODE_20MHZ BIT(2)
532 #define BW_OPMODE_5G BIT(1)
533 #define BW_OPMODE_11J BIT(0)
535 #define CAM_VALID BIT(15)
536 #define CAM_NOTVALID 0x0000
537 #define CAM_USEDK BIT(5)
540 #define CAM_WEP40 0x01
541 #define CAM_TKIP 0x02
543 #define CAM_WEP104 0x05
545 #define TOTAL_CAM_ENTRY 32
546 #define HALF_CAM_ENTRY 16
548 #define CAM_WRITE BIT(16)
549 #define CAM_READ 0x00000000
550 #define CAM_POLLINIG BIT(31)
552 #define SCR_USEDK 0x01
553 #define SCR_TXSEC_ENABLE 0x02
554 #define SCR_RXSEC_ENABLE 0x04
556 #define WOW_PMEN BIT(0)
557 #define WOW_WOMEN BIT(1)
558 #define WOW_MAGIC BIT(2)
559 #define WOW_UWF BIT(3)
561 /*********************************************
563 **********************************************/
564 #define IMR_DISABLED 0x0
565 /* IMR DW0(0x0060-0063) Bit 0-31 */
566 #define IMR_TXCCK BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */
567 #define IMR_PSTIMEOUT BIT(29) /* Power Save Time Out Interrupt */
568 #define IMR_GTINT4 BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
569 #define IMR_GTINT3 BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
570 #define IMR_TBDER BIT(26) /* Transmit Beacon0 Error */
571 #define IMR_TBDOK BIT(25) /* Transmit Beacon0 OK */
572 #define IMR_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle indication interrupt */
573 #define IMR_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
574 #define IMR_BCNDOK0 BIT(16) /* Beacon Queue DMA OK0 */
575 #define IMR_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
576 #define IMR_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
577 #define IMR_ATIMEND BIT(12) /* CTWidnow End or ATIM Window End */
578 #define IMR_HISR1_IND_INT BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/
579 #define IMR_C2HCMD BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
580 #define IMR_CPWM2 BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
581 #define IMR_CPWM BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
582 #define IMR_HIGHDOK BIT(7) /* High Queue DMA OK */
583 #define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK */
584 #define IMR_BKDOK BIT(5) /* AC_BK DMA OK */
585 #define IMR_BEDOK BIT(4) /* AC_BE DMA OK */
586 #define IMR_VIDOK BIT(3) /* AC_VI DMA OK */
587 #define IMR_VODOK BIT(2) /* AC_VO DMA OK */
588 #define IMR_RDU BIT(1) /* Rx Descriptor Unavailable */
589 #define IMR_ROK BIT(0) /* Receive DMA OK */
591 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
592 #define IMR_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
593 #define IMR_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
594 #define IMR_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
595 #define IMR_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
596 #define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
597 #define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
598 #define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
599 #define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrupt 7 */
600 #define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrupt 6 */
601 #define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrupt 5 */
602 #define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrupt 4 */
603 #define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrupt 3 */
604 #define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrupt 2 */
605 #define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrupt 1 */
606 #define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */
607 #define IMR_TXERR BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */
608 #define IMR_RXERR BIT(10) /* Rx Error Flag INT Status, Write 1 clear */
609 #define IMR_TXFOVW BIT(9) /* Transmit FIFO Overflow */
610 #define IMR_RXFOVW BIT(8) /* Receive FIFO Overflow */
613 #define HWSET_MAX_SIZE 512
614 #define EFUSE_MAX_SECTION 64
615 #define EFUSE_REAL_CONTENT_LEN 256
616 #define EFUSE_OOB_PROTECT_BYTES 18 /* PG data exclude header, dummy 7 bytes from CP test and reserved 1byte.*/
619 #define EEPROM_DEFAULT_TSSI 0x0
620 #define EEPROM_DEFAULT_TXPOWERDIFF 0x0
621 #define EEPROM_DEFAULT_CRYSTALCAP 0x5
622 #define EEPROM_DEFAULT_BOARDTYPE 0x02
623 #define EEPROM_DEFAULT_TXPOWER 0x1010
624 #define EEPROM_DEFAULT_HT2T_TXPWR 0x10
626 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
627 #define EEPROM_DEFAULT_THERMALMETER 0x18
628 #define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0
629 #define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5
630 #define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
631 #define EEPROM_DEFAULT_HT40_2SDIFF 0x0
632 #define EEPROM_DEFAULT_HT20_DIFF 2
633 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
634 #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
635 #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
637 #define RF_OPTION1 0x79
638 #define RF_OPTION2 0x7A
639 #define RF_OPTION3 0x7B
640 #define RF_OPTION4 0xC3
642 #define EEPROM_DEFAULT_PID 0x1234
643 #define EEPROM_DEFAULT_VID 0x5678
644 #define EEPROM_DEFAULT_CUSTOMERID 0xAB
645 #define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD
646 #define EEPROM_DEFAULT_VERSION 0
648 #define EEPROM_CHANNEL_PLAN_FCC 0x0
649 #define EEPROM_CHANNEL_PLAN_IC 0x1
650 #define EEPROM_CHANNEL_PLAN_ETSI 0x2
651 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3
652 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4
653 #define EEPROM_CHANNEL_PLAN_MKK 0x5
654 #define EEPROM_CHANNEL_PLAN_MKK1 0x6
655 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
656 #define EEPROM_CHANNEL_PLAN_TELEC 0x8
657 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
658 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
659 #define EEPROM_CHANNEL_PLAN_NCC 0xB
660 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
662 #define EEPROM_CID_DEFAULT 0x0
663 #define EEPROM_CID_TOSHIBA 0x4
664 #define EEPROM_CID_CCX 0x10
665 #define EEPROM_CID_QMI 0x0D
666 #define EEPROM_CID_WHQL 0xFE
668 #define RTL_EEPROM_ID 0x8129
670 #define EEPROM_HPON 0x02
671 #define EEPROM_CLK 0x06
672 #define EEPROM_TESTR 0x08
675 #define EEPROM_TXPOWERCCK 0x10
676 #define EEPROM_TXPOWERHT40_1S 0x16
677 #define EEPROM_TXPOWERHT20DIFF 0x1B
678 #define EEPROM_TXPOWER_OFDMDIFF 0x1B
682 #define EEPROM_TX_PWR_INX 0x10
684 #define EEPROM_CHANNELPLAN 0xB8
685 #define EEPROM_XTAL_8821AE 0xB9
686 #define EEPROM_THERMAL_METER 0xBA
687 #define EEPROM_IQK_LCK_88E 0xBB
689 #define EEPROM_RF_BOARD_OPTION 0xC1
690 #define EEPROM_RF_FEATURE_OPTION_88E 0xC2
691 #define EEPROM_RF_BT_SETTING 0xC3
692 #define EEPROM_VERSION 0xC4
693 #define EEPROM_CUSTOMER_ID 0xC5
694 #define EEPROM_RF_ANTENNA_OPT_88E 0xC9
696 #define EEPROM_MAC_ADDR 0xD0
697 #define EEPROM_VID 0xD6
698 #define EEPROM_DID 0xD8
699 #define EEPROM_SVID 0xDA
700 #define EEPROM_SMID 0xDC
702 #define STOPBECON BIT(6)
703 #define STOPHIGHT BIT(5)
704 #define STOPMGT BIT(4)
705 #define STOPVO BIT(3)
706 #define STOPVI BIT(2)
707 #define STOPBE BIT(1)
708 #define STOPBK BIT(0)
710 #define RCR_APPFCS BIT(31)
711 #define RCR_APP_MIC BIT(30)
712 #define RCR_APP_ICV BIT(29)
713 #define RCR_APP_PHYST_RXFF BIT(28)
714 #define RCR_APP_BA_SSN BIT(27)
715 #define RCR_NONQOS_VHT BIT(26)
716 #define RCR_ENMBID BIT(24)
717 #define RCR_LSIGEN BIT(23)
718 #define RCR_MFBEN BIT(22)
719 #define RCR_HTC_LOC_CTRL BIT(14)
720 #define RCR_AMF BIT(13)
721 #define RCR_ACF BIT(12)
722 #define RCR_ADF BIT(11)
723 #define RCR_AICV BIT(9)
724 #define RCR_ACRC32 BIT(8)
725 #define RCR_CBSSID_BCN BIT(7)
726 #define RCR_CBSSID_DATA BIT(6)
727 #define RCR_CBSSID RCR_CBSSID_DATA
728 #define RCR_APWRMGT BIT(5)
729 #define RCR_ADD3 BIT(4)
730 #define RCR_AB BIT(3)
731 #define RCR_AM BIT(2)
732 #define RCR_APM BIT(1)
733 #define RCR_AAP BIT(0)
734 #define RCR_MXDMA_OFFSET 8
735 #define RCR_FIFO_OFFSET 13
737 #define RSV_CTRL 0x001C
738 #define RD_CTRL 0x0524
740 #define REG_USB_INFO 0xFE17
741 #define REG_USB_SPECIAL_OPTION 0xFE55
742 #define REG_USB_DMA_AGG_TO 0xFE5B
743 #define REG_USB_AGG_TO 0xFE5C
744 #define REG_USB_AGG_TH 0xFE5D
746 #define REG_USB_VID 0xFE60
747 #define REG_USB_PID 0xFE62
748 #define REG_USB_OPTIONAL 0xFE64
749 #define REG_USB_CHIRP_K 0xFE65
750 #define REG_USB_PHY 0xFE66
751 #define REG_USB_MAC_ADDR 0xFE70
752 #define REG_USB_HRPWM 0xFE58
753 #define REG_USB_HCPWM 0xFE57
755 #define SW18_FPWM BIT(3)
757 #define ISO_MD2PP BIT(0)
758 #define ISO_UA2USB BIT(1)
759 #define ISO_UD2CORE BIT(2)
760 #define ISO_PA2PCIE BIT(3)
761 #define ISO_PD2CORE BIT(4)
762 #define ISO_IP2MAC BIT(5)
763 #define ISO_DIOP BIT(6)
764 #define ISO_DIOE BIT(7)
765 #define ISO_EB2CORE BIT(8)
766 #define ISO_DIOR BIT(9)
768 #define PWC_EV25V BIT(14)
769 #define PWC_EV12V BIT(15)
771 #define FEN_BBRSTB BIT(0)
772 #define FEN_BB_GLB_RSTN BIT(1)
773 #define FEN_USBA BIT(2)
774 #define FEN_UPLL BIT(3)
775 #define FEN_USBD BIT(4)
776 #define FEN_DIO_PCIE BIT(5)
777 #define FEN_PCIEA BIT(6)
778 #define FEN_PPLL BIT(7)
779 #define FEN_PCIED BIT(8)
780 #define FEN_DIOE BIT(9)
781 #define FEN_CPUEN BIT(10)
782 #define FEN_DCORE BIT(11)
783 #define FEN_ELDR BIT(12)
784 #define FEN_DIO_RF BIT(13)
785 #define FEN_HWPDN BIT(14)
786 #define FEN_MREGEN BIT(15)
788 #define PFM_LDALL BIT(0)
789 #define PFM_ALDN BIT(1)
790 #define PFM_LDKP BIT(2)
791 #define PFM_WOWL BIT(3)
793 #define PDN_PL BIT(5)
794 #define APFM_ONMAC BIT(8)
795 #define APFM_OFF BIT(9)
796 #define APFM_RSM BIT(10)
797 #define AFSM_HSUS BIT(11)
798 #define AFSM_PCIE BIT(12)
799 #define APDM_MAC BIT(13)
800 #define APDM_HOST BIT(14)
801 #define APDM_HPDN BIT(15)
802 #define RDY_MACON BIT(16)
803 #define SUS_HOST BIT(17)
804 #define ROP_ALD BIT(20)
805 #define ROP_PWR BIT(21)
806 #define ROP_SPS BIT(22)
807 #define SOP_MRST BIT(25)
808 #define SOP_FUSE BIT(26)
809 #define SOP_ABG BIT(27)
810 #define SOP_AMB BIT(28)
811 #define SOP_RCK BIT(29)
812 #define SOP_A8M BIT(30)
813 #define XOP_BTCK BIT(31)
815 #define ANAD16V_EN BIT(0)
817 #define MACSLP BIT(4)
818 #define LOADER_CLK_EN BIT(5)
819 #define _80M_SSC_DIS BIT(7)
820 #define _80M_SSC_EN_HO BIT(8)
821 #define PHY_SSC_RSTB BIT(9)
822 #define SEC_CLK_EN BIT(10)
823 #define MAC_CLK_EN BIT(11)
824 #define SYS_CLK_EN BIT(12)
825 #define RING_CLK_EN BIT(13)
827 #define BOOT_FROM_EEPROM BIT(4)
828 #define EEPROM_EN BIT(5)
830 #define AFE_BGEN BIT(0)
831 #define AFE_MBEN BIT(1)
832 #define MAC_ID_EN BIT(7)
834 #define WLOCK_ALL BIT(0)
835 #define WLOCK_00 BIT(1)
836 #define WLOCK_04 BIT(2)
837 #define WLOCK_08 BIT(3)
838 #define WLOCK_40 BIT(4)
839 #define R_DIS_PRST_0 BIT(5)
840 #define R_DIS_PRST_1 BIT(6)
841 #define LOCK_ALL_EN BIT(7)
844 #define RF_RSTB BIT(1)
845 #define RF_SDMRSTB BIT(2)
847 #define LDA15_EN BIT(0)
848 #define LDA15_STBY BIT(1)
849 #define LDA15_OBUF BIT(2)
850 #define LDA15_REG_VOS BIT(3)
851 #define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
853 #define LDV12_EN BIT(0)
854 #define LDV12_SDBY BIT(1)
855 #define LPLDO_HSM BIT(2)
856 #define LPLDO_LSM_DIS BIT(3)
857 #define _LDV12_VADJ(x) (((x) & 0xF) << 4)
859 #define XTAL_EN BIT(0)
860 #define XTAL_BSEL BIT(1)
861 #define _XTAL_BOSC(x) (((x) & 0x3) << 2)
862 #define _XTAL_CADJ(x) (((x) & 0xF) << 4)
863 #define XTAL_GATE_USB BIT(8)
864 #define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
865 #define XTAL_GATE_AFE BIT(11)
866 #define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
867 #define XTAL_RF_GATE BIT(14)
868 #define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
869 #define XTAL_GATE_DIG BIT(17)
870 #define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
871 #define XTAL_BT_GATE BIT(20)
872 #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
873 #define _XTAL_GPIO(x) (((x) & 0x7) << 23)
875 #define CKDLY_AFE BIT(26)
876 #define CKDLY_USB BIT(27)
877 #define CKDLY_DIG BIT(28)
878 #define CKDLY_BT BIT(29)
880 #define APLL_EN BIT(0)
881 #define APLL_320_EN BIT(1)
882 #define APLL_FREF_SEL BIT(2)
883 #define APLL_EDGE_SEL BIT(3)
884 #define APLL_WDOGB BIT(4)
885 #define APLL_LPFEN BIT(5)
887 #define APLL_REF_CLK_13MHZ 0x1
888 #define APLL_REF_CLK_19_2MHZ 0x2
889 #define APLL_REF_CLK_20MHZ 0x3
890 #define APLL_REF_CLK_25MHZ 0x4
891 #define APLL_REF_CLK_26MHZ 0x5
892 #define APLL_REF_CLK_38_4MHZ 0x6
893 #define APLL_REF_CLK_40MHZ 0x7
895 #define APLL_320EN BIT(14)
896 #define APLL_80EN BIT(15)
897 #define APLL_1MEN BIT(24)
899 #define ALD_EN BIT(18)
900 #define EF_PD BIT(19)
901 #define EF_FLAG BIT(31)
903 #define EF_TRPT BIT(7)
904 #define LDOE25_EN BIT(31)
906 #define RSM_EN BIT(0)
907 #define Timer_EN BIT(4)
909 #define TRSW0EN BIT(2)
910 #define TRSW1EN BIT(3)
911 #define EROM_EN BIT(4)
913 #define EnUart BIT(8)
914 #define Uart_910 BIT(9)
915 #define EnPMAC BIT(10)
916 #define SIC_SWRST BIT(11)
917 #define EnSIC BIT(12)
918 #define SIC_23 BIT(13)
919 #define EnHDP BIT(14)
920 #define SIC_LBK BIT(15)
922 #define LED0PL BIT(4)
923 #define LED1PL BIT(12)
924 #define LED0DIS BIT(7)
926 #define MCUFWDL_EN BIT(0)
927 #define MCUFWDL_RDY BIT(1)
928 #define FWDL_CHKSUM_RPT BIT(2)
929 #define MACINI_RDY BIT(3)
930 #define BBINI_RDY BIT(4)
931 #define RFINI_RDY BIT(5)
932 #define WINTINI_RDY BIT(6)
933 #define CPRST BIT(23)
935 #define XCLK_VLD BIT(0)
936 #define ACLK_VLD BIT(1)
937 #define UCLK_VLD BIT(2)
938 #define PCLK_VLD BIT(3)
939 #define PCIRSTB BIT(4)
940 #define V15_VLD BIT(5)
941 #define TRP_B15V_EN BIT(7)
942 #define SIC_IDLE BIT(8)
943 #define BD_MAC2 BIT(9)
944 #define BD_MAC1 BIT(10)
945 #define IC_MACPHY_MODE BIT(11)
946 #define VENDOR_ID BIT(19)
947 #define PAD_HWPD_IDN BIT(22)
948 #define TRP_VAUX_EN BIT(23)
949 #define TRP_BT_EN BIT(24)
950 #define BD_PKG_SEL BIT(25)
951 #define BD_HCI_SEL BIT(26)
952 #define TYPE_ID BIT(27)
954 #define CHIP_VER_RTL_MASK 0xF000
955 #define CHIP_VER_RTL_SHIFT 12
957 #define REG_LBMODE (REG_CR + 3)
959 #define HCI_TXDMA_EN BIT(0)
960 #define HCI_RXDMA_EN BIT(1)
961 #define TXDMA_EN BIT(2)
962 #define RXDMA_EN BIT(3)
963 #define PROTOCOL_EN BIT(4)
964 #define SCHEDULE_EN BIT(5)
965 #define MACTXEN BIT(6)
966 #define MACRXEN BIT(7)
967 #define ENSWBCN BIT(8)
970 #define _NETTYPE(x) (((x) & 0x3) << 16)
971 #define MASK_NETTYPE 0x30000
972 #define NT_NO_LINK 0x0
973 #define NT_LINK_AD_HOC 0x1
974 #define NT_LINK_AP 0x2
977 #define _LBMODE(x) (((x) & 0xF) << 24)
978 #define MASK_LBMODE 0xF000000
979 #define LOOPBACK_NORMAL 0x0
980 #define LOOPBACK_IMMEDIATELY 0xB
981 #define LOOPBACK_MAC_DELAY 0x3
982 #define LOOPBACK_PHY 0x1
983 #define LOOPBACK_DMA 0x7
985 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
986 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
987 #define _PSRX_MASK 0xF
988 #define _PSTX_MASK 0xF0
990 #define _PSTX(x) ((x) << 4)
998 #define RXDMA_ARBBW_EN BIT(0)
999 #define RXSHFT_EN BIT(1)
1000 #define RXDMA_AGG_EN BIT(2)
1001 #define QS_VO_QUEUE BIT(8)
1002 #define QS_VI_QUEUE BIT(9)
1003 #define QS_BE_QUEUE BIT(10)
1004 #define QS_BK_QUEUE BIT(11)
1005 #define QS_MANAGER_QUEUE BIT(12)
1006 #define QS_HIGH_QUEUE BIT(13)
1008 #define HQSEL_VOQ BIT(0)
1009 #define HQSEL_VIQ BIT(1)
1010 #define HQSEL_BEQ BIT(2)
1011 #define HQSEL_BKQ BIT(3)
1012 #define HQSEL_MGTQ BIT(4)
1013 #define HQSEL_HIQ BIT(5)
1015 #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
1016 #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
1017 #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
1018 #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
1019 #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
1020 #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
1023 #define QUEUE_NORMAL 2
1024 #define QUEUE_HIGH 3
1026 #define _LLT_NO_ACTIVE 0x0
1027 #define _LLT_WRITE_ACCESS 0x1
1028 #define _LLT_READ_ACCESS 0x2
1030 #define _LLT_INIT_DATA(x) ((x) & 0xFF)
1031 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
1032 #define _LLT_OP(x) (((x) & 0x3) << 30)
1033 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
1035 #define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
1036 #define BB_WRITE_EN BIT(30)
1037 #define BB_READ_EN BIT(31)
1039 #define _HPQ(x) ((x) & 0xFF)
1040 #define _LPQ(x) (((x) & 0xFF) << 8)
1041 #define _PUBQ(x) (((x) & 0xFF) << 16)
1042 #define _NPQ(x) ((x) & 0xFF)
1044 #define HPQ_PUBLIC_DIS BIT(24)
1045 #define LPQ_PUBLIC_DIS BIT(25)
1046 #define LD_RQPN BIT(31)
1048 #define BCN_VALID BIT(16)
1049 #define BCN_HEAD(x) (((x) & 0xFF) << 8)
1050 #define BCN_HEAD_MASK 0xFF00
1052 #define BLK_DESC_NUM_SHIFT 4
1053 #define BLK_DESC_NUM_MASK 0xF
1055 #define DROP_DATA_EN BIT(9)
1057 #define EN_AMPDU_RTY_NEW BIT(7)
1059 #define _INIRTSMCS_SEL(x) ((x) & 0x3F)
1061 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1062 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1064 #define RATE_REG_BITMAP_ALL 0xFFFFF
1066 #define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
1068 #define _RRSR_RSC(x) (((x) & 0x3) << 21)
1069 #define RRSR_RSC_RESERVED 0x0
1070 #define RRSR_RSC_UPPER_SUBCHANNEL 0x1
1071 #define RRSR_RSC_LOWER_SUBCHANNEL 0x2
1072 #define RRSR_RSC_DUPLICATE_MODE 0x3
1074 #define USE_SHORT_G1 BIT(20)
1076 #define _AGGLMT_MCS0(x) ((x) & 0xF)
1077 #define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
1078 #define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
1079 #define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
1080 #define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
1081 #define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
1082 #define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
1083 #define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
1085 #define RETRY_LIMIT_SHORT_SHIFT 8
1086 #define RETRY_LIMIT_LONG_SHIFT 0
1088 #define _DARF_RC1(x) ((x) & 0x1F)
1089 #define _DARF_RC2(x) (((x) & 0x1F) << 8)
1090 #define _DARF_RC3(x) (((x) & 0x1F) << 16)
1091 #define _DARF_RC4(x) (((x) & 0x1F) << 24)
1092 #define _DARF_RC5(x) ((x) & 0x1F)
1093 #define _DARF_RC6(x) (((x) & 0x1F) << 8)
1094 #define _DARF_RC7(x) (((x) & 0x1F) << 16)
1095 #define _DARF_RC8(x) (((x) & 0x1F) << 24)
1097 #define _RARF_RC1(x) ((x) & 0x1F)
1098 #define _RARF_RC2(x) (((x) & 0x1F) << 8)
1099 #define _RARF_RC3(x) (((x) & 0x1F) << 16)
1100 #define _RARF_RC4(x) (((x) & 0x1F) << 24)
1101 #define _RARF_RC5(x) ((x) & 0x1F)
1102 #define _RARF_RC6(x) (((x) & 0x1F) << 8)
1103 #define _RARF_RC7(x) (((x) & 0x1F) << 16)
1104 #define _RARF_RC8(x) (((x) & 0x1F) << 24)
1106 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
1107 #define AC_PARAM_ECW_MAX_OFFSET 12
1108 #define AC_PARAM_ECW_MIN_OFFSET 8
1109 #define AC_PARAM_AIFS_OFFSET 0
1111 #define _AIFS(x) (x)
1112 #define _ECW_MAX_MIN(x) ((x) << 8)
1113 #define _TXOP_LIMIT(x) ((x) << 16)
1115 #define _BCNIFS(x) ((x) & 0xFF)
1116 #define _BCNECW(x) ((((x) & 0xF))<< 8)
1118 #define _LRL(x) ((x) & 0x3F)
1119 #define _SRL(x) (((x) & 0x3F) << 8)
1121 #define _SIFS_CCK_CTX(x) ((x) & 0xFF)
1122 #define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8);
1124 #define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
1125 #define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8);
1127 #define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
1129 #define DIS_EDCA_CNT_DWN BIT(11)
1131 #define EN_MBSSID BIT(1)
1132 #define EN_TXBCN_RPT BIT(2)
1133 #define EN_BCN_FUNCTION BIT(3)
1135 #define TSFTR_RST BIT(0)
1136 #define TSFTR1_RST BIT(1)
1138 #define STOP_BCNQ BIT(6)
1140 #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1141 #define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1143 #define AcmHw_HwEn BIT(0)
1144 #define AcmHw_BeqEn BIT(1)
1145 #define AcmHw_ViqEn BIT(2)
1146 #define AcmHw_VoqEn BIT(3)
1147 #define AcmHw_BeqStatus BIT(4)
1148 #define AcmHw_ViqStatus BIT(5)
1149 #define AcmHw_VoqStatus BIT(6)
1151 #define APSDOFF BIT(6)
1152 #define APSDOFF_STATUS BIT(7)
1154 #define BW_20MHZ BIT(2)
1156 #define RATE_BITMAP_ALL 0xFFFFF
1158 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1160 #define TSFRST BIT(0)
1161 #define DIS_GCLK BIT(1)
1162 #define PAD_SEL BIT(2)
1163 #define PWR_ST BIT(6)
1164 #define PWRBIT_OW_EN BIT(7)
1166 #define CFENDFORM BIT(9)
1174 #define APWRMGT BIT(5)
1175 #define CBSSID BIT(6)
1176 #define CBSSID_DATA BIT(6)
1177 #define CBSSID_BCN BIT(7)
1178 #define ACRC32 BIT(8)
1183 #define HTC_LOC_CTRL BIT(14)
1184 #define UC_DATA_EN BIT(16)
1185 #define BM_DATA_EN BIT(17)
1186 #define MFBEN BIT(22)
1187 #define LSIGEN BIT(23)
1188 #define EnMBID BIT(24)
1189 #define APP_BASSN BIT(27)
1190 #define APP_PHYSTS BIT(28)
1191 #define APP_ICV BIT(29)
1192 #define APP_MIC BIT(30)
1193 #define APP_FCS BIT(31)
1195 #define _MIN_SPACE(x) ((x) & 0x7)
1196 #define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1198 #define RXERR_TYPE_OFDM_PPDU 0
1199 #define RXERR_TYPE_OFDM_FALSE_ALARM 1
1200 #define RXERR_TYPE_OFDM_MPDU_OK 2
1201 #define RXERR_TYPE_OFDM_MPDU_FAIL 3
1202 #define RXERR_TYPE_CCK_PPDU 4
1203 #define RXERR_TYPE_CCK_FALSE_ALARM 5
1204 #define RXERR_TYPE_CCK_MPDU_OK 6
1205 #define RXERR_TYPE_CCK_MPDU_FAIL 7
1206 #define RXERR_TYPE_HT_PPDU 8
1207 #define RXERR_TYPE_HT_FALSE_ALARM 9
1208 #define RXERR_TYPE_HT_MPDU_TOTAL 10
1209 #define RXERR_TYPE_HT_MPDU_OK 11
1210 #define RXERR_TYPE_HT_MPDU_FAIL 12
1211 #define RXERR_TYPE_RX_FULL_DROP 15
1213 #define RXERR_COUNTER_MASK 0xFFFFF
1214 #define RXERR_RPT_RST BIT(27)
1215 #define _RXERR_RPT_SEL(type) ((type) << 28)
1217 #define SCR_TxUseDK BIT(0)
1218 #define SCR_RxUseDK BIT(1)
1219 #define SCR_TxEncEnable BIT(2)
1220 #define SCR_RxDecEnable BIT(3)
1221 #define SCR_SKByA2 BIT(4)
1222 #define SCR_NoSKMC BIT(5)
1223 #define SCR_TXBCUSEDK BIT(6)
1224 #define SCR_RXBCUSEDK BIT(7)
1226 #define XCLK_VLD BIT(0)
1227 #define ACLK_VLD BIT(1)
1228 #define UCLK_VLD BIT(2)
1229 #define PCLK_VLD BIT(3)
1230 #define PCIRSTB BIT(4)
1231 #define V15_VLD BIT(5)
1232 #define TRP_B15V_EN BIT(7)
1233 #define SIC_IDLE BIT(8)
1234 #define BD_MAC2 BIT(9)
1235 #define BD_MAC1 BIT(10)
1236 #define IC_MACPHY_MODE BIT(11)
1237 #define BT_FUNC BIT(16)
1238 #define VENDOR_ID BIT(19)
1239 #define PAD_HWPD_IDN BIT(22)
1240 #define TRP_VAUX_EN BIT(23)
1241 #define TRP_BT_EN BIT(24)
1242 #define BD_PKG_SEL BIT(25)
1243 #define BD_HCI_SEL BIT(26)
1244 #define TYPE_ID BIT(27)
1246 #define USB_IS_HIGH_SPEED 0
1247 #define USB_IS_FULL_SPEED 1
1248 #define USB_SPEED_MASK BIT(5)
1250 #define USB_NORMAL_SIE_EP_MASK 0xF
1251 #define USB_NORMAL_SIE_EP_SHIFT 4
1253 #define USB_TEST_EP_MASK 0x30
1254 #define USB_TEST_EP_SHIFT 4
1256 #define USB_AGG_EN BIT(3)
1258 #define MAC_ADDR_LEN 6
1259 #define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/
1261 #define POLLING_LLT_THRESHOLD 20
1262 #define POLLING_READY_TIMEOUT_COUNT 3000
1264 #define MAX_MSS_DENSITY_2T 0x13
1265 #define MAX_MSS_DENSITY_1T 0x0A
1267 #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
1268 #define EPROM_CMD_CONFIG 0x3
1269 #define EPROM_CMD_LOAD 1
1271 #define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1273 #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1275 #define RA_LSSIWRITE_8821A 0xc90
1276 #define RB_LSSIWRITE_8821A 0xe90
1278 #define RA_PIREAD_8821A 0xd04
1279 #define RB_PIREAD_8821A 0xd44
1280 #define RA_SIREAD_8821A 0xd08
1281 #define RB_SIREAD_8821A 0xd48
1283 #define RPMAC_RESET 0x100
1284 #define RPMAC_TXSTART 0x104
1285 #define RPMAC_TXLEGACYSIG 0x108
1286 #define RPMAC_TXHTSIG1 0x10c
1287 #define RPMAC_TXHTSIG2 0x110
1288 #define RPMAC_PHYDEBUG 0x114
1289 #define RPMAC_TXPACKETNUM 0x118
1290 #define RPMAC_TXIDLE 0x11c
1291 #define RPMAC_TXMACHEADER0 0x120
1292 #define RPMAC_TXMACHEADER1 0x124
1293 #define RPMAC_TXMACHEADER2 0x128
1294 #define RPMAC_TXMACHEADER3 0x12c
1295 #define RPMAC_TXMACHEADER4 0x130
1296 #define RPMAC_TXMACHEADER5 0x134
1297 #define RPMAC_TXDADATYPE 0x138
1298 #define RPMAC_TXRANDOMSEED 0x13c
1299 #define RPMAC_CCKPLCPPREAMBLE 0x140
1300 #define RPMAC_CCKPLCPHEADER 0x144
1301 #define RPMAC_CCKCRC16 0x148
1302 #define RPMAC_OFDMRXCRC32OK 0x170
1303 #define RPMAC_OFDMRXCRC32Er 0x174
1304 #define RPMAC_OFDMRXPARITYER 0x178
1305 #define RPMAC_OFDMRXCRC8ER 0x17c
1306 #define RPMAC_CCKCRXRC16ER 0x180
1307 #define RPMAC_CCKCRXRC32ER 0x184
1308 #define RPMAC_CCKCRXRC32OK 0x188
1309 #define RPMAC_TXSTATUS 0x18c
1311 #define RFPGA0_RFMOD 0x800
1313 #define RFPGA0_TXINFO 0x804
1314 #define RFPGA0_PSDFUNCTION 0x808
1316 #define RFPGA0_TXGAINSTAGE 0x80c
1318 #define RFPGA0_RFTIMING1 0x810
1319 #define RFPGA0_RFTIMING2 0x814
1321 #define RFPGA0_XA_HSSIPARAMETER1 0x820
1322 #define RFPGA0_XA_HSSIPARAMETER2 0x824
1323 #define RFPGA0_XB_HSSIPARAMETER1 0x828
1324 #define RFPGA0_XB_HSSIPARAMETER2 0x82c
1325 #define RCCAONSEC 0x838
1327 #define RFPGA0_XA_LSSIPARAMETER 0x840
1328 #define RFPGA0_XB_LSSIPARAMETER 0x844
1329 #define RL1PEAKTH 0x848
1331 #define RFPGA0_RFWAKEUPPARAMETER 0x850
1332 #define RFPGA0_RFSLEEPUPPARAMETER 0x854
1334 #define RFPGA0_XAB_SWITCHCONTROL 0x858
1335 #define RFPGA0_XCD_SWITCHCONTROL 0x85c
1337 #define RFPGA0_XA_RFINTERFACEOE 0x860
1338 #define RFC_AREA 0x860
1339 #define RFPGA0_XB_RFINTERFACEOE 0x864
1341 #define RFPGA0_XAB_RFINTERFACESW 0x870
1342 #define RFPGA0_XCD_RFINTERFACESW 0x874
1344 #define rFPGA0_XAB_RFPARAMETER 0x878
1345 #define rFPGA0_XCD_RFPARAMETER 0x87c
1347 #define RFPGA0_ANALOGPARAMETER1 0x880
1348 #define RFPGA0_ANALOGPARAMETER2 0x884
1349 #define RFPGA0_ANALOGPARAMETER3 0x888
1350 #define RFPGA0_ANALOGPARAMETER4 0x88c
1352 #define RFPGA0_XA_LSSIREADBACK 0x8a0
1353 #define RFPGA0_XB_LSSIREADBACK 0x8a4
1354 #define RFPGA0_XC_LSSIREADBACK 0x8a8
1355 //#define RFPGA0_XD_LSSIREADBACK 0x8ac
1356 #define RRFMOD 0x8ac
1357 #define RHSSIREAD_8821AE 0x8b0
1359 #define RFPGA0_PSDREPORT 0x8b4
1360 #define TRANSCEIVEA_HSPI_READBACK 0x8b8
1361 #define TRANSCEIVEB_HSPI_READBACK 0x8bc
1362 //#define REG_SC_CNT 0x8c4
1363 #define RADC_BUF_CLK 0x8c4
1364 #define RFPGA0_XAB_RFINTERFACERB 0x8e0
1365 #define RFPGA0_XCD_RFINTERFACERB 0x8e4
1367 #define RFPGA1_RFMOD 0x900
1369 #define RFPGA1_TXBLOCK 0x904
1370 #define RFPGA1_DEBUGSELECT 0x908
1371 #define RFPGA1_TXINFO 0x90c
1373 #define RCCK_SYSTEM 0xa00
1374 #define BCCK_SYSTEM 0x10
1377 #define RCCK0_AFESETTING 0xa04
1378 #define RCCK0_CCA 0xa08
1380 #define RCCK0_RXAGC1 0xa0c
1381 #define RCCK0_RXAGC2 0xa10
1383 #define RCCK0_RXHP 0xa14
1385 #define RCCK0_DSPPARAMETER1 0xa18
1386 #define RCCK0_DSPPARAMETER2 0xa1c
1388 #define RCCK0_TXFILTER1 0xa20
1389 #define RCCK0_TXFILTER2 0xa24
1390 #define RCCK0_DEBUGPORT 0xa28
1391 #define RCCK0_FALSEALARMREPORT 0xa2c
1392 #define RCCK0_TRSSIREPORT 0xa50
1393 #define RCCK0_RXREPORT 0xa54
1394 #define RCCK0_FACOUNTERLOWER 0xa5c
1395 #define RCCK0_FACOUNTERUPPER 0xa58
1396 #define RCCK0_CCA_CNT 0xa60
1400 #define rPdp_AntA 0xb00
1401 #define rPdp_AntA_4 0xb04
1402 #define rPdp_AntA_8 0xb08
1403 #define rPdp_AntA_C 0xb0c
1404 #define rPdp_AntA_10 0xb10
1405 #define rPdp_AntA_14 0xb14
1406 #define rPdp_AntA_18 0xb18
1407 #define rPdp_AntA_1C 0xb1c
1408 #define rPdp_AntA_20 0xb20
1409 #define rPdp_AntA_24 0xb24
1411 #define rConfig_Pmpd_AntA 0xb28
1412 #define rConfig_ram64x16 0xb2c
1415 #define rHssiPar 0xb34
1417 #define rConfig_AntA 0xb68
1418 #define rConfig_AntB 0xb6c
1420 #define rPdp_AntB 0xb70
1421 #define rPdp_AntB_4 0xb74
1422 #define rPdp_AntB_8 0xb78
1423 #define rPdp_AntB_C 0xb7c
1424 #define rPdp_AntB_10 0xb80
1425 #define rPdp_AntB_14 0xb84
1426 #define rPdp_AntB_18 0xb88
1427 #define rPdp_AntB_1C 0xb8c
1428 #define rPdp_AntB_20 0xb90
1429 #define rPdp_AntB_24 0xb94
1431 #define rConfig_Pmpd_AntB 0xb98
1436 #define rPm_Rx0_AntA 0xbdc
1437 #define rPm_Rx1_AntA 0xbe0
1438 #define rPm_Rx2_AntA 0xbe4
1439 #define rPm_Rx3_AntA 0xbe8
1440 #define rPm_Rx0_AntB 0xbec
1441 #define rPm_Rx1_AntB 0xbf0
1442 #define rPm_Rx2_AntB 0xbf4
1443 #define rPm_Rx3_AntB 0xbf8
1446 #define RA_RSSI_DUMP 0xBF0
1447 #define RB_RSSI_DUMP 0xBF1
1448 #define RS1_RX_EVM_DUMP 0xBF4
1449 #define RS2_RX_EVM_DUMP 0xBF5
1450 #define RA_RX_SNR_DUMP 0xBF6
1451 #define RB_RX_SNR_DUMP 0xBF7
1452 #define RA_CFO_SHORT_DUMP 0xBF8
1453 #define RB_CFO_SHORT_DUMP 0xBFA
1454 #define RA_CFO_LONG_DUMP 0xBEC
1455 #define RB_CFO_LONG_DUMP 0xBEE
1458 #define ROFDM0_LSTF 0xc00
1460 #define ROFDM0_TRXPATHENABLE 0xc04
1461 #define ROFDM0_TRMUXPAR 0xc08
1462 #define ROFDM0_TRSWISOLATION 0xc0c
1464 #define ROFDM0_XARXAFE 0xc10
1465 #define ROFDM0_XARXIQIMBALANCE 0xc14
1466 #define ROFDM0_XBRXAFE 0xc18
1467 #define ROFDM0_XBRXIQIMBALANCE 0xc1c
1468 #define ROFDM0_XCRXAFE 0xc20
1469 #define ROFDM0_XCRXIQIMBANLANCE 0xc24
1470 #define ROFDM0_XDRXAFE 0xc28
1471 #define ROFDM0_XDRXIQIMBALANCE 0xc2c
1473 #define ROFDM0_RXDETECTOR1 0xc30
1474 #define ROFDM0_RXDETECTOR2 0xc34
1475 #define ROFDM0_RXDETECTOR3 0xc38
1476 #define ROFDM0_RXDETECTOR4 0xc3c
1478 #define ROFDM0_RXDSP 0xc40
1479 #define ROFDM0_CFOANDDAGC 0xc44
1480 #define ROFDM0_CCADROPTHRESHOLD 0xc48
1481 #define ROFDM0_ECCATHRESHOLD 0xc4c
1483 #define ROFDM0_XAAGCCORE1 0xc50
1484 #define ROFDM0_XAAGCCORE2 0xc54
1485 #define ROFDM0_XBAGCCORE1 0xc58
1486 #define ROFDM0_XBAGCCORE2 0xc5c
1487 #define ROFDM0_XCAGCCORE1 0xc60
1488 #define ROFDM0_XCAGCCORE2 0xc64
1489 #define ROFDM0_XDAGCCORE1 0xc68
1490 #define ROFDM0_XDAGCCORE2 0xc6c
1492 #define ROFDM0_AGCPARAMETER1 0xc70
1493 #define ROFDM0_AGCPARAMETER2 0xc74
1494 #define ROFDM0_AGCRSSITABLE 0xc78
1495 #define ROFDM0_HTSTFAGC 0xc7c
1497 #define ROFDM0_XATXIQIMBALANCE 0xc80
1498 #define ROFDM0_XATXAFE 0xc84
1499 #define ROFDM0_XBTXIQIMBALANCE 0xc88
1500 #define ROFDM0_XBTXAFE 0xc8c
1501 #define ROFDM0_XCTXIQIMBALANCE 0xc90
1502 #define ROFDM0_XCTXAFE 0xc94
1503 #define ROFDM0_XDTXIQIMBALANCE 0xc98
1504 #define ROFDM0_XDTXAFE 0xc9c
1506 #define ROFDM0_RXIQEXTANTA 0xca0
1507 #define ROFDM0_TXCOEFF1 0xca4
1508 #define ROFDM0_TXCOEFF2 0xca8
1509 #define ROFDM0_TXCOEFF3 0xcac
1510 #define ROFDM0_TXCOEFF4 0xcb0
1511 #define ROFDM0_TXCOEFF5 0xcb4
1512 #define ROFDM0_TXCOEFF6 0xcb8
1514 /*Path_A RFE control */
1515 #define RA_RFE_CTRL_8812 0xcb8
1516 /*Path_B RFE control*/
1517 #define RB_RFE_CTRL_8812 0xeb8
1519 #define ROFDM0_RXHPPARAMETER 0xce0
1520 #define ROFDM0_TXPSEUDONOISEWGT 0xce4
1521 #define ROFDM0_FRAMESYNC 0xcf0
1522 #define ROFDM0_DFSREPORT 0xcf4
1525 #define ROFDM1_LSTF 0xd00
1526 #define ROFDM1_TRXPATHENABLE 0xd04
1528 #define ROFDM1_CF0 0xd08
1529 #define ROFDM1_CSI1 0xd10
1530 #define ROFDM1_SBD 0xd14
1531 #define ROFDM1_CSI2 0xd18
1532 #define ROFDM1_CFOTRACKING 0xd2c
1533 #define ROFDM1_TRXMESAURE1 0xd34
1534 #define ROFDM1_INTFDET 0xd3c
1535 #define ROFDM1_PSEUDONOISESTATEAB 0xd50
1536 #define ROFDM1_PSEUDONOISESTATECD 0xd54
1537 #define ROFDM1_RXPSEUDONOISEWGT 0xd58
1539 #define ROFDM_PHYCOUNTER1 0xda0
1540 #define ROFDM_PHYCOUNTER2 0xda4
1541 #define ROFDM_PHYCOUNTER3 0xda8
1543 #define ROFDM_SHORTCFOAB 0xdac
1544 #define ROFDM_SHORTCFOCD 0xdb0
1545 #define ROFDM_LONGCFOAB 0xdb4
1546 #define ROFDM_LONGCFOCD 0xdb8
1547 #define ROFDM_TAILCF0AB 0xdbc
1548 #define ROFDM_TAILCF0CD 0xdc0
1549 #define ROFDM_PWMEASURE1 0xdc4
1550 #define ROFDM_PWMEASURE2 0xdc8
1551 #define ROFDM_BWREPORT 0xdcc
1552 #define ROFDM_AGCREPORT 0xdd0
1553 #define ROFDM_RXSNR 0xdd4
1554 #define ROFDM_RXEVMCSI 0xdd8
1555 #define ROFDM_SIGREPORT 0xddc
1557 #define RTXAGC_A_CCK11_CCK1 0xc20
1558 #define RTXAGC_A_OFDM18_OFDM6 0xc24
1559 #define RTXAGC_A_OFDM54_OFDM24 0xc28
1560 #define RTXAGC_A_MCS03_MCS00 0xc2c
1561 #define RTXAGC_A_MCS07_MCS04 0xc30
1562 #define RTXAGC_A_MCS11_MCS08 0xc34
1563 #define RTXAGC_A_MCS15_MCS12 0xc38
1564 #define RTXAGC_A_NSS1INDEX3_NSS1INDEX0 0xc3c
1565 #define RTXAGC_A_NSS1INDEX7_NSS1INDEX4 0xc40
1566 #define RTXAGC_A_NSS2INDEX1_NSS1INDEX8 0xc44
1567 #define RTXAGC_A_NSS2INDEX5_NSS2INDEX2 0xc48
1568 #define RTXAGC_A_NSS2INDEX9_NSS2INDEX6 0xc4c
1569 #define RTXAGC_B_CCK11_CCK1 0xe20
1570 #define RTXAGC_B_OFDM18_OFDM6 0xe24
1571 #define RTXAGC_B_OFDM54_OFDM24 0xe28
1572 #define RTXAGC_B_MCS03_MCS00 0xe2c
1573 #define RTXAGC_B_MCS07_MCS04 0xe30
1574 #define RTXAGC_B_MCS11_MCS08 0xe34
1575 #define RTXAGC_B_MCS15_MCS12 0xe38
1576 #define RTXAGC_B_NSS1INDEX3_NSS1INDEX0 0xe3c
1577 #define RTXAGC_B_NSS1INDEX7_NSS1INDEX4 0xe40
1578 #define RTXAGC_B_NSS2INDEX1_NSS1INDEX8 0xe44
1579 #define RTXAGC_B_NSS2INDEX5_NSS2INDEX2 0xe48
1580 #define RTXAGC_B_NSS2INDEX9_NSS2INDEX6 0xe4c
1582 #define RA_TXPWRTRAING 0xc54
1583 #define RB_TXPWRTRAING 0xe54
1586 #define RFPGA0_IQK 0xe28
1587 #define RTx_IQK_Tone_A 0xe30
1588 #define RRx_IQK_Tone_A 0xe34
1589 #define RTx_IQK_PI_A 0xe38
1590 #define RRx_IQK_PI_A 0xe3c
1592 #define RTx_IQK 0xe40
1593 #define RRx_IQK 0xe44
1594 #define RIQK_AGC_Pts 0xe48
1595 #define RIQK_AGC_Rsp 0xe4c
1596 #define RTx_IQK_Tone_B 0xe50
1597 #define RRx_IQK_Tone_B 0xe54
1598 #define RTx_IQK_PI_B 0xe58
1599 #define RRx_IQK_PI_B 0xe5c
1600 #define RIQK_AGC_Cont 0xe60
1602 #define RBlue_Tooth 0xe6c
1603 #define RRx_Wait_CCA 0xe70
1604 #define RTx_CCK_RFON 0xe74
1605 #define RTx_CCK_BBON 0xe78
1606 #define RTx_OFDM_RFON 0xe7c
1607 #define RTx_OFDM_BBON 0xe80
1608 #define RTx_To_Rx 0xe84
1609 #define RTx_To_Tx 0xe88
1610 #define RRx_CCK 0xe8c
1612 #define RTx_Power_Before_IQK_A 0xe94
1613 #define RTx_Power_After_IQK_A 0xe9c
1615 #define RRx_Power_Before_IQK_A 0xea0
1616 #define RRx_Power_Before_IQK_A_2 0xea4
1617 #define RRx_Power_After_IQK_A 0xea8
1618 #define RRx_Power_After_IQK_A_2 0xeac
1620 #define RTx_Power_Before_IQK_B 0xeb4
1621 #define RTx_Power_After_IQK_B 0xebc
1623 #define RRx_Power_Before_IQK_B 0xec0
1624 #define RRx_Power_Before_IQK_B_2 0xec4
1625 #define RRx_Power_After_IQK_B 0xec8
1626 #define RRx_Power_After_IQK_B_2 0xecc
1628 #define RRx_OFDM 0xed0
1629 #define RRx_Wait_RIFS 0xed4
1630 #define RRx_TO_Rx 0xed8
1631 #define RStandby 0xedc
1632 #define RSleep 0xee0
1633 #define RPMPD_ANAEN 0xeec
1635 #define RZEBRA1_HSSIENABLE 0x0
1636 #define RZEBRA1_TRXENABLE1 0x1
1637 #define RZEBRA1_TRXENABLE2 0x2
1638 #define RZEBRA1_AGC 0x4
1639 #define RZEBRA1_CHARGEPUMP 0x5
1640 #define RZEBRA1_CHANNEL 0x7
1642 #define RZEBRA1_TXGAIN 0x8
1643 #define RZEBRA1_TXLPF 0x9
1644 #define RZEBRA1_RXLPF 0xb
1645 #define RZEBRA1_RXHPFCORNER 0xc
1647 #define RGLOBALCTRL 0
1648 #define RRTL8256_TXLPF 19
1649 #define RRTL8256_RXLPF 11
1650 #define RRTL8258_TXLPF 0x11
1651 #define RRTL8258_RXLPF 0x13
1652 #define RRTL8258_RSSILPF 0xa
1656 #define RF_IQADJ_G1 0x01
1657 #define RF_IQADJ_G2 0x02
1658 #define RF_POW_TRSW 0x05
1660 #define RF_GAIN_RX 0x06
1661 #define RF_GAIN_TX 0x07
1663 #define RF_TXM_IDAC 0x08
1664 #define RF_BS_IQGEN 0x0F
1666 #define RF_MODE1 0x10
1667 #define RF_MODE2 0x11
1669 #define RF_RX_AGC_HP 0x12
1670 #define RF_TX_AGC 0x13
1671 #define RF_BIAS 0x14
1673 #define RF_POW_ABILITY 0x17
1674 #define RF_MODE_AG 0x18
1675 #define RRFCHANNEL 0x18
1676 #define RF_CHNLBW 0x18
1679 #define RF_RX_G1 0x1A
1680 #define RF_RX_G2 0x1B
1682 #define RF_RX_BB2 0x1C
1683 #define RF_RX_BB1 0x1D
1685 #define RF_RCK1 0x1E
1686 #define RF_RCK2 0x1F
1688 #define RF_TX_G1 0x20
1689 #define RF_TX_G2 0x21
1690 #define RF_TX_G3 0x22
1692 #define RF_TX_BB1 0x23
1693 #define RF_T_METER 0x24
1694 #define RF_T_METER_88E 0x42
1695 #define RF_T_METER_8812A 0x42
1697 #define RF_SYN_G1 0x25
1698 #define RF_SYN_G2 0x26
1699 #define RF_SYN_G3 0x27
1700 #define RF_SYN_G4 0x28
1701 #define RF_SYN_G5 0x29
1702 #define RF_SYN_G6 0x2A
1703 #define RF_SYN_G7 0x2B
1704 #define RF_SYN_G8 0x2C
1706 #define RF_RCK_OS 0x30
1707 #define RF_TXPA_G1 0x31
1708 #define RF_TXPA_G2 0x32
1709 #define RF_TXPA_G3 0x33
1711 #define RF_TX_BIAS_A 0x35
1712 #define RF_TX_BIAS_D 0x36
1713 #define RF_LOBF_9 0x38
1714 #define RF_RXRF_A3 0x3C
1715 #define RF_TRSW 0x3F
1717 #define RF_TXRF_A2 0x41
1718 #define RF_TXPA_G4 0x46
1719 #define RF_TXPA_A4 0x4B
1723 #define RF_WE_LUT 0xEF
1725 #define BBBRESETB 0x100
1726 #define BGLOBALRESETB 0x200
1727 #define BOFDMTXSTART 0x4
1728 #define BCCKTXSTART 0x8
1729 #define BCRC32DEBUG 0x100
1730 #define BPMACLOOPBACK 0x10
1731 #define BTXLSIG 0xffffff
1732 #define BOFDMTXRATE 0xf
1733 #define BOFDMTXRESERVED 0x10
1734 #define BOFDMTXLENGTH 0x1ffe0
1735 #define BOFDMTXPARITY 0x20000
1736 #define BTXHTSIG1 0xffffff
1737 #define BTXHTMCSRATE 0x7f
1738 #define BTXHTBW 0x80
1739 #define BTXHTLENGTH 0xffff00
1740 #define BTXHTSIG2 0xffffff
1741 #define BTXHTSMOOTHING 0x1
1742 #define BTXHTSOUNDING 0x2
1743 #define BTXHTRESERVED 0x4
1744 #define BTXHTAGGREATION 0x8
1745 #define BTXHTSTBC 0x30
1746 #define BTXHTADVANCECODING 0x40
1747 #define BTXHTSHORTGI 0x80
1748 #define BTXHTNUMBERHT_LTF 0x300
1749 #define BTXHTCRC8 0x3fc00
1750 #define BCOUNTERRESET 0x10000
1751 #define BNUMOFOFDMTX 0xffff
1752 #define BNUMOFCCKTX 0xffff0000
1753 #define BTXIDLEINTERVAL 0xffff
1754 #define BOFDMSERVICE 0xffff0000
1755 #define BTXMACHEADER 0xffffffff
1756 #define BTXDATAINIT 0xff
1757 #define BTXHTMODE 0x100
1758 #define BTXDATATYPE 0x30000
1759 #define BTXRANDOMSEED 0xffffffff
1760 #define BCCKTXPREAMBLE 0x1
1761 #define BCCKTXSFD 0xffff0000
1762 #define BCCKTXSIG 0xff
1763 #define BCCKTXSERVICE 0xff00
1764 #define BCCKLENGTHEXT 0x8000
1765 #define BCCKTXLENGHT 0xffff0000
1766 #define BCCKTXCRC16 0xffff
1767 #define BCCKTXSTATUS 0x1
1768 #define BOFDMTXSTATUS 0x2
1769 #define IS_BB_REG_OFFSET_92S(_Offset) \
1770 ((_Offset >= 0x800) && (_Offset <= 0xfff))
1773 #define BJAPANMODE 0x2
1774 #define BCCKTXSC 0x30
1775 /* Block & Path enable*/
1776 #define ROFDMCCKEN 0x808
1777 #define BCCKEN 0x10000000
1778 #define BOFDMEN 0x20000000
1779 #define RRXPATH 0x808 /* Rx antenna*/
1780 #define BRXPATH 0xff
1781 #define RTXPATH 0x80c /* Tx antenna*/
1782 #define BTXPATH 0x0fffffff
1783 #define RCCK_RX 0xa04 /* for cck rx path selection*/
1784 #define BCCK_RX 0x0c000000
1785 #define RVHTLEN_USE_LSIG 0x8c3 /* Use LSIG for VHT length*/
1788 #define BOFDMRXADCPHASE 0x10000
1789 #define BOFDMTXDACPHASE 0x40000
1790 #define BXATXAGC 0x3f
1792 #define BXBTXAGC 0xf00
1793 #define BXCTXAGC 0xf000
1794 #define BXDTXAGC 0xf0000
1796 #define BPASTART 0xf0000000
1797 #define BTRSTART 0x00f00000
1798 #define BRFSTART 0x0000f000
1799 #define BBBSTART 0x000000f0
1800 #define BBBCCKSTART 0x0000000f
1802 #define BTREND 0x0f000000
1803 #define BRFEND 0x000f0000
1804 #define BCCAMASK 0x000000f0
1805 #define BR2RCCAMASK 0x00000f00
1806 #define BHSSI_R2TDELAY 0xf8000000
1807 #define BHSSI_T2RDELAY 0xf80000
1808 #define BCONTXHSSI 0x400
1809 #define BIGFROMCCK 0x200
1810 #define BAGCADDRESS 0x3f
1811 #define BRXHPTX 0x7000
1812 #define BRXHP2RX 0x38000
1813 #define BRXHPCCKINI 0xc0000
1814 #define BAGCTXCODE 0xc00000
1815 #define BAGCRXCODE 0x300000
1817 #define B3WIREDATALENGTH 0x800
1818 #define B3WIREADDREAALENGTH 0x400
1820 #define B3WIRERFPOWERDOWN 0x1
1821 #define B5GPAPEPOLARITY 0x40000000
1822 #define B2GPAPEPOLARITY 0x80000000
1823 #define BRFSW_TXDEFAULTANT 0x3
1824 #define BRFSW_TXOPTIONANT 0x30
1825 #define BRFSW_RXDEFAULTANT 0x300
1826 #define BRFSW_RXOPTIONANT 0x3000
1827 #define BRFSI_3WIREDATA 0x1
1828 #define BRFSI_3WIRECLOCK 0x2
1829 #define BRFSI_3WIRELOAD 0x4
1830 #define BRFSI_3WIRERW 0x8
1831 #define BRFSI_3WIRE 0xf
1833 #define BRFSI_RFENV 0x10
1835 #define BRFSI_TRSW 0x20
1836 #define BRFSI_TRSWB 0x40
1837 #define BRFSI_ANTSW 0x100
1838 #define BRFSI_ANTSWB 0x200
1839 #define BRFSI_PAPE 0x400
1840 #define BRFSI_PAPE5G 0x800
1841 #define BBANDSELECT 0x1
1842 #define BHTSIG2_GI 0x80
1843 #define BHTSIG2_SMOOTHING 0x01
1844 #define BHTSIG2_SOUNDING 0x02
1845 #define BHTSIG2_AGGREATON 0x08
1846 #define BHTSIG2_STBC 0x30
1847 #define BHTSIG2_ADVCODING 0x40
1848 #define BHTSIG2_NUMOFHTLTF 0x300
1849 #define BHTSIG2_CRC8 0x3fc
1850 #define BHTSIG1_MCS 0x7f
1851 #define BHTSIG1_BANDWIDTH 0x80
1852 #define BHTSIG1_HTLENGTH 0xffff
1853 #define BLSIG_RATE 0xf
1854 #define BLSIG_RESERVED 0x10
1855 #define BLSIG_LENGTH 0x1fffe
1856 #define BLSIG_PARITY 0x20
1857 #define BCCKRXPHASE 0x4
1859 #define BLSSIREADADDRESS 0x7f800000
1860 #define BLSSIREADEDGE 0x80000000
1862 #define BLSSIREADBACKDATA 0xfffff
1864 #define BLSSIREADOKFLAG 0x1000
1865 #define BCCKSAMPLERATE 0x8
1866 #define BREGULATOR0STANDBY 0x1
1867 #define BREGULATORPLLSTANDBY 0x2
1868 #define BREGULATOR1STANDBY 0x4
1869 #define BPLLPOWERUP 0x8
1870 #define BDPLLPOWERUP 0x10
1871 #define BDA10POWERUP 0x20
1872 #define BAD7POWERUP 0x200
1873 #define BDA6POWERUP 0x2000
1874 #define BXTALPOWERUP 0x4000
1875 #define B40MDCLKPOWERUP 0x8000
1876 #define BDA6DEBUGMODE 0x20000
1877 #define BDA6SWING 0x380000
1879 #define BADCLKPHASE 0x4000000
1880 #define B80MCLKDELAY 0x18000000
1881 #define BAFEWATCHDOGENABLE 0x20000000
1883 #define BXTALCAP01 0xc0000000
1884 #define BXTALCAP23 0x3
1885 #define BXTALCAP92X 0x0f000000
1886 #define BXTALCAP 0x0f000000
1888 #define BINTDIFCLKENABLE 0x400
1889 #define BEXTSIGCLKENABLE 0x800
1890 #define BBANDGAP_MBIAS_POWERUP 0x10000
1891 #define BAD11SH_GAIN 0xc0000
1892 #define BAD11NPUT_RANGE 0x700000
1893 #define BAD110P_CURRENT 0x3800000
1894 #define BLPATH_LOOPBACK 0x4000000
1895 #define BQPATH_LOOPBACK 0x8000000
1896 #define BAFE_LOOPBACK 0x10000000
1897 #define BDA10_SWING 0x7e0
1898 #define BDA10_REVERSE 0x800
1899 #define BDA_CLK_SOURCE 0x1000
1900 #define BDA7INPUT_RANGE 0x6000
1901 #define BDA7_GAIN 0x38000
1902 #define BDA7OUTPUT_CM_MODE 0x40000
1903 #define BDA7INPUT_CM_MODE 0x380000
1904 #define BDA7CURRENT 0xc00000
1905 #define BREGULATOR_ADJUST 0x7000000
1906 #define BAD11POWERUP_ATTX 0x1
1907 #define BDA10PS_ATTX 0x10
1908 #define BAD11POWERUP_ATRX 0x100
1909 #define BDA10PS_ATRX 0x1000
1910 #define BCCKRX_AGC_FORMAT 0x200
1911 #define BPSDFFT_SAMPLE_POINT 0xc000
1912 #define BPSD_AVERAGE_NUM 0x3000
1913 #define BIQPATH_CONTROL 0xc00
1914 #define BPSD_FREQ 0x3ff
1915 #define BPSD_ANTENNA_PATH 0x30
1916 #define BPSD_IQ_SWITCH 0x40
1917 #define BPSD_RX_TRIGGER 0x400000
1918 #define BPSD_TX_TRIGGER 0x80000000
1919 #define BPSD_SINE_TONE_SCALE 0x7f000000
1920 #define BPSD_REPORT 0xffff
1922 #define BOFDM_TXSC 0x30000000
1923 #define BCCK_TXON 0x1
1924 #define BOFDM_TXON 0x2
1925 #define BDEBUG_PAGE 0xfff
1926 #define BDEBUG_ITEM 0xff
1928 #define BANT_NONHT 0x100
1929 #define BANT_HT1 0x1000
1930 #define BANT_HT2 0x10000
1931 #define BANT_HT1S1 0x100000
1932 #define BANT_NONHTS1 0x1000000
1934 #define BCCK_BBMODE 0x3
1935 #define BCCK_TXPOWERSAVING 0x80
1936 #define BCCK_RXPOWERSAVING 0x40
1938 #define BCCK_SIDEBAND 0x10
1940 #define BCCK_SCRAMBLE 0x8
1941 #define BCCK_ANTDIVERSITY 0x8000
1942 #define BCCK_CARRIER_RECOVERY 0x4000
1943 #define BCCK_TXRATE 0x3000
1944 #define BCCK_DCCANCEL 0x0800
1945 #define BCCK_ISICANCEL 0x0400
1946 #define BCCK_MATCH_FILTER 0x0200
1947 #define BCCK_EQUALIZER 0x0100
1948 #define BCCK_PREAMBLE_DETECT 0x800000
1949 #define BCCK_FAST_FALSECCA 0x400000
1950 #define BCCK_CH_ESTSTART 0x300000
1951 #define BCCK_CCA_COUNT 0x080000
1952 #define BCCK_CS_LIM 0x070000
1953 #define BCCK_BIST_MODE 0x80000000
1954 #define BCCK_CCAMASK 0x40000000
1955 #define BCCK_TX_DAC_PHASE 0x4
1956 #define BCCK_RX_ADC_PHASE 0x20000000
1957 #define BCCKR_CP_MODE 0x0100
1958 #define BCCK_TXDC_OFFSET 0xf0
1959 #define BCCK_RXDC_OFFSET 0xf
1960 #define BCCK_CCA_MODE 0xc000
1961 #define BCCK_FALSECS_LIM 0x3f00
1962 #define BCCK_CS_RATIO 0xc00000
1963 #define BCCK_CORGBIT_SEL 0x300000
1964 #define BCCK_PD_LIM 0x0f0000
1965 #define BCCK_NEWCCA 0x80000000
1966 #define BCCK_RXHP_OF_IG 0x8000
1967 #define BCCK_RXIG 0x7f00
1968 #define BCCK_LNA_POLARITY 0x800000
1969 #define BCCK_RX1ST_BAIN 0x7f0000
1970 #define BCCK_RF_EXTEND 0x20000000
1971 #define BCCK_RXAGC_SATLEVEL 0x1f000000
1972 #define BCCK_RXAGC_SATCOUNT 0xe0
1973 #define bCCKRxRFSettle 0x1f
1974 #define BCCK_FIXED_RXAGC 0x8000
1975 #define BCCK_ANTENNA_POLARITY 0x2000
1976 #define BCCK_TXFILTER_TYPE 0x0c00
1977 #define BCCK_RXAGC_REPORTTYPE 0x0300
1978 #define BCCK_RXDAGC_EN 0x80000000
1979 #define BCCK_RXDAGC_PERIOD 0x20000000
1980 #define BCCK_RXDAGC_SATLEVEL 0x1f000000
1981 #define BCCK_TIMING_RECOVERY 0x800000
1982 #define BCCK_TXC0 0x3f0000
1983 #define BCCK_TXC1 0x3f000000
1984 #define BCCK_TXC2 0x3f
1985 #define BCCK_TXC3 0x3f00
1986 #define BCCK_TXC4 0x3f0000
1987 #define BCCK_TXC5 0x3f000000
1988 #define BCCK_TXC6 0x3f
1989 #define BCCK_TXC7 0x3f00
1990 #define BCCK_DEBUGPORT 0xff0000
1991 #define BCCK_DAC_DEBUG 0x0f000000
1992 #define BCCK_FALSEALARM_ENABLE 0x8000
1993 #define BCCK_FALSEALARM_READ 0x4000
1994 #define BCCK_TRSSI 0x7f
1995 #define BCCK_RXAGC_REPORT 0xfe
1996 #define BCCK_RXREPORT_ANTSEL 0x80000000
1997 #define BCCK_RXREPORT_MFOFF 0x40000000
1998 #define BCCK_RXREPORT_SQLOSS 0x20000000
1999 #define BCCK_RXREPORT_PKTLOSS 0x10000000
2000 #define BCCK_RXREPORT_LOCKEDBIT 0x08000000
2001 #define BCCK_RXREPORT_RATEERROR 0x04000000
2002 #define BCCK_RXREPORT_RXRATE 0x03000000
2003 #define BCCK_RXFA_COUNTER_LOWER 0xff
2004 #define BCCK_RXFA_COUNTER_UPPER 0xff000000
2005 #define BCCK_RXHPAGC_START 0xe000
2006 #define BCCK_RXHPAGC_FINAL 0x1c00
2007 #define BCCK_RXFALSEALARM_ENABLE 0x8000
2008 #define BCCK_FACOUNTER_FREEZE 0x4000
2009 #define BCCK_TXPATH_SEL 0x10000000
2010 #define BCCK_DEFAULT_RXPATH 0xc000000
2011 #define BCCK_OPTION_RXPATH 0x3000000
2013 #define BNUM_OFSTF 0x3
2014 #define BSHIFT_L 0xc0
2016 #define BRXPATH_A 0x1
2017 #define BRXPATH_B 0x2
2018 #define BRXPATH_C 0x4
2019 #define BRXPATH_D 0x8
2020 #define BTXPATH_A 0x1
2021 #define BTXPATH_B 0x2
2022 #define BTXPATH_C 0x4
2023 #define BTXPATH_D 0x8
2024 #define BTRSSI_FREQ 0x200
2025 #define BADC_BACKOFF 0x3000
2026 #define BDFIR_BACKOFF 0xc000
2027 #define BTRSSI_LATCH_PHASE 0x10000
2028 #define BRX_LDC_OFFSET 0xff
2029 #define BRX_QDC_OFFSET 0xff00
2030 #define BRX_DFIR_MODE 0x1800000
2031 #define BRX_DCNF_TYPE 0xe000000
2032 #define BRXIQIMB_A 0x3ff
2033 #define BRXIQIMB_B 0xfc00
2034 #define BRXIQIMB_C 0x3f0000
2035 #define BRXIQIMB_D 0xffc00000
2036 #define BDC_DC_NOTCH 0x60000
2037 #define BRXNB_NOTCH 0x1f000000
2039 #define BPD_TH_OPT2 0xc000
2040 #define BPWED_TH 0x700
2041 #define BIFMF_WIN_L 0x800
2042 #define BPD_OPTION 0x1000
2043 #define BMF_WIN_L 0xe000
2044 #define BBW_SEARCH_L 0x30000
2045 #define BWIN_ENH_L 0xc0000
2046 #define BBW_TH 0x700000
2047 #define BED_TH2 0x3800000
2048 #define BBW_OPTION 0x4000000
2049 #define BRADIO_TH 0x18000000
2050 #define BWINDOW_L 0xe0000000
2051 #define BSBD_OPTION 0x1
2052 #define BFRAME_TH 0x1c
2053 #define BFS_OPTION 0x60
2054 #define BDC_SLOPE_CHECK 0x80
2055 #define BFGUARD_COUNTER_DC_L 0xe00
2056 #define BFRAME_WEIGHT_SHORT 0x7000
2057 #define BSUB_TUNE 0xe00000
2058 #define BFRAME_DC_LENGTH 0xe000000
2059 #define BSBD_START_OFFSET 0x30000000
2060 #define BFRAME_TH_2 0x7
2061 #define BFRAME_GI2_TH 0x38
2062 #define BGI2_SYNC_EN 0x40
2063 #define BSARCH_SHORT_EARLY 0x300
2064 #define BSARCH_SHORT_LATE 0xc00
2065 #define BSARCH_GI2_LATE 0x70000
2066 #define BCFOANTSUM 0x1
2068 #define BCFOSTARTOFFSET 0xc
2069 #define BCFOLOOPBACK 0x70
2070 #define BCFOSUMWEIGHT 0x80
2071 #define BDAGCENABLE 0x10000
2072 #define BTXIQIMB_A 0x3ff
2073 #define BTXIQIMB_b 0xfc00
2074 #define BTXIQIMB_C 0x3f0000
2075 #define BTXIQIMB_D 0xffc00000
2076 #define BTXIDCOFFSET 0xff
2077 #define BTXIQDCOFFSET 0xff00
2078 #define BTXDFIRMODE 0x10000
2079 #define BTXPESUDO_NOISEON 0x4000000
2080 #define BTXPESUDO_NOISE_A 0xff
2081 #define BTXPESUDO_NOISE_B 0xff00
2082 #define BTXPESUDO_NOISE_C 0xff0000
2083 #define BTXPESUDO_NOISE_D 0xff000000
2084 #define BCCA_DROPOPTION 0x20000
2085 #define BCCA_DROPTHRES 0xfff00000
2086 #define BEDCCA_H 0xf
2087 #define BEDCCA_L 0xf0
2088 #define BLAMBDA_ED 0x300
2089 #define BRX_INITIALGAIN 0x7f
2090 #define BRX_ANTDIV_EN 0x80
2091 #define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
2092 #define BRX_HIGHPOWER_FLOW 0x8000
2093 #define BRX_AGC_FREEZE_THRES 0xc0000
2094 #define BRX_FREEZESTEP_AGC1 0x300000
2095 #define BRX_FREEZESTEP_AGC2 0xc00000
2096 #define BRX_FREEZESTEP_AGC3 0x3000000
2097 #define BRX_FREEZESTEP_AGC0 0xc000000
2098 #define BRXRSSI_CMP_EN 0x10000000
2099 #define BRXQUICK_AGCEN 0x20000000
2100 #define BRXAGC_FREEZE_THRES_MODE 0x40000000
2101 #define BRX_OVERFLOW_CHECKTYPE 0x80000000
2102 #define BRX_AGCSHIFT 0x7f
2103 #define BTRSW_TRI_ONLY 0x80
2104 #define BPOWER_THRES 0x300
2105 #define BRXAGC_EN 0x1
2106 #define BRXAGC_TOGETHER_EN 0x2
2107 #define BRXAGC_MIN 0x4
2108 #define BRXHP_INI 0x7
2109 #define BRXHP_TRLNA 0x70
2110 #define BRXHP_RSSI 0x700
2111 #define BRXHP_BBP1 0x7000
2112 #define BRXHP_BBP2 0x70000
2113 #define BRXHP_BBP3 0x700000
2114 #define BRSSI_H 0x7f0000
2115 #define BRSSI_GEN 0x7f000000
2116 #define BRXSETTLE_TRSW 0x7
2117 #define BRXSETTLE_LNA 0x38
2118 #define BRXSETTLE_RSSI 0x1c0
2119 #define BRXSETTLE_BBP 0xe00
2120 #define BRXSETTLE_RXHP 0x7000
2121 #define BRXSETTLE_ANTSW_RSSI 0x38000
2122 #define BRXSETTLE_ANTSW 0xc0000
2123 #define BRXPROCESS_TIME_DAGC 0x300000
2124 #define BRXSETTLE_HSSI 0x400000
2125 #define BRXPROCESS_TIME_BBPPW 0x800000
2126 #define BRXANTENNA_POWER_SHIFT 0x3000000
2127 #define BRSSI_TABLE_SELECT 0xc000000
2128 #define BRXHP_FINAL 0x7000000
2129 #define BRXHPSETTLE_BBP 0x7
2130 #define BRXHTSETTLE_HSSI 0x8
2131 #define BRXHTSETTLE_RXHP 0x70
2132 #define BRXHTSETTLE_BBPPW 0x80
2133 #define BRXHTSETTLE_IDLE 0x300
2134 #define BRXHTSETTLE_RESERVED 0x1c00
2135 #define BRXHT_RXHP_EN 0x8000
2136 #define BRXAGC_FREEZE_THRES 0x30000
2137 #define BRXAGC_TOGETHEREN 0x40000
2138 #define BRXHTAGC_MIN 0x80000
2139 #define BRXHTAGC_EN 0x100000
2140 #define BRXHTDAGC_EN 0x200000
2141 #define BRXHT_RXHP_BBP 0x1c00000
2142 #define BRXHT_RXHP_FINAL 0xe0000000
2143 #define BRXPW_RADIO_TH 0x3
2144 #define BRXPW_RADIO_EN 0x4
2145 #define BRXMF_HOLD 0x3800
2146 #define BRXPD_DELAY_TH1 0x38
2147 #define BRXPD_DELAY_TH2 0x1c0
2148 #define BRXPD_DC_COUNT_MAX 0x600
2149 #define BRXPD_DELAY_TH 0x8000
2150 #define BRXPROCESS_DELAY 0xf0000
2151 #define BRXSEARCHRANGE_GI2_EARLY 0x700000
2152 #define BRXFRAME_FUARD_COUNTER_L 0x3800000
2153 #define BRXSGI_GUARD_L 0xc000000
2154 #define BRXSGI_SEARCH_L 0x30000000
2155 #define BRXSGI_TH 0xc0000000
2156 #define BDFSCNT0 0xff
2157 #define BDFSCNT1 0xff00
2158 #define BDFSFLAG 0xf0000
2159 #define BMF_WEIGHT_SUM 0x300000
2160 #define BMINIDX_TH 0x7f000000
2161 #define BDAFORMAT 0x40000
2162 #define BTXCH_EMU_ENABLE 0x01000000
2163 #define BTRSW_ISOLATION_A 0x7f
2164 #define BTRSW_ISOLATION_B 0x7f00
2165 #define BTRSW_ISOLATION_C 0x7f0000
2166 #define BTRSW_ISOLATION_D 0x7f000000
2167 #define BEXT_LNA_GAIN 0x7c00
2169 #define BSTBC_EN 0x4
2170 #define BANTENNA_MAPPING 0x10
2172 #define BCFO_ANTSUM_ID 0x200
2173 #define BPHY_COUNTER_RESET 0x8000000
2174 #define BCFO_REPORT_GET 0x4000000
2175 #define BOFDM_CONTINUE_TX 0x10000000
2176 #define BOFDM_SINGLE_CARRIER 0x20000000
2177 #define BOFDM_SINGLE_TONE 0x40000000
2178 #define BHT_DETECT 0x100
2179 #define BCFOEN 0x10000
2180 #define BCFOVALUE 0xfff00000
2181 #define BSIGTONE_RE 0x3f
2182 #define BSIGTONE_IM 0x7f00
2183 #define BCOUNTER_CCA 0xffff
2184 #define BCOUNTER_PARITYFAIL 0xffff0000
2185 #define BCOUNTER_RATEILLEGAL 0xffff
2186 #define BCOUNTER_CRC8FAIL 0xffff0000
2187 #define BCOUNTER_MCSNOSUPPORT 0xffff
2188 #define BCOUNTER_FASTSYNC 0xffff
2189 #define BSHORTCFO 0xfff
2190 #define BSHORTCFOT_LENGTH 12
2191 #define BSHORTCFOF_LENGTH 11
2192 #define BLONGCFO 0x7ff
2193 #define BLONGCFOT_LENGTH 11
2194 #define BLONGCFOF_LENGTH 11
2195 #define BTAILCFO 0x1fff
2196 #define BTAILCFOT_LENGTH 13
2197 #define BTAILCFOF_LENGTH 12
2198 #define BNOISE_EN_PWDB 0xffff
2199 #define BCC_POWER_DB 0xffff0000
2200 #define BMOISE_PWDB 0xffff
2201 #define BPOWERMEAST_LENGTH 10
2202 #define BPOWERMEASF_LENGTH 3
2203 #define BRX_HT_BW 0x1
2206 #define BNB_INTF_DET_ON 0x1
2207 #define BINTF_WIN_LEN_CFG 0x30
2208 #define BNB_INTF_TH_CFG 0x1c0
2209 #define BRFGAIN 0x3f
2210 #define BTABLESEL 0x40
2212 #define BRXSNR_A 0xff
2213 #define BRXSNR_B 0xff00
2214 #define BRXSNR_C 0xff0000
2215 #define BRXSNR_D 0xff000000
2216 #define BSNR_EVMT_LENGTH 8
2217 #define BSNR_EVMF_LENGTH 1
2218 #define BCSI1ST 0xff
2219 #define BCSI2ND 0xff00
2220 #define BRXEVM1ST 0xff0000
2221 #define BRXEVM2ND 0xff000000
2222 #define BSIGEVM 0xff
2223 #define BPWDB 0xff00
2224 #define BSGIEN 0x10000
2226 #define BSFACTOR_QMA1 0xf
2227 #define BSFACTOR_QMA2 0xf0
2228 #define BSFACTOR_QMA3 0xf00
2229 #define BSFACTOR_QMA4 0xf000
2230 #define BSFACTOR_QMA5 0xf0000
2231 #define BSFACTOR_QMA6 0xf0000
2232 #define BSFACTOR_QMA7 0xf00000
2233 #define BSFACTOR_QMA8 0xf000000
2234 #define BSFACTOR_QMA9 0xf0000000
2235 #define BCSI_SCHEME 0x100000
2237 #define BNOISE_LVL_TOP_SET 0x3
2238 #define BCHSMOOTH 0x4
2239 #define BCHSMOOTH_CFG1 0x38
2240 #define BCHSMOOTH_CFG2 0x1c0
2241 #define BCHSMOOTH_CFG3 0xe00
2242 #define BCHSMOOTH_CFG4 0x7000
2243 #define BMRCMODE 0x800000
2244 #define BTHEVMCFG 0x7000000
2246 #define BLOOP_FIT_TYPE 0x1
2247 #define BUPD_CFO 0x40
2248 #define BUPD_CFO_OFFDATA 0x80
2249 #define BADV_UPD_CFO 0x100
2250 #define BADV_TIME_CTRL 0x800
2251 #define BUPD_CLKO 0x1000
2253 #define BTRACKING_MODE 0x8000
2254 #define BPHCMP_ENABLE 0x10000
2255 #define BUPD_CLKO_LTF 0x20000
2256 #define BCOM_CH_CFO 0x40000
2257 #define BCSI_ESTI_MODE 0x80000
2258 #define BADV_UPD_EQZ 0x100000
2259 #define BUCHCFG 0x7000000
2260 #define BUPDEQZ 0x8000000
2262 #define BRX_PESUDO_NOISE_ON 0x20000000
2263 #define BRX_PESUDO_NOISE_A 0xff
2264 #define BRX_PESUDO_NOISE_B 0xff00
2265 #define BRX_PESUDO_NOISE_C 0xff0000
2266 #define BRX_PESUDO_NOISE_D 0xff000000
2267 #define BRX_PESUDO_NOISESTATE_A 0xffff
2268 #define BRX_PESUDO_NOISESTATE_B 0xffff0000
2269 #define BRX_PESUDO_NOISESTATE_C 0xffff
2270 #define BRX_PESUDO_NOISESTATE_D 0xffff0000
2272 #define BZEBRA1_HSSIENABLE 0x8
2273 #define BZEBRA1_TRXCONTROL 0xc00
2274 #define BZEBRA1_TRXGAINSETTING 0x07f
2275 #define BZEBRA1_RXCOUNTER 0xc00
2276 #define BZEBRA1_TXCHANGEPUMP 0x38
2277 #define BZEBRA1_RXCHANGEPUMP 0x7
2278 #define BZEBRA1_CHANNEL_NUM 0xf80
2279 #define BZEBRA1_TXLPFBW 0x400
2280 #define BZEBRA1_RXLPFBW 0x600
2282 #define BRTL8256REG_MODE_CTRL1 0x100
2283 #define BRTL8256REG_MODE_CTRL0 0x40
2284 #define BRTL8256REG_TXLPFBW 0x18
2285 #define BRTL8256REG_RXLPFBW 0x600
2287 #define BRTL8258_TXLPFBW 0xc
2288 #define BRTL8258_RXLPFBW 0xc00
2289 #define BRTL8258_RSSILPFBW 0xc0
2299 #define MASKBYTE0 0xff
2300 #define MASKBYTE1 0xff00
2301 #define MASKBYTE2 0xff0000
2302 #define MASKBYTE3 0xff000000
2303 #define MASKHWORD 0xffff0000
2304 #define MASKLWORD 0x0000ffff
2305 #define MASKDWORD 0xffffffff
2306 #define MASK12BITS 0xfff
2307 #define MASKH4BITS 0xf0000000
2308 #define MASKOFDM_D 0xffc00000
2309 #define MASKCCK 0x3f3f3f3f
2311 #define MASK4BITS 0x0f
2312 #define MASK20BITS 0xfffff
2313 #define RFREG_OFFSET_MASK 0xfffff
2316 #define BDISABLE 0x0
2318 #define LEFT_ANTENNA 0x0
2319 #define RIGHT_ANTENNA 0x1
2321 #define TCHECK_TXSTATUS 500
2322 #define TUPDATE_RXCOUNTER 100
2324 #define REG_UN_used_register 0x01bf
2326 /* WOL bit information */
2327 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
2328 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
2329 #define HAL92C_WOL_DISASSOC_EVENT BIT(2)
2330 #define HAL92C_WOL_DEAUTH_EVENT BIT(3)
2331 #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)
2333 #define WOL_REASON_PTK_UPDATE BIT(0)
2334 #define WOL_REASON_GTK_UPDATE BIT(1)
2335 #define WOL_REASON_DISASSOC BIT(2)
2336 #define WOL_REASON_DEAUTH BIT(3)
2337 #define WOL_REASON_FW_DISCONNECT BIT(4)
2339 #define RA_RFE_PINMUX 0xcb0 /* Path_A RFE control pinmux*/
2340 #define RB_RFE_PINMUX 0xeb0 /* Path_B RFE control pinmux*/
2342 #define RA_RFE_INV 0xcb4
2343 #define RB_RFE_INV 0xeb4
2346 #define RA_RXIQC_AB 0xc10 /*RxIQ imbalance matrix coeff. A & B*/
2347 #define RA_RXIQC_CD 0xc14 /*RxIQ imbalance matrix coeff. C & D*/
2348 #define RA_TXSCALE 0xc1c /* Pah_A TX scaling factor*/
2349 #define RB_TXSCALE 0xe1c /* Path_B TX scaling factor*/
2350 #define RB_RXIQC_AB 0xe10 /*RxIQ imbalance matrix coeff. A & B*/
2351 #define RB_RXIQC_CD 0xe14 /*RxIQ imbalance matrix coeff. C & D*/
2352 #define RXIQC_AC 0x02ff /*bit mask for IQC matrix element A & C*/
2353 #define RXIQC_BD 0x02ff0000 /*bit mask for IQC matrix element A & C*/
2355 /* 2 EFUSE_TEST (For RTL8723 partially) */
2356 #define EFUSE_SEL(x) (((x) & 0x3) << 8)
2357 #define EFUSE_SEL_MASK 0x300
2358 #define EFUSE_WIFI_SEL_0 0x0
2360 /*REG_MULTI_FUNC_CTRL(For RTL8723 Only)*/
2361 #define WL_HWPDN_EN BIT(0) /* Enable GPIO[9] as WiFi HW PDn source*/
2362 #define WL_HWPDN_SL BIT(1) /* WiFi HW PDn polarity control*/
2363 #define WL_FUNC_EN BIT(2) // WiFi function enable
2364 #define WL_HWROF_EN BIT(3) // Enable GPIO[9] as WiFi RF HW PDn source
2365 #define BT_HWPDN_EN BIT(16) // Enable GPIO[11] as BT HW PDn source
2366 #define BT_HWPDN_SL BIT(17) // BT HW PDn polarity control
2367 #define BT_FUNC_EN BIT(18) // BT function enable
2368 #define BT_HWROF_EN BIT(19) // Enable GPIO[11] as BT/GPS RF HW PDn source
2369 #define GPS_HWPDN_EN BIT(20) // Enable GPIO[10] as GPS HW PDn source
2370 #define GPS_HWPDN_SL BIT(21) // GPS HW PDn polarity control
2371 #define GPS_FUNC_EN BIT(22) // GPS function enable
2374 #define BMASKBYTE0 0xff
2375 #define BMASKBYTE1 0xff00
2376 #define BMASKBYTE2 0xff0000
2377 #define BMASKBYTE3 0xff000000
2378 #define BMASKHWORD 0xffff0000
2379 #define BMASKLWORD 0x0000ffff
2380 #define BMASKDWORD 0xffffffff
2381 #define BMASK12BITS 0xfff
2382 #define BMASKH4BITS 0xf0000000
2383 #define BMASKOFDM_D 0xffc00000
2384 #define BMASKCCK 0x3f3f3f3f
2386 #define BRFREGOFFSETMASK 0xfffff
2388 #define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
2389 #define ODM_REG_BB_RX_PATH_11AC 0x808
2391 #define ODM_REG_OFDM_FA_RST_11AC 0x9A4
2393 #define ODM_REG_CCK_CCA_11AC 0xA0A
2394 #define ODM_REG_CCK_FA_RST_11AC 0xA2C
2395 #define ODM_REG_CCK_FA_11AC 0xA5C
2397 #define ODM_REG_IGI_A_11AC 0xC50
2399 #define ODM_REG_IGI_B_11AC 0xE50
2401 #define ODM_REG_OFDM_FA_11AC 0xF48
2410 #define ODM_BIT_IGI_11AC 0xFFFFFFFF
2411 #define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16
2412 #define ODM_BIT_BB_RX_PATH_11AC 0xF
2414 typedef enum AGGRE_SIZE{
2416 HT_AGG_SIZE_16K = 1,
2417 HT_AGG_SIZE_32K = 2,
2418 HT_AGG_SIZE_64K = 3,
2419 VHT_AGG_SIZE_128K = 4,
2420 VHT_AGG_SIZE_256K = 5,
2421 VHT_AGG_SIZE_512K = 6,
2422 VHT_AGG_SIZE_1024K = 7,
2423 }AGGRE_SIZE_E, *PAGGRE_SIZE_E;
2425 #define REG_AMPDU_MAX_LENGTH_8812 0x0458
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