drivers/tty/serial/fsl_lpuart.c

   1 /*
   2  *  Freescale lpuart serial port driver
   3  *
   4  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/clk.h>
  17 #include <linux/console.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_dma.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/slab.h>
  29 #include <linux/tty_flip.h>
  30
  31 /* All registers are 8-bit width */
  32 #define UARTBDH                 0x00
  33 #define UARTBDL                 0x01
  34 #define UARTCR1                 0x02
  35 #define UARTCR2                 0x03
  36 #define UARTSR1                 0x04
  37 #define UARTCR3                 0x06
  38 #define UARTDR                  0x07
  39 #define UARTCR4                 0x0a
  40 #define UARTCR5                 0x0b
  41 #define UARTMODEM               0x0d
  42 #define UARTPFIFO               0x10
  43 #define UARTCFIFO               0x11
  44 #define UARTSFIFO               0x12
  45 #define UARTTWFIFO              0x13
  46 #define UARTTCFIFO              0x14
  47 #define UARTRWFIFO              0x15
  48
  49 #define UARTBDH_LBKDIE          0x80
  50 #define UARTBDH_RXEDGIE         0x40
  51 #define UARTBDH_SBR_MASK        0x1f
  52
  53 #define UARTCR1_LOOPS           0x80
  54 #define UARTCR1_RSRC            0x20
  55 #define UARTCR1_M               0x10
  56 #define UARTCR1_WAKE            0x08
  57 #define UARTCR1_ILT             0x04
  58 #define UARTCR1_PE              0x02
  59 #define UARTCR1_PT              0x01
  60
  61 #define UARTCR2_TIE             0x80
  62 #define UARTCR2_TCIE            0x40
  63 #define UARTCR2_RIE             0x20
  64 #define UARTCR2_ILIE            0x10
  65 #define UARTCR2_TE              0x08
  66 #define UARTCR2_RE              0x04
  67 #define UARTCR2_RWU             0x02
  68 #define UARTCR2_SBK             0x01
  69
  70 #define UARTSR1_TDRE            0x80
  71 #define UARTSR1_TC              0x40
  72 #define UARTSR1_RDRF            0x20
  73 #define UARTSR1_IDLE            0x10
  74 #define UARTSR1_OR              0x08
  75 #define UARTSR1_NF              0x04
  76 #define UARTSR1_FE              0x02
  77 #define UARTSR1_PE              0x01
  78
  79 #define UARTCR3_R8              0x80
  80 #define UARTCR3_T8              0x40
  81 #define UARTCR3_TXDIR           0x20
  82 #define UARTCR3_TXINV           0x10
  83 #define UARTCR3_ORIE            0x08
  84 #define UARTCR3_NEIE            0x04
  85 #define UARTCR3_FEIE            0x02
  86 #define UARTCR3_PEIE            0x01
  87
  88 #define UARTCR4_MAEN1           0x80
  89 #define UARTCR4_MAEN2           0x40
  90 #define UARTCR4_M10             0x20
  91 #define UARTCR4_BRFA_MASK       0x1f
  92 #define UARTCR4_BRFA_OFF        0
  93
  94 #define UARTCR5_TDMAS           0x80
  95 #define UARTCR5_RDMAS           0x20
  96
  97 #define UARTMODEM_RXRTSE        0x08
  98 #define UARTMODEM_TXRTSPOL      0x04
  99 #define UARTMODEM_TXRTSE        0x02
 100 #define UARTMODEM_TXCTSE        0x01
 101
 102 #define UARTPFIFO_TXFE          0x80
 103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 104 #define UARTPFIFO_TXSIZE_OFF    4
 105 #define UARTPFIFO_RXFE          0x08
 106 #define UARTPFIFO_RXSIZE_OFF    0
 107
 108 #define UARTCFIFO_TXFLUSH       0x80
 109 #define UARTCFIFO_RXFLUSH       0x40
 110 #define UARTCFIFO_RXOFE         0x04
 111 #define UARTCFIFO_TXOFE         0x02
 112 #define UARTCFIFO_RXUFE         0x01
 113
 114 #define UARTSFIFO_TXEMPT        0x80
 115 #define UARTSFIFO_RXEMPT        0x40
 116 #define UARTSFIFO_RXOF          0x04
 117 #define UARTSFIFO_TXOF          0x02
 118 #define UARTSFIFO_RXUF          0x01
 119
 120 /* 32-bit register defination */
 121 #define UARTBAUD                0x00
 122 #define UARTSTAT                0x04
 123 #define UARTCTRL                0x08
 124 #define UARTDATA                0x0C
 125 #define UARTMATCH               0x10
 126 #define UARTMODIR               0x14
 127 #define UARTFIFO                0x18
 128 #define UARTWATER               0x1c
 129
 130 #define UARTBAUD_MAEN1          0x80000000
 131 #define UARTBAUD_MAEN2          0x40000000
 132 #define UARTBAUD_M10            0x20000000
 133 #define UARTBAUD_TDMAE          0x00800000
 134 #define UARTBAUD_RDMAE          0x00200000
 135 #define UARTBAUD_MATCFG         0x00400000
 136 #define UARTBAUD_BOTHEDGE       0x00020000
 137 #define UARTBAUD_RESYNCDIS      0x00010000
 138 #define UARTBAUD_LBKDIE         0x00008000
 139 #define UARTBAUD_RXEDGIE        0x00004000
 140 #define UARTBAUD_SBNS           0x00002000
 141 #define UARTBAUD_SBR            0x00000000
 142 #define UARTBAUD_SBR_MASK       0x1fff
 143
 144 #define UARTSTAT_LBKDIF         0x80000000
 145 #define UARTSTAT_RXEDGIF        0x40000000
 146 #define UARTSTAT_MSBF           0x20000000
 147 #define UARTSTAT_RXINV          0x10000000
 148 #define UARTSTAT_RWUID          0x08000000
 149 #define UARTSTAT_BRK13          0x04000000
 150 #define UARTSTAT_LBKDE          0x02000000
 151 #define UARTSTAT_RAF            0x01000000
 152 #define UARTSTAT_TDRE           0x00800000
 153 #define UARTSTAT_TC             0x00400000
 154 #define UARTSTAT_RDRF           0x00200000
 155 #define UARTSTAT_IDLE           0x00100000
 156 #define UARTSTAT_OR             0x00080000
 157 #define UARTSTAT_NF             0x00040000
 158 #define UARTSTAT_FE             0x00020000
 159 #define UARTSTAT_PE             0x00010000
 160 #define UARTSTAT_MA1F           0x00008000
 161 #define UARTSTAT_M21F           0x00004000
 162
 163 #define UARTCTRL_R8T9           0x80000000
 164 #define UARTCTRL_R9T8           0x40000000
 165 #define UARTCTRL_TXDIR          0x20000000
 166 #define UARTCTRL_TXINV          0x10000000
 167 #define UARTCTRL_ORIE           0x08000000
 168 #define UARTCTRL_NEIE           0x04000000
 169 #define UARTCTRL_FEIE           0x02000000
 170 #define UARTCTRL_PEIE           0x01000000
 171 #define UARTCTRL_TIE            0x00800000
 172 #define UARTCTRL_TCIE           0x00400000
 173 #define UARTCTRL_RIE            0x00200000
 174 #define UARTCTRL_ILIE           0x00100000
 175 #define UARTCTRL_TE             0x00080000
 176 #define UARTCTRL_RE             0x00040000
 177 #define UARTCTRL_RWU            0x00020000
 178 #define UARTCTRL_SBK            0x00010000
 179 #define UARTCTRL_MA1IE          0x00008000
 180 #define UARTCTRL_MA2IE          0x00004000
 181 #define UARTCTRL_IDLECFG        0x00000100
 182 #define UARTCTRL_LOOPS          0x00000080
 183 #define UARTCTRL_DOZEEN         0x00000040
 184 #define UARTCTRL_RSRC           0x00000020
 185 #define UARTCTRL_M              0x00000010
 186 #define UARTCTRL_WAKE           0x00000008
 187 #define UARTCTRL_ILT            0x00000004
 188 #define UARTCTRL_PE             0x00000002
 189 #define UARTCTRL_PT             0x00000001
 190
 191 #define UARTDATA_NOISY          0x00008000
 192 #define UARTDATA_PARITYE        0x00004000
 193 #define UARTDATA_FRETSC         0x00002000
 194 #define UARTDATA_RXEMPT         0x00001000
 195 #define UARTDATA_IDLINE         0x00000800
 196 #define UARTDATA_MASK           0x3ff
 197
 198 #define UARTMODIR_IREN          0x00020000
 199 #define UARTMODIR_TXCTSSRC      0x00000020
 200 #define UARTMODIR_TXCTSC        0x00000010
 201 #define UARTMODIR_RXRTSE        0x00000008
 202 #define UARTMODIR_TXRTSPOL      0x00000004
 203 #define UARTMODIR_TXRTSE        0x00000002
 204 #define UARTMODIR_TXCTSE        0x00000001
 205
 206 #define UARTFIFO_TXEMPT         0x00800000
 207 #define UARTFIFO_RXEMPT         0x00400000
 208 #define UARTFIFO_TXOF           0x00020000
 209 #define UARTFIFO_RXUF           0x00010000
 210 #define UARTFIFO_TXFLUSH        0x00008000
 211 #define UARTFIFO_RXFLUSH        0x00004000
 212 #define UARTFIFO_TXOFE          0x00000200
 213 #define UARTFIFO_RXUFE          0x00000100
 214 #define UARTFIFO_TXFE           0x00000080
 215 #define UARTFIFO_FIFOSIZE_MASK  0x7
 216 #define UARTFIFO_TXSIZE_OFF     4
 217 #define UARTFIFO_RXFE           0x00000008
 218 #define UARTFIFO_RXSIZE_OFF     0
 219
 220 #define UARTWATER_COUNT_MASK    0xff
 221 #define UARTWATER_TXCNT_OFF     8
 222 #define UARTWATER_RXCNT_OFF     24
 223 #define UARTWATER_WATER_MASK    0xff
 224 #define UARTWATER_TXWATER_OFF   0
 225 #define UARTWATER_RXWATER_OFF   16
 226
 227 #define FSL_UART_RX_DMA_BUFFER_SIZE     64
 228
 229 #define DRIVER_NAME     "fsl-lpuart"
 230 #define DEV_NAME        "ttyLP"
 231 #define UART_NR         6
 232
 233 struct lpuart_port {
 234         struct uart_port        port;
 235         struct clk              *clk;
 236         unsigned int            txfifo_size;
 237         unsigned int            rxfifo_size;
 238         bool                    lpuart32;
 239
 240         bool                    lpuart_dma_tx_use;
 241         bool                    lpuart_dma_rx_use;
 242         struct dma_chan         *dma_tx_chan;
 243         struct dma_chan         *dma_rx_chan;
 244         struct dma_async_tx_descriptor  *dma_tx_desc;
 245         struct dma_async_tx_descriptor  *dma_rx_desc;
 246         dma_addr_t              dma_tx_buf_bus;
 247         dma_addr_t              dma_rx_buf_bus;
 248         dma_cookie_t            dma_tx_cookie;
 249         dma_cookie_t            dma_rx_cookie;
 250         unsigned char           *dma_tx_buf_virt;
 251         unsigned char           *dma_rx_buf_virt;
 252         unsigned int            dma_tx_bytes;
 253         unsigned int            dma_rx_bytes;
 254         int                     dma_tx_in_progress;
 255         int                     dma_rx_in_progress;
 256         unsigned int            dma_rx_timeout;
 257         struct timer_list       lpuart_timer;
 258 };
 259
 260 static struct of_device_id lpuart_dt_ids[] = {
 261         {
 262                 .compatible = "fsl,vf610-lpuart",
 263         },
 264         {
 265                 .compatible = "fsl,ls1021a-lpuart",
 266         },
 267         { /* sentinel */ }
 268 };
 269 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 270
 271 /* Forward declare this for the dma callbacks*/
 272 static void lpuart_dma_tx_complete(void *arg);
 273 static void lpuart_dma_rx_complete(void *arg);
 274
 275 static u32 lpuart32_read(void __iomem *addr)
 276 {
 277         return ioread32be(addr);
 278 }
 279
 280 static void lpuart32_write(u32 val, void __iomem *addr)
 281 {
 282         iowrite32be(val, addr);
 283 }
 284
 285 static void lpuart_stop_tx(struct uart_port *port)
 286 {
 287         unsigned char temp;
 288
 289         temp = readb(port->membase + UARTCR2);
 290         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 291         writeb(temp, port->membase + UARTCR2);
 292 }
 293
 294 static void lpuart32_stop_tx(struct uart_port *port)
 295 {
 296         unsigned long temp;
 297
 298         temp = lpuart32_read(port->membase + UARTCTRL);
 299         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 300         lpuart32_write(temp, port->membase + UARTCTRL);
 301 }
 302
 303 static void lpuart_stop_rx(struct uart_port *port)
 304 {
 305         unsigned char temp;
 306
 307         temp = readb(port->membase + UARTCR2);
 308         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 309 }
 310
 311 static void lpuart32_stop_rx(struct uart_port *port)
 312 {
 313         unsigned long temp;
 314
 315         temp = lpuart32_read(port->membase + UARTCTRL);
 316         lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
 317 }
 318
 319 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
 320                 struct tty_port *tty, int count)
 321 {
 322         int copied;
 323
 324         sport->port.icount.rx += count;
 325
 326         if (!tty) {
 327                 dev_err(sport->port.dev, "No tty port\n");
 328                 return;
 329         }
 330
 331         dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
 332                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
 333         copied = tty_insert_flip_string(tty,
 334                         ((unsigned char *)(sport->dma_rx_buf_virt)), count);
 335
 336         if (copied != count) {
 337                 WARN_ON(1);
 338                 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
 339         }
 340
 341         dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
 342                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
 343 }
 344
 345 static void lpuart_pio_tx(struct lpuart_port *sport)
 346 {
 347         struct circ_buf *xmit = &sport->port.state->xmit;
 348         unsigned long flags;
 349
 350         spin_lock_irqsave(&sport->port.lock, flags);
 351
 352         while (!uart_circ_empty(xmit) &&
 353                 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
 354                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 355                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 356                 sport->port.icount.tx++;
 357         }
 358
 359         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 360                 uart_write_wakeup(&sport->port);
 361
 362         if (uart_circ_empty(xmit))
 363                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
 364                         sport->port.membase + UARTCR5);
 365
 366         spin_unlock_irqrestore(&sport->port.lock, flags);
 367 }
 368
 369 static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
 370 {
 371         struct circ_buf *xmit = &sport->port.state->xmit;
 372         dma_addr_t tx_bus_addr;
 373
 374         dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
 375                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 376         sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
 377         tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
 378         sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
 379                                         tx_bus_addr, sport->dma_tx_bytes,
 380                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 381
 382         if (!sport->dma_tx_desc) {
 383                 dev_err(sport->port.dev, "Not able to get desc for tx\n");
 384                 return -EIO;
 385         }
 386
 387         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 388         sport->dma_tx_desc->callback_param = sport;
 389         sport->dma_tx_in_progress = 1;
 390         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 391         dma_async_issue_pending(sport->dma_tx_chan);
 392
 393         return 0;
 394 }
 395
 396 static void lpuart_prepare_tx(struct lpuart_port *sport)
 397 {
 398         struct circ_buf *xmit = &sport->port.state->xmit;
 399         unsigned long count =  CIRC_CNT_TO_END(xmit->head,
 400                                         xmit->tail, UART_XMIT_SIZE);
 401
 402         if (!count)
 403                 return;
 404
 405         if (count < sport->txfifo_size)
 406                 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
 407                                 sport->port.membase + UARTCR5);
 408         else {
 409                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
 410                                 sport->port.membase + UARTCR5);
 411                 lpuart_dma_tx(sport, count);
 412         }
 413 }
 414
 415 static void lpuart_dma_tx_complete(void *arg)
 416 {
 417         struct lpuart_port *sport = arg;
 418         struct circ_buf *xmit = &sport->port.state->xmit;
 419         unsigned long flags;
 420
 421         async_tx_ack(sport->dma_tx_desc);
 422
 423         spin_lock_irqsave(&sport->port.lock, flags);
 424
 425         xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
 426         sport->dma_tx_in_progress = 0;
 427
 428         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 429                 uart_write_wakeup(&sport->port);
 430
 431         lpuart_prepare_tx(sport);
 432
 433         spin_unlock_irqrestore(&sport->port.lock, flags);
 434 }
 435
 436 static int lpuart_dma_rx(struct lpuart_port *sport)
 437 {
 438         dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
 439                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
 440         sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
 441                         sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
 442                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
 443
 444         if (!sport->dma_rx_desc) {
 445                 dev_err(sport->port.dev, "Not able to get desc for rx\n");
 446                 return -EIO;
 447         }
 448
 449         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
 450         sport->dma_rx_desc->callback_param = sport;
 451         sport->dma_rx_in_progress = 1;
 452         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
 453         dma_async_issue_pending(sport->dma_rx_chan);
 454
 455         return 0;
 456 }
 457
 458 static void lpuart_dma_rx_complete(void *arg)
 459 {
 460         struct lpuart_port *sport = arg;
 461         struct tty_port *port = &sport->port.state->port;
 462         unsigned long flags;
 463
 464         async_tx_ack(sport->dma_rx_desc);
 465         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
 466
 467         spin_lock_irqsave(&sport->port.lock, flags);
 468
 469         sport->dma_rx_in_progress = 0;
 470         lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
 471         tty_flip_buffer_push(port);
 472         lpuart_dma_rx(sport);
 473
 474         spin_unlock_irqrestore(&sport->port.lock, flags);
 475 }
 476
 477 static void lpuart_timer_func(unsigned long data)
 478 {
 479         struct lpuart_port *sport = (struct lpuart_port *)data;
 480         struct tty_port *port = &sport->port.state->port;
 481         struct dma_tx_state state;
 482         unsigned long flags;
 483         unsigned char temp;
 484         int count;
 485
 486         del_timer(&sport->lpuart_timer);
 487         dmaengine_pause(sport->dma_rx_chan);
 488         dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
 489         dmaengine_terminate_all(sport->dma_rx_chan);
 490         count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
 491         async_tx_ack(sport->dma_rx_desc);
 492
 493         spin_lock_irqsave(&sport->port.lock, flags);
 494
 495         sport->dma_rx_in_progress = 0;
 496         lpuart_copy_rx_to_tty(sport, port, count);
 497         tty_flip_buffer_push(port);
 498         temp = readb(sport->port.membase + UARTCR5);
 499         writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
 500
 501         spin_unlock_irqrestore(&sport->port.lock, flags);
 502 }
 503
 504 static inline void lpuart_prepare_rx(struct lpuart_port *sport)
 505 {
 506         unsigned long flags;
 507         unsigned char temp;
 508
 509         spin_lock_irqsave(&sport->port.lock, flags);
 510
 511         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
 512         add_timer(&sport->lpuart_timer);
 513
 514         lpuart_dma_rx(sport);
 515         temp = readb(sport->port.membase + UARTCR5);
 516         writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
 517
 518         spin_unlock_irqrestore(&sport->port.lock, flags);
 519 }
 520
 521 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 522 {
 523         struct circ_buf *xmit = &sport->port.state->xmit;
 524
 525         while (!uart_circ_empty(xmit) &&
 526                 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
 527                 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
 528                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 529                 sport->port.icount.tx++;
 530         }
 531
 532         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 533                 uart_write_wakeup(&sport->port);
 534
 535         if (uart_circ_empty(xmit))
 536                 lpuart_stop_tx(&sport->port);
 537 }
 538
 539 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 540 {
 541         struct circ_buf *xmit = &sport->port.state->xmit;
 542         unsigned long txcnt;
 543
 544         txcnt = lpuart32_read(sport->port.membase + UARTWATER);
 545         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 546         txcnt &= UARTWATER_COUNT_MASK;
 547         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 548                 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
 549                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 550                 sport->port.icount.tx++;
 551                 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
 552                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 553                 txcnt &= UARTWATER_COUNT_MASK;
 554         }
 555
 556         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 557                 uart_write_wakeup(&sport->port);
 558
 559         if (uart_circ_empty(xmit))
 560                 lpuart32_stop_tx(&sport->port);
 561 }
 562
 563 static void lpuart_start_tx(struct uart_port *port)
 564 {
 565         struct lpuart_port *sport = container_of(port,
 566                         struct lpuart_port, port);
 567         struct circ_buf *xmit = &sport->port.state->xmit;
 568         unsigned char temp;
 569
 570         temp = readb(port->membase + UARTCR2);
 571         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 572
 573         if (sport->lpuart_dma_tx_use) {
 574                 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
 575                         lpuart_prepare_tx(sport);
 576         } else {
 577                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 578                         lpuart_transmit_buffer(sport);
 579         }
 580 }
 581
 582 static void lpuart32_start_tx(struct uart_port *port)
 583 {
 584         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 585         unsigned long temp;
 586
 587         temp = lpuart32_read(port->membase + UARTCTRL);
 588         lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
 589
 590         if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
 591                 lpuart32_transmit_buffer(sport);
 592 }
 593
 594 static irqreturn_t lpuart_txint(int irq, void *dev_id)
 595 {
 596         struct lpuart_port *sport = dev_id;
 597         struct circ_buf *xmit = &sport->port.state->xmit;
 598         unsigned long flags;
 599
 600         spin_lock_irqsave(&sport->port.lock, flags);
 601         if (sport->port.x_char) {
 602                 if (sport->lpuart32)
 603                         lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
 604                 else
 605                         writeb(sport->port.x_char, sport->port.membase + UARTDR);
 606                 goto out;
 607         }
 608
 609         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 610                 if (sport->lpuart32)
 611                         lpuart32_stop_tx(&sport->port);
 612                 else
 613                         lpuart_stop_tx(&sport->port);
 614                 goto out;
 615         }
 616
 617         if (sport->lpuart32)
 618                 lpuart32_transmit_buffer(sport);
 619         else
 620                 lpuart_transmit_buffer(sport);
 621
 622         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 623                 uart_write_wakeup(&sport->port);
 624
 625 out:
 626         spin_unlock_irqrestore(&sport->port.lock, flags);
 627         return IRQ_HANDLED;
 628 }
 629
 630 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
 631 {
 632         struct lpuart_port *sport = dev_id;
 633         unsigned int flg, ignored = 0;
 634         struct tty_port *port = &sport->port.state->port;
 635         unsigned long flags;
 636         unsigned char rx, sr;
 637
 638         spin_lock_irqsave(&sport->port.lock, flags);
 639
 640         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 641                 flg = TTY_NORMAL;
 642                 sport->port.icount.rx++;
 643                 /*
 644                  * to clear the FE, OR, NF, FE, PE flags,
 645                  * read SR1 then read DR
 646                  */
 647                 sr = readb(sport->port.membase + UARTSR1);
 648                 rx = readb(sport->port.membase + UARTDR);
 649
 650                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 651                         continue;
 652
 653                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 654                         if (sr & UARTSR1_PE)
 655                                 sport->port.icount.parity++;
 656                         else if (sr & UARTSR1_FE)
 657                                 sport->port.icount.frame++;
 658
 659                         if (sr & UARTSR1_OR)
 660                                 sport->port.icount.overrun++;
 661
 662                         if (sr & sport->port.ignore_status_mask) {
 663                                 if (++ignored > 100)
 664                                         goto out;
 665                                 continue;
 666                         }
 667
 668                         sr &= sport->port.read_status_mask;
 669
 670                         if (sr & UARTSR1_PE)
 671                                 flg = TTY_PARITY;
 672                         else if (sr & UARTSR1_FE)
 673                                 flg = TTY_FRAME;
 674
 675                         if (sr & UARTSR1_OR)
 676                                 flg = TTY_OVERRUN;
 677
 678 #ifdef SUPPORT_SYSRQ
 679                         sport->port.sysrq = 0;
 680 #endif
 681                 }
 682
 683                 tty_insert_flip_char(port, rx, flg);
 684         }
 685
 686 out:
 687         spin_unlock_irqrestore(&sport->port.lock, flags);
 688
 689         tty_flip_buffer_push(port);
 690         return IRQ_HANDLED;
 691 }
 692
 693 static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
 694 {
 695         struct lpuart_port *sport = dev_id;
 696         unsigned int flg, ignored = 0;
 697         struct tty_port *port = &sport->port.state->port;
 698         unsigned long flags;
 699         unsigned long rx, sr;
 700
 701         spin_lock_irqsave(&sport->port.lock, flags);
 702
 703         while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
 704                 flg = TTY_NORMAL;
 705                 sport->port.icount.rx++;
 706                 /*
 707                  * to clear the FE, OR, NF, FE, PE flags,
 708                  * read STAT then read DATA reg
 709                  */
 710                 sr = lpuart32_read(sport->port.membase + UARTSTAT);
 711                 rx = lpuart32_read(sport->port.membase + UARTDATA);
 712                 rx &= 0x3ff;
 713
 714                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 715                         continue;
 716
 717                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 718                         if (sr & UARTSTAT_PE)
 719                                 sport->port.icount.parity++;
 720                         else if (sr & UARTSTAT_FE)
 721                                 sport->port.icount.frame++;
 722
 723                         if (sr & UARTSTAT_OR)
 724                                 sport->port.icount.overrun++;
 725
 726                         if (sr & sport->port.ignore_status_mask) {
 727                                 if (++ignored > 100)
 728                                         goto out;
 729                                 continue;
 730                         }
 731
 732                         sr &= sport->port.read_status_mask;
 733
 734                         if (sr & UARTSTAT_PE)
 735                                 flg = TTY_PARITY;
 736                         else if (sr & UARTSTAT_FE)
 737                                 flg = TTY_FRAME;
 738
 739                         if (sr & UARTSTAT_OR)
 740                                 flg = TTY_OVERRUN;
 741
 742 #ifdef SUPPORT_SYSRQ
 743                         sport->port.sysrq = 0;
 744 #endif
 745                 }
 746
 747                 tty_insert_flip_char(port, rx, flg);
 748         }
 749
 750 out:
 751         spin_unlock_irqrestore(&sport->port.lock, flags);
 752
 753         tty_flip_buffer_push(port);
 754         return IRQ_HANDLED;
 755 }
 756
 757 static irqreturn_t lpuart_int(int irq, void *dev_id)
 758 {
 759         struct lpuart_port *sport = dev_id;
 760         unsigned char sts, crdma;
 761
 762         sts = readb(sport->port.membase + UARTSR1);
 763         crdma = readb(sport->port.membase + UARTCR5);
 764
 765         if (sts & UARTSR1_RDRF && !(crdma & UARTCR5_RDMAS)) {
 766                 if (sport->lpuart_dma_rx_use)
 767                         lpuart_prepare_rx(sport);
 768                 else
 769                         lpuart_rxint(irq, dev_id);
 770         }
 771         if (sts & UARTSR1_TDRE && !(crdma & UARTCR5_TDMAS)) {
 772                 if (sport->lpuart_dma_tx_use)
 773                         lpuart_pio_tx(sport);
 774                 else
 775                         lpuart_txint(irq, dev_id);
 776         }
 777
 778         return IRQ_HANDLED;
 779 }
 780
 781 static irqreturn_t lpuart32_int(int irq, void *dev_id)
 782 {
 783         struct lpuart_port *sport = dev_id;
 784         unsigned long sts, rxcount;
 785
 786         sts = lpuart32_read(sport->port.membase + UARTSTAT);
 787         rxcount = lpuart32_read(sport->port.membase + UARTWATER);
 788         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
 789
 790         if (sts & UARTSTAT_RDRF || rxcount > 0)
 791                 lpuart32_rxint(irq, dev_id);
 792
 793         if ((sts & UARTSTAT_TDRE) &&
 794                 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
 795                 lpuart_txint(irq, dev_id);
 796
 797         lpuart32_write(sts, sport->port.membase + UARTSTAT);
 798         return IRQ_HANDLED;
 799 }
 800
 801 /* return TIOCSER_TEMT when transmitter is not busy */
 802 static unsigned int lpuart_tx_empty(struct uart_port *port)
 803 {
 804         return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
 805                 TIOCSER_TEMT : 0;
 806 }
 807
 808 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 809 {
 810         return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
 811                 TIOCSER_TEMT : 0;
 812 }
 813
 814 static unsigned int lpuart_get_mctrl(struct uart_port *port)
 815 {
 816         unsigned int temp = 0;
 817         unsigned char reg;
 818
 819         reg = readb(port->membase + UARTMODEM);
 820         if (reg & UARTMODEM_TXCTSE)
 821                 temp |= TIOCM_CTS;
 822
 823         if (reg & UARTMODEM_RXRTSE)
 824                 temp |= TIOCM_RTS;
 825
 826         return temp;
 827 }
 828
 829 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
 830 {
 831         unsigned int temp = 0;
 832         unsigned long reg;
 833
 834         reg = lpuart32_read(port->membase + UARTMODIR);
 835         if (reg & UARTMODIR_TXCTSE)
 836                 temp |= TIOCM_CTS;
 837
 838         if (reg & UARTMODIR_RXRTSE)
 839                 temp |= TIOCM_RTS;
 840
 841         return temp;
 842 }
 843
 844 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 845 {
 846         unsigned char temp;
 847
 848         temp = readb(port->membase + UARTMODEM) &
 849                         ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
 850
 851         if (mctrl & TIOCM_RTS)
 852                 temp |= UARTMODEM_RXRTSE;
 853
 854         if (mctrl & TIOCM_CTS)
 855                 temp |= UARTMODEM_TXCTSE;
 856
 857         writeb(temp, port->membase + UARTMODEM);
 858 }
 859
 860 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 861 {
 862         unsigned long temp;
 863
 864         temp = lpuart32_read(port->membase + UARTMODIR) &
 865                         ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
 866
 867         if (mctrl & TIOCM_RTS)
 868                 temp |= UARTMODIR_RXRTSE;
 869
 870         if (mctrl & TIOCM_CTS)
 871                 temp |= UARTMODIR_TXCTSE;
 872
 873         lpuart32_write(temp, port->membase + UARTMODIR);
 874 }
 875
 876 static void lpuart_break_ctl(struct uart_port *port, int break_state)
 877 {
 878         unsigned char temp;
 879
 880         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
 881
 882         if (break_state != 0)
 883                 temp |= UARTCR2_SBK;
 884
 885         writeb(temp, port->membase + UARTCR2);
 886 }
 887
 888 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
 889 {
 890         unsigned long temp;
 891
 892         temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
 893
 894         if (break_state != 0)
 895                 temp |= UARTCTRL_SBK;
 896
 897         lpuart32_write(temp, port->membase + UARTCTRL);
 898 }
 899
 900 static void lpuart_setup_watermark(struct lpuart_port *sport)
 901 {
 902         unsigned char val, cr2;
 903         unsigned char cr2_saved;
 904
 905         cr2 = readb(sport->port.membase + UARTCR2);
 906         cr2_saved = cr2;
 907         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
 908                         UARTCR2_RIE | UARTCR2_RE);
 909         writeb(cr2, sport->port.membase + UARTCR2);
 910
 911         val = readb(sport->port.membase + UARTPFIFO);
 912         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
 913                         sport->port.membase + UARTPFIFO);
 914
 915         /* flush Tx and Rx FIFO */
 916         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 917                         sport->port.membase + UARTCFIFO);
 918
 919         writeb(0, sport->port.membase + UARTTWFIFO);
 920         writeb(1, sport->port.membase + UARTRWFIFO);
 921
 922         /* Restore cr2 */
 923         writeb(cr2_saved, sport->port.membase + UARTCR2);
 924 }
 925
 926 static void lpuart32_setup_watermark(struct lpuart_port *sport)
 927 {
 928         unsigned long val, ctrl;
 929         unsigned long ctrl_saved;
 930
 931         ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
 932         ctrl_saved = ctrl;
 933         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
 934                         UARTCTRL_RIE | UARTCTRL_RE);
 935         lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
 936
 937         /* enable FIFO mode */
 938         val = lpuart32_read(sport->port.membase + UARTFIFO);
 939         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
 940         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 941         lpuart32_write(val, sport->port.membase + UARTFIFO);
 942
 943         /* set the watermark */
 944         val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
 945         lpuart32_write(val, sport->port.membase + UARTWATER);
 946
 947         /* Restore cr2 */
 948         lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
 949 }
 950
 951 static int lpuart_dma_tx_request(struct uart_port *port)
 952 {
 953         struct lpuart_port *sport = container_of(port,
 954                                         struct lpuart_port, port);
 955         struct dma_slave_config dma_tx_sconfig;
 956         dma_addr_t dma_bus;
 957         unsigned char *dma_buf;
 958         int ret;
 959
 960         dma_bus = dma_map_single(sport->dma_tx_chan->device->dev,
 961                                 sport->port.state->xmit.buf,
 962                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 963
 964         if (dma_mapping_error(sport->dma_tx_chan->device->dev, dma_bus)) {
 965                 dev_err(sport->port.dev, "dma_map_single tx failed\n");
 966                 return -ENOMEM;
 967         }
 968
 969         dma_buf = sport->port.state->xmit.buf;
 970         dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
 971         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 972         dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
 973         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 974         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 975
 976         if (ret < 0) {
 977                 dev_err(sport->port.dev,
 978                                 "Dma slave config failed, err = %d\n", ret);
 979                 return ret;
 980         }
 981
 982         sport->dma_tx_buf_virt = dma_buf;
 983         sport->dma_tx_buf_bus = dma_bus;
 984         sport->dma_tx_in_progress = 0;
 985
 986         return 0;
 987 }
 988
 989 static int lpuart_dma_rx_request(struct uart_port *port)
 990 {
 991         struct lpuart_port *sport = container_of(port,
 992                                         struct lpuart_port, port);
 993         struct dma_slave_config dma_rx_sconfig;
 994         dma_addr_t dma_bus;
 995         unsigned char *dma_buf;
 996         int ret;
 997
 998         dma_buf = devm_kzalloc(sport->port.dev,
 999                                 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
1000
1001         if (!dma_buf) {
1002                 dev_err(sport->port.dev, "Dma rx alloc failed\n");
1003                 return -ENOMEM;
1004         }
1005
1006         dma_bus = dma_map_single(sport->dma_rx_chan->device->dev, dma_buf,
1007                                 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1008
1009         if (dma_mapping_error(sport->dma_rx_chan->device->dev, dma_bus)) {
1010                 dev_err(sport->port.dev, "dma_map_single rx failed\n");
1011                 return -ENOMEM;
1012         }
1013
1014         dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1015         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1016         dma_rx_sconfig.src_maxburst = 1;
1017         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1018         ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1019
1020         if (ret < 0) {
1021                 dev_err(sport->port.dev,
1022                                 "Dma slave config failed, err = %d\n", ret);
1023                 return ret;
1024         }
1025
1026         sport->dma_rx_buf_virt = dma_buf;
1027         sport->dma_rx_buf_bus = dma_bus;
1028         sport->dma_rx_in_progress = 0;
1029
1030         return 0;
1031 }
1032
1033 static void lpuart_dma_tx_free(struct uart_port *port)
1034 {
1035         struct lpuart_port *sport = container_of(port,
1036                                         struct lpuart_port, port);
1037
1038         dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
1039                         UART_XMIT_SIZE, DMA_TO_DEVICE);
1040
1041         sport->dma_tx_buf_bus = 0;
1042         sport->dma_tx_buf_virt = NULL;
1043 }
1044
1045 static void lpuart_dma_rx_free(struct uart_port *port)
1046 {
1047         struct lpuart_port *sport = container_of(port,
1048                                         struct lpuart_port, port);
1049
1050         dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
1051                         FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1052
1053         sport->dma_rx_buf_bus = 0;
1054         sport->dma_rx_buf_virt = NULL;
1055 }
1056
1057 static int lpuart_startup(struct uart_port *port)
1058 {
1059         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1060         int ret;
1061         unsigned long flags;
1062         unsigned char temp;
1063
1064         /* determine FIFO size and enable FIFO mode */
1065         temp = readb(sport->port.membase + UARTPFIFO);
1066
1067         sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1068                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1069
1070         sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1071                 UARTPFIFO_FIFOSIZE_MASK) + 1);
1072
1073         if (sport->dma_rx_chan && !lpuart_dma_rx_request(port)) {
1074                 sport->lpuart_dma_rx_use = true;
1075                 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1076                             (unsigned long)sport);
1077         } else
1078                 sport->lpuart_dma_rx_use = false;
1079
1080
1081         if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
1082                 sport->lpuart_dma_tx_use = true;
1083                 temp = readb(port->membase + UARTCR5);
1084                 temp &= ~UARTCR5_RDMAS;
1085                 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1086         } else
1087                 sport->lpuart_dma_tx_use = false;
1088
1089         ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1090                                 DRIVER_NAME, sport);
1091         if (ret)
1092                 return ret;
1093
1094         spin_lock_irqsave(&sport->port.lock, flags);
1095
1096         lpuart_setup_watermark(sport);
1097
1098         temp = readb(sport->port.membase + UARTCR2);
1099         temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1100         writeb(temp, sport->port.membase + UARTCR2);
1101
1102         spin_unlock_irqrestore(&sport->port.lock, flags);
1103         return 0;
1104 }
1105
1106 static int lpuart32_startup(struct uart_port *port)
1107 {
1108         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1109         int ret;
1110         unsigned long flags;
1111         unsigned long temp;
1112
1113         /* determine FIFO size */
1114         temp = lpuart32_read(sport->port.membase + UARTFIFO);
1115
1116         sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1117                 UARTFIFO_FIFOSIZE_MASK) - 1);
1118
1119         sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1120                 UARTFIFO_FIFOSIZE_MASK) - 1);
1121
1122         ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1123                                 DRIVER_NAME, sport);
1124         if (ret)
1125                 return ret;
1126
1127         spin_lock_irqsave(&sport->port.lock, flags);
1128
1129         lpuart32_setup_watermark(sport);
1130
1131         temp = lpuart32_read(sport->port.membase + UARTCTRL);
1132         temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1133         temp |= UARTCTRL_ILIE;
1134         lpuart32_write(temp, sport->port.membase + UARTCTRL);
1135
1136         spin_unlock_irqrestore(&sport->port.lock, flags);
1137         return 0;
1138 }
1139
1140 static void lpuart_shutdown(struct uart_port *port)
1141 {
1142         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1143         unsigned char temp;
1144         unsigned long flags;
1145
1146         spin_lock_irqsave(&port->lock, flags);
1147
1148         /* disable Rx/Tx and interrupts */
1149         temp = readb(port->membase + UARTCR2);
1150         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1151                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1152         writeb(temp, port->membase + UARTCR2);
1153
1154         spin_unlock_irqrestore(&port->lock, flags);
1155
1156         devm_free_irq(port->dev, port->irq, sport);
1157
1158         if (sport->lpuart_dma_rx_use) {
1159                 lpuart_dma_rx_free(&sport->port);
1160                 del_timer_sync(&sport->lpuart_timer);
1161         }
1162
1163         if (sport->lpuart_dma_tx_use)
1164                 lpuart_dma_tx_free(&sport->port);
1165 }
1166
1167 static void lpuart32_shutdown(struct uart_port *port)
1168 {
1169         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1170         unsigned long temp;
1171         unsigned long flags;
1172
1173         spin_lock_irqsave(&port->lock, flags);
1174
1175         /* disable Rx/Tx and interrupts */
1176         temp = lpuart32_read(port->membase + UARTCTRL);
1177         temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1178                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1179         lpuart32_write(temp, port->membase + UARTCTRL);
1180
1181         spin_unlock_irqrestore(&port->lock, flags);
1182
1183         devm_free_irq(port->dev, port->irq, sport);
1184 }
1185
1186 static void
1187 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1188                    struct ktermios *old)
1189 {
1190         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1191         unsigned long flags;
1192         unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
1193         unsigned int  baud;
1194         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1195         unsigned int sbr, brfa;
1196
1197         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1198         old_cr2 = readb(sport->port.membase + UARTCR2);
1199         cr4 = readb(sport->port.membase + UARTCR4);
1200         bdh = readb(sport->port.membase + UARTBDH);
1201         modem = readb(sport->port.membase + UARTMODEM);
1202         /*
1203          * only support CS8 and CS7, and for CS7 must enable PE.
1204          * supported mode:
1205          *  - (7,e/o,1)
1206          *  - (8,n,1)
1207          *  - (8,m/s,1)
1208          *  - (8,e/o,1)
1209          */
1210         while ((termios->c_cflag & CSIZE) != CS8 &&
1211                 (termios->c_cflag & CSIZE) != CS7) {
1212                 termios->c_cflag &= ~CSIZE;
1213                 termios->c_cflag |= old_csize;
1214                 old_csize = CS8;
1215         }
1216
1217         if ((termios->c_cflag & CSIZE) == CS8 ||
1218                 (termios->c_cflag & CSIZE) == CS7)
1219                 cr1 = old_cr1 & ~UARTCR1_M;
1220
1221         if (termios->c_cflag & CMSPAR) {
1222                 if ((termios->c_cflag & CSIZE) != CS8) {
1223                         termios->c_cflag &= ~CSIZE;
1224                         termios->c_cflag |= CS8;
1225                 }
1226                 cr1 |= UARTCR1_M;
1227         }
1228
1229         if (termios->c_cflag & CRTSCTS) {
1230                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1231         } else {
1232                 termios->c_cflag &= ~CRTSCTS;
1233                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1234         }
1235
1236         if (termios->c_cflag & CSTOPB)
1237                 termios->c_cflag &= ~CSTOPB;
1238
1239         /* parity must be enabled when CS7 to match 8-bits format */
1240         if ((termios->c_cflag & CSIZE) == CS7)
1241                 termios->c_cflag |= PARENB;
1242
1243         if ((termios->c_cflag & PARENB)) {
1244                 if (termios->c_cflag & CMSPAR) {
1245                         cr1 &= ~UARTCR1_PE;
1246                         cr1 |= UARTCR1_M;
1247                 } else {
1248                         cr1 |= UARTCR1_PE;
1249                         if ((termios->c_cflag & CSIZE) == CS8)
1250                                 cr1 |= UARTCR1_M;
1251                         if (termios->c_cflag & PARODD)
1252                                 cr1 |= UARTCR1_PT;
1253                         else
1254                                 cr1 &= ~UARTCR1_PT;
1255                 }
1256         }
1257
1258         /* ask the core to calculate the divisor */
1259         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1260
1261         spin_lock_irqsave(&sport->port.lock, flags);
1262
1263         sport->port.read_status_mask = 0;
1264         if (termios->c_iflag & INPCK)
1265                 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
1266         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1267                 sport->port.read_status_mask |= UARTSR1_FE;
1268
1269         /* characters to ignore */
1270         sport->port.ignore_status_mask = 0;
1271         if (termios->c_iflag & IGNPAR)
1272                 sport->port.ignore_status_mask |= UARTSR1_PE;
1273         if (termios->c_iflag & IGNBRK) {
1274                 sport->port.ignore_status_mask |= UARTSR1_FE;
1275                 /*
1276                  * if we're ignoring parity and break indicators,
1277                  * ignore overruns too (for real raw support).
1278                  */
1279                 if (termios->c_iflag & IGNPAR)
1280                         sport->port.ignore_status_mask |= UARTSR1_OR;
1281         }
1282
1283         /* update the per-port timeout */
1284         uart_update_timeout(port, termios->c_cflag, baud);
1285
1286         if (sport->lpuart_dma_rx_use) {
1287                 /* Calculate delay for 1.5 DMA buffers */
1288                 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
1289                                         FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
1290                                         sport->rxfifo_size / 2;
1291                 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1292                         sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
1293                 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
1294                         sport->dma_rx_timeout = msecs_to_jiffies(20);
1295         }
1296
1297         /* wait transmit engin complete */
1298         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1299                 barrier();
1300
1301         /* disable transmit and receive */
1302         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1303                         sport->port.membase + UARTCR2);
1304
1305         sbr = sport->port.uartclk / (16 * baud);
1306         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1307         bdh &= ~UARTBDH_SBR_MASK;
1308         bdh |= (sbr >> 8) & 0x1F;
1309         cr4 &= ~UARTCR4_BRFA_MASK;
1310         brfa &= UARTCR4_BRFA_MASK;
1311         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1312         writeb(bdh, sport->port.membase + UARTBDH);
1313         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1314         writeb(cr1, sport->port.membase + UARTCR1);
1315         writeb(modem, sport->port.membase + UARTMODEM);
1316
1317         /* restore control register */
1318         writeb(old_cr2, sport->port.membase + UARTCR2);
1319
1320         spin_unlock_irqrestore(&sport->port.lock, flags);
1321 }
1322
1323 static void
1324 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1325                    struct ktermios *old)
1326 {
1327         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1328         unsigned long flags;
1329         unsigned long ctrl, old_ctrl, bd, modem;
1330         unsigned int  baud;
1331         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1332         unsigned int sbr;
1333
1334         ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1335         bd = lpuart32_read(sport->port.membase + UARTBAUD);
1336         modem = lpuart32_read(sport->port.membase + UARTMODIR);
1337         /*
1338          * only support CS8 and CS7, and for CS7 must enable PE.
1339          * supported mode:
1340          *  - (7,e/o,1)
1341          *  - (8,n,1)
1342          *  - (8,m/s,1)
1343          *  - (8,e/o,1)
1344          */
1345         while ((termios->c_cflag & CSIZE) != CS8 &&
1346                 (termios->c_cflag & CSIZE) != CS7) {
1347                 termios->c_cflag &= ~CSIZE;
1348                 termios->c_cflag |= old_csize;
1349                 old_csize = CS8;
1350         }
1351
1352         if ((termios->c_cflag & CSIZE) == CS8 ||
1353                 (termios->c_cflag & CSIZE) == CS7)
1354                 ctrl = old_ctrl & ~UARTCTRL_M;
1355
1356         if (termios->c_cflag & CMSPAR) {
1357                 if ((termios->c_cflag & CSIZE) != CS8) {
1358                         termios->c_cflag &= ~CSIZE;
1359                         termios->c_cflag |= CS8;
1360                 }
1361                 ctrl |= UARTCTRL_M;
1362         }
1363
1364         if (termios->c_cflag & CRTSCTS) {
1365                 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1366         } else {
1367                 termios->c_cflag &= ~CRTSCTS;
1368                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1369         }
1370
1371         if (termios->c_cflag & CSTOPB)
1372                 termios->c_cflag &= ~CSTOPB;
1373
1374         /* parity must be enabled when CS7 to match 8-bits format */
1375         if ((termios->c_cflag & CSIZE) == CS7)
1376                 termios->c_cflag |= PARENB;
1377
1378         if ((termios->c_cflag & PARENB)) {
1379                 if (termios->c_cflag & CMSPAR) {
1380                         ctrl &= ~UARTCTRL_PE;
1381                         ctrl |= UARTCTRL_M;
1382                 } else {
1383                         ctrl |= UARTCR1_PE;
1384                         if ((termios->c_cflag & CSIZE) == CS8)
1385                                 ctrl |= UARTCTRL_M;
1386                         if (termios->c_cflag & PARODD)
1387                                 ctrl |= UARTCTRL_PT;
1388                         else
1389                                 ctrl &= ~UARTCTRL_PT;
1390                 }
1391         }
1392
1393         /* ask the core to calculate the divisor */
1394         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1395
1396         spin_lock_irqsave(&sport->port.lock, flags);
1397
1398         sport->port.read_status_mask = 0;
1399         if (termios->c_iflag & INPCK)
1400                 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1401         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1402                 sport->port.read_status_mask |= UARTSTAT_FE;
1403
1404         /* characters to ignore */
1405         sport->port.ignore_status_mask = 0;
1406         if (termios->c_iflag & IGNPAR)
1407                 sport->port.ignore_status_mask |= UARTSTAT_PE;
1408         if (termios->c_iflag & IGNBRK) {
1409                 sport->port.ignore_status_mask |= UARTSTAT_FE;
1410                 /*
1411                  * if we're ignoring parity and break indicators,
1412                  * ignore overruns too (for real raw support).
1413                  */
1414                 if (termios->c_iflag & IGNPAR)
1415                         sport->port.ignore_status_mask |= UARTSTAT_OR;
1416         }
1417
1418         /* update the per-port timeout */
1419         uart_update_timeout(port, termios->c_cflag, baud);
1420
1421         /* wait transmit engin complete */
1422         while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1423                 barrier();
1424
1425         /* disable transmit and receive */
1426         lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1427                         sport->port.membase + UARTCTRL);
1428
1429         sbr = sport->port.uartclk / (16 * baud);
1430         bd &= ~UARTBAUD_SBR_MASK;
1431         bd |= sbr & UARTBAUD_SBR_MASK;
1432         bd |= UARTBAUD_BOTHEDGE;
1433         bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1434         lpuart32_write(bd, sport->port.membase + UARTBAUD);
1435         lpuart32_write(modem, sport->port.membase + UARTMODIR);
1436         lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1437         /* restore control register */
1438
1439         spin_unlock_irqrestore(&sport->port.lock, flags);
1440 }
1441
1442 static const char *lpuart_type(struct uart_port *port)
1443 {
1444         return "FSL_LPUART";
1445 }
1446
1447 static void lpuart_release_port(struct uart_port *port)
1448 {
1449         /* nothing to do */
1450 }
1451
1452 static int lpuart_request_port(struct uart_port *port)
1453 {
1454         return  0;
1455 }
1456
1457 /* configure/autoconfigure the port */
1458 static void lpuart_config_port(struct uart_port *port, int flags)
1459 {
1460         if (flags & UART_CONFIG_TYPE)
1461                 port->type = PORT_LPUART;
1462 }
1463
1464 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1465 {
1466         int ret = 0;
1467
1468         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1469                 ret = -EINVAL;
1470         if (port->irq != ser->irq)
1471                 ret = -EINVAL;
1472         if (ser->io_type != UPIO_MEM)
1473                 ret = -EINVAL;
1474         if (port->uartclk / 16 != ser->baud_base)
1475                 ret = -EINVAL;
1476         if (port->iobase != ser->port)
1477                 ret = -EINVAL;
1478         if (ser->hub6 != 0)
1479                 ret = -EINVAL;
1480         return ret;
1481 }
1482
1483 static struct uart_ops lpuart_pops = {
1484         .tx_empty       = lpuart_tx_empty,
1485         .set_mctrl      = lpuart_set_mctrl,
1486         .get_mctrl      = lpuart_get_mctrl,
1487         .stop_tx        = lpuart_stop_tx,
1488         .start_tx       = lpuart_start_tx,
1489         .stop_rx        = lpuart_stop_rx,
1490         .break_ctl      = lpuart_break_ctl,
1491         .startup        = lpuart_startup,
1492         .shutdown       = lpuart_shutdown,
1493         .set_termios    = lpuart_set_termios,
1494         .type           = lpuart_type,
1495         .request_port   = lpuart_request_port,
1496         .release_port   = lpuart_release_port,
1497         .config_port    = lpuart_config_port,
1498         .verify_port    = lpuart_verify_port,
1499 };
1500
1501 static struct uart_ops lpuart32_pops = {
1502         .tx_empty       = lpuart32_tx_empty,
1503         .set_mctrl      = lpuart32_set_mctrl,
1504         .get_mctrl      = lpuart32_get_mctrl,
1505         .stop_tx        = lpuart32_stop_tx,
1506         .start_tx       = lpuart32_start_tx,
1507         .stop_rx        = lpuart32_stop_rx,
1508         .break_ctl      = lpuart32_break_ctl,
1509         .startup        = lpuart32_startup,
1510         .shutdown       = lpuart32_shutdown,
1511         .set_termios    = lpuart32_set_termios,
1512         .type           = lpuart_type,
1513         .request_port   = lpuart_request_port,
1514         .release_port   = lpuart_release_port,
1515         .config_port    = lpuart_config_port,
1516         .verify_port    = lpuart_verify_port,
1517 };
1518
1519 static struct lpuart_port *lpuart_ports[UART_NR];
1520
1521 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1522 static void lpuart_console_putchar(struct uart_port *port, int ch)
1523 {
1524         while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1525                 barrier();
1526
1527         writeb(ch, port->membase + UARTDR);
1528 }
1529
1530 static void lpuart32_console_putchar(struct uart_port *port, int ch)
1531 {
1532         while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1533                 barrier();
1534
1535         lpuart32_write(ch, port->membase + UARTDATA);
1536 }
1537
1538 static void
1539 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1540 {
1541         struct lpuart_port *sport = lpuart_ports[co->index];
1542         unsigned char  old_cr2, cr2;
1543
1544         /* first save CR2 and then disable interrupts */
1545         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1546         cr2 |= (UARTCR2_TE |  UARTCR2_RE);
1547         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1548         writeb(cr2, sport->port.membase + UARTCR2);
1549
1550         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1551
1552         /* wait for transmitter finish complete and restore CR2 */
1553         while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1554                 barrier();
1555
1556         writeb(old_cr2, sport->port.membase + UARTCR2);
1557 }
1558
1559 static void
1560 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1561 {
1562         struct lpuart_port *sport = lpuart_ports[co->index];
1563         unsigned long  old_cr, cr;
1564
1565         /* first save CR2 and then disable interrupts */
1566         cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1567         cr |= (UARTCTRL_TE |  UARTCTRL_RE);
1568         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1569         lpuart32_write(cr, sport->port.membase + UARTCTRL);
1570
1571         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1572
1573         /* wait for transmitter finish complete and restore CR2 */
1574         while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1575                 barrier();
1576
1577         lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1578 }
1579
1580 /*
1581  * if the port was already initialised (eg, by a boot loader),
1582  * try to determine the current setup.
1583  */
1584 static void __init
1585 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1586                            int *parity, int *bits)
1587 {
1588         unsigned char cr, bdh, bdl, brfa;
1589         unsigned int sbr, uartclk, baud_raw;
1590
1591         cr = readb(sport->port.membase + UARTCR2);
1592         cr &= UARTCR2_TE | UARTCR2_RE;
1593         if (!cr)
1594                 return;
1595
1596         /* ok, the port was enabled */
1597
1598         cr = readb(sport->port.membase + UARTCR1);
1599
1600         *parity = 'n';
1601         if (cr & UARTCR1_PE) {
1602                 if (cr & UARTCR1_PT)
1603                         *parity = 'o';
1604                 else
1605                         *parity = 'e';
1606         }
1607
1608         if (cr & UARTCR1_M)
1609                 *bits = 9;
1610         else
1611                 *bits = 8;
1612
1613         bdh = readb(sport->port.membase + UARTBDH);
1614         bdh &= UARTBDH_SBR_MASK;
1615         bdl = readb(sport->port.membase + UARTBDL);
1616         sbr = bdh;
1617         sbr <<= 8;
1618         sbr |= bdl;
1619         brfa = readb(sport->port.membase + UARTCR4);
1620         brfa &= UARTCR4_BRFA_MASK;
1621
1622         uartclk = clk_get_rate(sport->clk);
1623         /*
1624          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1625          */
1626         baud_raw = uartclk / (16 * (sbr + brfa / 32));
1627
1628         if (*baud != baud_raw)
1629                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1630                                 "from %d to %d\n", baud_raw, *baud);
1631 }
1632
1633 static void __init
1634 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1635                            int *parity, int *bits)
1636 {
1637         unsigned long cr, bd;
1638         unsigned int sbr, uartclk, baud_raw;
1639
1640         cr = lpuart32_read(sport->port.membase + UARTCTRL);
1641         cr &= UARTCTRL_TE | UARTCTRL_RE;
1642         if (!cr)
1643                 return;
1644
1645         /* ok, the port was enabled */
1646
1647         cr = lpuart32_read(sport->port.membase + UARTCTRL);
1648
1649         *parity = 'n';
1650         if (cr & UARTCTRL_PE) {
1651                 if (cr & UARTCTRL_PT)
1652                         *parity = 'o';
1653                 else
1654                         *parity = 'e';
1655         }
1656
1657         if (cr & UARTCTRL_M)
1658                 *bits = 9;
1659         else
1660                 *bits = 8;
1661
1662         bd = lpuart32_read(sport->port.membase + UARTBAUD);
1663         bd &= UARTBAUD_SBR_MASK;
1664         sbr = bd;
1665         uartclk = clk_get_rate(sport->clk);
1666         /*
1667          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1668          */
1669         baud_raw = uartclk / (16 * sbr);
1670
1671         if (*baud != baud_raw)
1672                 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1673                                 "from %d to %d\n", baud_raw, *baud);
1674 }
1675
1676 static int __init lpuart_console_setup(struct console *co, char *options)
1677 {
1678         struct lpuart_port *sport;
1679         int baud = 115200;
1680         int bits = 8;
1681         int parity = 'n';
1682         int flow = 'n';
1683
1684         /*
1685          * check whether an invalid uart number has been specified, and
1686          * if so, search for the first available port that does have
1687          * console support.
1688          */
1689         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1690                 co->index = 0;
1691
1692         sport = lpuart_ports[co->index];
1693         if (sport == NULL)
1694                 return -ENODEV;
1695
1696         if (options)
1697                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1698         else
1699                 if (sport->lpuart32)
1700                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
1701                 else
1702                         lpuart_console_get_options(sport, &baud, &parity, &bits);
1703
1704         if (sport->lpuart32)
1705                 lpuart32_setup_watermark(sport);
1706         else
1707                 lpuart_setup_watermark(sport);
1708
1709         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1710 }
1711
1712 static struct uart_driver lpuart_reg;
1713 static struct console lpuart_console = {
1714         .name           = DEV_NAME,
1715         .write          = lpuart_console_write,
1716         .device         = uart_console_device,
1717         .setup          = lpuart_console_setup,
1718         .flags          = CON_PRINTBUFFER,
1719         .index          = -1,
1720         .data           = &lpuart_reg,
1721 };
1722
1723 static struct console lpuart32_console = {
1724         .name           = DEV_NAME,
1725         .write          = lpuart32_console_write,
1726         .device         = uart_console_device,
1727         .setup          = lpuart_console_setup,
1728         .flags          = CON_PRINTBUFFER,
1729         .index          = -1,
1730         .data           = &lpuart_reg,
1731 };
1732
1733 #define LPUART_CONSOLE  (&lpuart_console)
1734 #define LPUART32_CONSOLE        (&lpuart32_console)
1735 #else
1736 #define LPUART_CONSOLE  NULL
1737 #define LPUART32_CONSOLE        NULL
1738 #endif
1739
1740 static struct uart_driver lpuart_reg = {
1741         .owner          = THIS_MODULE,
1742         .driver_name    = DRIVER_NAME,
1743         .dev_name       = DEV_NAME,
1744         .nr             = ARRAY_SIZE(lpuart_ports),
1745         .cons           = LPUART_CONSOLE,
1746 };
1747
1748 static int lpuart_probe(struct platform_device *pdev)
1749 {
1750         struct device_node *np = pdev->dev.of_node;
1751         struct lpuart_port *sport;
1752         struct resource *res;
1753         int ret;
1754
1755         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1756         if (!sport)
1757                 return -ENOMEM;
1758
1759         pdev->dev.coherent_dma_mask = 0;
1760
1761         ret = of_alias_get_id(np, "serial");
1762         if (ret < 0) {
1763                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1764                 return ret;
1765         }
1766         sport->port.line = ret;
1767         sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
1768
1769         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1770         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1771         if (IS_ERR(sport->port.membase))
1772                 return PTR_ERR(sport->port.membase);
1773
1774         sport->port.mapbase = res->start;
1775         sport->port.dev = &pdev->dev;
1776         sport->port.type = PORT_LPUART;
1777         sport->port.iotype = UPIO_MEM;
1778         sport->port.irq = platform_get_irq(pdev, 0);
1779         if (sport->lpuart32)
1780                 sport->port.ops = &lpuart32_pops;
1781         else
1782                 sport->port.ops = &lpuart_pops;
1783         sport->port.flags = UPF_BOOT_AUTOCONF;
1784
1785         sport->clk = devm_clk_get(&pdev->dev, "ipg");
1786         if (IS_ERR(sport->clk)) {
1787                 ret = PTR_ERR(sport->clk);
1788                 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1789                 return ret;
1790         }
1791
1792         ret = clk_prepare_enable(sport->clk);
1793         if (ret) {
1794                 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1795                 return ret;
1796         }
1797
1798         sport->port.uartclk = clk_get_rate(sport->clk);
1799
1800         lpuart_ports[sport->port.line] = sport;
1801
1802         platform_set_drvdata(pdev, &sport->port);
1803
1804         if (sport->lpuart32)
1805                 lpuart_reg.cons = LPUART32_CONSOLE;
1806         else
1807                 lpuart_reg.cons = LPUART_CONSOLE;
1808
1809         ret = uart_add_one_port(&lpuart_reg, &sport->port);
1810         if (ret) {
1811                 clk_disable_unprepare(sport->clk);
1812                 return ret;
1813         }
1814
1815         sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1816         if (!sport->dma_tx_chan)
1817                 dev_info(sport->port.dev, "DMA tx channel request failed, "
1818                                 "operating without tx DMA\n");
1819
1820         sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1821         if (!sport->dma_rx_chan)
1822                 dev_info(sport->port.dev, "DMA rx channel request failed, "
1823                                 "operating without rx DMA\n");
1824
1825         return 0;
1826 }
1827
1828 static int lpuart_remove(struct platform_device *pdev)
1829 {
1830         struct lpuart_port *sport = platform_get_drvdata(pdev);
1831
1832         uart_remove_one_port(&lpuart_reg, &sport->port);
1833
1834         clk_disable_unprepare(sport->clk);
1835
1836         if (sport->dma_tx_chan)
1837                 dma_release_channel(sport->dma_tx_chan);
1838
1839         if (sport->dma_rx_chan)
1840                 dma_release_channel(sport->dma_rx_chan);
1841
1842         return 0;
1843 }
1844
1845 #ifdef CONFIG_PM_SLEEP
1846 static int lpuart_suspend(struct device *dev)
1847 {
1848         struct lpuart_port *sport = dev_get_drvdata(dev);
1849         unsigned long temp;
1850
1851         if (sport->lpuart32) {
1852                 /* disable Rx/Tx and interrupts */
1853                 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1854                 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
1855                 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1856         } else {
1857                 /* disable Rx/Tx and interrupts */
1858                 temp = readb(sport->port.membase + UARTCR2);
1859                 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
1860                 writeb(temp, sport->port.membase + UARTCR2);
1861         }
1862
1863         uart_suspend_port(&lpuart_reg, &sport->port);
1864
1865         return 0;
1866 }
1867
1868 static int lpuart_resume(struct device *dev)
1869 {
1870         struct lpuart_port *sport = dev_get_drvdata(dev);
1871         unsigned long temp;
1872
1873         if (sport->lpuart32) {
1874                 lpuart32_setup_watermark(sport);
1875                 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1876                 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
1877                          UARTCTRL_TE | UARTCTRL_ILIE);
1878                 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1879         } else {
1880                 lpuart_setup_watermark(sport);
1881                 temp = readb(sport->port.membase + UARTCR2);
1882                 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1883                 writeb(temp, sport->port.membase + UARTCR2);
1884         }
1885
1886         uart_resume_port(&lpuart_reg, &sport->port);
1887
1888         return 0;
1889 }
1890 #endif
1891
1892 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1893
1894 static struct platform_driver lpuart_driver = {
1895         .probe          = lpuart_probe,
1896         .remove         = lpuart_remove,
1897         .driver         = {
1898                 .name   = "fsl-lpuart",
1899                 .of_match_table = lpuart_dt_ids,
1900                 .pm     = &lpuart_pm_ops,
1901         },
1902 };
1903
1904 static int __init lpuart_serial_init(void)
1905 {
1906         int ret = uart_register_driver(&lpuart_reg);
1907
1908         if (ret)
1909                 return ret;
1910
1911         ret = platform_driver_register(&lpuart_driver);
1912         if (ret)
1913                 uart_unregister_driver(&lpuart_reg);
1914
1915         return ret;
1916 }
1917
1918 static void __exit lpuart_serial_exit(void)
1919 {
1920         platform_driver_unregister(&lpuart_driver);
1921         uart_unregister_driver(&lpuart_reg);
1922 }
1923
1924 module_init(lpuart_serial_init);
1925 module_exit(lpuart_serial_exit);
1926
1927 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1928 MODULE_LICENSE("GPL v2");