2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 * based off of the old drivers/char/sh-sci.c by:
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
60 #include "serial_mctrl_gpio.h"
63 /* Offsets into the sci_port->irqs array */
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
74 #define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
81 SCI_FCK, /* Functional Clock */
82 SCI_SCK, /* Optional External Clock */
83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
88 /* Bit x set means sampling rate x + 1 is supported */
89 #define SCI_SR(x) BIT((x) - 1)
90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
96 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
97 #define max_sr(_port) fls((_port)->sampling_rate_mask)
99 /* Iterate over all supported sampling rates, from high to low */
100 #define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
105 struct uart_port port;
107 /* Platform configuration */
108 struct plat_sci_port *cfg;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int error_mask;
112 unsigned int error_clear;
113 unsigned int sampling_rate_mask;
114 resource_size_t reg_size;
115 struct mctrl_gpios *gpios;
118 struct timer_list break_timer;
122 struct clk *clks[SCI_NUM_CLKS];
123 unsigned long clk_rates[SCI_NUM_CLKS];
125 int irqs[SCIx_NR_IRQS];
126 char *irqstr[SCIx_NR_IRQS];
128 struct dma_chan *chan_tx;
129 struct dma_chan *chan_rx;
131 #ifdef CONFIG_SERIAL_SH_SCI_DMA
132 dma_cookie_t cookie_tx;
133 dma_cookie_t cookie_rx[2];
134 dma_cookie_t active_rx;
135 dma_addr_t tx_dma_addr;
136 unsigned int tx_dma_len;
137 struct scatterlist sg_rx[2];
140 struct work_struct work_tx;
141 struct timer_list rx_timer;
142 unsigned int rx_timeout;
146 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
148 static struct sci_port sci_ports[SCI_NPORTS];
149 static struct uart_driver sci_uart_driver;
151 static inline struct sci_port *
152 to_sci_port(struct uart_port *uart)
154 return container_of(uart, struct sci_port, port);
157 struct plat_sci_reg {
161 /* Helper for invalidating specific entries of an inherited map. */
162 #define sci_reg_invalid { .offset = 0, .size = 0 }
164 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
165 [SCIx_PROBE_REGTYPE] = {
166 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
170 * Common SCI definitions, dependent on the port's regshift
173 [SCIx_SCI_REGTYPE] = {
174 [SCSMR] = { 0x00, 8 },
175 [SCBRR] = { 0x01, 8 },
176 [SCSCR] = { 0x02, 8 },
177 [SCxTDR] = { 0x03, 8 },
178 [SCxSR] = { 0x04, 8 },
179 [SCxRDR] = { 0x05, 8 },
180 [SCFCR] = sci_reg_invalid,
181 [SCFDR] = sci_reg_invalid,
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
186 [HSSRR] = sci_reg_invalid,
187 [SCPCR] = sci_reg_invalid,
188 [SCPDR] = sci_reg_invalid,
189 [SCDL] = sci_reg_invalid,
190 [SCCKS] = sci_reg_invalid,
194 * Common definitions for legacy IrDA ports, dependent on
197 [SCIx_IRDA_REGTYPE] = {
198 [SCSMR] = { 0x00, 8 },
199 [SCBRR] = { 0x01, 8 },
200 [SCSCR] = { 0x02, 8 },
201 [SCxTDR] = { 0x03, 8 },
202 [SCxSR] = { 0x04, 8 },
203 [SCxRDR] = { 0x05, 8 },
204 [SCFCR] = { 0x06, 8 },
205 [SCFDR] = { 0x07, 16 },
206 [SCTFDR] = sci_reg_invalid,
207 [SCRFDR] = sci_reg_invalid,
208 [SCSPTR] = sci_reg_invalid,
209 [SCLSR] = sci_reg_invalid,
210 [HSSRR] = sci_reg_invalid,
211 [SCPCR] = sci_reg_invalid,
212 [SCPDR] = sci_reg_invalid,
213 [SCDL] = sci_reg_invalid,
214 [SCCKS] = sci_reg_invalid,
218 * Common SCIFA definitions.
220 [SCIx_SCIFA_REGTYPE] = {
221 [SCSMR] = { 0x00, 16 },
222 [SCBRR] = { 0x04, 8 },
223 [SCSCR] = { 0x08, 16 },
224 [SCxTDR] = { 0x20, 8 },
225 [SCxSR] = { 0x14, 16 },
226 [SCxRDR] = { 0x24, 8 },
227 [SCFCR] = { 0x18, 16 },
228 [SCFDR] = { 0x1c, 16 },
229 [SCTFDR] = sci_reg_invalid,
230 [SCRFDR] = sci_reg_invalid,
231 [SCSPTR] = sci_reg_invalid,
232 [SCLSR] = sci_reg_invalid,
233 [HSSRR] = sci_reg_invalid,
234 [SCPCR] = { 0x30, 16 },
235 [SCPDR] = { 0x34, 16 },
236 [SCDL] = sci_reg_invalid,
237 [SCCKS] = sci_reg_invalid,
241 * Common SCIFB definitions.
243 [SCIx_SCIFB_REGTYPE] = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x40, 8 },
248 [SCxSR] = { 0x14, 16 },
249 [SCxRDR] = { 0x60, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCFDR] = sci_reg_invalid,
252 [SCTFDR] = { 0x38, 16 },
253 [SCRFDR] = { 0x3c, 16 },
254 [SCSPTR] = sci_reg_invalid,
255 [SCLSR] = sci_reg_invalid,
256 [HSSRR] = sci_reg_invalid,
257 [SCPCR] = { 0x30, 16 },
258 [SCPDR] = { 0x34, 16 },
259 [SCDL] = sci_reg_invalid,
260 [SCCKS] = sci_reg_invalid,
264 * Common SH-2(A) SCIF definitions for ports with FIFO data
267 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
268 [SCSMR] = { 0x00, 16 },
269 [SCBRR] = { 0x04, 8 },
270 [SCSCR] = { 0x08, 16 },
271 [SCxTDR] = { 0x0c, 8 },
272 [SCxSR] = { 0x10, 16 },
273 [SCxRDR] = { 0x14, 8 },
274 [SCFCR] = { 0x18, 16 },
275 [SCFDR] = { 0x1c, 16 },
276 [SCTFDR] = sci_reg_invalid,
277 [SCRFDR] = sci_reg_invalid,
278 [SCSPTR] = { 0x20, 16 },
279 [SCLSR] = { 0x24, 16 },
280 [HSSRR] = sci_reg_invalid,
281 [SCPCR] = sci_reg_invalid,
282 [SCPDR] = sci_reg_invalid,
283 [SCDL] = sci_reg_invalid,
284 [SCCKS] = sci_reg_invalid,
288 * Common SH-3 SCIF definitions.
290 [SCIx_SH3_SCIF_REGTYPE] = {
291 [SCSMR] = { 0x00, 8 },
292 [SCBRR] = { 0x02, 8 },
293 [SCSCR] = { 0x04, 8 },
294 [SCxTDR] = { 0x06, 8 },
295 [SCxSR] = { 0x08, 16 },
296 [SCxRDR] = { 0x0a, 8 },
297 [SCFCR] = { 0x0c, 8 },
298 [SCFDR] = { 0x0e, 16 },
299 [SCTFDR] = sci_reg_invalid,
300 [SCRFDR] = sci_reg_invalid,
301 [SCSPTR] = sci_reg_invalid,
302 [SCLSR] = sci_reg_invalid,
303 [HSSRR] = sci_reg_invalid,
304 [SCPCR] = sci_reg_invalid,
305 [SCPDR] = sci_reg_invalid,
306 [SCDL] = sci_reg_invalid,
307 [SCCKS] = sci_reg_invalid,
311 * Common SH-4(A) SCIF(B) definitions.
313 [SCIx_SH4_SCIF_REGTYPE] = {
314 [SCSMR] = { 0x00, 16 },
315 [SCBRR] = { 0x04, 8 },
316 [SCSCR] = { 0x08, 16 },
317 [SCxTDR] = { 0x0c, 8 },
318 [SCxSR] = { 0x10, 16 },
319 [SCxRDR] = { 0x14, 8 },
320 [SCFCR] = { 0x18, 16 },
321 [SCFDR] = { 0x1c, 16 },
322 [SCTFDR] = sci_reg_invalid,
323 [SCRFDR] = sci_reg_invalid,
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
326 [HSSRR] = sci_reg_invalid,
327 [SCPCR] = sci_reg_invalid,
328 [SCPDR] = sci_reg_invalid,
329 [SCDL] = sci_reg_invalid,
330 [SCCKS] = sci_reg_invalid,
334 * Common SCIF definitions for ports with a Baud Rate Generator for
335 * External Clock (BRG).
337 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
338 [SCSMR] = { 0x00, 16 },
339 [SCBRR] = { 0x04, 8 },
340 [SCSCR] = { 0x08, 16 },
341 [SCxTDR] = { 0x0c, 8 },
342 [SCxSR] = { 0x10, 16 },
343 [SCxRDR] = { 0x14, 8 },
344 [SCFCR] = { 0x18, 16 },
345 [SCFDR] = { 0x1c, 16 },
346 [SCTFDR] = sci_reg_invalid,
347 [SCRFDR] = sci_reg_invalid,
348 [SCSPTR] = { 0x20, 16 },
349 [SCLSR] = { 0x24, 16 },
350 [HSSRR] = sci_reg_invalid,
351 [SCPCR] = sci_reg_invalid,
352 [SCPDR] = sci_reg_invalid,
353 [SCDL] = { 0x30, 16 },
354 [SCCKS] = { 0x34, 16 },
358 * Common HSCIF definitions.
360 [SCIx_HSCIF_REGTYPE] = {
361 [SCSMR] = { 0x00, 16 },
362 [SCBRR] = { 0x04, 8 },
363 [SCSCR] = { 0x08, 16 },
364 [SCxTDR] = { 0x0c, 8 },
365 [SCxSR] = { 0x10, 16 },
366 [SCxRDR] = { 0x14, 8 },
367 [SCFCR] = { 0x18, 16 },
368 [SCFDR] = { 0x1c, 16 },
369 [SCTFDR] = sci_reg_invalid,
370 [SCRFDR] = sci_reg_invalid,
371 [SCSPTR] = { 0x20, 16 },
372 [SCLSR] = { 0x24, 16 },
373 [HSSRR] = { 0x40, 16 },
374 [SCPCR] = sci_reg_invalid,
375 [SCPDR] = sci_reg_invalid,
376 [SCDL] = { 0x30, 16 },
377 [SCCKS] = { 0x34, 16 },
381 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
384 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
385 [SCSMR] = { 0x00, 16 },
386 [SCBRR] = { 0x04, 8 },
387 [SCSCR] = { 0x08, 16 },
388 [SCxTDR] = { 0x0c, 8 },
389 [SCxSR] = { 0x10, 16 },
390 [SCxRDR] = { 0x14, 8 },
391 [SCFCR] = { 0x18, 16 },
392 [SCFDR] = { 0x1c, 16 },
393 [SCTFDR] = sci_reg_invalid,
394 [SCRFDR] = sci_reg_invalid,
395 [SCSPTR] = sci_reg_invalid,
396 [SCLSR] = { 0x24, 16 },
397 [HSSRR] = sci_reg_invalid,
398 [SCPCR] = sci_reg_invalid,
399 [SCPDR] = sci_reg_invalid,
400 [SCDL] = sci_reg_invalid,
401 [SCCKS] = sci_reg_invalid,
405 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
408 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
409 [SCSMR] = { 0x00, 16 },
410 [SCBRR] = { 0x04, 8 },
411 [SCSCR] = { 0x08, 16 },
412 [SCxTDR] = { 0x0c, 8 },
413 [SCxSR] = { 0x10, 16 },
414 [SCxRDR] = { 0x14, 8 },
415 [SCFCR] = { 0x18, 16 },
416 [SCFDR] = { 0x1c, 16 },
417 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
418 [SCRFDR] = { 0x20, 16 },
419 [SCSPTR] = { 0x24, 16 },
420 [SCLSR] = { 0x28, 16 },
421 [HSSRR] = sci_reg_invalid,
422 [SCPCR] = sci_reg_invalid,
423 [SCPDR] = sci_reg_invalid,
424 [SCDL] = sci_reg_invalid,
425 [SCCKS] = sci_reg_invalid,
429 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
432 [SCIx_SH7705_SCIF_REGTYPE] = {
433 [SCSMR] = { 0x00, 16 },
434 [SCBRR] = { 0x04, 8 },
435 [SCSCR] = { 0x08, 16 },
436 [SCxTDR] = { 0x20, 8 },
437 [SCxSR] = { 0x14, 16 },
438 [SCxRDR] = { 0x24, 8 },
439 [SCFCR] = { 0x18, 16 },
440 [SCFDR] = { 0x1c, 16 },
441 [SCTFDR] = sci_reg_invalid,
442 [SCRFDR] = sci_reg_invalid,
443 [SCSPTR] = sci_reg_invalid,
444 [SCLSR] = sci_reg_invalid,
445 [HSSRR] = sci_reg_invalid,
446 [SCPCR] = sci_reg_invalid,
447 [SCPDR] = sci_reg_invalid,
448 [SCDL] = sci_reg_invalid,
449 [SCCKS] = sci_reg_invalid,
453 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
456 * The "offset" here is rather misleading, in that it refers to an enum
457 * value relative to the port mapping rather than the fixed offset
458 * itself, which needs to be manually retrieved from the platform's
459 * register map for the given port.
461 static unsigned int sci_serial_in(struct uart_port *p, int offset)
463 const struct plat_sci_reg *reg = sci_getreg(p, offset);
466 return ioread8(p->membase + (reg->offset << p->regshift));
467 else if (reg->size == 16)
468 return ioread16(p->membase + (reg->offset << p->regshift));
470 WARN(1, "Invalid register access\n");
475 static void sci_serial_out(struct uart_port *p, int offset, int value)
477 const struct plat_sci_reg *reg = sci_getreg(p, offset);
480 iowrite8(value, p->membase + (reg->offset << p->regshift));
481 else if (reg->size == 16)
482 iowrite16(value, p->membase + (reg->offset << p->regshift));
484 WARN(1, "Invalid register access\n");
487 static int sci_probe_regmap(struct plat_sci_port *cfg)
491 cfg->regtype = SCIx_SCI_REGTYPE;
494 cfg->regtype = SCIx_IRDA_REGTYPE;
497 cfg->regtype = SCIx_SCIFA_REGTYPE;
500 cfg->regtype = SCIx_SCIFB_REGTYPE;
504 * The SH-4 is a bit of a misnomer here, although that's
505 * where this particular port layout originated. This
506 * configuration (or some slight variation thereof)
507 * remains the dominant model for all SCIFs.
509 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
512 cfg->regtype = SCIx_HSCIF_REGTYPE;
515 pr_err("Can't probe register map for given port\n");
522 static void sci_port_enable(struct sci_port *sci_port)
526 if (!sci_port->port.dev)
529 pm_runtime_get_sync(sci_port->port.dev);
531 for (i = 0; i < SCI_NUM_CLKS; i++) {
532 clk_prepare_enable(sci_port->clks[i]);
533 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
535 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
538 static void sci_port_disable(struct sci_port *sci_port)
542 if (!sci_port->port.dev)
545 /* Cancel the break timer to ensure that the timer handler will not try
546 * to access the hardware with clocks and power disabled. Reset the
547 * break flag to make the break debouncing state machine ready for the
550 del_timer_sync(&sci_port->break_timer);
551 sci_port->break_flag = 0;
553 for (i = SCI_NUM_CLKS; i-- > 0; )
554 clk_disable_unprepare(sci_port->clks[i]);
556 pm_runtime_put_sync(sci_port->port.dev);
559 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562 * Not all ports (such as SCIFA) will support REIE. Rather than
563 * special-casing the port type, we check the port initialization
564 * IRQ enable mask to see whether the IRQ is desired at all. If
565 * it's unset, it's logically inferred that there's no point in
568 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571 static void sci_start_tx(struct uart_port *port)
573 struct sci_port *s = to_sci_port(port);
576 #ifdef CONFIG_SERIAL_SH_SCI_DMA
577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
578 u16 new, scr = serial_port_in(port, SCSCR);
580 new = scr | SCSCR_TDRQE;
582 new = scr & ~SCSCR_TDRQE;
584 serial_port_out(port, SCSCR, new);
587 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
588 dma_submit_error(s->cookie_tx)) {
590 schedule_work(&s->work_tx);
594 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
595 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
596 ctrl = serial_port_in(port, SCSCR);
597 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
601 static void sci_stop_tx(struct uart_port *port)
605 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
606 ctrl = serial_port_in(port, SCSCR);
608 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
609 ctrl &= ~SCSCR_TDRQE;
613 serial_port_out(port, SCSCR, ctrl);
616 static void sci_start_rx(struct uart_port *port)
620 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
622 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
623 ctrl &= ~SCSCR_RDRQE;
625 serial_port_out(port, SCSCR, ctrl);
628 static void sci_stop_rx(struct uart_port *port)
632 ctrl = serial_port_in(port, SCSCR);
634 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
635 ctrl &= ~SCSCR_RDRQE;
637 ctrl &= ~port_rx_irq_mask(port);
639 serial_port_out(port, SCSCR, ctrl);
642 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
644 if (port->type == PORT_SCI) {
645 /* Just store the mask */
646 serial_port_out(port, SCxSR, mask);
647 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
648 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
649 /* Only clear the status bits we want to clear */
650 serial_port_out(port, SCxSR,
651 serial_port_in(port, SCxSR) & mask);
653 /* Store the mask, clear parity/framing errors */
654 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
658 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
659 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
661 #ifdef CONFIG_CONSOLE_POLL
662 static int sci_poll_get_char(struct uart_port *port)
664 unsigned short status;
668 status = serial_port_in(port, SCxSR);
669 if (status & SCxSR_ERRORS(port)) {
670 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
676 if (!(status & SCxSR_RDxF(port)))
679 c = serial_port_in(port, SCxRDR);
682 serial_port_in(port, SCxSR);
683 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
689 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
691 unsigned short status;
694 status = serial_port_in(port, SCxSR);
695 } while (!(status & SCxSR_TDxE(port)));
697 serial_port_out(port, SCxTDR, c);
698 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
700 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
701 CONFIG_SERIAL_SH_SCI_EARLYCON */
703 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
705 struct sci_port *s = to_sci_port(port);
708 * Use port-specific handler if provided.
710 if (s->cfg->ops && s->cfg->ops->init_pins) {
711 s->cfg->ops->init_pins(port, cflag);
716 * For the generic path SCSPTR is necessary. Bail out if that's
719 if (!sci_getreg(port, SCSPTR)->size)
722 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
723 ((!(cflag & CRTSCTS)))) {
724 unsigned short status;
726 status = serial_port_in(port, SCSPTR);
727 status &= ~SCSPTR_CTSIO;
728 status |= SCSPTR_RTSIO;
729 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
733 static int sci_txfill(struct uart_port *port)
735 const struct plat_sci_reg *reg;
737 reg = sci_getreg(port, SCTFDR);
739 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
741 reg = sci_getreg(port, SCFDR);
743 return serial_port_in(port, SCFDR) >> 8;
745 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
748 static int sci_txroom(struct uart_port *port)
750 return port->fifosize - sci_txfill(port);
753 static int sci_rxfill(struct uart_port *port)
755 const struct plat_sci_reg *reg;
757 reg = sci_getreg(port, SCRFDR);
759 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
761 reg = sci_getreg(port, SCFDR);
763 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
765 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
769 * SCI helper for checking the state of the muxed port/RXD pins.
771 static inline int sci_rxd_in(struct uart_port *port)
773 struct sci_port *s = to_sci_port(port);
775 if (s->cfg->port_reg <= 0)
778 /* Cast for ARM damage */
779 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
782 /* ********************************************************************** *
783 * the interrupt related routines *
784 * ********************************************************************** */
786 static void sci_transmit_chars(struct uart_port *port)
788 struct circ_buf *xmit = &port->state->xmit;
789 unsigned int stopped = uart_tx_stopped(port);
790 unsigned short status;
794 status = serial_port_in(port, SCxSR);
795 if (!(status & SCxSR_TDxE(port))) {
796 ctrl = serial_port_in(port, SCSCR);
797 if (uart_circ_empty(xmit))
801 serial_port_out(port, SCSCR, ctrl);
805 count = sci_txroom(port);
813 } else if (!uart_circ_empty(xmit) && !stopped) {
814 c = xmit->buf[xmit->tail];
815 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
820 serial_port_out(port, SCxTDR, c);
823 } while (--count > 0);
825 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
827 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
828 uart_write_wakeup(port);
829 if (uart_circ_empty(xmit)) {
832 ctrl = serial_port_in(port, SCSCR);
834 if (port->type != PORT_SCI) {
835 serial_port_in(port, SCxSR); /* Dummy read */
836 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
840 serial_port_out(port, SCSCR, ctrl);
844 /* On SH3, SCIF may read end-of-break as a space->mark char */
845 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
847 static void sci_receive_chars(struct uart_port *port)
849 struct sci_port *sci_port = to_sci_port(port);
850 struct tty_port *tport = &port->state->port;
851 int i, count, copied = 0;
852 unsigned short status;
855 status = serial_port_in(port, SCxSR);
856 if (!(status & SCxSR_RDxF(port)))
860 /* Don't copy more bytes than there is room for in the buffer */
861 count = tty_buffer_request_room(tport, sci_rxfill(port));
863 /* If for any reason we can't copy more data, we're done! */
867 if (port->type == PORT_SCI) {
868 char c = serial_port_in(port, SCxRDR);
869 if (uart_handle_sysrq_char(port, c) ||
870 sci_port->break_flag)
873 tty_insert_flip_char(tport, c, TTY_NORMAL);
875 for (i = 0; i < count; i++) {
876 char c = serial_port_in(port, SCxRDR);
878 status = serial_port_in(port, SCxSR);
879 #if defined(CONFIG_CPU_SH3)
880 /* Skip "chars" during break */
881 if (sci_port->break_flag) {
883 (status & SCxSR_FER(port))) {
888 /* Nonzero => end-of-break */
889 dev_dbg(port->dev, "debounce<%02x>\n", c);
890 sci_port->break_flag = 0;
897 #endif /* CONFIG_CPU_SH3 */
898 if (uart_handle_sysrq_char(port, c)) {
903 /* Store data and status */
904 if (status & SCxSR_FER(port)) {
906 port->icount.frame++;
907 dev_notice(port->dev, "frame error\n");
908 } else if (status & SCxSR_PER(port)) {
910 port->icount.parity++;
911 dev_notice(port->dev, "parity error\n");
915 tty_insert_flip_char(tport, c, flag);
919 serial_port_in(port, SCxSR); /* dummy read */
920 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
923 port->icount.rx += count;
927 /* Tell the rest of the system the news. New characters! */
928 tty_flip_buffer_push(tport);
930 serial_port_in(port, SCxSR); /* dummy read */
931 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
935 #define SCI_BREAK_JIFFIES (HZ/20)
938 * The sci generates interrupts during the break,
939 * 1 per millisecond or so during the break period, for 9600 baud.
940 * So dont bother disabling interrupts.
941 * But dont want more than 1 break event.
942 * Use a kernel timer to periodically poll the rx line until
943 * the break is finished.
945 static inline void sci_schedule_break_timer(struct sci_port *port)
947 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
950 /* Ensure that two consecutive samples find the break over. */
951 static void sci_break_timer(unsigned long data)
953 struct sci_port *port = (struct sci_port *)data;
955 if (sci_rxd_in(&port->port) == 0) {
956 port->break_flag = 1;
957 sci_schedule_break_timer(port);
958 } else if (port->break_flag == 1) {
960 port->break_flag = 2;
961 sci_schedule_break_timer(port);
963 port->break_flag = 0;
966 static int sci_handle_errors(struct uart_port *port)
969 unsigned short status = serial_port_in(port, SCxSR);
970 struct tty_port *tport = &port->state->port;
971 struct sci_port *s = to_sci_port(port);
973 /* Handle overruns */
974 if (status & s->overrun_mask) {
975 port->icount.overrun++;
978 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
981 dev_notice(port->dev, "overrun error\n");
984 if (status & SCxSR_FER(port)) {
985 if (sci_rxd_in(port) == 0) {
986 /* Notify of BREAK */
987 struct sci_port *sci_port = to_sci_port(port);
989 if (!sci_port->break_flag) {
992 sci_port->break_flag = 1;
993 sci_schedule_break_timer(sci_port);
995 /* Do sysrq handling. */
996 if (uart_handle_break(port))
999 dev_dbg(port->dev, "BREAK detected\n");
1001 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1007 port->icount.frame++;
1009 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1012 dev_notice(port->dev, "frame error\n");
1016 if (status & SCxSR_PER(port)) {
1018 port->icount.parity++;
1020 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1023 dev_notice(port->dev, "parity error\n");
1027 tty_flip_buffer_push(tport);
1032 static int sci_handle_fifo_overrun(struct uart_port *port)
1034 struct tty_port *tport = &port->state->port;
1035 struct sci_port *s = to_sci_port(port);
1036 const struct plat_sci_reg *reg;
1040 reg = sci_getreg(port, s->overrun_reg);
1044 status = serial_port_in(port, s->overrun_reg);
1045 if (status & s->overrun_mask) {
1046 status &= ~s->overrun_mask;
1047 serial_port_out(port, s->overrun_reg, status);
1049 port->icount.overrun++;
1051 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1052 tty_flip_buffer_push(tport);
1054 dev_dbg(port->dev, "overrun error\n");
1061 static int sci_handle_breaks(struct uart_port *port)
1064 unsigned short status = serial_port_in(port, SCxSR);
1065 struct tty_port *tport = &port->state->port;
1066 struct sci_port *s = to_sci_port(port);
1068 if (uart_handle_break(port))
1071 if (!s->break_flag && status & SCxSR_BRK(port)) {
1072 #if defined(CONFIG_CPU_SH3)
1073 /* Debounce break */
1079 /* Notify of BREAK */
1080 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1083 dev_dbg(port->dev, "BREAK detected\n");
1087 tty_flip_buffer_push(tport);
1089 copied += sci_handle_fifo_overrun(port);
1094 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1095 static void sci_dma_tx_complete(void *arg)
1097 struct sci_port *s = arg;
1098 struct uart_port *port = &s->port;
1099 struct circ_buf *xmit = &port->state->xmit;
1100 unsigned long flags;
1102 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1104 spin_lock_irqsave(&port->lock, flags);
1106 xmit->tail += s->tx_dma_len;
1107 xmit->tail &= UART_XMIT_SIZE - 1;
1109 port->icount.tx += s->tx_dma_len;
1111 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1112 uart_write_wakeup(port);
1114 if (!uart_circ_empty(xmit)) {
1116 schedule_work(&s->work_tx);
1118 s->cookie_tx = -EINVAL;
1119 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1120 u16 ctrl = serial_port_in(port, SCSCR);
1121 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1125 spin_unlock_irqrestore(&port->lock, flags);
1128 /* Locking: called with port lock held */
1129 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1131 struct uart_port *port = &s->port;
1132 struct tty_port *tport = &port->state->port;
1135 copied = tty_insert_flip_string(tport, buf, count);
1136 if (copied < count) {
1137 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1139 port->icount.buf_overrun++;
1142 port->icount.rx += copied;
1147 static int sci_dma_rx_find_active(struct sci_port *s)
1151 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1152 if (s->active_rx == s->cookie_rx[i])
1155 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1160 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1162 struct dma_chan *chan = s->chan_rx;
1163 struct uart_port *port = &s->port;
1164 unsigned long flags;
1166 spin_lock_irqsave(&port->lock, flags);
1168 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1169 spin_unlock_irqrestore(&port->lock, flags);
1170 dmaengine_terminate_all(chan);
1171 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1172 sg_dma_address(&s->sg_rx[0]));
1173 dma_release_channel(chan);
1178 static void sci_dma_rx_complete(void *arg)
1180 struct sci_port *s = arg;
1181 struct dma_chan *chan = s->chan_rx;
1182 struct uart_port *port = &s->port;
1183 struct dma_async_tx_descriptor *desc;
1184 unsigned long flags;
1185 int active, count = 0;
1187 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1190 spin_lock_irqsave(&port->lock, flags);
1192 active = sci_dma_rx_find_active(s);
1194 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1196 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1199 tty_flip_buffer_push(&port->state->port);
1201 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1203 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1207 desc->callback = sci_dma_rx_complete;
1208 desc->callback_param = s;
1209 s->cookie_rx[active] = dmaengine_submit(desc);
1210 if (dma_submit_error(s->cookie_rx[active]))
1213 s->active_rx = s->cookie_rx[!active];
1215 dma_async_issue_pending(chan);
1217 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1218 __func__, s->cookie_rx[active], active, s->active_rx);
1219 spin_unlock_irqrestore(&port->lock, flags);
1223 spin_unlock_irqrestore(&port->lock, flags);
1224 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1225 sci_rx_dma_release(s, true);
1228 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1230 struct dma_chan *chan = s->chan_tx;
1231 struct uart_port *port = &s->port;
1232 unsigned long flags;
1234 spin_lock_irqsave(&port->lock, flags);
1236 s->cookie_tx = -EINVAL;
1237 spin_unlock_irqrestore(&port->lock, flags);
1238 dmaengine_terminate_all(chan);
1239 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1241 dma_release_channel(chan);
1246 static void sci_submit_rx(struct sci_port *s)
1248 struct dma_chan *chan = s->chan_rx;
1251 for (i = 0; i < 2; i++) {
1252 struct scatterlist *sg = &s->sg_rx[i];
1253 struct dma_async_tx_descriptor *desc;
1255 desc = dmaengine_prep_slave_sg(chan,
1256 sg, 1, DMA_DEV_TO_MEM,
1257 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1261 desc->callback = sci_dma_rx_complete;
1262 desc->callback_param = s;
1263 s->cookie_rx[i] = dmaengine_submit(desc);
1264 if (dma_submit_error(s->cookie_rx[i]))
1267 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1268 s->cookie_rx[i], i);
1271 s->active_rx = s->cookie_rx[0];
1273 dma_async_issue_pending(chan);
1278 dmaengine_terminate_all(chan);
1279 for (i = 0; i < 2; i++)
1280 s->cookie_rx[i] = -EINVAL;
1281 s->active_rx = -EINVAL;
1282 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1283 sci_rx_dma_release(s, true);
1286 static void work_fn_tx(struct work_struct *work)
1288 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1289 struct dma_async_tx_descriptor *desc;
1290 struct dma_chan *chan = s->chan_tx;
1291 struct uart_port *port = &s->port;
1292 struct circ_buf *xmit = &port->state->xmit;
1297 * Port xmit buffer is already mapped, and it is one page... Just adjust
1298 * offsets and lengths. Since it is a circular buffer, we have to
1299 * transmit till the end, and then the rest. Take the port lock to get a
1300 * consistent xmit buffer state.
1302 spin_lock_irq(&port->lock);
1303 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1304 s->tx_dma_len = min_t(unsigned int,
1305 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1306 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1307 spin_unlock_irq(&port->lock);
1309 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1311 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1313 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1315 sci_tx_dma_release(s, true);
1319 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1322 spin_lock_irq(&port->lock);
1323 desc->callback = sci_dma_tx_complete;
1324 desc->callback_param = s;
1325 spin_unlock_irq(&port->lock);
1326 s->cookie_tx = dmaengine_submit(desc);
1327 if (dma_submit_error(s->cookie_tx)) {
1328 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1330 sci_tx_dma_release(s, true);
1334 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1335 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1337 dma_async_issue_pending(chan);
1340 static void rx_timer_fn(unsigned long arg)
1342 struct sci_port *s = (struct sci_port *)arg;
1343 struct dma_chan *chan = s->chan_rx;
1344 struct uart_port *port = &s->port;
1345 struct dma_tx_state state;
1346 enum dma_status status;
1347 unsigned long flags;
1352 spin_lock_irqsave(&port->lock, flags);
1354 dev_dbg(port->dev, "DMA Rx timed out\n");
1356 active = sci_dma_rx_find_active(s);
1358 spin_unlock_irqrestore(&port->lock, flags);
1362 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1363 if (status == DMA_COMPLETE) {
1364 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1365 s->active_rx, active);
1366 spin_unlock_irqrestore(&port->lock, flags);
1368 /* Let packet complete handler take care of the packet */
1372 dmaengine_pause(chan);
1375 * sometimes DMA transfer doesn't stop even if it is stopped and
1376 * data keeps on coming until transaction is complete so check
1377 * for DMA_COMPLETE again
1378 * Let packet complete handler take care of the packet
1380 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1381 if (status == DMA_COMPLETE) {
1382 spin_unlock_irqrestore(&port->lock, flags);
1383 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1387 /* Handle incomplete DMA receive */
1388 dmaengine_terminate_all(s->chan_rx);
1389 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1390 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1394 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1396 tty_flip_buffer_push(&port->state->port);
1399 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1402 /* Direct new serial port interrupts back to CPU */
1403 scr = serial_port_in(port, SCSCR);
1404 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1405 scr &= ~SCSCR_RDRQE;
1406 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1408 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1410 spin_unlock_irqrestore(&port->lock, flags);
1413 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1414 enum dma_transfer_direction dir,
1417 dma_cap_mask_t mask;
1418 struct dma_chan *chan;
1419 struct dma_slave_config cfg;
1423 dma_cap_set(DMA_SLAVE, mask);
1425 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1426 (void *)(unsigned long)id, port->dev,
1427 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1430 "dma_request_slave_channel_compat failed\n");
1434 memset(&cfg, 0, sizeof(cfg));
1435 cfg.direction = dir;
1436 if (dir == DMA_MEM_TO_DEV) {
1437 cfg.dst_addr = port->mapbase +
1438 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1439 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1441 cfg.src_addr = port->mapbase +
1442 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1443 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1446 ret = dmaengine_slave_config(chan, &cfg);
1448 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1449 dma_release_channel(chan);
1456 static void sci_request_dma(struct uart_port *port)
1458 struct sci_port *s = to_sci_port(port);
1459 struct dma_chan *chan;
1461 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1463 if (!port->dev->of_node &&
1464 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1467 s->cookie_tx = -EINVAL;
1468 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1469 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1472 /* UART circular tx buffer is an aligned page. */
1473 s->tx_dma_addr = dma_map_single(chan->device->dev,
1474 port->state->xmit.buf,
1477 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1478 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1479 dma_release_channel(chan);
1482 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1483 __func__, UART_XMIT_SIZE,
1484 port->state->xmit.buf, &s->tx_dma_addr);
1487 INIT_WORK(&s->work_tx, work_fn_tx);
1490 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1491 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1499 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1500 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1504 "Failed to allocate Rx dma buffer, using PIO\n");
1505 dma_release_channel(chan);
1510 for (i = 0; i < 2; i++) {
1511 struct scatterlist *sg = &s->sg_rx[i];
1513 sg_init_table(sg, 1);
1515 sg_dma_address(sg) = dma;
1516 sg_dma_len(sg) = s->buf_len_rx;
1518 buf += s->buf_len_rx;
1519 dma += s->buf_len_rx;
1522 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1524 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1529 static void sci_free_dma(struct uart_port *port)
1531 struct sci_port *s = to_sci_port(port);
1534 sci_tx_dma_release(s, false);
1536 sci_rx_dma_release(s, false);
1539 static inline void sci_request_dma(struct uart_port *port)
1543 static inline void sci_free_dma(struct uart_port *port)
1548 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1550 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1551 struct uart_port *port = ptr;
1552 struct sci_port *s = to_sci_port(port);
1555 u16 scr = serial_port_in(port, SCSCR);
1556 u16 ssr = serial_port_in(port, SCxSR);
1558 /* Disable future Rx interrupts */
1559 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1560 disable_irq_nosync(irq);
1566 serial_port_out(port, SCSCR, scr);
1567 /* Clear current interrupt */
1568 serial_port_out(port, SCxSR,
1569 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1570 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1571 jiffies, s->rx_timeout);
1572 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1578 /* I think sci_receive_chars has to be called irrespective
1579 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1582 sci_receive_chars(ptr);
1587 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1589 struct uart_port *port = ptr;
1590 unsigned long flags;
1592 spin_lock_irqsave(&port->lock, flags);
1593 sci_transmit_chars(port);
1594 spin_unlock_irqrestore(&port->lock, flags);
1599 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1601 struct uart_port *port = ptr;
1602 struct sci_port *s = to_sci_port(port);
1605 if (port->type == PORT_SCI) {
1606 if (sci_handle_errors(port)) {
1607 /* discard character in rx buffer */
1608 serial_port_in(port, SCxSR);
1609 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1612 sci_handle_fifo_overrun(port);
1614 sci_receive_chars(ptr);
1617 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1619 /* Kick the transmission */
1621 sci_tx_interrupt(irq, ptr);
1626 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1628 struct uart_port *port = ptr;
1631 sci_handle_breaks(port);
1632 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1637 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1639 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1640 struct uart_port *port = ptr;
1641 struct sci_port *s = to_sci_port(port);
1642 irqreturn_t ret = IRQ_NONE;
1644 ssr_status = serial_port_in(port, SCxSR);
1645 scr_status = serial_port_in(port, SCSCR);
1646 if (s->overrun_reg == SCxSR)
1647 orer_status = ssr_status;
1649 if (sci_getreg(port, s->overrun_reg)->size)
1650 orer_status = serial_port_in(port, s->overrun_reg);
1653 err_enabled = scr_status & port_rx_irq_mask(port);
1656 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1658 ret = sci_tx_interrupt(irq, ptr);
1661 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1664 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1665 (scr_status & SCSCR_RIE))
1666 ret = sci_rx_interrupt(irq, ptr);
1668 /* Error Interrupt */
1669 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1670 ret = sci_er_interrupt(irq, ptr);
1672 /* Break Interrupt */
1673 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1674 ret = sci_br_interrupt(irq, ptr);
1676 /* Overrun Interrupt */
1677 if (orer_status & s->overrun_mask) {
1678 sci_handle_fifo_overrun(port);
1685 static const struct sci_irq_desc {
1687 irq_handler_t handler;
1688 } sci_irq_desc[] = {
1690 * Split out handlers, the default case.
1694 .handler = sci_er_interrupt,
1699 .handler = sci_rx_interrupt,
1704 .handler = sci_tx_interrupt,
1709 .handler = sci_br_interrupt,
1713 * Special muxed handler.
1717 .handler = sci_mpxed_interrupt,
1721 static int sci_request_irq(struct sci_port *port)
1723 struct uart_port *up = &port->port;
1726 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1727 const struct sci_irq_desc *desc;
1730 if (SCIx_IRQ_IS_MUXED(port)) {
1734 irq = port->irqs[i];
1737 * Certain port types won't support all of the
1738 * available interrupt sources.
1740 if (unlikely(irq < 0))
1744 desc = sci_irq_desc + i;
1745 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1746 dev_name(up->dev), desc->desc);
1747 if (!port->irqstr[j])
1750 ret = request_irq(irq, desc->handler, up->irqflags,
1751 port->irqstr[j], port);
1752 if (unlikely(ret)) {
1753 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1762 free_irq(port->irqs[i], port);
1766 kfree(port->irqstr[j]);
1771 static void sci_free_irq(struct sci_port *port)
1776 * Intentionally in reverse order so we iterate over the muxed
1779 for (i = 0; i < SCIx_NR_IRQS; i++) {
1780 int irq = port->irqs[i];
1783 * Certain port types won't support all of the available
1784 * interrupt sources.
1786 if (unlikely(irq < 0))
1789 free_irq(port->irqs[i], port);
1790 kfree(port->irqstr[i]);
1792 if (SCIx_IRQ_IS_MUXED(port)) {
1793 /* If there's only one IRQ, we're done. */
1799 static unsigned int sci_tx_empty(struct uart_port *port)
1801 unsigned short status = serial_port_in(port, SCxSR);
1802 unsigned short in_tx_fifo = sci_txfill(port);
1804 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1808 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1809 * CTS/RTS is supported in hardware by at least one port and controlled
1810 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1811 * handled via the ->init_pins() op, which is a bit of a one-way street,
1812 * lacking any ability to defer pin control -- this will later be
1813 * converted over to the GPIO framework).
1815 * Other modes (such as loopback) are supported generically on certain
1816 * port types, but not others. For these it's sufficient to test for the
1817 * existence of the support register and simply ignore the port type.
1819 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1821 struct sci_port *s = to_sci_port(port);
1823 if (mctrl & TIOCM_LOOP) {
1824 const struct plat_sci_reg *reg;
1827 * Standard loopback mode for SCFCR ports.
1829 reg = sci_getreg(port, SCFCR);
1831 serial_port_out(port, SCFCR,
1832 serial_port_in(port, SCFCR) |
1836 mctrl_gpio_set(s->gpios, mctrl);
1839 static unsigned int sci_get_mctrl(struct uart_port *port)
1841 struct sci_port *s = to_sci_port(port);
1842 struct mctrl_gpios *gpios = s->gpios;
1843 unsigned int mctrl = 0;
1845 mctrl_gpio_get(gpios, &mctrl);
1848 * CTS/RTS is handled in hardware when supported, while nothing
1849 * else is wired up. Keep it simple and simply assert CTS/DSR/CAR.
1851 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)))
1853 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1855 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1861 static void sci_enable_ms(struct uart_port *port)
1863 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1866 static void sci_break_ctl(struct uart_port *port, int break_state)
1868 unsigned short scscr, scsptr;
1870 /* check wheter the port has SCSPTR */
1871 if (!sci_getreg(port, SCSPTR)->size) {
1873 * Not supported by hardware. Most parts couple break and rx
1874 * interrupts together, with break detection always enabled.
1879 scsptr = serial_port_in(port, SCSPTR);
1880 scscr = serial_port_in(port, SCSCR);
1882 if (break_state == -1) {
1883 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1886 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1890 serial_port_out(port, SCSPTR, scsptr);
1891 serial_port_out(port, SCSCR, scscr);
1894 static int sci_startup(struct uart_port *port)
1896 struct sci_port *s = to_sci_port(port);
1897 unsigned long flags;
1900 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1902 ret = sci_request_irq(s);
1903 if (unlikely(ret < 0))
1906 sci_request_dma(port);
1908 spin_lock_irqsave(&port->lock, flags);
1911 spin_unlock_irqrestore(&port->lock, flags);
1916 static void sci_shutdown(struct uart_port *port)
1918 struct sci_port *s = to_sci_port(port);
1919 unsigned long flags;
1921 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1923 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
1925 spin_lock_irqsave(&port->lock, flags);
1928 spin_unlock_irqrestore(&port->lock, flags);
1930 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1932 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1934 del_timer_sync(&s->rx_timer);
1942 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1945 unsigned long freq = s->clk_rates[SCI_SCK];
1946 int err, min_err = INT_MAX;
1949 if (s->port.type != PORT_HSCIF)
1952 for_each_sr(sr, s) {
1953 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1954 if (abs(err) >= abs(min_err))
1964 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1969 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1970 unsigned long freq, unsigned int *dlr,
1973 int err, min_err = INT_MAX;
1974 unsigned int sr, dl;
1976 if (s->port.type != PORT_HSCIF)
1979 for_each_sr(sr, s) {
1980 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1981 dl = clamp(dl, 1U, 65535U);
1983 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1984 if (abs(err) >= abs(min_err))
1995 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
1996 min_err, *dlr, *srr + 1);
2000 /* calculate sample rate, BRR, and clock select */
2001 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2002 unsigned int *brr, unsigned int *srr,
2005 unsigned long freq = s->clk_rates[SCI_FCK];
2006 unsigned int sr, br, prediv, scrate, c;
2007 int err, min_err = INT_MAX;
2009 if (s->port.type != PORT_HSCIF)
2013 * Find the combination of sample rate and clock select with the
2014 * smallest deviation from the desired baud rate.
2015 * Prefer high sample rates to maximise the receive margin.
2017 * M: Receive margin (%)
2018 * N: Ratio of bit rate to clock (N = sampling rate)
2019 * D: Clock duty (D = 0 to 1.0)
2020 * L: Frame length (L = 9 to 12)
2021 * F: Absolute value of clock frequency deviation
2023 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2024 * (|D - 0.5| / N * (1 + F))|
2025 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2027 for_each_sr(sr, s) {
2028 for (c = 0; c <= 3; c++) {
2029 /* integerized formulas from HSCIF documentation */
2030 prediv = sr * (1 << (2 * c + 1));
2033 * We need to calculate:
2035 * br = freq / (prediv * bps) clamped to [1..256]
2036 * err = freq / (br * prediv) - bps
2038 * Watch out for overflow when calculating the desired
2039 * sampling clock rate!
2041 if (bps > UINT_MAX / prediv)
2044 scrate = prediv * bps;
2045 br = DIV_ROUND_CLOSEST(freq, scrate);
2046 br = clamp(br, 1U, 256U);
2048 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2049 if (abs(err) >= abs(min_err))
2063 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2064 min_err, *brr, *srr + 1, *cks);
2068 static void sci_reset(struct uart_port *port)
2070 const struct plat_sci_reg *reg;
2071 unsigned int status;
2074 status = serial_port_in(port, SCxSR);
2075 } while (!(status & SCxSR_TEND(port)));
2077 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2079 reg = sci_getreg(port, SCFCR);
2081 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2084 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2085 struct ktermios *old)
2087 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2088 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2089 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2090 struct sci_port *s = to_sci_port(port);
2091 const struct plat_sci_reg *reg;
2092 int min_err = INT_MAX, err;
2093 unsigned long max_freq = 0;
2096 if ((termios->c_cflag & CSIZE) == CS7)
2097 smr_val |= SCSMR_CHR;
2098 if (termios->c_cflag & PARENB)
2099 smr_val |= SCSMR_PE;
2100 if (termios->c_cflag & PARODD)
2101 smr_val |= SCSMR_PE | SCSMR_ODD;
2102 if (termios->c_cflag & CSTOPB)
2103 smr_val |= SCSMR_STOP;
2106 * earlyprintk comes here early on with port->uartclk set to zero.
2107 * the clock framework is not up and running at this point so here
2108 * we assume that 115200 is the maximum baud rate. please note that
2109 * the baud rate is not programmed during earlyprintk - it is assumed
2110 * that the previous boot loader has enabled required clocks and
2111 * setup the baud rate generator hardware for us already.
2113 if (!port->uartclk) {
2114 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2118 for (i = 0; i < SCI_NUM_CLKS; i++)
2119 max_freq = max(max_freq, s->clk_rates[i]);
2121 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2126 * There can be multiple sources for the sampling clock. Find the one
2127 * that gives us the smallest deviation from the desired baud rate.
2130 /* Optional Undivided External Clock */
2131 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2132 port->type != PORT_SCIFB) {
2133 err = sci_sck_calc(s, baud, &srr1);
2134 if (abs(err) < abs(min_err)) {
2136 scr_val = SCSCR_CKE1;
2145 /* Optional BRG Frequency Divided External Clock */
2146 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2147 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2149 if (abs(err) < abs(min_err)) {
2150 best_clk = SCI_SCIF_CLK;
2151 scr_val = SCSCR_CKE1;
2161 /* Optional BRG Frequency Divided Internal Clock */
2162 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2163 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2165 if (abs(err) < abs(min_err)) {
2166 best_clk = SCI_BRG_INT;
2167 scr_val = SCSCR_CKE1;
2177 /* Divided Functional Clock using standard Bit Rate Register */
2178 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2179 if (abs(err) < abs(min_err)) {
2190 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2191 s->clks[best_clk], baud, min_err);
2196 * Program the optional External Baud Rate Generator (BRG) first.
2197 * It controls the mux to select (H)SCK or frequency divided clock.
2199 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2200 serial_port_out(port, SCDL, dl);
2201 serial_port_out(port, SCCKS, sccks);
2206 uart_update_timeout(port, termios->c_cflag, baud);
2208 if (best_clk >= 0) {
2209 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2211 case 5: smr_val |= SCSMR_SRC_5; break;
2212 case 7: smr_val |= SCSMR_SRC_7; break;
2213 case 11: smr_val |= SCSMR_SRC_11; break;
2214 case 13: smr_val |= SCSMR_SRC_13; break;
2215 case 16: smr_val |= SCSMR_SRC_16; break;
2216 case 17: smr_val |= SCSMR_SRC_17; break;
2217 case 19: smr_val |= SCSMR_SRC_19; break;
2218 case 27: smr_val |= SCSMR_SRC_27; break;
2222 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2223 scr_val, smr_val, brr, sccks, dl, srr);
2224 serial_port_out(port, SCSCR, scr_val);
2225 serial_port_out(port, SCSMR, smr_val);
2226 serial_port_out(port, SCBRR, brr);
2227 if (sci_getreg(port, HSSRR)->size)
2228 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2230 /* Wait one bit interval */
2231 udelay((1000000 + (baud - 1)) / baud);
2233 /* Don't touch the bit rate configuration */
2234 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2235 smr_val |= serial_port_in(port, SCSMR) &
2236 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2237 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2238 serial_port_out(port, SCSCR, scr_val);
2239 serial_port_out(port, SCSMR, smr_val);
2242 sci_init_pins(port, termios->c_cflag);
2244 reg = sci_getreg(port, SCFCR);
2246 unsigned short ctrl = serial_port_in(port, SCFCR);
2248 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2249 if (termios->c_cflag & CRTSCTS)
2256 * As we've done a sci_reset() above, ensure we don't
2257 * interfere with the FIFOs while toggling MCE. As the
2258 * reset values could still be set, simply mask them out.
2260 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2262 serial_port_out(port, SCFCR, ctrl);
2265 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2266 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2267 serial_port_out(port, SCSCR, scr_val);
2268 if ((srr + 1 == 5) &&
2269 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2271 * In asynchronous mode, when the sampling rate is 1/5, first
2272 * received data may become invalid on some SCIFA and SCIFB.
2273 * To avoid this problem wait more than 1 serial data time (1
2274 * bit time x serial data number) after setting SCSCR.RE = 1.
2276 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2279 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2281 * Calculate delay for 2 DMA buffers (4 FIFO).
2282 * See serial_core.c::uart_update_timeout().
2283 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2284 * function calculates 1 jiffie for the data plus 5 jiffies for the
2285 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2286 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2287 * value obtained by this formula is too small. Therefore, if the value
2288 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2293 /* byte size and parity */
2294 switch (termios->c_cflag & CSIZE) {
2309 if (termios->c_cflag & CSTOPB)
2311 if (termios->c_cflag & PARENB)
2313 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2315 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2316 s->rx_timeout * 1000 / HZ, port->timeout);
2317 if (s->rx_timeout < msecs_to_jiffies(20))
2318 s->rx_timeout = msecs_to_jiffies(20);
2322 if ((termios->c_cflag & CREAD) != 0)
2325 sci_port_disable(s);
2327 if (UART_ENABLE_MS(port, termios->c_cflag))
2328 sci_enable_ms(port);
2331 static void sci_pm(struct uart_port *port, unsigned int state,
2332 unsigned int oldstate)
2334 struct sci_port *sci_port = to_sci_port(port);
2337 case UART_PM_STATE_OFF:
2338 sci_port_disable(sci_port);
2341 sci_port_enable(sci_port);
2346 static const char *sci_type(struct uart_port *port)
2348 switch (port->type) {
2366 static int sci_remap_port(struct uart_port *port)
2368 struct sci_port *sport = to_sci_port(port);
2371 * Nothing to do if there's already an established membase.
2376 if (port->flags & UPF_IOREMAP) {
2377 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2378 if (unlikely(!port->membase)) {
2379 dev_err(port->dev, "can't remap port#%d\n", port->line);
2384 * For the simple (and majority of) cases where we don't
2385 * need to do any remapping, just cast the cookie
2388 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2394 static void sci_release_port(struct uart_port *port)
2396 struct sci_port *sport = to_sci_port(port);
2398 if (port->flags & UPF_IOREMAP) {
2399 iounmap(port->membase);
2400 port->membase = NULL;
2403 release_mem_region(port->mapbase, sport->reg_size);
2406 static int sci_request_port(struct uart_port *port)
2408 struct resource *res;
2409 struct sci_port *sport = to_sci_port(port);
2412 res = request_mem_region(port->mapbase, sport->reg_size,
2413 dev_name(port->dev));
2414 if (unlikely(res == NULL)) {
2415 dev_err(port->dev, "request_mem_region failed.");
2419 ret = sci_remap_port(port);
2420 if (unlikely(ret != 0)) {
2421 release_resource(res);
2428 static void sci_config_port(struct uart_port *port, int flags)
2430 if (flags & UART_CONFIG_TYPE) {
2431 struct sci_port *sport = to_sci_port(port);
2433 port->type = sport->cfg->type;
2434 sci_request_port(port);
2438 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2440 if (ser->baud_base < 2400)
2441 /* No paper tape reader for Mitch.. */
2447 static struct uart_ops sci_uart_ops = {
2448 .tx_empty = sci_tx_empty,
2449 .set_mctrl = sci_set_mctrl,
2450 .get_mctrl = sci_get_mctrl,
2451 .start_tx = sci_start_tx,
2452 .stop_tx = sci_stop_tx,
2453 .stop_rx = sci_stop_rx,
2454 .enable_ms = sci_enable_ms,
2455 .break_ctl = sci_break_ctl,
2456 .startup = sci_startup,
2457 .shutdown = sci_shutdown,
2458 .set_termios = sci_set_termios,
2461 .release_port = sci_release_port,
2462 .request_port = sci_request_port,
2463 .config_port = sci_config_port,
2464 .verify_port = sci_verify_port,
2465 #ifdef CONFIG_CONSOLE_POLL
2466 .poll_get_char = sci_poll_get_char,
2467 .poll_put_char = sci_poll_put_char,
2471 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2473 const char *clk_names[] = {
2476 [SCI_BRG_INT] = "brg_int",
2477 [SCI_SCIF_CLK] = "scif_clk",
2482 if (sci_port->cfg->type == PORT_HSCIF)
2483 clk_names[SCI_SCK] = "hsck";
2485 for (i = 0; i < SCI_NUM_CLKS; i++) {
2486 clk = devm_clk_get(dev, clk_names[i]);
2487 if (PTR_ERR(clk) == -EPROBE_DEFER)
2488 return -EPROBE_DEFER;
2490 if (IS_ERR(clk) && i == SCI_FCK) {
2492 * "fck" used to be called "sci_ick", and we need to
2493 * maintain DT backward compatibility.
2495 clk = devm_clk_get(dev, "sci_ick");
2496 if (PTR_ERR(clk) == -EPROBE_DEFER)
2497 return -EPROBE_DEFER;
2503 * Not all SH platforms declare a clock lookup entry
2504 * for SCI devices, in which case we need to get the
2505 * global "peripheral_clk" clock.
2507 clk = devm_clk_get(dev, "peripheral_clk");
2511 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2513 return PTR_ERR(clk);
2518 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2521 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2523 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2528 static int sci_init_single(struct platform_device *dev,
2529 struct sci_port *sci_port, unsigned int index,
2530 struct plat_sci_port *p, bool early)
2532 struct uart_port *port = &sci_port->port;
2533 const struct resource *res;
2539 port->ops = &sci_uart_ops;
2540 port->iotype = UPIO_MEM;
2543 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2547 port->mapbase = res->start;
2548 sci_port->reg_size = resource_size(res);
2550 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2551 sci_port->irqs[i] = platform_get_irq(dev, i);
2553 /* The SCI generates several interrupts. They can be muxed together or
2554 * connected to different interrupt lines. In the muxed case only one
2555 * interrupt resource is specified. In the non-muxed case three or four
2556 * interrupt resources are specified, as the BRI interrupt is optional.
2558 if (sci_port->irqs[0] < 0)
2561 if (sci_port->irqs[1] < 0) {
2562 sci_port->irqs[1] = sci_port->irqs[0];
2563 sci_port->irqs[2] = sci_port->irqs[0];
2564 sci_port->irqs[3] = sci_port->irqs[0];
2567 if (p->regtype == SCIx_PROBE_REGTYPE) {
2568 ret = sci_probe_regmap(p);
2575 port->fifosize = 256;
2576 sci_port->overrun_reg = SCxSR;
2577 sci_port->overrun_mask = SCIFA_ORER;
2578 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2581 port->fifosize = 128;
2582 sci_port->overrun_reg = SCLSR;
2583 sci_port->overrun_mask = SCLSR_ORER;
2584 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
2587 port->fifosize = 64;
2588 sci_port->overrun_reg = SCxSR;
2589 sci_port->overrun_mask = SCIFA_ORER;
2590 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2593 port->fifosize = 16;
2594 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2595 sci_port->overrun_reg = SCxSR;
2596 sci_port->overrun_mask = SCIFA_ORER;
2597 sci_port->sampling_rate_mask = SCI_SR(16);
2599 sci_port->overrun_reg = SCLSR;
2600 sci_port->overrun_mask = SCLSR_ORER;
2601 sci_port->sampling_rate_mask = SCI_SR(32);
2606 sci_port->overrun_reg = SCxSR;
2607 sci_port->overrun_mask = SCI_ORER;
2608 sci_port->sampling_rate_mask = SCI_SR(32);
2612 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2613 * match the SoC datasheet, this should be investigated. Let platform
2614 * data override the sampling rate for now.
2616 if (p->sampling_rate)
2617 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
2620 ret = sci_init_clocks(sci_port, &dev->dev);
2624 port->dev = &dev->dev;
2626 pm_runtime_enable(&dev->dev);
2629 sci_port->break_timer.data = (unsigned long)sci_port;
2630 sci_port->break_timer.function = sci_break_timer;
2631 init_timer(&sci_port->break_timer);
2634 * Establish some sensible defaults for the error detection.
2636 if (p->type == PORT_SCI) {
2637 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2638 sci_port->error_clear = SCI_ERROR_CLEAR;
2640 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2641 sci_port->error_clear = SCIF_ERROR_CLEAR;
2645 * Make the error mask inclusive of overrun detection, if
2648 if (sci_port->overrun_reg == SCxSR) {
2649 sci_port->error_mask |= sci_port->overrun_mask;
2650 sci_port->error_clear &= ~sci_port->overrun_mask;
2653 port->type = p->type;
2654 port->flags = UPF_FIXED_PORT | p->flags;
2655 port->regshift = p->regshift;
2658 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2659 * for the multi-IRQ ports, which is where we are primarily
2660 * concerned with the shutdown path synchronization.
2662 * For the muxed case there's nothing more to do.
2664 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2667 port->serial_in = sci_serial_in;
2668 port->serial_out = sci_serial_out;
2670 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2671 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2672 p->dma_slave_tx, p->dma_slave_rx);
2677 static void sci_cleanup_single(struct sci_port *port)
2679 pm_runtime_disable(port->port.dev);
2682 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2683 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2684 static void serial_console_putchar(struct uart_port *port, int ch)
2686 sci_poll_put_char(port, ch);
2690 * Print a string to the serial port trying not to disturb
2691 * any possible real use of the port...
2693 static void serial_console_write(struct console *co, const char *s,
2696 struct sci_port *sci_port = &sci_ports[co->index];
2697 struct uart_port *port = &sci_port->port;
2698 unsigned short bits, ctrl, ctrl_temp;
2699 unsigned long flags;
2702 local_irq_save(flags);
2703 #if defined(SUPPORT_SYSRQ)
2708 if (oops_in_progress)
2709 locked = spin_trylock(&port->lock);
2711 spin_lock(&port->lock);
2713 /* first save SCSCR then disable interrupts, keep clock source */
2714 ctrl = serial_port_in(port, SCSCR);
2715 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2716 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2717 serial_port_out(port, SCSCR, ctrl_temp);
2719 uart_console_write(port, s, count, serial_console_putchar);
2721 /* wait until fifo is empty and last bit has been transmitted */
2722 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2723 while ((serial_port_in(port, SCxSR) & bits) != bits)
2726 /* restore the SCSCR */
2727 serial_port_out(port, SCSCR, ctrl);
2730 spin_unlock(&port->lock);
2731 local_irq_restore(flags);
2734 static int serial_console_setup(struct console *co, char *options)
2736 struct sci_port *sci_port;
2737 struct uart_port *port;
2745 * Refuse to handle any bogus ports.
2747 if (co->index < 0 || co->index >= SCI_NPORTS)
2750 sci_port = &sci_ports[co->index];
2751 port = &sci_port->port;
2754 * Refuse to handle uninitialized ports.
2759 ret = sci_remap_port(port);
2760 if (unlikely(ret != 0))
2764 uart_parse_options(options, &baud, &parity, &bits, &flow);
2766 return uart_set_options(port, co, baud, parity, bits, flow);
2769 static struct console serial_console = {
2771 .device = uart_console_device,
2772 .write = serial_console_write,
2773 .setup = serial_console_setup,
2774 .flags = CON_PRINTBUFFER,
2776 .data = &sci_uart_driver,
2779 static struct console early_serial_console = {
2780 .name = "early_ttySC",
2781 .write = serial_console_write,
2782 .flags = CON_PRINTBUFFER,
2786 static char early_serial_buf[32];
2788 static int sci_probe_earlyprintk(struct platform_device *pdev)
2790 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2792 if (early_serial_console.data)
2795 early_serial_console.index = pdev->id;
2797 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2799 serial_console_setup(&early_serial_console, early_serial_buf);
2801 if (!strstr(early_serial_buf, "keep"))
2802 early_serial_console.flags |= CON_BOOT;
2804 register_console(&early_serial_console);
2808 #define SCI_CONSOLE (&serial_console)
2811 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2816 #define SCI_CONSOLE NULL
2818 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2820 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2822 static struct uart_driver sci_uart_driver = {
2823 .owner = THIS_MODULE,
2824 .driver_name = "sci",
2825 .dev_name = "ttySC",
2827 .minor = SCI_MINOR_START,
2829 .cons = SCI_CONSOLE,
2832 static int sci_remove(struct platform_device *dev)
2834 struct sci_port *port = platform_get_drvdata(dev);
2836 uart_remove_one_port(&sci_uart_driver, &port->port);
2838 sci_cleanup_single(port);
2844 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2845 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2846 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2848 static const struct of_device_id of_sci_match[] = {
2849 /* SoC-specific types */
2851 .compatible = "renesas,scif-r7s72100",
2852 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2854 /* Family-specific types */
2856 .compatible = "renesas,rcar-gen1-scif",
2857 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2859 .compatible = "renesas,rcar-gen2-scif",
2860 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2862 .compatible = "renesas,rcar-gen3-scif",
2863 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2867 .compatible = "renesas,scif",
2868 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2870 .compatible = "renesas,scifa",
2871 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2873 .compatible = "renesas,scifb",
2874 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2876 .compatible = "renesas,hscif",
2877 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2879 .compatible = "renesas,sci",
2880 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2885 MODULE_DEVICE_TABLE(of, of_sci_match);
2887 static struct plat_sci_port *
2888 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2890 struct device_node *np = pdev->dev.of_node;
2891 const struct of_device_id *match;
2892 struct plat_sci_port *p;
2895 if (!IS_ENABLED(CONFIG_OF) || !np)
2898 match = of_match_node(of_sci_match, np);
2902 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2906 /* Get the line number from the aliases node. */
2907 id = of_alias_get_id(np, "serial");
2909 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2915 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2916 p->type = SCI_OF_TYPE(match->data);
2917 p->regtype = SCI_OF_REGTYPE(match->data);
2918 p->scscr = SCSCR_RE | SCSCR_TE;
2923 static int sci_probe_single(struct platform_device *dev,
2925 struct plat_sci_port *p,
2926 struct sci_port *sciport)
2931 if (unlikely(index >= SCI_NPORTS)) {
2932 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2933 index+1, SCI_NPORTS);
2934 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2938 ret = sci_init_single(dev, sciport, index, p, false);
2942 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
2943 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
2944 return PTR_ERR(sciport->gpios);
2946 if (p->capabilities & SCIx_HAVE_RTSCTS) {
2947 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2949 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2951 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
2956 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2958 sci_cleanup_single(sciport);
2965 static int sci_probe(struct platform_device *dev)
2967 struct plat_sci_port *p;
2968 struct sci_port *sp;
2969 unsigned int dev_id;
2973 * If we've come here via earlyprintk initialization, head off to
2974 * the special early probe. We don't have sufficient device state
2975 * to make it beyond this yet.
2977 if (is_early_platform_device(dev))
2978 return sci_probe_earlyprintk(dev);
2980 if (dev->dev.of_node) {
2981 p = sci_parse_dt(dev, &dev_id);
2985 p = dev->dev.platform_data;
2987 dev_err(&dev->dev, "no platform data supplied\n");
2994 sp = &sci_ports[dev_id];
2995 platform_set_drvdata(dev, sp);
2997 ret = sci_probe_single(dev, dev_id, p, sp);
3001 #ifdef CONFIG_SH_STANDARD_BIOS
3002 sh_bios_gdb_detach();
3008 static __maybe_unused int sci_suspend(struct device *dev)
3010 struct sci_port *sport = dev_get_drvdata(dev);
3013 uart_suspend_port(&sci_uart_driver, &sport->port);
3018 static __maybe_unused int sci_resume(struct device *dev)
3020 struct sci_port *sport = dev_get_drvdata(dev);
3023 uart_resume_port(&sci_uart_driver, &sport->port);
3028 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3030 static struct platform_driver sci_driver = {
3032 .remove = sci_remove,
3035 .pm = &sci_dev_pm_ops,
3036 .of_match_table = of_match_ptr(of_sci_match),
3040 static int __init sci_init(void)
3044 pr_info("%s\n", banner);
3046 ret = uart_register_driver(&sci_uart_driver);
3047 if (likely(ret == 0)) {
3048 ret = platform_driver_register(&sci_driver);
3050 uart_unregister_driver(&sci_uart_driver);
3056 static void __exit sci_exit(void)
3058 platform_driver_unregister(&sci_driver);
3059 uart_unregister_driver(&sci_uart_driver);
3062 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3063 early_platform_init_buffer("earlyprintk", &sci_driver,
3064 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3066 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3067 static struct __init plat_sci_port port_cfg;
3069 static int __init early_console_setup(struct earlycon_device *device,
3072 if (!device->port.membase)
3075 device->port.serial_in = sci_serial_in;
3076 device->port.serial_out = sci_serial_out;
3077 device->port.type = type;
3078 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3079 sci_ports[0].cfg = &port_cfg;
3080 sci_ports[0].cfg->type = type;
3081 sci_probe_regmap(sci_ports[0].cfg);
3082 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3083 SCSCR_RE | SCSCR_TE;
3084 sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3086 device->con->write = serial_console_write;
3089 static int __init sci_early_console_setup(struct earlycon_device *device,
3092 return early_console_setup(device, PORT_SCI);
3094 static int __init scif_early_console_setup(struct earlycon_device *device,
3097 return early_console_setup(device, PORT_SCIF);
3099 static int __init scifa_early_console_setup(struct earlycon_device *device,
3102 return early_console_setup(device, PORT_SCIFA);
3104 static int __init scifb_early_console_setup(struct earlycon_device *device,
3107 return early_console_setup(device, PORT_SCIFB);
3109 static int __init hscif_early_console_setup(struct earlycon_device *device,
3112 return early_console_setup(device, PORT_HSCIF);
3115 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3116 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3117 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3118 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3119 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3120 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3122 module_init(sci_init);
3123 module_exit(sci_exit);
3125 MODULE_LICENSE("GPL");
3126 MODULE_ALIAS("platform:sh-sci");
3127 MODULE_AUTHOR("Paul Mundt");
3128 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");