drivers/usb/dwc2/platform.c

   1 /*
   2  * platform.c - DesignWare HS OTG Controller platform driver
   3  *
   4  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/slab.h>
  40 #include <linux/clk.h>
  41 #include <linux/device.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/of_device.h>
  44 #include <linux/mutex.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/phy/phy.h>
  47 #include <linux/platform_data/s3c-hsotg.h>
  48
  49 #include <linux/usb/of.h>
  50
  51 #include "core.h"
  52 #include "hcd.h"
  53 #include "debug.h"
  54
  55 static const char dwc2_driver_name[] = "dwc2";
  56
  57 static const struct dwc2_core_params params_bcm2835 = {
  58         .otg_cap                        = 0,    /* HNP/SRP capable */
  59         .otg_ver                        = 0,    /* 1.3 */
  60         .dma_enable                     = 1,
  61         .dma_desc_enable                = 0,
  62         .speed                          = 0,    /* High Speed */
  63         .enable_dynamic_fifo            = 1,
  64         .en_multiple_tx_fifo            = 1,
  65         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
  66         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
  67         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
  68         .max_transfer_size              = 65535,
  69         .max_packet_count               = 511,
  70         .host_channels                  = 8,
  71         .phy_type                       = 1,    /* UTMI */
  72         .phy_utmi_width                 = 8,    /* 8 bits */
  73         .phy_ulpi_ddr                   = 0,    /* Single */
  74         .phy_ulpi_ext_vbus              = 0,
  75         .i2c_enable                     = 0,
  76         .ulpi_fs_ls                     = 0,
  77         .host_support_fs_ls_low_power   = 0,
  78         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  79         .ts_dline                       = 0,
  80         .reload_ctl                     = 0,
  81         .ahbcfg                         = 0x10,
  82         .uframe_sched                   = 0,
  83         .external_id_pin_ctl            = -1,
  84         .hibernation                    = -1,
  85 };
  86
  87 static const struct dwc2_core_params params_rk3066 = {
  88         .otg_cap                        = 2,    /* non-HNP/non-SRP */
  89         .otg_ver                        = -1,
  90         .dma_enable                     = -1,
  91         .dma_desc_enable                = 0,
  92         .speed                          = -1,
  93         .enable_dynamic_fifo            = 1,
  94         .en_multiple_tx_fifo            = -1,
  95         .host_rx_fifo_size              = 520,  /* 520 DWORDs */
  96         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
  97         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
  98         .max_transfer_size              = 65535,
  99         .max_packet_count               = -1,
 100         .host_channels                  = -1,
 101         .phy_type                       = -1,
 102         .phy_utmi_width                 = -1,
 103         .phy_ulpi_ddr                   = -1,
 104         .phy_ulpi_ext_vbus              = -1,
 105         .i2c_enable                     = -1,
 106         .ulpi_fs_ls                     = -1,
 107         .host_support_fs_ls_low_power   = -1,
 108         .host_ls_low_power_phy_clk      = -1,
 109         .ts_dline                       = -1,
 110         .reload_ctl                     = -1,
 111         .ahbcfg                         = 0x7, /* INCR16 */
 112         .uframe_sched                   = -1,
 113         .external_id_pin_ctl            = -1,
 114         .hibernation                    = -1,
 115 };
 116
 117 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 118 {
 119         struct platform_device *pdev = to_platform_device(hsotg->dev);
 120         int ret;
 121
 122         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
 123                                     hsotg->supplies);
 124         if (ret)
 125                 return ret;
 126
 127         ret = clk_prepare_enable(hsotg->clk);
 128         if (ret)
 129                 return ret;
 130
 131         if (hsotg->uphy)
 132                 ret = usb_phy_init(hsotg->uphy);
 133         else if (hsotg->plat && hsotg->plat->phy_init)
 134                 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 135         else {
 136                 ret = phy_power_on(hsotg->phy);
 137                 if (ret == 0)
 138                         ret = phy_init(hsotg->phy);
 139         }
 140
 141         return ret;
 142 }
 143
 144 /**
 145  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
 146  * @hsotg: The driver state
 147  *
 148  * A wrapper for platform code responsible for controlling
 149  * low-level USB platform resources (phy, clock, regulators)
 150  */
 151 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 152 {
 153         int ret = __dwc2_lowlevel_hw_enable(hsotg);
 154
 155         if (ret == 0)
 156                 hsotg->ll_hw_enabled = true;
 157         return ret;
 158 }
 159
 160 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 161 {
 162         struct platform_device *pdev = to_platform_device(hsotg->dev);
 163         int ret = 0;
 164
 165         if (hsotg->uphy)
 166                 usb_phy_shutdown(hsotg->uphy);
 167         else if (hsotg->plat && hsotg->plat->phy_exit)
 168                 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 169         else {
 170                 ret = phy_exit(hsotg->phy);
 171                 if (ret == 0)
 172                         ret = phy_power_off(hsotg->phy);
 173         }
 174         if (ret)
 175                 return ret;
 176
 177         clk_disable_unprepare(hsotg->clk);
 178
 179         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
 180                                      hsotg->supplies);
 181
 182         return ret;
 183 }
 184
 185 /**
 186  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
 187  * @hsotg: The driver state
 188  *
 189  * A wrapper for platform code responsible for controlling
 190  * low-level USB platform resources (phy, clock, regulators)
 191  */
 192 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 193 {
 194         int ret = __dwc2_lowlevel_hw_disable(hsotg);
 195
 196         if (ret == 0)
 197                 hsotg->ll_hw_enabled = false;
 198         return ret;
 199 }
 200
 201 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 202 {
 203         int i, ret;
 204
 205         /* Set default UTMI width */
 206         hsotg->phyif = GUSBCFG_PHYIF16;
 207
 208         /*
 209          * Attempt to find a generic PHY, then look for an old style
 210          * USB PHY and then fall back to pdata
 211          */
 212         hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
 213         if (IS_ERR(hsotg->phy)) {
 214                 hsotg->phy = NULL;
 215                 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
 216                 if (IS_ERR(hsotg->uphy))
 217                         hsotg->uphy = NULL;
 218                 else
 219                         hsotg->plat = dev_get_platdata(hsotg->dev);
 220         }
 221
 222         if (hsotg->phy) {
 223                 /*
 224                  * If using the generic PHY framework, check if the PHY bus
 225                  * width is 8-bit and set the phyif appropriately.
 226                  */
 227                 if (phy_get_bus_width(hsotg->phy) == 8)
 228                         hsotg->phyif = GUSBCFG_PHYIF8;
 229         }
 230
 231         if (!hsotg->phy && !hsotg->uphy && !hsotg->plat) {
 232                 dev_err(hsotg->dev, "no platform data or transceiver defined\n");
 233                 return -EPROBE_DEFER;
 234         }
 235
 236         /* Clock */
 237         hsotg->clk = devm_clk_get(hsotg->dev, "otg");
 238         if (IS_ERR(hsotg->clk)) {
 239                 hsotg->clk = NULL;
 240                 dev_dbg(hsotg->dev, "cannot get otg clock\n");
 241         }
 242
 243         /* Regulators */
 244         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
 245                 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
 246
 247         ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
 248                                       hsotg->supplies);
 249         if (ret) {
 250                 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
 251                 return ret;
 252         }
 253         return 0;
 254 }
 255
 256 /**
 257  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
 258  * DWC_otg driver
 259  *
 260  * @dev: Platform device
 261  *
 262  * This routine is called, for example, when the rmmod command is executed. The
 263  * device may or may not be electrically present. If it is present, the driver
 264  * stops device processing. Any resources used on behalf of this device are
 265  * freed.
 266  */
 267 static int dwc2_driver_remove(struct platform_device *dev)
 268 {
 269         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 270
 271         dwc2_debugfs_exit(hsotg);
 272         if (hsotg->hcd_enabled)
 273                 dwc2_hcd_remove(hsotg);
 274         if (hsotg->gadget_enabled)
 275                 dwc2_hsotg_remove(hsotg);
 276
 277         if (hsotg->ll_hw_enabled)
 278                 dwc2_lowlevel_hw_disable(hsotg);
 279
 280         return 0;
 281 }
 282
 283 static const struct of_device_id dwc2_of_match_table[] = {
 284         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
 285         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 286         { .compatible = "snps,dwc2", .data = NULL },
 287         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
 288         {},
 289 };
 290 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 291
 292 /**
 293  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
 294  * driver
 295  *
 296  * @dev: Platform device
 297  *
 298  * This routine creates the driver components required to control the device
 299  * (core, HCD, and PCD) and initializes the device. The driver components are
 300  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
 301  * in the device private data. This allows the driver to access the dwc2_hsotg
 302  * structure on subsequent calls to driver methods for this device.
 303  */
 304 static int dwc2_driver_probe(struct platform_device *dev)
 305 {
 306         const struct of_device_id *match;
 307         const struct dwc2_core_params *params;
 308         struct dwc2_core_params defparams;
 309         struct dwc2_hsotg *hsotg;
 310         struct resource *res;
 311         int retval;
 312         int irq;
 313
 314         match = of_match_device(dwc2_of_match_table, &dev->dev);
 315         if (match && match->data) {
 316                 params = match->data;
 317         } else {
 318                 /* Default all params to autodetect */
 319                 dwc2_set_all_params(&defparams, -1);
 320                 params = &defparams;
 321
 322                 /*
 323                  * Disable descriptor dma mode by default as the HW can support
 324                  * it, but does not support it for SPLIT transactions.
 325                  */
 326                 defparams.dma_desc_enable = 0;
 327         }
 328
 329         hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
 330         if (!hsotg)
 331                 return -ENOMEM;
 332
 333         hsotg->dev = &dev->dev;
 334
 335         /*
 336          * Use reasonable defaults so platforms don't have to provide these.
 337          */
 338         if (!dev->dev.dma_mask)
 339                 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
 340         retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 341         if (retval)
 342                 return retval;
 343
 344         irq = platform_get_irq(dev, 0);
 345         if (irq < 0) {
 346                 dev_err(&dev->dev, "missing IRQ resource\n");
 347                 return irq;
 348         }
 349
 350         dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
 351                 irq);
 352         retval = devm_request_irq(hsotg->dev, irq,
 353                                   dwc2_handle_common_intr, IRQF_SHARED,
 354                                   dev_name(hsotg->dev), hsotg);
 355         if (retval)
 356                 return retval;
 357
 358         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 359         hsotg->regs = devm_ioremap_resource(&dev->dev, res);
 360         if (IS_ERR(hsotg->regs))
 361                 return PTR_ERR(hsotg->regs);
 362
 363         dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
 364                 (unsigned long)res->start, hsotg->regs);
 365
 366         hsotg->dr_mode = usb_get_dr_mode(&dev->dev);
 367         if (IS_ENABLED(CONFIG_USB_DWC2_HOST) &&
 368                         hsotg->dr_mode != USB_DR_MODE_HOST) {
 369                 hsotg->dr_mode = USB_DR_MODE_HOST;
 370                 dev_warn(hsotg->dev,
 371                         "Configuration mismatch. Forcing host mode\n");
 372         } else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) &&
 373                         hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 374                 hsotg->dr_mode = USB_DR_MODE_PERIPHERAL;
 375                 dev_warn(hsotg->dev,
 376                         "Configuration mismatch. Forcing peripheral mode\n");
 377         }
 378
 379         retval = dwc2_lowlevel_hw_init(hsotg);
 380         if (retval)
 381                 return retval;
 382
 383         spin_lock_init(&hsotg->lock);
 384
 385         hsotg->core_params = devm_kzalloc(&dev->dev,
 386                                 sizeof(*hsotg->core_params), GFP_KERNEL);
 387         if (!hsotg->core_params)
 388                 return -ENOMEM;
 389
 390         dwc2_set_all_params(hsotg->core_params, -1);
 391
 392         retval = dwc2_lowlevel_hw_enable(hsotg);
 393         if (retval)
 394                 return retval;
 395
 396         /* Detect config values from hardware */
 397         retval = dwc2_get_hwparams(hsotg);
 398         if (retval)
 399                 goto error;
 400
 401         /* Validate parameter values */
 402         dwc2_set_parameters(hsotg, params);
 403
 404         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
 405                 retval = dwc2_gadget_init(hsotg, irq);
 406                 if (retval)
 407                         goto error;
 408                 hsotg->gadget_enabled = 1;
 409         }
 410
 411         if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 412                 retval = dwc2_hcd_init(hsotg, irq);
 413                 if (retval) {
 414                         if (hsotg->gadget_enabled)
 415                                 dwc2_hsotg_remove(hsotg);
 416                         goto error;
 417                 }
 418                 hsotg->hcd_enabled = 1;
 419         }
 420
 421         platform_set_drvdata(dev, hsotg);
 422
 423         dwc2_debugfs_init(hsotg);
 424
 425         /* Gadget code manages lowlevel hw on its own */
 426         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 427                 dwc2_lowlevel_hw_disable(hsotg);
 428
 429         return 0;
 430
 431 error:
 432         dwc2_lowlevel_hw_disable(hsotg);
 433         return retval;
 434 }
 435
 436 static int __maybe_unused dwc2_suspend(struct device *dev)
 437 {
 438         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 439         int ret = 0;
 440
 441         if (dwc2_is_device_mode(dwc2))
 442                 dwc2_hsotg_suspend(dwc2);
 443
 444         if (dwc2->ll_hw_enabled)
 445                 ret = __dwc2_lowlevel_hw_disable(dwc2);
 446
 447         return ret;
 448 }
 449
 450 static int __maybe_unused dwc2_resume(struct device *dev)
 451 {
 452         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 453         int ret = 0;
 454
 455         if (dwc2->ll_hw_enabled) {
 456                 ret = __dwc2_lowlevel_hw_enable(dwc2);
 457                 if (ret)
 458                         return ret;
 459         }
 460
 461         if (dwc2_is_device_mode(dwc2))
 462                 ret = dwc2_hsotg_resume(dwc2);
 463
 464         return ret;
 465 }
 466
 467 static const struct dev_pm_ops dwc2_dev_pm_ops = {
 468         SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
 469 };
 470
 471 static struct platform_driver dwc2_platform_driver = {
 472         .driver = {
 473                 .name = dwc2_driver_name,
 474                 .of_match_table = dwc2_of_match_table,
 475                 .pm = &dwc2_dev_pm_ops,
 476         },
 477         .probe = dwc2_driver_probe,
 478         .remove = dwc2_driver_remove,
 479 };
 480
 481 module_platform_driver(dwc2_platform_driver);
 482
 483 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
 484 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
 485 MODULE_LICENSE("Dual BSD/GPL");