drivers/usb/dwc2/platform.c

   1 /*
   2  * platform.c - DesignWare HS OTG Controller platform driver
   3  *
   4  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/slab.h>
  40 #include <linux/clk.h>
  41 #include <linux/device.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/of_device.h>
  44 #include <linux/mutex.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/phy/phy.h>
  47 #include <linux/platform_data/s3c-hsotg.h>
  48
  49 #include <linux/usb/of.h>
  50
  51 #include "core.h"
  52 #include "hcd.h"
  53 #include "debug.h"
  54
  55 static const char dwc2_driver_name[] = "dwc2";
  56
  57 static const struct dwc2_core_params params_hi6220 = {
  58         .otg_cap                        = 2,    /* No HNP/SRP capable */
  59         .otg_ver                        = 0,    /* 1.3 */
  60         .dma_enable                     = 1,
  61         .dma_desc_enable                = 0,
  62         .dma_desc_fs_enable             = 0,
  63         .speed                          = 0,    /* High Speed */
  64         .enable_dynamic_fifo            = 1,
  65         .en_multiple_tx_fifo            = 1,
  66         .host_rx_fifo_size              = 512,
  67         .host_nperio_tx_fifo_size       = 512,
  68         .host_perio_tx_fifo_size        = 512,
  69         .max_transfer_size              = 65535,
  70         .max_packet_count               = 511,
  71         .host_channels                  = 16,
  72         .phy_type                       = 1,    /* UTMI */
  73         .phy_utmi_width                 = 8,
  74         .phy_ulpi_ddr                   = 0,    /* Single */
  75         .phy_ulpi_ext_vbus              = 0,
  76         .i2c_enable                     = 0,
  77         .ulpi_fs_ls                     = 0,
  78         .host_support_fs_ls_low_power   = 0,
  79         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  80         .ts_dline                       = 0,
  81         .reload_ctl                     = 0,
  82         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
  83                                           GAHBCFG_HBSTLEN_SHIFT,
  84         .uframe_sched                   = 0,
  85         .external_id_pin_ctl            = -1,
  86         .hibernation                    = -1,
  87 };
  88
  89 static const struct dwc2_core_params params_bcm2835 = {
  90         .otg_cap                        = 0,    /* HNP/SRP capable */
  91         .otg_ver                        = 0,    /* 1.3 */
  92         .dma_enable                     = 1,
  93         .dma_desc_enable                = 0,
  94         .dma_desc_fs_enable             = 0,
  95         .speed                          = 0,    /* High Speed */
  96         .enable_dynamic_fifo            = 1,
  97         .en_multiple_tx_fifo            = 1,
  98         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
  99         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
 100         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
 101         .max_transfer_size              = 65535,
 102         .max_packet_count               = 511,
 103         .host_channels                  = 8,
 104         .phy_type                       = 1,    /* UTMI */
 105         .phy_utmi_width                 = 8,    /* 8 bits */
 106         .phy_ulpi_ddr                   = 0,    /* Single */
 107         .phy_ulpi_ext_vbus              = 0,
 108         .i2c_enable                     = 0,
 109         .ulpi_fs_ls                     = 0,
 110         .host_support_fs_ls_low_power   = 0,
 111         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
 112         .ts_dline                       = 0,
 113         .reload_ctl                     = 0,
 114         .ahbcfg                         = 0x10,
 115         .uframe_sched                   = 0,
 116         .external_id_pin_ctl            = -1,
 117         .hibernation                    = -1,
 118 };
 119
 120 static const struct dwc2_core_params params_rk3066 = {
 121         .otg_cap                        = 2,    /* non-HNP/non-SRP */
 122         .otg_ver                        = -1,
 123         .dma_enable                     = -1,
 124         .dma_desc_enable                = 0,
 125         .dma_desc_fs_enable             = 0,
 126         .speed                          = -1,
 127         .enable_dynamic_fifo            = 1,
 128         .en_multiple_tx_fifo            = -1,
 129         .host_rx_fifo_size              = 525,  /* 525 DWORDs */
 130         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
 131         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
 132         .max_transfer_size              = -1,
 133         .max_packet_count               = -1,
 134         .host_channels                  = -1,
 135         .phy_type                       = -1,
 136         .phy_utmi_width                 = -1,
 137         .phy_ulpi_ddr                   = -1,
 138         .phy_ulpi_ext_vbus              = -1,
 139         .i2c_enable                     = -1,
 140         .ulpi_fs_ls                     = -1,
 141         .host_support_fs_ls_low_power   = -1,
 142         .host_ls_low_power_phy_clk      = -1,
 143         .ts_dline                       = -1,
 144         .reload_ctl                     = -1,
 145         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 146                                           GAHBCFG_HBSTLEN_SHIFT,
 147         .uframe_sched                   = -1,
 148         .external_id_pin_ctl            = -1,
 149         .hibernation                    = -1,
 150 };
 151
 152 static const struct dwc2_core_params params_ltq = {
 153         .otg_cap                        = 2,    /* non-HNP/non-SRP */
 154         .otg_ver                        = -1,
 155         .dma_enable                     = -1,
 156         .dma_desc_enable                = -1,
 157         .dma_desc_fs_enable             = -1,
 158         .speed                          = -1,
 159         .enable_dynamic_fifo            = -1,
 160         .en_multiple_tx_fifo            = -1,
 161         .host_rx_fifo_size              = 288,  /* 288 DWORDs */
 162         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
 163         .host_perio_tx_fifo_size        = 96,   /* 96 DWORDs */
 164         .max_transfer_size              = 65535,
 165         .max_packet_count               = 511,
 166         .host_channels                  = -1,
 167         .phy_type                       = -1,
 168         .phy_utmi_width                 = -1,
 169         .phy_ulpi_ddr                   = -1,
 170         .phy_ulpi_ext_vbus              = -1,
 171         .i2c_enable                     = -1,
 172         .ulpi_fs_ls                     = -1,
 173         .host_support_fs_ls_low_power   = -1,
 174         .host_ls_low_power_phy_clk      = -1,
 175         .ts_dline                       = -1,
 176         .reload_ctl                     = -1,
 177         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 178                                           GAHBCFG_HBSTLEN_SHIFT,
 179         .uframe_sched                   = -1,
 180         .external_id_pin_ctl            = -1,
 181         .hibernation                    = -1,
 182 };
 183
 184 static const struct dwc2_core_params params_amlogic = {
 185         .otg_cap                        = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
 186         .otg_ver                        = -1,
 187         .dma_enable                     = 1,
 188         .dma_desc_enable                = 0,
 189         .dma_desc_fs_enable             = 0,
 190         .speed                          = DWC2_SPEED_PARAM_HIGH,
 191         .enable_dynamic_fifo            = 1,
 192         .en_multiple_tx_fifo            = -1,
 193         .host_rx_fifo_size              = 512,
 194         .host_nperio_tx_fifo_size       = 500,
 195         .host_perio_tx_fifo_size        = 500,
 196         .max_transfer_size              = -1,
 197         .max_packet_count               = -1,
 198         .host_channels                  = 16,
 199         .phy_type                       = DWC2_PHY_TYPE_PARAM_UTMI,
 200         .phy_utmi_width                 = -1,
 201         .phy_ulpi_ddr                   = -1,
 202         .phy_ulpi_ext_vbus              = -1,
 203         .i2c_enable                     = -1,
 204         .ulpi_fs_ls                     = -1,
 205         .host_support_fs_ls_low_power   = -1,
 206         .host_ls_low_power_phy_clk      = -1,
 207         .ts_dline                       = -1,
 208         .reload_ctl                     = 1,
 209         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR8 <<
 210                                           GAHBCFG_HBSTLEN_SHIFT,
 211         .uframe_sched                   = 0,
 212         .external_id_pin_ctl            = -1,
 213         .hibernation                    = -1,
 214 };
 215
 216 /*
 217  * Check the dr_mode against the module configuration and hardware
 218  * capabilities.
 219  *
 220  * The hardware, module, and dr_mode, can each be set to host, device,
 221  * or otg. Check that all these values are compatible and adjust the
 222  * value of dr_mode if possible.
 223  *
 224  *                      actual
 225  *    HW  MOD dr_mode   dr_mode
 226  *  ------------------------------
 227  *   HST  HST  any    :  HST
 228  *   HST  DEV  any    :  ---
 229  *   HST  OTG  any    :  HST
 230  *
 231  *   DEV  HST  any    :  ---
 232  *   DEV  DEV  any    :  DEV
 233  *   DEV  OTG  any    :  DEV
 234  *
 235  *   OTG  HST  any    :  HST
 236  *   OTG  DEV  any    :  DEV
 237  *   OTG  OTG  any    :  dr_mode
 238  */
 239 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
 240 {
 241         enum usb_dr_mode mode;
 242
 243         hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
 244         if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
 245                 hsotg->dr_mode = USB_DR_MODE_OTG;
 246
 247         mode = hsotg->dr_mode;
 248
 249         if (dwc2_hw_is_device(hsotg)) {
 250                 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
 251                         dev_err(hsotg->dev,
 252                                 "Controller does not support host mode.\n");
 253                         return -EINVAL;
 254                 }
 255                 mode = USB_DR_MODE_PERIPHERAL;
 256         } else if (dwc2_hw_is_host(hsotg)) {
 257                 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
 258                         dev_err(hsotg->dev,
 259                                 "Controller does not support device mode.\n");
 260                         return -EINVAL;
 261                 }
 262                 mode = USB_DR_MODE_HOST;
 263         } else {
 264                 if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
 265                         mode = USB_DR_MODE_HOST;
 266                 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
 267                         mode = USB_DR_MODE_PERIPHERAL;
 268         }
 269
 270         if (mode != hsotg->dr_mode) {
 271                 dev_warn(hsotg->dev,
 272                         "Configuration mismatch. dr_mode forced to %s\n",
 273                         mode == USB_DR_MODE_HOST ? "host" : "device");
 274
 275                 hsotg->dr_mode = mode;
 276         }
 277
 278         return 0;
 279 }
 280
 281 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 282 {
 283         struct platform_device *pdev = to_platform_device(hsotg->dev);
 284         int ret;
 285
 286         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
 287                                     hsotg->supplies);
 288         if (ret)
 289                 return ret;
 290
 291         if (hsotg->clk) {
 292                 ret = clk_prepare_enable(hsotg->clk);
 293                 if (ret)
 294                         return ret;
 295         }
 296
 297         if (hsotg->uphy)
 298                 ret = usb_phy_init(hsotg->uphy);
 299         else if (hsotg->plat && hsotg->plat->phy_init)
 300                 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 301         else {
 302                 ret = phy_power_on(hsotg->phy);
 303                 if (ret == 0)
 304                         ret = phy_init(hsotg->phy);
 305         }
 306
 307         return ret;
 308 }
 309
 310 /**
 311  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
 312  * @hsotg: The driver state
 313  *
 314  * A wrapper for platform code responsible for controlling
 315  * low-level USB platform resources (phy, clock, regulators)
 316  */
 317 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 318 {
 319         int ret = __dwc2_lowlevel_hw_enable(hsotg);
 320
 321         if (ret == 0)
 322                 hsotg->ll_hw_enabled = true;
 323         return ret;
 324 }
 325
 326 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 327 {
 328         struct platform_device *pdev = to_platform_device(hsotg->dev);
 329         int ret = 0;
 330
 331         if (hsotg->uphy)
 332                 usb_phy_shutdown(hsotg->uphy);
 333         else if (hsotg->plat && hsotg->plat->phy_exit)
 334                 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 335         else {
 336                 ret = phy_exit(hsotg->phy);
 337                 if (ret == 0)
 338                         ret = phy_power_off(hsotg->phy);
 339         }
 340         if (ret)
 341                 return ret;
 342
 343         if (hsotg->clk)
 344                 clk_disable_unprepare(hsotg->clk);
 345
 346         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
 347                                      hsotg->supplies);
 348
 349         return ret;
 350 }
 351
 352 /**
 353  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
 354  * @hsotg: The driver state
 355  *
 356  * A wrapper for platform code responsible for controlling
 357  * low-level USB platform resources (phy, clock, regulators)
 358  */
 359 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 360 {
 361         int ret = __dwc2_lowlevel_hw_disable(hsotg);
 362
 363         if (ret == 0)
 364                 hsotg->ll_hw_enabled = false;
 365         return ret;
 366 }
 367
 368 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 369 {
 370         int i, ret;
 371
 372         /* Set default UTMI width */
 373         hsotg->phyif = GUSBCFG_PHYIF16;
 374
 375         /*
 376          * Attempt to find a generic PHY, then look for an old style
 377          * USB PHY and then fall back to pdata
 378          */
 379         hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
 380         if (IS_ERR(hsotg->phy)) {
 381                 ret = PTR_ERR(hsotg->phy);
 382                 switch (ret) {
 383                 case -ENODEV:
 384                 case -ENOSYS:
 385                         hsotg->phy = NULL;
 386                         break;
 387                 case -EPROBE_DEFER:
 388                         return ret;
 389                 default:
 390                         dev_err(hsotg->dev, "error getting phy %d\n", ret);
 391                         return ret;
 392                 }
 393         }
 394
 395         if (!hsotg->phy) {
 396                 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
 397                 if (IS_ERR(hsotg->uphy)) {
 398                         ret = PTR_ERR(hsotg->uphy);
 399                         switch (ret) {
 400                         case -ENODEV:
 401                         case -ENXIO:
 402                                 hsotg->uphy = NULL;
 403                                 break;
 404                         case -EPROBE_DEFER:
 405                                 return ret;
 406                         default:
 407                                 dev_err(hsotg->dev, "error getting usb phy %d\n",
 408                                         ret);
 409                                 return ret;
 410                         }
 411                 }
 412         }
 413
 414         hsotg->plat = dev_get_platdata(hsotg->dev);
 415
 416         if (hsotg->phy) {
 417                 /*
 418                  * If using the generic PHY framework, check if the PHY bus
 419                  * width is 8-bit and set the phyif appropriately.
 420                  */
 421                 if (phy_get_bus_width(hsotg->phy) == 8)
 422                         hsotg->phyif = GUSBCFG_PHYIF8;
 423         }
 424
 425         /* Clock */
 426         hsotg->clk = devm_clk_get(hsotg->dev, "otg");
 427         if (IS_ERR(hsotg->clk)) {
 428                 hsotg->clk = NULL;
 429                 dev_dbg(hsotg->dev, "cannot get otg clock\n");
 430         }
 431
 432         /* Regulators */
 433         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
 434                 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
 435
 436         ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
 437                                       hsotg->supplies);
 438         if (ret) {
 439                 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
 440                 return ret;
 441         }
 442         return 0;
 443 }
 444
 445 /**
 446  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
 447  * DWC_otg driver
 448  *
 449  * @dev: Platform device
 450  *
 451  * This routine is called, for example, when the rmmod command is executed. The
 452  * device may or may not be electrically present. If it is present, the driver
 453  * stops device processing. Any resources used on behalf of this device are
 454  * freed.
 455  */
 456 static int dwc2_driver_remove(struct platform_device *dev)
 457 {
 458         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 459
 460         dwc2_debugfs_exit(hsotg);
 461         if (hsotg->hcd_enabled)
 462                 dwc2_hcd_remove(hsotg);
 463         if (hsotg->gadget_enabled)
 464                 dwc2_hsotg_remove(hsotg);
 465
 466         if (hsotg->ll_hw_enabled)
 467                 dwc2_lowlevel_hw_disable(hsotg);
 468
 469         return 0;
 470 }
 471
 472 /**
 473  * dwc2_driver_shutdown() - Called on device shutdown
 474  *
 475  * @dev: Platform device
 476  *
 477  * In specific conditions (involving usb hubs) dwc2 devices can create a
 478  * lot of interrupts, even to the point of overwhelming devices running
 479  * at low frequencies. Some devices need to do special clock handling
 480  * at shutdown-time which may bring the system clock below the threshold
 481  * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
 482  * prevents reboots/poweroffs from getting stuck in such cases.
 483  */
 484 static void dwc2_driver_shutdown(struct platform_device *dev)
 485 {
 486         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 487
 488         disable_irq(hsotg->irq);
 489 }
 490
 491 static const struct of_device_id dwc2_of_match_table[] = {
 492         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
 493         { .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
 494         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 495         { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
 496         { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
 497         { .compatible = "snps,dwc2", .data = NULL },
 498         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
 499         { .compatible = "amlogic,meson8b-usb", .data = &params_amlogic },
 500         { .compatible = "amlogic,meson-gxbb-usb", .data = &params_amlogic },
 501         {},
 502 };
 503 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 504
 505 /**
 506  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
 507  * driver
 508  *
 509  * @dev: Platform device
 510  *
 511  * This routine creates the driver components required to control the device
 512  * (core, HCD, and PCD) and initializes the device. The driver components are
 513  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
 514  * in the device private data. This allows the driver to access the dwc2_hsotg
 515  * structure on subsequent calls to driver methods for this device.
 516  */
 517 static int dwc2_driver_probe(struct platform_device *dev)
 518 {
 519         const struct of_device_id *match;
 520         const struct dwc2_core_params *params;
 521         struct dwc2_core_params defparams;
 522         struct dwc2_hsotg *hsotg;
 523         struct resource *res;
 524         int retval;
 525
 526         match = of_match_device(dwc2_of_match_table, &dev->dev);
 527         if (match && match->data) {
 528                 params = match->data;
 529         } else {
 530                 /* Default all params to autodetect */
 531                 dwc2_set_all_params(&defparams, -1);
 532                 params = &defparams;
 533
 534                 /*
 535                  * Disable descriptor dma mode by default as the HW can support
 536                  * it, but does not support it for SPLIT transactions.
 537                  * Disable it for FS devices as well.
 538                  */
 539                 defparams.dma_desc_enable = 0;
 540                 defparams.dma_desc_fs_enable = 0;
 541         }
 542
 543         hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
 544         if (!hsotg)
 545                 return -ENOMEM;
 546
 547         hsotg->dev = &dev->dev;
 548
 549         /*
 550          * Use reasonable defaults so platforms don't have to provide these.
 551          */
 552         if (!dev->dev.dma_mask)
 553                 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
 554         retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 555         if (retval)
 556                 return retval;
 557
 558         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 559         hsotg->regs = devm_ioremap_resource(&dev->dev, res);
 560         if (IS_ERR(hsotg->regs))
 561                 return PTR_ERR(hsotg->regs);
 562
 563         dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
 564                 (unsigned long)res->start, hsotg->regs);
 565
 566         retval = dwc2_lowlevel_hw_init(hsotg);
 567         if (retval)
 568                 return retval;
 569
 570         spin_lock_init(&hsotg->lock);
 571
 572         hsotg->core_params = devm_kzalloc(&dev->dev,
 573                                 sizeof(*hsotg->core_params), GFP_KERNEL);
 574         if (!hsotg->core_params)
 575                 return -ENOMEM;
 576
 577         dwc2_set_all_params(hsotg->core_params, -1);
 578
 579         hsotg->irq = platform_get_irq(dev, 0);
 580         if (hsotg->irq < 0) {
 581                 dev_err(&dev->dev, "missing IRQ resource\n");
 582                 return hsotg->irq;
 583         }
 584
 585         dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
 586                 hsotg->irq);
 587         retval = devm_request_irq(hsotg->dev, hsotg->irq,
 588                                   dwc2_handle_common_intr, IRQF_SHARED,
 589                                   dev_name(hsotg->dev), hsotg);
 590         if (retval)
 591                 return retval;
 592
 593         retval = dwc2_lowlevel_hw_enable(hsotg);
 594         if (retval)
 595                 return retval;
 596
 597         retval = dwc2_get_dr_mode(hsotg);
 598         if (retval)
 599                 goto error;
 600
 601         /*
 602          * Reset before dwc2_get_hwparams() then it could get power-on real
 603          * reset value form registers.
 604          */
 605         dwc2_core_reset_and_force_dr_mode(hsotg);
 606
 607         /* Detect config values from hardware */
 608         retval = dwc2_get_hwparams(hsotg);
 609         if (retval)
 610                 goto error;
 611
 612         /* Validate parameter values */
 613         dwc2_set_parameters(hsotg, params);
 614
 615         dwc2_force_dr_mode(hsotg);
 616
 617         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
 618                 retval = dwc2_gadget_init(hsotg, hsotg->irq);
 619                 if (retval)
 620                         goto error;
 621                 hsotg->gadget_enabled = 1;
 622         }
 623
 624         if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 625                 retval = dwc2_hcd_init(hsotg, hsotg->irq);
 626                 if (retval) {
 627                         if (hsotg->gadget_enabled)
 628                                 dwc2_hsotg_remove(hsotg);
 629                         goto error;
 630                 }
 631                 hsotg->hcd_enabled = 1;
 632         }
 633
 634         platform_set_drvdata(dev, hsotg);
 635
 636         dwc2_debugfs_init(hsotg);
 637
 638         /* Gadget code manages lowlevel hw on its own */
 639         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 640                 dwc2_lowlevel_hw_disable(hsotg);
 641
 642         return 0;
 643
 644 error:
 645         dwc2_lowlevel_hw_disable(hsotg);
 646         return retval;
 647 }
 648
 649 static int __maybe_unused dwc2_suspend(struct device *dev)
 650 {
 651         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 652         int ret = 0;
 653
 654         if (dwc2_is_device_mode(dwc2))
 655                 dwc2_hsotg_suspend(dwc2);
 656
 657         if (dwc2->ll_hw_enabled)
 658                 ret = __dwc2_lowlevel_hw_disable(dwc2);
 659
 660         return ret;
 661 }
 662
 663 static int __maybe_unused dwc2_resume(struct device *dev)
 664 {
 665         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 666         int ret = 0;
 667
 668         if (dwc2->ll_hw_enabled) {
 669                 ret = __dwc2_lowlevel_hw_enable(dwc2);
 670                 if (ret)
 671                         return ret;
 672         }
 673
 674         if (dwc2_is_device_mode(dwc2))
 675                 ret = dwc2_hsotg_resume(dwc2);
 676
 677         return ret;
 678 }
 679
 680 static const struct dev_pm_ops dwc2_dev_pm_ops = {
 681         SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
 682 };
 683
 684 static struct platform_driver dwc2_platform_driver = {
 685         .driver = {
 686                 .name = dwc2_driver_name,
 687                 .of_match_table = dwc2_of_match_table,
 688                 .pm = &dwc2_dev_pm_ops,
 689         },
 690         .probe = dwc2_driver_probe,
 691         .remove = dwc2_driver_remove,
 692         .shutdown = dwc2_driver_shutdown,
 693 };
 694
 695 module_platform_driver(dwc2_platform_driver);
 696
 697 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
 698 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
 699 MODULE_LICENSE("Dual BSD/GPL");