drivers/usb/dwc2/platform.c

   1 /*
   2  * platform.c - DesignWare HS OTG Controller platform driver
   3  *
   4  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/slab.h>
  40 #include <linux/clk.h>
  41 #include <linux/device.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/of_device.h>
  44 #include <linux/mutex.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/phy/phy.h>
  47 #include <linux/platform_data/s3c-hsotg.h>
  48
  49 #include <linux/usb/of.h>
  50
  51 #include "core.h"
  52 #include "hcd.h"
  53 #include "debug.h"
  54
  55 static const char dwc2_driver_name[] = "dwc2";
  56
  57 static const struct dwc2_core_params params_hi6220 = {
  58         .otg_cap                        = 2,    /* No HNP/SRP capable */
  59         .otg_ver                        = 0,    /* 1.3 */
  60         .dma_enable                     = 1,
  61         .dma_desc_enable                = 0,
  62         .dma_desc_fs_enable             = 0,
  63         .speed                          = 0,    /* High Speed */
  64         .enable_dynamic_fifo            = 1,
  65         .en_multiple_tx_fifo            = 1,
  66         .host_rx_fifo_size              = 512,
  67         .host_nperio_tx_fifo_size       = 512,
  68         .host_perio_tx_fifo_size        = 512,
  69         .max_transfer_size              = 65535,
  70         .max_packet_count               = 511,
  71         .host_channels                  = 16,
  72         .phy_type                       = 1,    /* UTMI */
  73         .phy_utmi_width                 = 8,
  74         .phy_ulpi_ddr                   = 0,    /* Single */
  75         .phy_ulpi_ext_vbus              = 0,
  76         .i2c_enable                     = 0,
  77         .ulpi_fs_ls                     = 0,
  78         .host_support_fs_ls_low_power   = 0,
  79         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  80         .ts_dline                       = 0,
  81         .reload_ctl                     = 0,
  82         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
  83                                           GAHBCFG_HBSTLEN_SHIFT,
  84         .uframe_sched                   = 0,
  85         .external_id_pin_ctl            = -1,
  86         .hibernation                    = -1,
  87 };
  88
  89 static const struct dwc2_core_params params_bcm2835 = {
  90         .otg_cap                        = 0,    /* HNP/SRP capable */
  91         .otg_ver                        = 0,    /* 1.3 */
  92         .dma_enable                     = 1,
  93         .dma_desc_enable                = 0,
  94         .dma_desc_fs_enable             = 0,
  95         .speed                          = 0,    /* High Speed */
  96         .enable_dynamic_fifo            = 1,
  97         .en_multiple_tx_fifo            = 1,
  98         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
  99         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
 100         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
 101         .max_transfer_size              = 65535,
 102         .max_packet_count               = 511,
 103         .host_channels                  = 8,
 104         .phy_type                       = 1,    /* UTMI */
 105         .phy_utmi_width                 = 8,    /* 8 bits */
 106         .phy_ulpi_ddr                   = 0,    /* Single */
 107         .phy_ulpi_ext_vbus              = 0,
 108         .i2c_enable                     = 0,
 109         .ulpi_fs_ls                     = 0,
 110         .host_support_fs_ls_low_power   = 0,
 111         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
 112         .ts_dline                       = 0,
 113         .reload_ctl                     = 0,
 114         .ahbcfg                         = 0x10,
 115         .uframe_sched                   = 0,
 116         .external_id_pin_ctl            = -1,
 117         .hibernation                    = -1,
 118 };
 119
 120 static const struct dwc2_core_params params_rk3066 = {
 121         .otg_cap                        = 2,    /* non-HNP/non-SRP */
 122         .otg_ver                        = -1,
 123         .dma_enable                     = -1,
 124         .dma_desc_enable                = 0,
 125         .dma_desc_fs_enable             = 0,
 126         .speed                          = -1,
 127         .enable_dynamic_fifo            = 1,
 128         .en_multiple_tx_fifo            = -1,
 129         .host_rx_fifo_size              = 525,  /* 525 DWORDs */
 130         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
 131         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
 132         .max_transfer_size              = -1,
 133         .max_packet_count               = -1,
 134         .host_channels                  = -1,
 135         .phy_type                       = -1,
 136         .phy_utmi_width                 = -1,
 137         .phy_ulpi_ddr                   = -1,
 138         .phy_ulpi_ext_vbus              = -1,
 139         .i2c_enable                     = -1,
 140         .ulpi_fs_ls                     = -1,
 141         .host_support_fs_ls_low_power   = -1,
 142         .host_ls_low_power_phy_clk      = -1,
 143         .ts_dline                       = -1,
 144         .reload_ctl                     = -1,
 145         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 146                                           GAHBCFG_HBSTLEN_SHIFT,
 147         .uframe_sched                   = -1,
 148         .external_id_pin_ctl            = -1,
 149         .hibernation                    = -1,
 150 };
 151
 152 static const struct dwc2_core_params params_ltq = {
 153         .otg_cap                        = 2,    /* non-HNP/non-SRP */
 154         .otg_ver                        = -1,
 155         .dma_enable                     = -1,
 156         .dma_desc_enable                = -1,
 157         .dma_desc_fs_enable             = -1,
 158         .speed                          = -1,
 159         .enable_dynamic_fifo            = -1,
 160         .en_multiple_tx_fifo            = -1,
 161         .host_rx_fifo_size              = 288,  /* 288 DWORDs */
 162         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
 163         .host_perio_tx_fifo_size        = 96,   /* 96 DWORDs */
 164         .max_transfer_size              = 65535,
 165         .max_packet_count               = 511,
 166         .host_channels                  = -1,
 167         .phy_type                       = -1,
 168         .phy_utmi_width                 = -1,
 169         .phy_ulpi_ddr                   = -1,
 170         .phy_ulpi_ext_vbus              = -1,
 171         .i2c_enable                     = -1,
 172         .ulpi_fs_ls                     = -1,
 173         .host_support_fs_ls_low_power   = -1,
 174         .host_ls_low_power_phy_clk      = -1,
 175         .ts_dline                       = -1,
 176         .reload_ctl                     = -1,
 177         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 178                                           GAHBCFG_HBSTLEN_SHIFT,
 179         .uframe_sched                   = -1,
 180         .external_id_pin_ctl            = -1,
 181         .hibernation                    = -1,
 182 };
 183
 184 /*
 185  * Check the dr_mode against the module configuration and hardware
 186  * capabilities.
 187  *
 188  * The hardware, module, and dr_mode, can each be set to host, device,
 189  * or otg. Check that all these values are compatible and adjust the
 190  * value of dr_mode if possible.
 191  *
 192  *                      actual
 193  *    HW  MOD dr_mode   dr_mode
 194  *  ------------------------------
 195  *   HST  HST  any    :  HST
 196  *   HST  DEV  any    :  ---
 197  *   HST  OTG  any    :  HST
 198  *
 199  *   DEV  HST  any    :  ---
 200  *   DEV  DEV  any    :  DEV
 201  *   DEV  OTG  any    :  DEV
 202  *
 203  *   OTG  HST  any    :  HST
 204  *   OTG  DEV  any    :  DEV
 205  *   OTG  OTG  any    :  dr_mode
 206  */
 207 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
 208 {
 209         enum usb_dr_mode mode;
 210
 211         hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
 212         if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
 213                 hsotg->dr_mode = USB_DR_MODE_OTG;
 214
 215         mode = hsotg->dr_mode;
 216
 217         if (dwc2_hw_is_device(hsotg)) {
 218                 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
 219                         dev_err(hsotg->dev,
 220                                 "Controller does not support host mode.\n");
 221                         return -EINVAL;
 222                 }
 223                 mode = USB_DR_MODE_PERIPHERAL;
 224         } else if (dwc2_hw_is_host(hsotg)) {
 225                 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
 226                         dev_err(hsotg->dev,
 227                                 "Controller does not support device mode.\n");
 228                         return -EINVAL;
 229                 }
 230                 mode = USB_DR_MODE_HOST;
 231         } else {
 232                 if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
 233                         mode = USB_DR_MODE_HOST;
 234                 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
 235                         mode = USB_DR_MODE_PERIPHERAL;
 236         }
 237
 238         if (mode != hsotg->dr_mode) {
 239                 dev_warn(hsotg->dev,
 240                         "Configuration mismatch. dr_mode forced to %s\n",
 241                         mode == USB_DR_MODE_HOST ? "host" : "device");
 242
 243                 hsotg->dr_mode = mode;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 250 {
 251         struct platform_device *pdev = to_platform_device(hsotg->dev);
 252         int ret;
 253
 254         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
 255                                     hsotg->supplies);
 256         if (ret)
 257                 return ret;
 258
 259         if (hsotg->clk) {
 260                 ret = clk_prepare_enable(hsotg->clk);
 261                 if (ret)
 262                         return ret;
 263         }
 264
 265         if (hsotg->uphy)
 266                 ret = usb_phy_init(hsotg->uphy);
 267         else if (hsotg->plat && hsotg->plat->phy_init)
 268                 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 269         else {
 270                 ret = phy_power_on(hsotg->phy);
 271                 if (ret == 0)
 272                         ret = phy_init(hsotg->phy);
 273         }
 274
 275         return ret;
 276 }
 277
 278 /**
 279  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
 280  * @hsotg: The driver state
 281  *
 282  * A wrapper for platform code responsible for controlling
 283  * low-level USB platform resources (phy, clock, regulators)
 284  */
 285 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 286 {
 287         int ret = __dwc2_lowlevel_hw_enable(hsotg);
 288
 289         if (ret == 0)
 290                 hsotg->ll_hw_enabled = true;
 291         return ret;
 292 }
 293
 294 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 295 {
 296         struct platform_device *pdev = to_platform_device(hsotg->dev);
 297         int ret = 0;
 298
 299         if (hsotg->uphy)
 300                 usb_phy_shutdown(hsotg->uphy);
 301         else if (hsotg->plat && hsotg->plat->phy_exit)
 302                 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 303         else {
 304                 ret = phy_exit(hsotg->phy);
 305                 if (ret == 0)
 306                         ret = phy_power_off(hsotg->phy);
 307         }
 308         if (ret)
 309                 return ret;
 310
 311         if (hsotg->clk)
 312                 clk_disable_unprepare(hsotg->clk);
 313
 314         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
 315                                      hsotg->supplies);
 316
 317         return ret;
 318 }
 319
 320 /**
 321  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
 322  * @hsotg: The driver state
 323  *
 324  * A wrapper for platform code responsible for controlling
 325  * low-level USB platform resources (phy, clock, regulators)
 326  */
 327 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 328 {
 329         int ret = __dwc2_lowlevel_hw_disable(hsotg);
 330
 331         if (ret == 0)
 332                 hsotg->ll_hw_enabled = false;
 333         return ret;
 334 }
 335
 336 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 337 {
 338         int i, ret;
 339
 340         /* Set default UTMI width */
 341         hsotg->phyif = GUSBCFG_PHYIF16;
 342
 343         /*
 344          * Attempt to find a generic PHY, then look for an old style
 345          * USB PHY and then fall back to pdata
 346          */
 347         hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
 348         if (IS_ERR(hsotg->phy)) {
 349                 ret = PTR_ERR(hsotg->phy);
 350                 switch (ret) {
 351                 case -ENODEV:
 352                 case -ENOSYS:
 353                         hsotg->phy = NULL;
 354                         break;
 355                 case -EPROBE_DEFER:
 356                         return ret;
 357                 default:
 358                         dev_err(hsotg->dev, "error getting phy %d\n", ret);
 359                         return ret;
 360                 }
 361         }
 362
 363         if (!hsotg->phy) {
 364                 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
 365                 if (IS_ERR(hsotg->uphy)) {
 366                         ret = PTR_ERR(hsotg->uphy);
 367                         switch (ret) {
 368                         case -ENODEV:
 369                         case -ENXIO:
 370                                 hsotg->uphy = NULL;
 371                                 break;
 372                         case -EPROBE_DEFER:
 373                                 return ret;
 374                         default:
 375                                 dev_err(hsotg->dev, "error getting usb phy %d\n",
 376                                         ret);
 377                                 return ret;
 378                         }
 379                 }
 380         }
 381
 382         hsotg->plat = dev_get_platdata(hsotg->dev);
 383
 384         if (hsotg->phy) {
 385                 /*
 386                  * If using the generic PHY framework, check if the PHY bus
 387                  * width is 8-bit and set the phyif appropriately.
 388                  */
 389                 if (phy_get_bus_width(hsotg->phy) == 8)
 390                         hsotg->phyif = GUSBCFG_PHYIF8;
 391         }
 392
 393         /* Clock */
 394         hsotg->clk = devm_clk_get(hsotg->dev, "otg");
 395         if (IS_ERR(hsotg->clk)) {
 396                 hsotg->clk = NULL;
 397                 dev_dbg(hsotg->dev, "cannot get otg clock\n");
 398         }
 399
 400         /* Regulators */
 401         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
 402                 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
 403
 404         ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
 405                                       hsotg->supplies);
 406         if (ret) {
 407                 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
 408                 return ret;
 409         }
 410         return 0;
 411 }
 412
 413 /**
 414  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
 415  * DWC_otg driver
 416  *
 417  * @dev: Platform device
 418  *
 419  * This routine is called, for example, when the rmmod command is executed. The
 420  * device may or may not be electrically present. If it is present, the driver
 421  * stops device processing. Any resources used on behalf of this device are
 422  * freed.
 423  */
 424 static int dwc2_driver_remove(struct platform_device *dev)
 425 {
 426         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 427
 428         dwc2_debugfs_exit(hsotg);
 429         if (hsotg->hcd_enabled)
 430                 dwc2_hcd_remove(hsotg);
 431         if (hsotg->gadget_enabled)
 432                 dwc2_hsotg_remove(hsotg);
 433
 434         if (hsotg->ll_hw_enabled)
 435                 dwc2_lowlevel_hw_disable(hsotg);
 436
 437         return 0;
 438 }
 439
 440 /**
 441  * dwc2_driver_shutdown() - Called on device shutdown
 442  *
 443  * @dev: Platform device
 444  *
 445  * In specific conditions (involving usb hubs) dwc2 devices can create a
 446  * lot of interrupts, even to the point of overwhelming devices running
 447  * at low frequencies. Some devices need to do special clock handling
 448  * at shutdown-time which may bring the system clock below the threshold
 449  * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
 450  * prevents reboots/poweroffs from getting stuck in such cases.
 451  */
 452 static void dwc2_driver_shutdown(struct platform_device *dev)
 453 {
 454         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 455
 456         disable_irq(hsotg->irq);
 457 }
 458
 459 static const struct of_device_id dwc2_of_match_table[] = {
 460         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
 461         { .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
 462         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 463         { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
 464         { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
 465         { .compatible = "snps,dwc2", .data = NULL },
 466         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
 467         {},
 468 };
 469 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 470
 471 /**
 472  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
 473  * driver
 474  *
 475  * @dev: Platform device
 476  *
 477  * This routine creates the driver components required to control the device
 478  * (core, HCD, and PCD) and initializes the device. The driver components are
 479  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
 480  * in the device private data. This allows the driver to access the dwc2_hsotg
 481  * structure on subsequent calls to driver methods for this device.
 482  */
 483 static int dwc2_driver_probe(struct platform_device *dev)
 484 {
 485         const struct of_device_id *match;
 486         const struct dwc2_core_params *params;
 487         struct dwc2_core_params defparams;
 488         struct dwc2_hsotg *hsotg;
 489         struct resource *res;
 490         int retval;
 491
 492         match = of_match_device(dwc2_of_match_table, &dev->dev);
 493         if (match && match->data) {
 494                 params = match->data;
 495         } else {
 496                 /* Default all params to autodetect */
 497                 dwc2_set_all_params(&defparams, -1);
 498                 params = &defparams;
 499
 500                 /*
 501                  * Disable descriptor dma mode by default as the HW can support
 502                  * it, but does not support it for SPLIT transactions.
 503                  * Disable it for FS devices as well.
 504                  */
 505                 defparams.dma_desc_enable = 0;
 506                 defparams.dma_desc_fs_enable = 0;
 507         }
 508
 509         hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
 510         if (!hsotg)
 511                 return -ENOMEM;
 512
 513         hsotg->dev = &dev->dev;
 514
 515         /*
 516          * Use reasonable defaults so platforms don't have to provide these.
 517          */
 518         if (!dev->dev.dma_mask)
 519                 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
 520         retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 521         if (retval)
 522                 return retval;
 523
 524         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 525         hsotg->regs = devm_ioremap_resource(&dev->dev, res);
 526         if (IS_ERR(hsotg->regs))
 527                 return PTR_ERR(hsotg->regs);
 528
 529         dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
 530                 (unsigned long)res->start, hsotg->regs);
 531
 532         retval = dwc2_lowlevel_hw_init(hsotg);
 533         if (retval)
 534                 return retval;
 535
 536         spin_lock_init(&hsotg->lock);
 537
 538         hsotg->core_params = devm_kzalloc(&dev->dev,
 539                                 sizeof(*hsotg->core_params), GFP_KERNEL);
 540         if (!hsotg->core_params)
 541                 return -ENOMEM;
 542
 543         dwc2_set_all_params(hsotg->core_params, -1);
 544
 545         hsotg->irq = platform_get_irq(dev, 0);
 546         if (hsotg->irq < 0) {
 547                 dev_err(&dev->dev, "missing IRQ resource\n");
 548                 return hsotg->irq;
 549         }
 550
 551         dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
 552                 hsotg->irq);
 553         retval = devm_request_irq(hsotg->dev, hsotg->irq,
 554                                   dwc2_handle_common_intr, IRQF_SHARED,
 555                                   dev_name(hsotg->dev), hsotg);
 556         if (retval)
 557                 return retval;
 558
 559         retval = dwc2_lowlevel_hw_enable(hsotg);
 560         if (retval)
 561                 return retval;
 562
 563         retval = dwc2_get_dr_mode(hsotg);
 564         if (retval)
 565                 goto error;
 566
 567         /*
 568          * Reset before dwc2_get_hwparams() then it could get power-on real
 569          * reset value form registers.
 570          */
 571         dwc2_core_reset_and_force_dr_mode(hsotg);
 572
 573         /* Detect config values from hardware */
 574         retval = dwc2_get_hwparams(hsotg);
 575         if (retval)
 576                 goto error;
 577
 578         /* Validate parameter values */
 579         dwc2_set_parameters(hsotg, params);
 580
 581         dwc2_force_dr_mode(hsotg);
 582
 583         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
 584                 retval = dwc2_gadget_init(hsotg, hsotg->irq);
 585                 if (retval)
 586                         goto error;
 587                 hsotg->gadget_enabled = 1;
 588         }
 589
 590         if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 591                 retval = dwc2_hcd_init(hsotg, hsotg->irq);
 592                 if (retval) {
 593                         if (hsotg->gadget_enabled)
 594                                 dwc2_hsotg_remove(hsotg);
 595                         goto error;
 596                 }
 597                 hsotg->hcd_enabled = 1;
 598         }
 599
 600         platform_set_drvdata(dev, hsotg);
 601
 602         dwc2_debugfs_init(hsotg);
 603
 604         /* Gadget code manages lowlevel hw on its own */
 605         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 606                 dwc2_lowlevel_hw_disable(hsotg);
 607
 608         return 0;
 609
 610 error:
 611         dwc2_lowlevel_hw_disable(hsotg);
 612         return retval;
 613 }
 614
 615 static int __maybe_unused dwc2_suspend(struct device *dev)
 616 {
 617         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 618         int ret = 0;
 619
 620         if (dwc2_is_device_mode(dwc2))
 621                 dwc2_hsotg_suspend(dwc2);
 622
 623         if (dwc2->ll_hw_enabled)
 624                 ret = __dwc2_lowlevel_hw_disable(dwc2);
 625
 626         return ret;
 627 }
 628
 629 static int __maybe_unused dwc2_resume(struct device *dev)
 630 {
 631         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 632         int ret = 0;
 633
 634         if (dwc2->ll_hw_enabled) {
 635                 ret = __dwc2_lowlevel_hw_enable(dwc2);
 636                 if (ret)
 637                         return ret;
 638         }
 639
 640         if (dwc2_is_device_mode(dwc2))
 641                 ret = dwc2_hsotg_resume(dwc2);
 642
 643         return ret;
 644 }
 645
 646 static const struct dev_pm_ops dwc2_dev_pm_ops = {
 647         SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
 648 };
 649
 650 static struct platform_driver dwc2_platform_driver = {
 651         .driver = {
 652                 .name = dwc2_driver_name,
 653                 .of_match_table = dwc2_of_match_table,
 654                 .pm = &dwc2_dev_pm_ops,
 655         },
 656         .probe = dwc2_driver_probe,
 657         .remove = dwc2_driver_remove,
 658         .shutdown = dwc2_driver_shutdown,
 659 };
 660
 661 module_platform_driver(dwc2_platform_driver);
 662
 663 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
 664 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
 665 MODULE_LICENSE("Dual BSD/GPL");