drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <asm/unaligned.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  32                          PORT_RC | PORT_PLC | PORT_PE)
  33
  34 /* USB 3 BOS descriptor and a capability descriptors, combined.
  35  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  36  */
  37 static u8 usb_bos_descriptor [] = {
  38         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  39         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  40         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  41         0x1,                            /*  __u8 bNumDeviceCaps */
  42         /* First device capability, SuperSpeed */
  43         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  44         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  45         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  46         0x00,                           /* bmAttributes, LTM off by default */
  47         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  48         0x03,                           /* bFunctionalitySupport,
  49                                            USB 3.0 speed only */
  50         0x00,                           /* bU1DevExitLat, set later. */
  51         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  52         /* Second device capability, SuperSpeedPlus */
  53         0x1c,                           /* bLength 28, will be adjusted later */
  54         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  55         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  56         0x00,                           /* bReserved 0 */
  57         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  58         0x01, 0x00,                     /* wFunctionalitySupport */
  59         0x00, 0x00,                     /* wReserved 0 */
  60         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  61         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  62         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  63         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  64         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  65 };
  66
  67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  68                                      u16 wLength)
  69 {
  70         int i, ssa_count;
  71         u32 temp;
  72         u16 desc_size, ssp_cap_size, ssa_size = 0;
  73         bool usb3_1 = false;
  74
  75         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  76         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  77
  78         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  79         if (xhci->usb3_rhub.min_rev >= 0x01) {
  80                 /* does xhci provide a PSI table for SSA speed attributes? */
  81                 if (xhci->usb3_rhub.psi_count) {
  82                         /* two SSA entries for each unique PSI ID, RX and TX */
  83                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  84                         ssa_size = ssa_count * sizeof(u32);
  85                         ssp_cap_size -= 16; /* skip copying the default SSA */
  86                 }
  87                 desc_size += ssp_cap_size;
  88                 usb3_1 = true;
  89         }
  90         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  91
  92         if (usb3_1) {
  93                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  94                 buf[4] += 1;
  95                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  96         }
  97
  98         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  99                 return wLength;
 100
 101         /* Indicate whether the host has LTM support. */
 102         temp = readl(&xhci->cap_regs->hcc_params);
 103         if (HCC_LTC(temp))
 104                 buf[8] |= USB_LTM_SUPPORT;
 105
 106         /* Set the U1 and U2 exit latencies. */
 107         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 108                 temp = readl(&xhci->cap_regs->hcs_params3);
 109                 buf[12] = HCS_U1_LATENCY(temp);
 110                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 111         }
 112
 113         /* If PSI table exists, add the custom speed attributes from it */
 114         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 115                 u32 ssp_cap_base, bm_attrib, psi;
 116                 int offset;
 117
 118                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 119
 120                 if (wLength < desc_size)
 121                         return wLength;
 122                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 123
 124                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 125                 bm_attrib = (ssa_count - 1) & 0x1f;
 126                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 127                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 128
 129                 if (wLength < desc_size + ssa_size)
 130                         return wLength;
 131                 /*
 132                  * Create the Sublink Speed Attributes (SSA) array.
 133                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 134                  * but link type bits 7:6 differ for values 01b and 10b.
 135                  * xhci has also only one PSI entry for a symmetric link when
 136                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 137                  */
 138                 offset = desc_size;
 139                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 140                         psi = xhci->usb3_rhub.psi[i];
 141                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 142                         if ((psi & PLT_MASK) == PLT_SYM) {
 143                         /* Symmetric, create SSA RX and TX from one PSI entry */
 144                                 put_unaligned_le32(psi, &buf[offset]);
 145                                 psi |= 1 << 7;  /* turn entry to TX */
 146                                 offset += 4;
 147                                 if (offset >= desc_size + ssa_size)
 148                                         return desc_size + ssa_size;
 149                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 150                                 /* Asymetric RX, flip bits 7:6 for SSA */
 151                                 psi ^= PLT_MASK;
 152                         }
 153                         put_unaligned_le32(psi, &buf[offset]);
 154                         offset += 4;
 155                         if (offset >= desc_size + ssa_size)
 156                                 return desc_size + ssa_size;
 157                 }
 158         }
 159         /* ssa_size is 0 for other than usb 3.1 hosts */
 160         return desc_size + ssa_size;
 161 }
 162
 163 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 164                 struct usb_hub_descriptor *desc, int ports)
 165 {
 166         u16 temp;
 167
 168         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 169         desc->bHubContrCurrent = 0;
 170
 171         desc->bNbrPorts = ports;
 172         temp = 0;
 173         /* Bits 1:0 - support per-port power switching, or power always on */
 174         if (HCC_PPC(xhci->hcc_params))
 175                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 176         else
 177                 temp |= HUB_CHAR_NO_LPSM;
 178         /* Bit  2 - root hubs are not part of a compound device */
 179         /* Bits 4:3 - individual port over current protection */
 180         temp |= HUB_CHAR_INDV_PORT_OCPM;
 181         /* Bits 6:5 - no TTs in root ports */
 182         /* Bit  7 - no port indicators */
 183         desc->wHubCharacteristics = cpu_to_le16(temp);
 184 }
 185
 186 /* Fill in the USB 2.0 roothub descriptor */
 187 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 188                 struct usb_hub_descriptor *desc)
 189 {
 190         int ports;
 191         u16 temp;
 192         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 193         u32 portsc;
 194         unsigned int i;
 195
 196         ports = xhci->num_usb2_ports;
 197
 198         xhci_common_hub_descriptor(xhci, desc, ports);
 199         desc->bDescriptorType = USB_DT_HUB;
 200         temp = 1 + (ports / 8);
 201         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 202
 203         /* The Device Removable bits are reported on a byte granularity.
 204          * If the port doesn't exist within that byte, the bit is set to 0.
 205          */
 206         memset(port_removable, 0, sizeof(port_removable));
 207         for (i = 0; i < ports; i++) {
 208                 portsc = readl(xhci->usb2_ports[i]);
 209                 /* If a device is removable, PORTSC reports a 0, same as in the
 210                  * hub descriptor DeviceRemovable bits.
 211                  */
 212                 if (portsc & PORT_DEV_REMOVE)
 213                         /* This math is hairy because bit 0 of DeviceRemovable
 214                          * is reserved, and bit 1 is for port 1, etc.
 215                          */
 216                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 217         }
 218
 219         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 220          * ports on it.  The USB 2.0 specification says that there are two
 221          * variable length fields at the end of the hub descriptor:
 222          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 223          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 224          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 225          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 226          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 227          * set of ports that actually exist.
 228          */
 229         memset(desc->u.hs.DeviceRemovable, 0xff,
 230                         sizeof(desc->u.hs.DeviceRemovable));
 231         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 232                         sizeof(desc->u.hs.PortPwrCtrlMask));
 233
 234         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 235                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 236                                 sizeof(__u8));
 237 }
 238
 239 /* Fill in the USB 3.0 roothub descriptor */
 240 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 241                 struct usb_hub_descriptor *desc)
 242 {
 243         int ports;
 244         u16 port_removable;
 245         u32 portsc;
 246         unsigned int i;
 247
 248         ports = xhci->num_usb3_ports;
 249         xhci_common_hub_descriptor(xhci, desc, ports);
 250         desc->bDescriptorType = USB_DT_SS_HUB;
 251         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 252
 253         /* header decode latency should be zero for roothubs,
 254          * see section 4.23.5.2.
 255          */
 256         desc->u.ss.bHubHdrDecLat = 0;
 257         desc->u.ss.wHubDelay = 0;
 258
 259         port_removable = 0;
 260         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 261         for (i = 0; i < ports; i++) {
 262                 portsc = readl(xhci->usb3_ports[i]);
 263                 if (portsc & PORT_DEV_REMOVE)
 264                         port_removable |= 1 << (i + 1);
 265         }
 266
 267         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 268 }
 269
 270 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 271                 struct usb_hub_descriptor *desc)
 272 {
 273
 274         if (hcd->speed >= HCD_USB3)
 275                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 276         else
 277                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 278
 279 }
 280
 281 static unsigned int xhci_port_speed(unsigned int port_status)
 282 {
 283         if (DEV_LOWSPEED(port_status))
 284                 return USB_PORT_STAT_LOW_SPEED;
 285         if (DEV_HIGHSPEED(port_status))
 286                 return USB_PORT_STAT_HIGH_SPEED;
 287         /*
 288          * FIXME: Yes, we should check for full speed, but the core uses that as
 289          * a default in portspeed() in usb/core/hub.c (which is the only place
 290          * USB_PORT_STAT_*_SPEED is used).
 291          */
 292         return 0;
 293 }
 294
 295 /*
 296  * These bits are Read Only (RO) and should be saved and written to the
 297  * registers: 0, 3, 10:13, 30
 298  * connect status, over-current status, port speed, and device removable.
 299  * connect status and port speed are also sticky - meaning they're in
 300  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 301  */
 302 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 303 /*
 304  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 305  * bits 5:8, 9, 14:15, 25:27
 306  * link state, port power, port indicator state, "wake on" enable state
 307  */
 308 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 309 /*
 310  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 311  * bit 4 (port reset)
 312  */
 313 #define XHCI_PORT_RW1S  ((1<<4))
 314 /*
 315  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 316  * bits 1, 17, 18, 19, 20, 21, 22, 23
 317  * port enable/disable, and
 318  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 319  * over-current, reset, link state, and L1 change
 320  */
 321 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 322 /*
 323  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 324  * latched in
 325  */
 326 #define XHCI_PORT_RW    ((1<<16))
 327 /*
 328  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 329  * bits 2, 24, 28:31
 330  */
 331 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 332
 333 /*
 334  * Given a port state, this function returns a value that would result in the
 335  * port being in the same state, if the value was written to the port status
 336  * control register.
 337  * Save Read Only (RO) bits and save read/write bits where
 338  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 339  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 340  */
 341 u32 xhci_port_state_to_neutral(u32 state)
 342 {
 343         /* Save read-only status and port state */
 344         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 345 }
 346
 347 /*
 348  * find slot id based on port number.
 349  * @port: The one-based port number from one of the two split roothubs.
 350  */
 351 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 352                 u16 port)
 353 {
 354         int slot_id;
 355         int i;
 356         enum usb_device_speed speed;
 357
 358         slot_id = 0;
 359         for (i = 0; i < MAX_HC_SLOTS; i++) {
 360                 if (!xhci->devs[i])
 361                         continue;
 362                 speed = xhci->devs[i]->udev->speed;
 363                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 364                                 && xhci->devs[i]->fake_port == port) {
 365                         slot_id = i;
 366                         break;
 367                 }
 368         }
 369
 370         return slot_id;
 371 }
 372
 373 /*
 374  * Stop device
 375  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 376  * to complete.
 377  * suspend will set to 1, if suspend bit need to set in command.
 378  */
 379 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 380 {
 381         struct xhci_virt_device *virt_dev;
 382         struct xhci_command *cmd;
 383         unsigned long flags;
 384         int ret;
 385         int i;
 386
 387         ret = 0;
 388         virt_dev = xhci->devs[slot_id];
 389         if (!virt_dev)
 390                 return -ENODEV;
 391
 392         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 393         if (!cmd) {
 394                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 395                 return -ENOMEM;
 396         }
 397
 398         spin_lock_irqsave(&xhci->lock, flags);
 399         for (i = LAST_EP_INDEX; i > 0; i--) {
 400                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 401                         struct xhci_command *command;
 402                         command = xhci_alloc_command(xhci, false, false,
 403                                                      GFP_NOWAIT);
 404                         if (!command) {
 405                                 spin_unlock_irqrestore(&xhci->lock, flags);
 406                                 xhci_free_command(xhci, cmd);
 407                                 return -ENOMEM;
 408
 409                         }
 410                         xhci_queue_stop_endpoint(xhci, command, slot_id, i,
 411                                                  suspend);
 412                 }
 413         }
 414         xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 415         xhci_ring_cmd_db(xhci);
 416         spin_unlock_irqrestore(&xhci->lock, flags);
 417
 418         /* Wait for last stop endpoint command to finish */
 419         wait_for_completion(cmd->completion);
 420
 421         if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
 422                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 423                 ret = -ETIME;
 424         }
 425         xhci_free_command(xhci, cmd);
 426         return ret;
 427 }
 428
 429 /*
 430  * Ring device, it rings the all doorbells unconditionally.
 431  */
 432 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 433 {
 434         int i, s;
 435         struct xhci_virt_ep *ep;
 436
 437         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 438                 ep = &xhci->devs[slot_id]->eps[i];
 439
 440                 if (ep->ep_state & EP_HAS_STREAMS) {
 441                         for (s = 1; s < ep->stream_info->num_streams; s++)
 442                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 443                 } else if (ep->ring && ep->ring->dequeue) {
 444                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 445                 }
 446         }
 447
 448         return;
 449 }
 450
 451 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 452                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 453 {
 454         /* Don't allow the USB core to disable SuperSpeed ports. */
 455         if (hcd->speed >= HCD_USB3) {
 456                 xhci_dbg(xhci, "Ignoring request to disable "
 457                                 "SuperSpeed port.\n");
 458                 return;
 459         }
 460
 461         /* Write 1 to disable the port */
 462         writel(port_status | PORT_PE, addr);
 463         port_status = readl(addr);
 464         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 465                         wIndex, port_status);
 466 }
 467
 468 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 469                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 470 {
 471         char *port_change_bit;
 472         u32 status;
 473
 474         switch (wValue) {
 475         case USB_PORT_FEAT_C_RESET:
 476                 status = PORT_RC;
 477                 port_change_bit = "reset";
 478                 break;
 479         case USB_PORT_FEAT_C_BH_PORT_RESET:
 480                 status = PORT_WRC;
 481                 port_change_bit = "warm(BH) reset";
 482                 break;
 483         case USB_PORT_FEAT_C_CONNECTION:
 484                 status = PORT_CSC;
 485                 port_change_bit = "connect";
 486                 break;
 487         case USB_PORT_FEAT_C_OVER_CURRENT:
 488                 status = PORT_OCC;
 489                 port_change_bit = "over-current";
 490                 break;
 491         case USB_PORT_FEAT_C_ENABLE:
 492                 status = PORT_PEC;
 493                 port_change_bit = "enable/disable";
 494                 break;
 495         case USB_PORT_FEAT_C_SUSPEND:
 496                 status = PORT_PLC;
 497                 port_change_bit = "suspend/resume";
 498                 break;
 499         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 500                 status = PORT_PLC;
 501                 port_change_bit = "link state";
 502                 break;
 503         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 504                 status = PORT_CEC;
 505                 port_change_bit = "config error";
 506                 break;
 507         default:
 508                 /* Should never happen */
 509                 return;
 510         }
 511         /* Change bits are all write 1 to clear */
 512         writel(port_status | status, addr);
 513         port_status = readl(addr);
 514         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 515                         port_change_bit, wIndex, port_status);
 516 }
 517
 518 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 519 {
 520         int max_ports;
 521         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 522
 523         if (hcd->speed >= HCD_USB3) {
 524                 max_ports = xhci->num_usb3_ports;
 525                 *port_array = xhci->usb3_ports;
 526         } else {
 527                 max_ports = xhci->num_usb2_ports;
 528                 *port_array = xhci->usb2_ports;
 529         }
 530
 531         return max_ports;
 532 }
 533
 534 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 535                                 int port_id, u32 link_state)
 536 {
 537         u32 temp;
 538
 539         temp = readl(port_array[port_id]);
 540         temp = xhci_port_state_to_neutral(temp);
 541         temp &= ~PORT_PLS_MASK;
 542         temp |= PORT_LINK_STROBE | link_state;
 543         writel(temp, port_array[port_id]);
 544 }
 545
 546 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 547                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 548 {
 549         u32 temp;
 550
 551         temp = readl(port_array[port_id]);
 552         temp = xhci_port_state_to_neutral(temp);
 553
 554         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 555                 temp |= PORT_WKCONN_E;
 556         else
 557                 temp &= ~PORT_WKCONN_E;
 558
 559         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 560                 temp |= PORT_WKDISC_E;
 561         else
 562                 temp &= ~PORT_WKDISC_E;
 563
 564         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 565                 temp |= PORT_WKOC_E;
 566         else
 567                 temp &= ~PORT_WKOC_E;
 568
 569         writel(temp, port_array[port_id]);
 570 }
 571
 572 /* Test and clear port RWC bit */
 573 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 574                                 int port_id, u32 port_bit)
 575 {
 576         u32 temp;
 577
 578         temp = readl(port_array[port_id]);
 579         if (temp & port_bit) {
 580                 temp = xhci_port_state_to_neutral(temp);
 581                 temp |= port_bit;
 582                 writel(temp, port_array[port_id]);
 583         }
 584 }
 585
 586 /* Updates Link Status for USB 2.1 port */
 587 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 588 {
 589         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 590                 *status |= USB_PORT_STAT_L1;
 591 }
 592
 593 /* Updates Link Status for super Speed port */
 594 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 595                 u32 *status, u32 status_reg)
 596 {
 597         u32 pls = status_reg & PORT_PLS_MASK;
 598
 599         /* resume state is a xHCI internal state.
 600          * Do not report it to usb core, instead, pretend to be U3,
 601          * thus usb core knows it's not ready for transfer
 602          */
 603         if (pls == XDEV_RESUME) {
 604                 *status |= USB_SS_PORT_LS_U3;
 605                 return;
 606         }
 607
 608         /* When the CAS bit is set then warm reset
 609          * should be performed on port
 610          */
 611         if (status_reg & PORT_CAS) {
 612                 /* The CAS bit can be set while the port is
 613                  * in any link state.
 614                  * Only roothubs have CAS bit, so we
 615                  * pretend to be in compliance mode
 616                  * unless we're already in compliance
 617                  * or the inactive state.
 618                  */
 619                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 620                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 621                         pls = USB_SS_PORT_LS_COMP_MOD;
 622                 }
 623                 /* Return also connection bit -
 624                  * hub state machine resets port
 625                  * when this bit is set.
 626                  */
 627                 pls |= USB_PORT_STAT_CONNECTION;
 628         } else {
 629                 /*
 630                  * If CAS bit isn't set but the Port is already at
 631                  * Compliance Mode, fake a connection so the USB core
 632                  * notices the Compliance state and resets the port.
 633                  * This resolves an issue generated by the SN65LVPE502CP
 634                  * in which sometimes the port enters compliance mode
 635                  * caused by a delay on the host-device negotiation.
 636                  */
 637                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 638                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 639                         pls |= USB_PORT_STAT_CONNECTION;
 640         }
 641
 642         /* update status field */
 643         *status |= pls;
 644 }
 645
 646 /*
 647  * Function for Compliance Mode Quirk.
 648  *
 649  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 650  * the compliance mode timer is deleted. A port won't enter
 651  * compliance mode if it has previously entered U0.
 652  */
 653 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 654                                     u16 wIndex)
 655 {
 656         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 657         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 658
 659         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 660                 return;
 661
 662         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 663                 xhci->port_status_u0 |= 1 << wIndex;
 664                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 665                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 666                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 667                                 "All USB3 ports have entered U0 already!");
 668                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 669                                 "Compliance Mode Recovery Timer Deleted.");
 670                 }
 671         }
 672 }
 673
 674 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 675 {
 676         u32 ext_stat = 0;
 677         int speed_id;
 678
 679         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 680         speed_id = DEV_PORT_SPEED(raw_port_status);
 681         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 682         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 683
 684         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 685         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 686
 687         return ext_stat;
 688 }
 689
 690 /*
 691  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 692  * 3.0 hubs use.
 693  *
 694  * Possible side effects:
 695  *  - Mark a port as being done with device resume,
 696  *    and ring the endpoint doorbells.
 697  *  - Stop the Synopsys redriver Compliance Mode polling.
 698  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 699  */
 700 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 701                 struct xhci_bus_state *bus_state,
 702                 __le32 __iomem **port_array,
 703                 u16 wIndex, u32 raw_port_status,
 704                 unsigned long flags)
 705         __releases(&xhci->lock)
 706         __acquires(&xhci->lock)
 707 {
 708         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 709         u32 status = 0;
 710         int slot_id;
 711
 712         /* wPortChange bits */
 713         if (raw_port_status & PORT_CSC)
 714                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 715         if (raw_port_status & PORT_PEC)
 716                 status |= USB_PORT_STAT_C_ENABLE << 16;
 717         if ((raw_port_status & PORT_OCC))
 718                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 719         if ((raw_port_status & PORT_RC))
 720                 status |= USB_PORT_STAT_C_RESET << 16;
 721         /* USB3.0 only */
 722         if (hcd->speed >= HCD_USB3) {
 723                 /* Port link change with port in resume state should not be
 724                  * reported to usbcore, as this is an internal state to be
 725                  * handled by xhci driver. Reporting PLC to usbcore may
 726                  * cause usbcore clearing PLC first and port change event
 727                  * irq won't be generated.
 728                  */
 729                 if ((raw_port_status & PORT_PLC) &&
 730                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 731                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 732                 if ((raw_port_status & PORT_WRC))
 733                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 734                 if ((raw_port_status & PORT_CEC))
 735                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 736         }
 737
 738         if (hcd->speed < HCD_USB3) {
 739                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 740                                 && (raw_port_status & PORT_POWER))
 741                         status |= USB_PORT_STAT_SUSPEND;
 742         }
 743         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 744                 !DEV_SUPERSPEED_ANY(raw_port_status)) {
 745                 if ((raw_port_status & PORT_RESET) ||
 746                                 !(raw_port_status & PORT_PE))
 747                         return 0xffffffff;
 748                 /* did port event handler already start resume timing? */
 749                 if (!bus_state->resume_done[wIndex]) {
 750                         /* If not, maybe we are in a host initated resume? */
 751                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 752                                 /* Host initated resume doesn't time the resume
 753                                  * signalling using resume_done[].
 754                                  * It manually sets RESUME state, sleeps 20ms
 755                                  * and sets U0 state. This should probably be
 756                                  * changed, but not right now.
 757                                  */
 758                         } else {
 759                                 /* port resume was discovered now and here,
 760                                  * start resume timing
 761                                  */
 762                                 unsigned long timeout = jiffies +
 763                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 764
 765                                 set_bit(wIndex, &bus_state->resuming_ports);
 766                                 bus_state->resume_done[wIndex] = timeout;
 767                                 mod_timer(&hcd->rh_timer, timeout);
 768                         }
 769                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 770                 } else if (time_after_eq(jiffies,
 771                                          bus_state->resume_done[wIndex])) {
 772                         int time_left;
 773
 774                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 775                                         wIndex + 1);
 776                         bus_state->resume_done[wIndex] = 0;
 777                         clear_bit(wIndex, &bus_state->resuming_ports);
 778
 779                         set_bit(wIndex, &bus_state->rexit_ports);
 780                         xhci_set_link_state(xhci, port_array, wIndex,
 781                                         XDEV_U0);
 782
 783                         spin_unlock_irqrestore(&xhci->lock, flags);
 784                         time_left = wait_for_completion_timeout(
 785                                         &bus_state->rexit_done[wIndex],
 786                                         msecs_to_jiffies(
 787                                                 XHCI_MAX_REXIT_TIMEOUT));
 788                         spin_lock_irqsave(&xhci->lock, flags);
 789
 790                         if (time_left) {
 791                                 slot_id = xhci_find_slot_id_by_port(hcd,
 792                                                 xhci, wIndex + 1);
 793                                 if (!slot_id) {
 794                                         xhci_dbg(xhci, "slot_id is zero\n");
 795                                         return 0xffffffff;
 796                                 }
 797                                 xhci_ring_device(xhci, slot_id);
 798                         } else {
 799                                 int port_status = readl(port_array[wIndex]);
 800                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 801                                                 XHCI_MAX_REXIT_TIMEOUT,
 802                                                 port_status);
 803                                 status |= USB_PORT_STAT_SUSPEND;
 804                                 clear_bit(wIndex, &bus_state->rexit_ports);
 805                         }
 806
 807                         bus_state->port_c_suspend |= 1 << wIndex;
 808                         bus_state->suspended_ports &= ~(1 << wIndex);
 809                 } else {
 810                         /*
 811                          * The resume has been signaling for less than
 812                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 813                          * let the usbcore check port status again and clear
 814                          * resume signaling later.
 815                          */
 816                         status |= USB_PORT_STAT_SUSPEND;
 817                 }
 818         }
 819         /*
 820          * Clear stale usb2 resume signalling variables in case port changed
 821          * state during resume signalling. For example on error
 822          */
 823         if ((bus_state->resume_done[wIndex] ||
 824              test_bit(wIndex, &bus_state->resuming_ports)) &&
 825             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 826             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 827                 bus_state->resume_done[wIndex] = 0;
 828                 clear_bit(wIndex, &bus_state->resuming_ports);
 829         }
 830
 831
 832         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 833             (raw_port_status & PORT_POWER)) {
 834                 if (bus_state->suspended_ports & (1 << wIndex)) {
 835                         bus_state->suspended_ports &= ~(1 << wIndex);
 836                         if (hcd->speed < HCD_USB3)
 837                                 bus_state->port_c_suspend |= 1 << wIndex;
 838                 }
 839                 bus_state->resume_done[wIndex] = 0;
 840                 clear_bit(wIndex, &bus_state->resuming_ports);
 841         }
 842         if (raw_port_status & PORT_CONNECT) {
 843                 status |= USB_PORT_STAT_CONNECTION;
 844                 status |= xhci_port_speed(raw_port_status);
 845         }
 846         if (raw_port_status & PORT_PE)
 847                 status |= USB_PORT_STAT_ENABLE;
 848         if (raw_port_status & PORT_OC)
 849                 status |= USB_PORT_STAT_OVERCURRENT;
 850         if (raw_port_status & PORT_RESET)
 851                 status |= USB_PORT_STAT_RESET;
 852         if (raw_port_status & PORT_POWER) {
 853                 if (hcd->speed >= HCD_USB3)
 854                         status |= USB_SS_PORT_STAT_POWER;
 855                 else
 856                         status |= USB_PORT_STAT_POWER;
 857         }
 858         /* Update Port Link State */
 859         if (hcd->speed >= HCD_USB3) {
 860                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
 861                 /*
 862                  * Verify if all USB3 Ports Have entered U0 already.
 863                  * Delete Compliance Mode Timer if so.
 864                  */
 865                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
 866         } else {
 867                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
 868         }
 869         if (bus_state->port_c_suspend & (1 << wIndex))
 870                 status |= USB_PORT_STAT_C_SUSPEND << 16;
 871
 872         return status;
 873 }
 874
 875 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 876                 u16 wIndex, char *buf, u16 wLength)
 877 {
 878         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 879         int max_ports;
 880         unsigned long flags;
 881         u32 temp, status;
 882         int retval = 0;
 883         __le32 __iomem **port_array;
 884         int slot_id;
 885         struct xhci_bus_state *bus_state;
 886         u16 link_state = 0;
 887         u16 wake_mask = 0;
 888         u16 timeout = 0;
 889
 890         max_ports = xhci_get_ports(hcd, &port_array);
 891         bus_state = &xhci->bus_state[hcd_index(hcd)];
 892
 893         spin_lock_irqsave(&xhci->lock, flags);
 894         switch (typeReq) {
 895         case GetHubStatus:
 896                 /* No power source, over-current reported per port */
 897                 memset(buf, 0, 4);
 898                 break;
 899         case GetHubDescriptor:
 900                 /* Check to make sure userspace is asking for the USB 3.0 hub
 901                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 902                  * endpoint, like external hubs do.
 903                  */
 904                 if (hcd->speed >= HCD_USB3 &&
 905                                 (wLength < USB_DT_SS_HUB_SIZE ||
 906                                  wValue != (USB_DT_SS_HUB << 8))) {
 907                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 908                                         "USB 3.0 roothub.\n");
 909                         goto error;
 910                 }
 911                 xhci_hub_descriptor(hcd, xhci,
 912                                 (struct usb_hub_descriptor *) buf);
 913                 break;
 914         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 915                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 916                         goto error;
 917
 918                 if (hcd->speed < HCD_USB3)
 919                         goto error;
 920
 921                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
 922                 spin_unlock_irqrestore(&xhci->lock, flags);
 923                 return retval;
 924         case GetPortStatus:
 925                 if (!wIndex || wIndex > max_ports)
 926                         goto error;
 927                 wIndex--;
 928                 temp = readl(port_array[wIndex]);
 929                 if (temp == 0xffffffff) {
 930                         retval = -ENODEV;
 931                         break;
 932                 }
 933                 status = xhci_get_port_status(hcd, bus_state, port_array,
 934                                 wIndex, temp, flags);
 935                 if (status == 0xffffffff)
 936                         goto error;
 937
 938                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
 939                                 wIndex, temp);
 940                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 941
 942                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 943                 /* if USB 3.1 extended port status return additional 4 bytes */
 944                 if (wValue == 0x02) {
 945                         u32 port_li;
 946
 947                         if (hcd->speed < HCD_USB31 || wLength != 8) {
 948                                 xhci_err(xhci, "get ext port status invalid parameter\n");
 949                                 retval = -EINVAL;
 950                                 break;
 951                         }
 952                         port_li = readl(port_array[wIndex] + PORTLI);
 953                         status = xhci_get_ext_port_status(temp, port_li);
 954                         put_unaligned_le32(cpu_to_le32(status), &buf[4]);
 955                 }
 956                 break;
 957         case SetPortFeature:
 958                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 959                         link_state = (wIndex & 0xff00) >> 3;
 960                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 961                         wake_mask = wIndex & 0xff00;
 962                 /* The MSB of wIndex is the U1/U2 timeout */
 963                 timeout = (wIndex & 0xff00) >> 8;
 964                 wIndex &= 0xff;
 965                 if (!wIndex || wIndex > max_ports)
 966                         goto error;
 967                 wIndex--;
 968                 temp = readl(port_array[wIndex]);
 969                 if (temp == 0xffffffff) {
 970                         retval = -ENODEV;
 971                         break;
 972                 }
 973                 temp = xhci_port_state_to_neutral(temp);
 974                 /* FIXME: What new port features do we need to support? */
 975                 switch (wValue) {
 976                 case USB_PORT_FEAT_SUSPEND:
 977                         temp = readl(port_array[wIndex]);
 978                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 979                                 /* Resume the port to U0 first */
 980                                 xhci_set_link_state(xhci, port_array, wIndex,
 981                                                         XDEV_U0);
 982                                 spin_unlock_irqrestore(&xhci->lock, flags);
 983                                 msleep(10);
 984                                 spin_lock_irqsave(&xhci->lock, flags);
 985                         }
 986                         /* In spec software should not attempt to suspend
 987                          * a port unless the port reports that it is in the
 988                          * enabled (PED = ‘1’,PLS < ‘3’) state.
 989                          */
 990                         temp = readl(port_array[wIndex]);
 991                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
 992                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
 993                                 xhci_warn(xhci, "USB core suspending device "
 994                                           "not in U0/U1/U2.\n");
 995                                 goto error;
 996                         }
 997
 998                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 999                                         wIndex + 1);
1000                         if (!slot_id) {
1001                                 xhci_warn(xhci, "slot_id is zero\n");
1002                                 goto error;
1003                         }
1004                         /* unlock to execute stop endpoint commands */
1005                         spin_unlock_irqrestore(&xhci->lock, flags);
1006                         xhci_stop_device(xhci, slot_id, 1);
1007                         spin_lock_irqsave(&xhci->lock, flags);
1008
1009                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1010
1011                         spin_unlock_irqrestore(&xhci->lock, flags);
1012                         msleep(10); /* wait device to enter */
1013                         spin_lock_irqsave(&xhci->lock, flags);
1014
1015                         temp = readl(port_array[wIndex]);
1016                         bus_state->suspended_ports |= 1 << wIndex;
1017                         break;
1018                 case USB_PORT_FEAT_LINK_STATE:
1019                         temp = readl(port_array[wIndex]);
1020
1021                         /* Disable port */
1022                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1023                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1024                                 temp = xhci_port_state_to_neutral(temp);
1025                                 /*
1026                                  * Clear all change bits, so that we get a new
1027                                  * connection event.
1028                                  */
1029                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1030                                         PORT_OCC | PORT_RC | PORT_PLC |
1031                                         PORT_CEC;
1032                                 writel(temp | PORT_PE, port_array[wIndex]);
1033                                 temp = readl(port_array[wIndex]);
1034                                 break;
1035                         }
1036
1037                         /* Put link in RxDetect (enable port) */
1038                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1039                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1040                                 xhci_set_link_state(xhci, port_array, wIndex,
1041                                                 link_state);
1042                                 temp = readl(port_array[wIndex]);
1043                                 break;
1044                         }
1045
1046                         /* Software should not attempt to set
1047                          * port link state above '3' (U3) and the port
1048                          * must be enabled.
1049                          */
1050                         if ((temp & PORT_PE) == 0 ||
1051                                 (link_state > USB_SS_PORT_LS_U3)) {
1052                                 xhci_warn(xhci, "Cannot set link state.\n");
1053                                 goto error;
1054                         }
1055
1056                         if (link_state == USB_SS_PORT_LS_U3) {
1057                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1058                                                 wIndex + 1);
1059                                 if (slot_id) {
1060                                         /* unlock to execute stop endpoint
1061                                          * commands */
1062                                         spin_unlock_irqrestore(&xhci->lock,
1063                                                                 flags);
1064                                         xhci_stop_device(xhci, slot_id, 1);
1065                                         spin_lock_irqsave(&xhci->lock, flags);
1066                                 }
1067                         }
1068
1069                         xhci_set_link_state(xhci, port_array, wIndex,
1070                                                 link_state);
1071
1072                         spin_unlock_irqrestore(&xhci->lock, flags);
1073                         msleep(20); /* wait device to enter */
1074                         spin_lock_irqsave(&xhci->lock, flags);
1075
1076                         temp = readl(port_array[wIndex]);
1077                         if (link_state == USB_SS_PORT_LS_U3)
1078                                 bus_state->suspended_ports |= 1 << wIndex;
1079                         break;
1080                 case USB_PORT_FEAT_POWER:
1081                         /*
1082                          * Turn on ports, even if there isn't per-port switching.
1083                          * HC will report connect events even before this is set.
1084                          * However, hub_wq will ignore the roothub events until
1085                          * the roothub is registered.
1086                          */
1087                         writel(temp | PORT_POWER, port_array[wIndex]);
1088
1089                         temp = readl(port_array[wIndex]);
1090                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
1091
1092                         spin_unlock_irqrestore(&xhci->lock, flags);
1093                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1094                                         wIndex);
1095                         if (temp)
1096                                 usb_acpi_set_power_state(hcd->self.root_hub,
1097                                                 wIndex, true);
1098                         spin_lock_irqsave(&xhci->lock, flags);
1099                         break;
1100                 case USB_PORT_FEAT_RESET:
1101                         temp = (temp | PORT_RESET);
1102                         writel(temp, port_array[wIndex]);
1103
1104                         temp = readl(port_array[wIndex]);
1105                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1106                         break;
1107                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1108                         xhci_set_remote_wake_mask(xhci, port_array,
1109                                         wIndex, wake_mask);
1110                         temp = readl(port_array[wIndex]);
1111                         xhci_dbg(xhci, "set port remote wake mask, "
1112                                         "actual port %d status  = 0x%x\n",
1113                                         wIndex, temp);
1114                         break;
1115                 case USB_PORT_FEAT_BH_PORT_RESET:
1116                         temp |= PORT_WR;
1117                         writel(temp, port_array[wIndex]);
1118
1119                         temp = readl(port_array[wIndex]);
1120                         break;
1121                 case USB_PORT_FEAT_U1_TIMEOUT:
1122                         if (hcd->speed < HCD_USB3)
1123                                 goto error;
1124                         temp = readl(port_array[wIndex] + PORTPMSC);
1125                         temp &= ~PORT_U1_TIMEOUT_MASK;
1126                         temp |= PORT_U1_TIMEOUT(timeout);
1127                         writel(temp, port_array[wIndex] + PORTPMSC);
1128                         break;
1129                 case USB_PORT_FEAT_U2_TIMEOUT:
1130                         if (hcd->speed < HCD_USB3)
1131                                 goto error;
1132                         temp = readl(port_array[wIndex] + PORTPMSC);
1133                         temp &= ~PORT_U2_TIMEOUT_MASK;
1134                         temp |= PORT_U2_TIMEOUT(timeout);
1135                         writel(temp, port_array[wIndex] + PORTPMSC);
1136                         break;
1137                 default:
1138                         goto error;
1139                 }
1140                 /* unblock any posted writes */
1141                 temp = readl(port_array[wIndex]);
1142                 break;
1143         case ClearPortFeature:
1144                 if (!wIndex || wIndex > max_ports)
1145                         goto error;
1146                 wIndex--;
1147                 temp = readl(port_array[wIndex]);
1148                 if (temp == 0xffffffff) {
1149                         retval = -ENODEV;
1150                         break;
1151                 }
1152                 /* FIXME: What new port features do we need to support? */
1153                 temp = xhci_port_state_to_neutral(temp);
1154                 switch (wValue) {
1155                 case USB_PORT_FEAT_SUSPEND:
1156                         temp = readl(port_array[wIndex]);
1157                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1158                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1159                         if (temp & PORT_RESET)
1160                                 goto error;
1161                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1162                                 if ((temp & PORT_PE) == 0)
1163                                         goto error;
1164
1165                                 set_bit(wIndex, &bus_state->resuming_ports);
1166                                 xhci_set_link_state(xhci, port_array, wIndex,
1167                                                         XDEV_RESUME);
1168                                 spin_unlock_irqrestore(&xhci->lock, flags);
1169                                 msleep(20);
1170                                 spin_lock_irqsave(&xhci->lock, flags);
1171                                 xhci_set_link_state(xhci, port_array, wIndex,
1172                                                         XDEV_U0);
1173                                 clear_bit(wIndex, &bus_state->resuming_ports);
1174                         }
1175                         bus_state->port_c_suspend |= 1 << wIndex;
1176
1177                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1178                                         wIndex + 1);
1179                         if (!slot_id) {
1180                                 xhci_dbg(xhci, "slot_id is zero\n");
1181                                 goto error;
1182                         }
1183                         xhci_ring_device(xhci, slot_id);
1184                         break;
1185                 case USB_PORT_FEAT_C_SUSPEND:
1186                         bus_state->port_c_suspend &= ~(1 << wIndex);
1187                 case USB_PORT_FEAT_C_RESET:
1188                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1189                 case USB_PORT_FEAT_C_CONNECTION:
1190                 case USB_PORT_FEAT_C_OVER_CURRENT:
1191                 case USB_PORT_FEAT_C_ENABLE:
1192                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1193                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1194                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1195                                         port_array[wIndex], temp);
1196                         break;
1197                 case USB_PORT_FEAT_ENABLE:
1198                         xhci_disable_port(hcd, xhci, wIndex,
1199                                         port_array[wIndex], temp);
1200                         break;
1201                 case USB_PORT_FEAT_POWER:
1202                         writel(temp & ~PORT_POWER, port_array[wIndex]);
1203
1204                         spin_unlock_irqrestore(&xhci->lock, flags);
1205                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1206                                         wIndex);
1207                         if (temp)
1208                                 usb_acpi_set_power_state(hcd->self.root_hub,
1209                                                 wIndex, false);
1210                         spin_lock_irqsave(&xhci->lock, flags);
1211                         break;
1212                 default:
1213                         goto error;
1214                 }
1215                 break;
1216         default:
1217 error:
1218                 /* "stall" on error */
1219                 retval = -EPIPE;
1220         }
1221         spin_unlock_irqrestore(&xhci->lock, flags);
1222         return retval;
1223 }
1224
1225 /*
1226  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1227  * Ports are 0-indexed from the HCD point of view,
1228  * and 1-indexed from the USB core pointer of view.
1229  *
1230  * Note that the status change bits will be cleared as soon as a port status
1231  * change event is generated, so we use the saved status from that event.
1232  */
1233 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1234 {
1235         unsigned long flags;
1236         u32 temp, status;
1237         u32 mask;
1238         int i, retval;
1239         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1240         int max_ports;
1241         __le32 __iomem **port_array;
1242         struct xhci_bus_state *bus_state;
1243         bool reset_change = false;
1244
1245         max_ports = xhci_get_ports(hcd, &port_array);
1246         bus_state = &xhci->bus_state[hcd_index(hcd)];
1247
1248         /* Initial status is no changes */
1249         retval = (max_ports + 8) / 8;
1250         memset(buf, 0, retval);
1251
1252         /*
1253          * Inform the usbcore about resume-in-progress by returning
1254          * a non-zero value even if there are no status changes.
1255          */
1256         status = bus_state->resuming_ports;
1257
1258         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1259
1260         spin_lock_irqsave(&xhci->lock, flags);
1261         /* For each port, did anything change?  If so, set that bit in buf. */
1262         for (i = 0; i < max_ports; i++) {
1263                 temp = readl(port_array[i]);
1264                 if (temp == 0xffffffff) {
1265                         retval = -ENODEV;
1266                         break;
1267                 }
1268                 if ((temp & mask) != 0 ||
1269                         (bus_state->port_c_suspend & 1 << i) ||
1270                         (bus_state->resume_done[i] && time_after_eq(
1271                             jiffies, bus_state->resume_done[i]))) {
1272                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1273                         status = 1;
1274                 }
1275                 if ((temp & PORT_RC))
1276                         reset_change = true;
1277         }
1278         if (!status && !reset_change) {
1279                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1280                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1281         }
1282         spin_unlock_irqrestore(&xhci->lock, flags);
1283         return status ? retval : 0;
1284 }
1285
1286 #ifdef CONFIG_PM
1287
1288 int xhci_bus_suspend(struct usb_hcd *hcd)
1289 {
1290         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1291         int max_ports, port_index;
1292         __le32 __iomem **port_array;
1293         struct xhci_bus_state *bus_state;
1294         unsigned long flags;
1295
1296         max_ports = xhci_get_ports(hcd, &port_array);
1297         bus_state = &xhci->bus_state[hcd_index(hcd)];
1298
1299         spin_lock_irqsave(&xhci->lock, flags);
1300
1301         if (hcd->self.root_hub->do_remote_wakeup) {
1302                 if (bus_state->resuming_ports ||        /* USB2 */
1303                     bus_state->port_remote_wakeup) {    /* USB3 */
1304                         spin_unlock_irqrestore(&xhci->lock, flags);
1305                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1306                         return -EBUSY;
1307                 }
1308         }
1309
1310         port_index = max_ports;
1311         bus_state->bus_suspended = 0;
1312         while (port_index--) {
1313                 /* suspend the port if the port is not suspended */
1314                 u32 t1, t2;
1315                 int slot_id;
1316
1317                 t1 = readl(port_array[port_index]);
1318                 t2 = xhci_port_state_to_neutral(t1);
1319
1320                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1321                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1322                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1323                                         port_index + 1);
1324                         if (slot_id) {
1325                                 spin_unlock_irqrestore(&xhci->lock, flags);
1326                                 xhci_stop_device(xhci, slot_id, 1);
1327                                 spin_lock_irqsave(&xhci->lock, flags);
1328                         }
1329                         t2 &= ~PORT_PLS_MASK;
1330                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1331                         set_bit(port_index, &bus_state->bus_suspended);
1332                 }
1333                 /* USB core sets remote wake mask for USB 3.0 hubs,
1334                  * including the USB 3.0 roothub, but only if CONFIG_PM
1335                  * is enabled, so also enable remote wake here.
1336                  */
1337                 if (hcd->self.root_hub->do_remote_wakeup) {
1338                         if (t1 & PORT_CONNECT) {
1339                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1340                                 t2 &= ~PORT_WKCONN_E;
1341                         } else {
1342                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1343                                 t2 &= ~PORT_WKDISC_E;
1344                         }
1345                 } else
1346                         t2 &= ~PORT_WAKE_BITS;
1347
1348                 t1 = xhci_port_state_to_neutral(t1);
1349                 if (t1 != t2)
1350                         writel(t2, port_array[port_index]);
1351         }
1352         hcd->state = HC_STATE_SUSPENDED;
1353         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1354         spin_unlock_irqrestore(&xhci->lock, flags);
1355         return 0;
1356 }
1357
1358 int xhci_bus_resume(struct usb_hcd *hcd)
1359 {
1360         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1361         int max_ports, port_index;
1362         __le32 __iomem **port_array;
1363         struct xhci_bus_state *bus_state;
1364         u32 temp;
1365         unsigned long flags;
1366         unsigned long port_was_suspended = 0;
1367         bool need_usb2_u3_exit = false;
1368         int slot_id;
1369         int sret;
1370
1371         max_ports = xhci_get_ports(hcd, &port_array);
1372         bus_state = &xhci->bus_state[hcd_index(hcd)];
1373
1374         if (time_before(jiffies, bus_state->next_statechange))
1375                 msleep(5);
1376
1377         spin_lock_irqsave(&xhci->lock, flags);
1378         if (!HCD_HW_ACCESSIBLE(hcd)) {
1379                 spin_unlock_irqrestore(&xhci->lock, flags);
1380                 return -ESHUTDOWN;
1381         }
1382
1383         /* delay the irqs */
1384         temp = readl(&xhci->op_regs->command);
1385         temp &= ~CMD_EIE;
1386         writel(temp, &xhci->op_regs->command);
1387
1388         port_index = max_ports;
1389         while (port_index--) {
1390                 /* Check whether need resume ports. If needed
1391                    resume port and disable remote wakeup */
1392                 u32 temp;
1393
1394                 temp = readl(port_array[port_index]);
1395                 if (DEV_SUPERSPEED_ANY(temp))
1396                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1397                 else
1398                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1399                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1400                     (temp & PORT_PLS_MASK)) {
1401                         set_bit(port_index, &port_was_suspended);
1402                         if (!DEV_SUPERSPEED_ANY(temp)) {
1403                                 xhci_set_link_state(xhci, port_array,
1404                                                 port_index, XDEV_RESUME);
1405                                 need_usb2_u3_exit = true;
1406                         }
1407                 } else
1408                         writel(temp, port_array[port_index]);
1409         }
1410
1411         if (need_usb2_u3_exit) {
1412                 spin_unlock_irqrestore(&xhci->lock, flags);
1413                 msleep(20);
1414                 spin_lock_irqsave(&xhci->lock, flags);
1415         }
1416
1417         port_index = max_ports;
1418         while (port_index--) {
1419                 if (!(port_was_suspended & BIT(port_index)))
1420                         continue;
1421                 /* Clear PLC to poll it later after XDEV_U0 */
1422                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1423                 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1424         }
1425
1426         port_index = max_ports;
1427         while (port_index--) {
1428                 if (!(port_was_suspended & BIT(port_index)))
1429                         continue;
1430                 /* Poll and Clear PLC */
1431                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1432                                       PORT_PLC, 10 * 1000);
1433                 if (sret)
1434                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1435                                   port_index);
1436                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1437                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1438                 if (slot_id)
1439                         xhci_ring_device(xhci, slot_id);
1440         }
1441
1442         (void) readl(&xhci->op_regs->command);
1443
1444         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1445         /* re-enable irqs */
1446         temp = readl(&xhci->op_regs->command);
1447         temp |= CMD_EIE;
1448         writel(temp, &xhci->op_regs->command);
1449         temp = readl(&xhci->op_regs->command);
1450
1451         spin_unlock_irqrestore(&xhci->lock, flags);
1452         return 0;
1453 }
1454
1455 #endif  /* CONFIG_PM */