drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70 #include "xhci-trace.h"
  71
  72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  73                 struct xhci_virt_device *virt_dev,
  74                 struct xhci_event_cmd *event);
  75
  76 /*
  77  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  78  * address of the TRB.
  79  */
  80 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  81                 union xhci_trb *trb)
  82 {
  83         unsigned long segment_offset;
  84
  85         if (!seg || !trb || trb < seg->trbs)
  86                 return 0;
  87         /* offset in TRBs */
  88         segment_offset = trb - seg->trbs;
  89         if (segment_offset > TRBS_PER_SEGMENT)
  90                 return 0;
  91         return seg->dma + (segment_offset * sizeof(*trb));
  92 }
  93
  94 /* Does this link TRB point to the first segment in a ring,
  95  * or was the previous TRB the last TRB on the last segment in the ERST?
  96  */
  97 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  98                 struct xhci_segment *seg, union xhci_trb *trb)
  99 {
 100         if (ring == xhci->event_ring)
 101                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 102                         (seg->next == xhci->event_ring->first_seg);
 103         else
 104                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 105 }
 106
 107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 108  * segment?  I.e. would the updated event TRB pointer step off the end of the
 109  * event seg?
 110  */
 111 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 112                 struct xhci_segment *seg, union xhci_trb *trb)
 113 {
 114         if (ring == xhci->event_ring)
 115                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 116         else
 117                 return TRB_TYPE_LINK_LE32(trb->link.control);
 118 }
 119
 120 static int enqueue_is_link_trb(struct xhci_ring *ring)
 121 {
 122         struct xhci_link_trb *link = &ring->enqueue->link;
 123         return TRB_TYPE_LINK_LE32(link->control);
 124 }
 125
 126 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
 127 {
 128         /* Enqueue pointer can be left pointing to the link TRB,
 129          * we must handle that
 130          */
 131         if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
 132                 return ring->enq_seg->next->trbs;
 133         return ring->enqueue;
 134 }
 135
 136 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 137  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 138  * effect the ring dequeue or enqueue pointers.
 139  */
 140 static void next_trb(struct xhci_hcd *xhci,
 141                 struct xhci_ring *ring,
 142                 struct xhci_segment **seg,
 143                 union xhci_trb **trb)
 144 {
 145         if (last_trb(xhci, ring, *seg, *trb)) {
 146                 *seg = (*seg)->next;
 147                 *trb = ((*seg)->trbs);
 148         } else {
 149                 (*trb)++;
 150         }
 151 }
 152
 153 /*
 154  * See Cycle bit rules. SW is the consumer for the event ring only.
 155  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 156  */
 157 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 158 {
 159         ring->deq_updates++;
 160
 161         /*
 162          * If this is not event ring, and the dequeue pointer
 163          * is not on a link TRB, there is one more usable TRB
 164          */
 165         if (ring->type != TYPE_EVENT &&
 166                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 167                 ring->num_trbs_free++;
 168
 169         do {
 170                 /*
 171                  * Update the dequeue pointer further if that was a link TRB or
 172                  * we're at the end of an event ring segment (which doesn't have
 173                  * link TRBS)
 174                  */
 175                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 176                         if (ring->type == TYPE_EVENT &&
 177                                         last_trb_on_last_seg(xhci, ring,
 178                                                 ring->deq_seg, ring->dequeue)) {
 179                                 ring->cycle_state ^= 1;
 180                         }
 181                         ring->deq_seg = ring->deq_seg->next;
 182                         ring->dequeue = ring->deq_seg->trbs;
 183                 } else {
 184                         ring->dequeue++;
 185                 }
 186         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 187 }
 188
 189 /*
 190  * See Cycle bit rules. SW is the consumer for the event ring only.
 191  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 192  *
 193  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 194  * chain bit is set), then set the chain bit in all the following link TRBs.
 195  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 196  * have their chain bit cleared (so that each Link TRB is a separate TD).
 197  *
 198  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 199  * set, but other sections talk about dealing with the chain bit set.  This was
 200  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 201  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 202  *
 203  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 204  *                      prepare_transfer()?
 205  */
 206 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 207                         bool more_trbs_coming)
 208 {
 209         u32 chain;
 210         union xhci_trb *next;
 211
 212         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 213         /* If this is not event ring, there is one less usable TRB */
 214         if (ring->type != TYPE_EVENT &&
 215                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 216                 ring->num_trbs_free--;
 217         next = ++(ring->enqueue);
 218
 219         ring->enq_updates++;
 220         /* Update the dequeue pointer further if that was a link TRB or we're at
 221          * the end of an event ring segment (which doesn't have link TRBS)
 222          */
 223         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 224                 if (ring->type != TYPE_EVENT) {
 225                         /*
 226                          * If the caller doesn't plan on enqueueing more
 227                          * TDs before ringing the doorbell, then we
 228                          * don't want to give the link TRB to the
 229                          * hardware just yet.  We'll give the link TRB
 230                          * back in prepare_ring() just before we enqueue
 231                          * the TD at the top of the ring.
 232                          */
 233                         if (!chain && !more_trbs_coming)
 234                                 break;
 235
 236                         /* If we're not dealing with 0.95 hardware or
 237                          * isoc rings on AMD 0.96 host,
 238                          * carry over the chain bit of the previous TRB
 239                          * (which may mean the chain bit is cleared).
 240                          */
 241                         if (!(ring->type == TYPE_ISOC &&
 242                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 243                                                 && !xhci_link_trb_quirk(xhci)) {
 244                                 next->link.control &=
 245                                         cpu_to_le32(~TRB_CHAIN);
 246                                 next->link.control |=
 247                                         cpu_to_le32(chain);
 248                         }
 249                         /* Give this link TRB to the hardware */
 250                         wmb();
 251                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 252
 253                         /* Toggle the cycle bit after the last ring segment. */
 254                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 255                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 256                         }
 257                 }
 258                 ring->enq_seg = ring->enq_seg->next;
 259                 ring->enqueue = ring->enq_seg->trbs;
 260                 next = ring->enqueue;
 261         }
 262 }
 263
 264 /*
 265  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 266  * enqueue pointer will not advance into dequeue segment. See rules above.
 267  */
 268 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 269                 unsigned int num_trbs)
 270 {
 271         int num_trbs_in_deq_seg;
 272
 273         if (ring->num_trbs_free < num_trbs)
 274                 return 0;
 275
 276         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 277                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 278                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 279                         return 0;
 280         }
 281
 282         return 1;
 283 }
 284
 285 /* Ring the host controller doorbell after placing a command on the ring */
 286 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 287 {
 288         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 289                 return;
 290
 291         xhci_dbg(xhci, "// Ding dong!\n");
 292         writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 293         /* Flush PCI posted writes */
 294         readl(&xhci->dba->doorbell[0]);
 295 }
 296
 297 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 298 {
 299         u64 temp_64;
 300         int ret;
 301
 302         xhci_dbg(xhci, "Abort command ring\n");
 303
 304         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 305                 xhci_dbg(xhci, "The command ring isn't running, "
 306                                 "Have the command ring been stopped?\n");
 307                 return 0;
 308         }
 309
 310         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 311         if (!(temp_64 & CMD_RING_RUNNING)) {
 312                 xhci_dbg(xhci, "Command ring had been stopped\n");
 313                 return 0;
 314         }
 315         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 316         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 317                         &xhci->op_regs->cmd_ring);
 318
 319         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 320          * time the completion od all xHCI commands, including
 321          * the Command Abort operation. If software doesn't see
 322          * CRR negated in a timely manner (e.g. longer than 5
 323          * seconds), then it should assume that the there are
 324          * larger problems with the xHC and assert HCRST.
 325          */
 326         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 327                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 328         if (ret < 0) {
 329                 xhci_err(xhci, "Stopped the command ring failed, "
 330                                 "maybe the host is dead\n");
 331                 xhci->xhc_state |= XHCI_STATE_DYING;
 332                 xhci_quiesce(xhci);
 333                 xhci_halt(xhci);
 334                 return -ESHUTDOWN;
 335         }
 336
 337         return 0;
 338 }
 339
 340 static int xhci_queue_cd(struct xhci_hcd *xhci,
 341                 struct xhci_command *command,
 342                 union xhci_trb *cmd_trb)
 343 {
 344         struct xhci_cd *cd;
 345         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 346         if (!cd)
 347                 return -ENOMEM;
 348         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 349
 350         cd->command = command;
 351         cd->cmd_trb = cmd_trb;
 352         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 353
 354         return 0;
 355 }
 356
 357 /*
 358  * Cancel the command which has issue.
 359  *
 360  * Some commands may hang due to waiting for acknowledgement from
 361  * usb device. It is outside of the xHC's ability to control and
 362  * will cause the command ring is blocked. When it occurs software
 363  * should intervene to recover the command ring.
 364  * See Section 4.6.1.1 and 4.6.1.2
 365  */
 366 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 367                 union xhci_trb *cmd_trb)
 368 {
 369         int retval = 0;
 370         unsigned long flags;
 371
 372         spin_lock_irqsave(&xhci->lock, flags);
 373
 374         if (xhci->xhc_state & XHCI_STATE_DYING) {
 375                 xhci_warn(xhci, "Abort the command ring,"
 376                                 " but the xHCI is dead.\n");
 377                 retval = -ESHUTDOWN;
 378                 goto fail;
 379         }
 380
 381         /* queue the cmd desriptor to cancel_cmd_list */
 382         retval = xhci_queue_cd(xhci, command, cmd_trb);
 383         if (retval) {
 384                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 385                 goto fail;
 386         }
 387
 388         /* abort command ring */
 389         retval = xhci_abort_cmd_ring(xhci);
 390         if (retval) {
 391                 xhci_err(xhci, "Abort command ring failed\n");
 392                 if (unlikely(retval == -ESHUTDOWN)) {
 393                         spin_unlock_irqrestore(&xhci->lock, flags);
 394                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 395                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 396                         return retval;
 397                 }
 398         }
 399
 400 fail:
 401         spin_unlock_irqrestore(&xhci->lock, flags);
 402         return retval;
 403 }
 404
 405 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 406                 unsigned int slot_id,
 407                 unsigned int ep_index,
 408                 unsigned int stream_id)
 409 {
 410         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 411         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 412         unsigned int ep_state = ep->ep_state;
 413
 414         /* Don't ring the doorbell for this endpoint if there are pending
 415          * cancellations because we don't want to interrupt processing.
 416          * We don't want to restart any stream rings if there's a set dequeue
 417          * pointer command pending because the device can choose to start any
 418          * stream once the endpoint is on the HW schedule.
 419          * FIXME - check all the stream rings for pending cancellations.
 420          */
 421         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 422             (ep_state & EP_HALTED))
 423                 return;
 424         writel(DB_VALUE(ep_index, stream_id), db_addr);
 425         /* The CPU has better things to do at this point than wait for a
 426          * write-posting flush.  It'll get there soon enough.
 427          */
 428 }
 429
 430 /* Ring the doorbell for any rings with pending URBs */
 431 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 432                 unsigned int slot_id,
 433                 unsigned int ep_index)
 434 {
 435         unsigned int stream_id;
 436         struct xhci_virt_ep *ep;
 437
 438         ep = &xhci->devs[slot_id]->eps[ep_index];
 439
 440         /* A ring has pending URBs if its TD list is not empty */
 441         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 442                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 443                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 444                 return;
 445         }
 446
 447         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 448                         stream_id++) {
 449                 struct xhci_stream_info *stream_info = ep->stream_info;
 450                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 451                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 452                                                 stream_id);
 453         }
 454 }
 455
 456 /*
 457  * Find the segment that trb is in.  Start searching in start_seg.
 458  * If we must move past a segment that has a link TRB with a toggle cycle state
 459  * bit set, then we will toggle the value pointed at by cycle_state.
 460  */
 461 static struct xhci_segment *find_trb_seg(
 462                 struct xhci_segment *start_seg,
 463                 union xhci_trb  *trb, int *cycle_state)
 464 {
 465         struct xhci_segment *cur_seg = start_seg;
 466         struct xhci_generic_trb *generic_trb;
 467
 468         while (cur_seg->trbs > trb ||
 469                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 470                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 471                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 472                         *cycle_state ^= 0x1;
 473                 cur_seg = cur_seg->next;
 474                 if (cur_seg == start_seg)
 475                         /* Looped over the entire list.  Oops! */
 476                         return NULL;
 477         }
 478         return cur_seg;
 479 }
 480
 481
 482 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 483                 unsigned int slot_id, unsigned int ep_index,
 484                 unsigned int stream_id)
 485 {
 486         struct xhci_virt_ep *ep;
 487
 488         ep = &xhci->devs[slot_id]->eps[ep_index];
 489         /* Common case: no streams */
 490         if (!(ep->ep_state & EP_HAS_STREAMS))
 491                 return ep->ring;
 492
 493         if (stream_id == 0) {
 494                 xhci_warn(xhci,
 495                                 "WARN: Slot ID %u, ep index %u has streams, "
 496                                 "but URB has no stream ID.\n",
 497                                 slot_id, ep_index);
 498                 return NULL;
 499         }
 500
 501         if (stream_id < ep->stream_info->num_streams)
 502                 return ep->stream_info->stream_rings[stream_id];
 503
 504         xhci_warn(xhci,
 505                         "WARN: Slot ID %u, ep index %u has "
 506                         "stream IDs 1 to %u allocated, "
 507                         "but stream ID %u is requested.\n",
 508                         slot_id, ep_index,
 509                         ep->stream_info->num_streams - 1,
 510                         stream_id);
 511         return NULL;
 512 }
 513
 514 /* Get the right ring for the given URB.
 515  * If the endpoint supports streams, boundary check the URB's stream ID.
 516  * If the endpoint doesn't support streams, return the singular endpoint ring.
 517  */
 518 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 519                 struct urb *urb)
 520 {
 521         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 522                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 523 }
 524
 525 /*
 526  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 527  * Record the new state of the xHC's endpoint ring dequeue segment,
 528  * dequeue pointer, and new consumer cycle state in state.
 529  * Update our internal representation of the ring's dequeue pointer.
 530  *
 531  * We do this in three jumps:
 532  *  - First we update our new ring state to be the same as when the xHC stopped.
 533  *  - Then we traverse the ring to find the segment that contains
 534  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 535  *    any link TRBs with the toggle cycle bit set.
 536  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 537  *    if we've moved it past a link TRB with the toggle cycle bit set.
 538  *
 539  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 540  * with correct __le32 accesses they should work fine.  Only users of this are
 541  * in here.
 542  */
 543 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 544                 unsigned int slot_id, unsigned int ep_index,
 545                 unsigned int stream_id, struct xhci_td *cur_td,
 546                 struct xhci_dequeue_state *state)
 547 {
 548         struct xhci_virt_device *dev = xhci->devs[slot_id];
 549         struct xhci_ring *ep_ring;
 550         struct xhci_generic_trb *trb;
 551         struct xhci_ep_ctx *ep_ctx;
 552         dma_addr_t addr;
 553
 554         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 555                         ep_index, stream_id);
 556         if (!ep_ring) {
 557                 xhci_warn(xhci, "WARN can't find new dequeue state "
 558                                 "for invalid stream ID %u.\n",
 559                                 stream_id);
 560                 return;
 561         }
 562         state->new_cycle_state = 0;
 563         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 564                         "Finding segment containing stopped TRB.");
 565         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 566                         dev->eps[ep_index].stopped_trb,
 567                         &state->new_cycle_state);
 568         if (!state->new_deq_seg) {
 569                 WARN_ON(1);
 570                 return;
 571         }
 572
 573         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 574         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 575                         "Finding endpoint context");
 576         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 577         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 578
 579         state->new_deq_ptr = cur_td->last_trb;
 580         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 581                         "Finding segment containing last TRB in TD.");
 582         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 583                         state->new_deq_ptr,
 584                         &state->new_cycle_state);
 585         if (!state->new_deq_seg) {
 586                 WARN_ON(1);
 587                 return;
 588         }
 589
 590         trb = &state->new_deq_ptr->generic;
 591         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 592             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 593                 state->new_cycle_state ^= 0x1;
 594         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 595
 596         /*
 597          * If there is only one segment in a ring, find_trb_seg()'s while loop
 598          * will not run, and it will return before it has a chance to see if it
 599          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 600          * ended just before the link TRB on a one-segment ring, or if the TD
 601          * wrapped around the top of the ring, because it doesn't have the TD in
 602          * question.  Look for the one-segment case where stalled TRB's address
 603          * is greater than the new dequeue pointer address.
 604          */
 605         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 606                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 607                 state->new_cycle_state ^= 0x1;
 608         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 609                         "Cycle state = 0x%x", state->new_cycle_state);
 610
 611         /* Don't update the ring cycle state for the producer (us). */
 612         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 613                         "New dequeue segment = %p (virtual)",
 614                         state->new_deq_seg);
 615         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 616         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 617                         "New dequeue pointer = 0x%llx (DMA)",
 618                         (unsigned long long) addr);
 619 }
 620
 621 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 622  * (The last TRB actually points to the ring enqueue pointer, which is not part
 623  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 624  */
 625 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 626                 struct xhci_td *cur_td, bool flip_cycle)
 627 {
 628         struct xhci_segment *cur_seg;
 629         union xhci_trb *cur_trb;
 630
 631         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 632                         true;
 633                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 634                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 635                         /* Unchain any chained Link TRBs, but
 636                          * leave the pointers intact.
 637                          */
 638                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 639                         /* Flip the cycle bit (link TRBs can't be the first
 640                          * or last TRB).
 641                          */
 642                         if (flip_cycle)
 643                                 cur_trb->generic.field[3] ^=
 644                                         cpu_to_le32(TRB_CYCLE);
 645                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 646                                         "Cancel (unchain) link TRB");
 647                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 648                                         "Address = %p (0x%llx dma); "
 649                                         "in seg %p (0x%llx dma)",
 650                                         cur_trb,
 651                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 652                                         cur_seg,
 653                                         (unsigned long long)cur_seg->dma);
 654                 } else {
 655                         cur_trb->generic.field[0] = 0;
 656                         cur_trb->generic.field[1] = 0;
 657                         cur_trb->generic.field[2] = 0;
 658                         /* Preserve only the cycle bit of this TRB */
 659                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 660                         /* Flip the cycle bit except on the first or last TRB */
 661                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 662                                         cur_trb != cur_td->last_trb)
 663                                 cur_trb->generic.field[3] ^=
 664                                         cpu_to_le32(TRB_CYCLE);
 665                         cur_trb->generic.field[3] |= cpu_to_le32(
 666                                 TRB_TYPE(TRB_TR_NOOP));
 667                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 668                                         "TRB to noop at offset 0x%llx",
 669                                         (unsigned long long)
 670                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 671                 }
 672                 if (cur_trb == cur_td->last_trb)
 673                         break;
 674         }
 675 }
 676
 677 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 678                 unsigned int ep_index, unsigned int stream_id,
 679                 struct xhci_segment *deq_seg,
 680                 union xhci_trb *deq_ptr, u32 cycle_state);
 681
 682 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 683                 unsigned int slot_id, unsigned int ep_index,
 684                 unsigned int stream_id,
 685                 struct xhci_dequeue_state *deq_state)
 686 {
 687         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 688
 689         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 690                         "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 691                         "new deq ptr = %p (0x%llx dma), new cycle = %u",
 692                         deq_state->new_deq_seg,
 693                         (unsigned long long)deq_state->new_deq_seg->dma,
 694                         deq_state->new_deq_ptr,
 695                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 696                         deq_state->new_cycle_state);
 697         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 698                         deq_state->new_deq_seg,
 699                         deq_state->new_deq_ptr,
 700                         (u32) deq_state->new_cycle_state);
 701         /* Stop the TD queueing code from ringing the doorbell until
 702          * this command completes.  The HC won't set the dequeue pointer
 703          * if the ring is running, and ringing the doorbell starts the
 704          * ring running.
 705          */
 706         ep->ep_state |= SET_DEQ_PENDING;
 707 }
 708
 709 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 710                 struct xhci_virt_ep *ep)
 711 {
 712         ep->ep_state &= ~EP_HALT_PENDING;
 713         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 714          * timer is running on another CPU, we don't decrement stop_cmds_pending
 715          * (since we didn't successfully stop the watchdog timer).
 716          */
 717         if (del_timer(&ep->stop_cmd_timer))
 718                 ep->stop_cmds_pending--;
 719 }
 720
 721 /* Must be called with xhci->lock held in interrupt context */
 722 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 723                 struct xhci_td *cur_td, int status)
 724 {
 725         struct usb_hcd *hcd;
 726         struct urb      *urb;
 727         struct urb_priv *urb_priv;
 728
 729         urb = cur_td->urb;
 730         urb_priv = urb->hcpriv;
 731         urb_priv->td_cnt++;
 732         hcd = bus_to_hcd(urb->dev->bus);
 733
 734         /* Only giveback urb when this is the last td in urb */
 735         if (urb_priv->td_cnt == urb_priv->length) {
 736                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 737                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 738                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 739                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 740                                         usb_amd_quirk_pll_enable();
 741                         }
 742                 }
 743                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 744
 745                 spin_unlock(&xhci->lock);
 746                 usb_hcd_giveback_urb(hcd, urb, status);
 747                 xhci_urb_free_priv(xhci, urb_priv);
 748                 spin_lock(&xhci->lock);
 749         }
 750 }
 751
 752 /*
 753  * When we get a command completion for a Stop Endpoint Command, we need to
 754  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 755  *
 756  *  1. If the HW was in the middle of processing the TD that needs to be
 757  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 758  *     in the TD with a Set Dequeue Pointer Command.
 759  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 760  *     bit cleared) so that the HW will skip over them.
 761  */
 762 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
 763                 union xhci_trb *trb, struct xhci_event_cmd *event)
 764 {
 765         unsigned int ep_index;
 766         struct xhci_virt_device *virt_dev;
 767         struct xhci_ring *ep_ring;
 768         struct xhci_virt_ep *ep;
 769         struct list_head *entry;
 770         struct xhci_td *cur_td = NULL;
 771         struct xhci_td *last_unlinked_td;
 772
 773         struct xhci_dequeue_state deq_state;
 774
 775         if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
 776                 virt_dev = xhci->devs[slot_id];
 777                 if (virt_dev)
 778                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 779                                 event);
 780                 else
 781                         xhci_warn(xhci, "Stop endpoint command "
 782                                 "completion for disabled slot %u\n",
 783                                 slot_id);
 784                 return;
 785         }
 786
 787         memset(&deq_state, 0, sizeof(deq_state));
 788         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 789         ep = &xhci->devs[slot_id]->eps[ep_index];
 790
 791         if (list_empty(&ep->cancelled_td_list)) {
 792                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 793                 ep->stopped_td = NULL;
 794                 ep->stopped_trb = NULL;
 795                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 796                 return;
 797         }
 798
 799         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 800          * We have the xHCI lock, so nothing can modify this list until we drop
 801          * it.  We're also in the event handler, so we can't get re-interrupted
 802          * if another Stop Endpoint command completes
 803          */
 804         list_for_each(entry, &ep->cancelled_td_list) {
 805                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 806                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 807                                 "Removing canceled TD starting at 0x%llx (dma).",
 808                                 (unsigned long long)xhci_trb_virt_to_dma(
 809                                         cur_td->start_seg, cur_td->first_trb));
 810                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 811                 if (!ep_ring) {
 812                         /* This shouldn't happen unless a driver is mucking
 813                          * with the stream ID after submission.  This will
 814                          * leave the TD on the hardware ring, and the hardware
 815                          * will try to execute it, and may access a buffer
 816                          * that has already been freed.  In the best case, the
 817                          * hardware will execute it, and the event handler will
 818                          * ignore the completion event for that TD, since it was
 819                          * removed from the td_list for that endpoint.  In
 820                          * short, don't muck with the stream ID after
 821                          * submission.
 822                          */
 823                         xhci_warn(xhci, "WARN Cancelled URB %p "
 824                                         "has invalid stream ID %u.\n",
 825                                         cur_td->urb,
 826                                         cur_td->urb->stream_id);
 827                         goto remove_finished_td;
 828                 }
 829                 /*
 830                  * If we stopped on the TD we need to cancel, then we have to
 831                  * move the xHC endpoint ring dequeue pointer past this TD.
 832                  */
 833                 if (cur_td == ep->stopped_td)
 834                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 835                                         cur_td->urb->stream_id,
 836                                         cur_td, &deq_state);
 837                 else
 838                         td_to_noop(xhci, ep_ring, cur_td, false);
 839 remove_finished_td:
 840                 /*
 841                  * The event handler won't see a completion for this TD anymore,
 842                  * so remove it from the endpoint ring's TD list.  Keep it in
 843                  * the cancelled TD list for URB completion later.
 844                  */
 845                 list_del_init(&cur_td->td_list);
 846         }
 847         last_unlinked_td = cur_td;
 848         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 849
 850         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 851         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 852                 xhci_queue_new_dequeue_state(xhci,
 853                                 slot_id, ep_index,
 854                                 ep->stopped_td->urb->stream_id,
 855                                 &deq_state);
 856                 xhci_ring_cmd_db(xhci);
 857         } else {
 858                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 859                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 860         }
 861
 862         /* Clear stopped_td and stopped_trb if endpoint is not halted */
 863         if (!(ep->ep_state & EP_HALTED)) {
 864                 ep->stopped_td = NULL;
 865                 ep->stopped_trb = NULL;
 866         }
 867
 868         /*
 869          * Drop the lock and complete the URBs in the cancelled TD list.
 870          * New TDs to be cancelled might be added to the end of the list before
 871          * we can complete all the URBs for the TDs we already unlinked.
 872          * So stop when we've completed the URB for the last TD we unlinked.
 873          */
 874         do {
 875                 cur_td = list_entry(ep->cancelled_td_list.next,
 876                                 struct xhci_td, cancelled_td_list);
 877                 list_del_init(&cur_td->cancelled_td_list);
 878
 879                 /* Clean up the cancelled URB */
 880                 /* Doesn't matter what we pass for status, since the core will
 881                  * just overwrite it (because the URB has been unlinked).
 882                  */
 883                 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
 884
 885                 /* Stop processing the cancelled list if the watchdog timer is
 886                  * running.
 887                  */
 888                 if (xhci->xhc_state & XHCI_STATE_DYING)
 889                         return;
 890         } while (cur_td != last_unlinked_td);
 891
 892         /* Return to the event handler with xhci->lock re-acquired */
 893 }
 894
 895 /* Watchdog timer function for when a stop endpoint command fails to complete.
 896  * In this case, we assume the host controller is broken or dying or dead.  The
 897  * host may still be completing some other events, so we have to be careful to
 898  * let the event ring handler and the URB dequeueing/enqueueing functions know
 899  * through xhci->state.
 900  *
 901  * The timer may also fire if the host takes a very long time to respond to the
 902  * command, and the stop endpoint command completion handler cannot delete the
 903  * timer before the timer function is called.  Another endpoint cancellation may
 904  * sneak in before the timer function can grab the lock, and that may queue
 905  * another stop endpoint command and add the timer back.  So we cannot use a
 906  * simple flag to say whether there is a pending stop endpoint command for a
 907  * particular endpoint.
 908  *
 909  * Instead we use a combination of that flag and a counter for the number of
 910  * pending stop endpoint commands.  If the timer is the tail end of the last
 911  * stop endpoint command, and the endpoint's command is still pending, we assume
 912  * the host is dying.
 913  */
 914 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 915 {
 916         struct xhci_hcd *xhci;
 917         struct xhci_virt_ep *ep;
 918         struct xhci_virt_ep *temp_ep;
 919         struct xhci_ring *ring;
 920         struct xhci_td *cur_td;
 921         int ret, i, j;
 922         unsigned long flags;
 923
 924         ep = (struct xhci_virt_ep *) arg;
 925         xhci = ep->xhci;
 926
 927         spin_lock_irqsave(&xhci->lock, flags);
 928
 929         ep->stop_cmds_pending--;
 930         if (xhci->xhc_state & XHCI_STATE_DYING) {
 931                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 932                                 "Stop EP timer ran, but another timer marked "
 933                                 "xHCI as DYING, exiting.");
 934                 spin_unlock_irqrestore(&xhci->lock, flags);
 935                 return;
 936         }
 937         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 938                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 939                                 "Stop EP timer ran, but no command pending, "
 940                                 "exiting.");
 941                 spin_unlock_irqrestore(&xhci->lock, flags);
 942                 return;
 943         }
 944
 945         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 946         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 947         /* Oops, HC is dead or dying or at least not responding to the stop
 948          * endpoint command.
 949          */
 950         xhci->xhc_state |= XHCI_STATE_DYING;
 951         /* Disable interrupts from the host controller and start halting it */
 952         xhci_quiesce(xhci);
 953         spin_unlock_irqrestore(&xhci->lock, flags);
 954
 955         ret = xhci_halt(xhci);
 956
 957         spin_lock_irqsave(&xhci->lock, flags);
 958         if (ret < 0) {
 959                 /* This is bad; the host is not responding to commands and it's
 960                  * not allowing itself to be halted.  At least interrupts are
 961                  * disabled. If we call usb_hc_died(), it will attempt to
 962                  * disconnect all device drivers under this host.  Those
 963                  * disconnect() methods will wait for all URBs to be unlinked,
 964                  * so we must complete them.
 965                  */
 966                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 967                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 968                 /* We could turn all TDs on the rings to no-ops.  This won't
 969                  * help if the host has cached part of the ring, and is slow if
 970                  * we want to preserve the cycle bit.  Skip it and hope the host
 971                  * doesn't touch the memory.
 972                  */
 973         }
 974         for (i = 0; i < MAX_HC_SLOTS; i++) {
 975                 if (!xhci->devs[i])
 976                         continue;
 977                 for (j = 0; j < 31; j++) {
 978                         temp_ep = &xhci->devs[i]->eps[j];
 979                         ring = temp_ep->ring;
 980                         if (!ring)
 981                                 continue;
 982                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 983                                         "Killing URBs for slot ID %u, "
 984                                         "ep index %u", i, j);
 985                         while (!list_empty(&ring->td_list)) {
 986                                 cur_td = list_first_entry(&ring->td_list,
 987                                                 struct xhci_td,
 988                                                 td_list);
 989                                 list_del_init(&cur_td->td_list);
 990                                 if (!list_empty(&cur_td->cancelled_td_list))
 991                                         list_del_init(&cur_td->cancelled_td_list);
 992                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 993                                                 -ESHUTDOWN);
 994                         }
 995                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 996                                 cur_td = list_first_entry(
 997                                                 &temp_ep->cancelled_td_list,
 998                                                 struct xhci_td,
 999                                                 cancelled_td_list);
1000                                 list_del_init(&cur_td->cancelled_td_list);
1001                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1002                                                 -ESHUTDOWN);
1003                         }
1004                 }
1005         }
1006         spin_unlock_irqrestore(&xhci->lock, flags);
1007         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1008                         "Calling usb_hc_died()");
1009         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1010         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1011                         "xHCI host controller is dead.");
1012 }
1013
1014
1015 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1016                 struct xhci_virt_device *dev,
1017                 struct xhci_ring *ep_ring,
1018                 unsigned int ep_index)
1019 {
1020         union xhci_trb *dequeue_temp;
1021         int num_trbs_free_temp;
1022         bool revert = false;
1023
1024         num_trbs_free_temp = ep_ring->num_trbs_free;
1025         dequeue_temp = ep_ring->dequeue;
1026
1027         /* If we get two back-to-back stalls, and the first stalled transfer
1028          * ends just before a link TRB, the dequeue pointer will be left on
1029          * the link TRB by the code in the while loop.  So we have to update
1030          * the dequeue pointer one segment further, or we'll jump off
1031          * the segment into la-la-land.
1032          */
1033         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1034                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1035                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1036         }
1037
1038         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1039                 /* We have more usable TRBs */
1040                 ep_ring->num_trbs_free++;
1041                 ep_ring->dequeue++;
1042                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1043                                 ep_ring->dequeue)) {
1044                         if (ep_ring->dequeue ==
1045                                         dev->eps[ep_index].queued_deq_ptr)
1046                                 break;
1047                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1048                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1049                 }
1050                 if (ep_ring->dequeue == dequeue_temp) {
1051                         revert = true;
1052                         break;
1053                 }
1054         }
1055
1056         if (revert) {
1057                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1058                 ep_ring->num_trbs_free = num_trbs_free_temp;
1059         }
1060 }
1061
1062 /*
1063  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1064  * we need to clear the set deq pending flag in the endpoint ring state, so that
1065  * the TD queueing code can ring the doorbell again.  We also need to ring the
1066  * endpoint doorbell to restart the ring, but only if there aren't more
1067  * cancellations pending.
1068  */
1069 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1070                 union xhci_trb *trb, u32 cmd_comp_code)
1071 {
1072         unsigned int ep_index;
1073         unsigned int stream_id;
1074         struct xhci_ring *ep_ring;
1075         struct xhci_virt_device *dev;
1076         struct xhci_ep_ctx *ep_ctx;
1077         struct xhci_slot_ctx *slot_ctx;
1078
1079         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1080         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1081         dev = xhci->devs[slot_id];
1082
1083         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1084         if (!ep_ring) {
1085                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1086                                 "freed stream ID %u\n",
1087                                 stream_id);
1088                 /* XXX: Harmless??? */
1089                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1090                 return;
1091         }
1092
1093         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1094         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1095
1096         if (cmd_comp_code != COMP_SUCCESS) {
1097                 unsigned int ep_state;
1098                 unsigned int slot_state;
1099
1100                 switch (cmd_comp_code) {
1101                 case COMP_TRB_ERR:
1102                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1103                                         "of stream ID configuration\n");
1104                         break;
1105                 case COMP_CTX_STATE:
1106                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1107                                         "to incorrect slot or ep state.\n");
1108                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1109                         ep_state &= EP_STATE_MASK;
1110                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1111                         slot_state = GET_SLOT_STATE(slot_state);
1112                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1113                                         "Slot state = %u, EP state = %u",
1114                                         slot_state, ep_state);
1115                         break;
1116                 case COMP_EBADSLT:
1117                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1118                                         "slot %u was not enabled.\n", slot_id);
1119                         break;
1120                 default:
1121                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1122                                         "completion code of %u.\n",
1123                                   cmd_comp_code);
1124                         break;
1125                 }
1126                 /* OK what do we do now?  The endpoint state is hosed, and we
1127                  * should never get to this point if the synchronization between
1128                  * queueing, and endpoint state are correct.  This might happen
1129                  * if the device gets disconnected after we've finished
1130                  * cancelling URBs, which might not be an error...
1131                  */
1132         } else {
1133                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1134                         "Successful Set TR Deq Ptr cmd, deq = @%08llx",
1135                          le64_to_cpu(ep_ctx->deq));
1136                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1137                                          dev->eps[ep_index].queued_deq_ptr) ==
1138                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1139                         /* Update the ring's dequeue segment and dequeue pointer
1140                          * to reflect the new position.
1141                          */
1142                         update_ring_for_set_deq_completion(xhci, dev,
1143                                 ep_ring, ep_index);
1144                 } else {
1145                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1146                                         "Ptr command & xHCI internal state.\n");
1147                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1148                                         dev->eps[ep_index].queued_deq_seg,
1149                                         dev->eps[ep_index].queued_deq_ptr);
1150                 }
1151         }
1152
1153         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1154         dev->eps[ep_index].queued_deq_seg = NULL;
1155         dev->eps[ep_index].queued_deq_ptr = NULL;
1156         /* Restart any rings with pending URBs */
1157         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1158 }
1159
1160 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1161                 union xhci_trb *trb, u32 cmd_comp_code)
1162 {
1163         unsigned int ep_index;
1164
1165         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1166         /* This command will only fail if the endpoint wasn't halted,
1167          * but we don't care.
1168          */
1169         xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1170                 "Ignoring reset ep completion code of %u", cmd_comp_code);
1171
1172         /* HW with the reset endpoint quirk needs to have a configure endpoint
1173          * command complete before the endpoint can be used.  Queue that here
1174          * because the HW can't handle two commands being queued in a row.
1175          */
1176         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1177                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1178                                 "Queueing configure endpoint command");
1179                 xhci_queue_configure_endpoint(xhci,
1180                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1181                                 false);
1182                 xhci_ring_cmd_db(xhci);
1183         } else {
1184                 /* Clear our internal halted state and restart the ring(s) */
1185                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1186                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1187         }
1188 }
1189
1190 /* Complete the command and detele it from the devcie's command queue.
1191  */
1192 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1193                 struct xhci_command *command, u32 status)
1194 {
1195         command->status = status;
1196         list_del(&command->cmd_list);
1197         if (command->completion)
1198                 complete(command->completion);
1199         else
1200                 xhci_free_command(xhci, command);
1201 }
1202
1203
1204 /* Check to see if a command in the device's command queue matches this one.
1205  * Signal the completion or free the command, and return 1.  Return 0 if the
1206  * completed command isn't at the head of the command list.
1207  */
1208 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1209                 struct xhci_virt_device *virt_dev,
1210                 struct xhci_event_cmd *event)
1211 {
1212         struct xhci_command *command;
1213
1214         if (list_empty(&virt_dev->cmd_list))
1215                 return 0;
1216
1217         command = list_entry(virt_dev->cmd_list.next,
1218                         struct xhci_command, cmd_list);
1219         if (xhci->cmd_ring->dequeue != command->command_trb)
1220                 return 0;
1221
1222         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1223                         GET_COMP_CODE(le32_to_cpu(event->status)));
1224         return 1;
1225 }
1226
1227 /*
1228  * Finding the command trb need to be cancelled and modifying it to
1229  * NO OP command. And if the command is in device's command wait
1230  * list, finishing and freeing it.
1231  *
1232  * If we can't find the command trb, we think it had already been
1233  * executed.
1234  */
1235 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1236 {
1237         struct xhci_segment *cur_seg;
1238         union xhci_trb *cmd_trb;
1239         u32 cycle_state;
1240
1241         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1242                 return;
1243
1244         /* find the current segment of command ring */
1245         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1246                         xhci->cmd_ring->dequeue, &cycle_state);
1247
1248         if (!cur_seg) {
1249                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1250                                 xhci->cmd_ring->dequeue,
1251                                 (unsigned long long)
1252                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1253                                         xhci->cmd_ring->dequeue));
1254                 xhci_debug_ring(xhci, xhci->cmd_ring);
1255                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1256                 return;
1257         }
1258
1259         /* find the command trb matched by cd from command ring */
1260         for (cmd_trb = xhci->cmd_ring->dequeue;
1261                         cmd_trb != xhci->cmd_ring->enqueue;
1262                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1263                 /* If the trb is link trb, continue */
1264                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1265                         continue;
1266
1267                 if (cur_cd->cmd_trb == cmd_trb) {
1268
1269                         /* If the command in device's command list, we should
1270                          * finish it and free the command structure.
1271                          */
1272                         if (cur_cd->command)
1273                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1274                                         cur_cd->command, COMP_CMD_STOP);
1275
1276                         /* get cycle state from the origin command trb */
1277                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1278                                 & TRB_CYCLE;
1279
1280                         /* modify the command trb to NO OP command */
1281                         cmd_trb->generic.field[0] = 0;
1282                         cmd_trb->generic.field[1] = 0;
1283                         cmd_trb->generic.field[2] = 0;
1284                         cmd_trb->generic.field[3] = cpu_to_le32(
1285                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1286                         break;
1287                 }
1288         }
1289 }
1290
1291 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1292 {
1293         struct xhci_cd *cur_cd, *next_cd;
1294
1295         if (list_empty(&xhci->cancel_cmd_list))
1296                 return;
1297
1298         list_for_each_entry_safe(cur_cd, next_cd,
1299                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1300                 xhci_cmd_to_noop(xhci, cur_cd);
1301                 list_del(&cur_cd->cancel_cmd_list);
1302                 kfree(cur_cd);
1303         }
1304 }
1305
1306 /*
1307  * traversing the cancel_cmd_list. If the command descriptor according
1308  * to cmd_trb is found, the function free it and return 1, otherwise
1309  * return 0.
1310  */
1311 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1312                 union xhci_trb *cmd_trb)
1313 {
1314         struct xhci_cd *cur_cd, *next_cd;
1315
1316         if (list_empty(&xhci->cancel_cmd_list))
1317                 return 0;
1318
1319         list_for_each_entry_safe(cur_cd, next_cd,
1320                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1321                 if (cur_cd->cmd_trb == cmd_trb) {
1322                         if (cur_cd->command)
1323                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1324                                         cur_cd->command, COMP_CMD_STOP);
1325                         list_del(&cur_cd->cancel_cmd_list);
1326                         kfree(cur_cd);
1327                         return 1;
1328                 }
1329         }
1330
1331         return 0;
1332 }
1333
1334 /*
1335  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1336  * trb pointed by the command ring dequeue pointer is the trb we want to
1337  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1338  * traverse the cancel_cmd_list to trun the all of the commands according
1339  * to command descriptor to NO-OP trb.
1340  */
1341 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1342                 int cmd_trb_comp_code)
1343 {
1344         int cur_trb_is_good = 0;
1345
1346         /* Searching the cmd trb pointed by the command ring dequeue
1347          * pointer in command descriptor list. If it is found, free it.
1348          */
1349         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1350                         xhci->cmd_ring->dequeue);
1351
1352         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1353                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1354         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1355                 /* traversing the cancel_cmd_list and canceling
1356                  * the command according to command descriptor
1357                  */
1358                 xhci_cancel_cmd_in_cd_list(xhci);
1359
1360                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1361                 /*
1362                  * ring command ring doorbell again to restart the
1363                  * command ring
1364                  */
1365                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1366                         xhci_ring_cmd_db(xhci);
1367         }
1368         return cur_trb_is_good;
1369 }
1370
1371 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1372                 u32 cmd_comp_code)
1373 {
1374         if (cmd_comp_code == COMP_SUCCESS)
1375                 xhci->slot_id = slot_id;
1376         else
1377                 xhci->slot_id = 0;
1378         complete(&xhci->addr_dev);
1379 }
1380
1381 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1382 {
1383         struct xhci_virt_device *virt_dev;
1384
1385         virt_dev = xhci->devs[slot_id];
1386         if (!virt_dev)
1387                 return;
1388         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1389                 /* Delete default control endpoint resources */
1390                 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1391         xhci_free_virt_device(xhci, slot_id);
1392 }
1393
1394 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1395                 struct xhci_event_cmd *event, u32 cmd_comp_code)
1396 {
1397         struct xhci_virt_device *virt_dev;
1398         struct xhci_input_control_ctx *ctrl_ctx;
1399         unsigned int ep_index;
1400         unsigned int ep_state;
1401         u32 add_flags, drop_flags;
1402
1403         virt_dev = xhci->devs[slot_id];
1404         if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1405                 return;
1406         /*
1407          * Configure endpoint commands can come from the USB core
1408          * configuration or alt setting changes, or because the HW
1409          * needed an extra configure endpoint command after a reset
1410          * endpoint command or streams were being configured.
1411          * If the command was for a halted endpoint, the xHCI driver
1412          * is not waiting on the configure endpoint command.
1413          */
1414         ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1415         if (!ctrl_ctx) {
1416                 xhci_warn(xhci, "Could not get input context, bad type.\n");
1417                 return;
1418         }
1419
1420         add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1421         drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1422         /* Input ctx add_flags are the endpoint index plus one */
1423         ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1424
1425         /* A usb_set_interface() call directly after clearing a halted
1426          * condition may race on this quirky hardware.  Not worth
1427          * worrying about, since this is prototype hardware.  Not sure
1428          * if this will work for streams, but streams support was
1429          * untested on this prototype.
1430          */
1431         if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1432                         ep_index != (unsigned int) -1 &&
1433                         add_flags - SLOT_FLAG == drop_flags) {
1434                 ep_state = virt_dev->eps[ep_index].ep_state;
1435                 if (!(ep_state & EP_HALTED))
1436                         goto bandwidth_change;
1437                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1438                                 "Completed config ep cmd - "
1439                                 "last ep index = %d, state = %d",
1440                                 ep_index, ep_state);
1441                 /* Clear internal halted state and restart ring(s) */
1442                 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1443                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1444                 return;
1445         }
1446 bandwidth_change:
1447         xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1448                         "Completed config ep cmd");
1449         virt_dev->cmd_status = cmd_comp_code;
1450         complete(&virt_dev->cmd_completion);
1451         return;
1452 }
1453
1454 static void xhci_handle_cmd_eval_ctx(struct xhci_hcd *xhci, int slot_id,
1455                 struct xhci_event_cmd *event, u32 cmd_comp_code)
1456 {
1457         struct xhci_virt_device *virt_dev;
1458
1459         virt_dev = xhci->devs[slot_id];
1460         if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1461                 return;
1462         virt_dev->cmd_status = cmd_comp_code;
1463         complete(&virt_dev->cmd_completion);
1464 }
1465
1466 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id,
1467                 u32 cmd_comp_code)
1468 {
1469         xhci->devs[slot_id]->cmd_status = cmd_comp_code;
1470         complete(&xhci->addr_dev);
1471 }
1472
1473 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1474                 struct xhci_event_cmd *event)
1475 {
1476         struct xhci_virt_device *virt_dev;
1477
1478         xhci_dbg(xhci, "Completed reset device command.\n");
1479         virt_dev = xhci->devs[slot_id];
1480         if (virt_dev)
1481                 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1482         else
1483                 xhci_warn(xhci, "Reset device command completion "
1484                                 "for disabled slot %u\n", slot_id);
1485 }
1486
1487 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1488                 struct xhci_event_cmd *event)
1489 {
1490         if (!(xhci->quirks & XHCI_NEC_HOST)) {
1491                 xhci->error_bitmask |= 1 << 6;
1492                 return;
1493         }
1494         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1495                         "NEC firmware version %2x.%02x",
1496                         NEC_FW_MAJOR(le32_to_cpu(event->status)),
1497                         NEC_FW_MINOR(le32_to_cpu(event->status)));
1498 }
1499
1500 static void handle_cmd_completion(struct xhci_hcd *xhci,
1501                 struct xhci_event_cmd *event)
1502 {
1503         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1504         u64 cmd_dma;
1505         dma_addr_t cmd_dequeue_dma;
1506         u32 cmd_comp_code;
1507         union xhci_trb *cmd_trb;
1508         u32 cmd_type;
1509
1510         cmd_dma = le64_to_cpu(event->cmd_trb);
1511         cmd_trb = xhci->cmd_ring->dequeue;
1512         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1513                         cmd_trb);
1514         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1515         if (cmd_dequeue_dma == 0) {
1516                 xhci->error_bitmask |= 1 << 4;
1517                 return;
1518         }
1519         /* Does the DMA address match our internal dequeue pointer address? */
1520         if (cmd_dma != (u64) cmd_dequeue_dma) {
1521                 xhci->error_bitmask |= 1 << 5;
1522                 return;
1523         }
1524
1525         trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1526
1527         cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1528         if (cmd_comp_code == COMP_CMD_ABORT || cmd_comp_code == COMP_CMD_STOP) {
1529                 /* If the return value is 0, we think the trb pointed by
1530                  * command ring dequeue pointer is a good trb. The good
1531                  * trb means we don't want to cancel the trb, but it have
1532                  * been stopped by host. So we should handle it normally.
1533                  * Otherwise, driver should invoke inc_deq() and return.
1534                  */
1535                 if (handle_stopped_cmd_ring(xhci, cmd_comp_code)) {
1536                         inc_deq(xhci, xhci->cmd_ring);
1537                         return;
1538                 }
1539                 /* There is no command to handle if we get a stop event when the
1540                  * command ring is empty, event->cmd_trb points to the next
1541                  * unset command
1542                  */
1543                 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1544                         return;
1545         }
1546
1547         cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1548         switch (cmd_type) {
1549         case TRB_ENABLE_SLOT:
1550                 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1551                 break;
1552         case TRB_DISABLE_SLOT:
1553                 xhci_handle_cmd_disable_slot(xhci, slot_id);
1554                 break;
1555         case TRB_CONFIG_EP:
1556                 xhci_handle_cmd_config_ep(xhci, slot_id, event, cmd_comp_code);
1557                 break;
1558         case TRB_EVAL_CONTEXT:
1559                 xhci_handle_cmd_eval_ctx(xhci, slot_id, event, cmd_comp_code);
1560                 break;
1561         case TRB_ADDR_DEV:
1562                 xhci_handle_cmd_addr_dev(xhci, slot_id, cmd_comp_code);
1563                 break;
1564         case TRB_STOP_RING:
1565                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1566                                 le32_to_cpu(cmd_trb->generic.field[3])));
1567                 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1568                 break;
1569         case TRB_SET_DEQ:
1570                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1571                                 le32_to_cpu(cmd_trb->generic.field[3])));
1572                 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1573                 break;
1574         case TRB_CMD_NOOP:
1575                 break;
1576         case TRB_RESET_EP:
1577                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1578                                 le32_to_cpu(cmd_trb->generic.field[3])));
1579                 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1580                 break;
1581         case TRB_RESET_DEV:
1582                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1583                                 le32_to_cpu(cmd_trb->generic.field[3])));
1584                 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1585                 break;
1586         case TRB_NEC_GET_FW:
1587                 xhci_handle_cmd_nec_get_fw(xhci, event);
1588                 break;
1589         default:
1590                 /* Skip over unknown commands on the event ring */
1591                 xhci->error_bitmask |= 1 << 6;
1592                 break;
1593         }
1594         inc_deq(xhci, xhci->cmd_ring);
1595 }
1596
1597 static void handle_vendor_event(struct xhci_hcd *xhci,
1598                 union xhci_trb *event)
1599 {
1600         u32 trb_type;
1601
1602         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1603         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1604         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1605                 handle_cmd_completion(xhci, &event->event_cmd);
1606 }
1607
1608 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1609  * port registers -- USB 3.0 and USB 2.0).
1610  *
1611  * Returns a zero-based port number, which is suitable for indexing into each of
1612  * the split roothubs' port arrays and bus state arrays.
1613  * Add one to it in order to call xhci_find_slot_id_by_port.
1614  */
1615 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1616                 struct xhci_hcd *xhci, u32 port_id)
1617 {
1618         unsigned int i;
1619         unsigned int num_similar_speed_ports = 0;
1620
1621         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1622          * and usb2_ports are 0-based indexes.  Count the number of similar
1623          * speed ports, up to 1 port before this port.
1624          */
1625         for (i = 0; i < (port_id - 1); i++) {
1626                 u8 port_speed = xhci->port_array[i];
1627
1628                 /*
1629                  * Skip ports that don't have known speeds, or have duplicate
1630                  * Extended Capabilities port speed entries.
1631                  */
1632                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1633                         continue;
1634
1635                 /*
1636                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1637                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1638                  * matches the device speed, it's a similar speed port.
1639                  */
1640                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1641                         num_similar_speed_ports++;
1642         }
1643         return num_similar_speed_ports;
1644 }
1645
1646 static void handle_device_notification(struct xhci_hcd *xhci,
1647                 union xhci_trb *event)
1648 {
1649         u32 slot_id;
1650         struct usb_device *udev;
1651
1652         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1653         if (!xhci->devs[slot_id]) {
1654                 xhci_warn(xhci, "Device Notification event for "
1655                                 "unused slot %u\n", slot_id);
1656                 return;
1657         }
1658
1659         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1660                         slot_id);
1661         udev = xhci->devs[slot_id]->udev;
1662         if (udev && udev->parent)
1663                 usb_wakeup_notification(udev->parent, udev->portnum);
1664 }
1665
1666 static void handle_port_status(struct xhci_hcd *xhci,
1667                 union xhci_trb *event)
1668 {
1669         struct usb_hcd *hcd;
1670         u32 port_id;
1671         u32 temp, temp1;
1672         int max_ports;
1673         int slot_id;
1674         unsigned int faked_port_index;
1675         u8 major_revision;
1676         struct xhci_bus_state *bus_state;
1677         __le32 __iomem **port_array;
1678         bool bogus_port_status = false;
1679
1680         /* Port status change events always have a successful completion code */
1681         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1682                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1683                 xhci->error_bitmask |= 1 << 8;
1684         }
1685         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1686         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1687
1688         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1689         if ((port_id <= 0) || (port_id > max_ports)) {
1690                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1691                 inc_deq(xhci, xhci->event_ring);
1692                 return;
1693         }
1694
1695         /* Figure out which usb_hcd this port is attached to:
1696          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1697          */
1698         major_revision = xhci->port_array[port_id - 1];
1699
1700         /* Find the right roothub. */
1701         hcd = xhci_to_hcd(xhci);
1702         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1703                 hcd = xhci->shared_hcd;
1704
1705         if (major_revision == 0) {
1706                 xhci_warn(xhci, "Event for port %u not in "
1707                                 "Extended Capabilities, ignoring.\n",
1708                                 port_id);
1709                 bogus_port_status = true;
1710                 goto cleanup;
1711         }
1712         if (major_revision == DUPLICATE_ENTRY) {
1713                 xhci_warn(xhci, "Event for port %u duplicated in"
1714                                 "Extended Capabilities, ignoring.\n",
1715                                 port_id);
1716                 bogus_port_status = true;
1717                 goto cleanup;
1718         }
1719
1720         /*
1721          * Hardware port IDs reported by a Port Status Change Event include USB
1722          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1723          * resume event, but we first need to translate the hardware port ID
1724          * into the index into the ports on the correct split roothub, and the
1725          * correct bus_state structure.
1726          */
1727         bus_state = &xhci->bus_state[hcd_index(hcd)];
1728         if (hcd->speed == HCD_USB3)
1729                 port_array = xhci->usb3_ports;
1730         else
1731                 port_array = xhci->usb2_ports;
1732         /* Find the faked port hub number */
1733         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1734                         port_id);
1735
1736         temp = readl(port_array[faked_port_index]);
1737         if (hcd->state == HC_STATE_SUSPENDED) {
1738                 xhci_dbg(xhci, "resume root hub\n");
1739                 usb_hcd_resume_root_hub(hcd);
1740         }
1741
1742         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1743                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1744
1745                 temp1 = readl(&xhci->op_regs->command);
1746                 if (!(temp1 & CMD_RUN)) {
1747                         xhci_warn(xhci, "xHC is not running.\n");
1748                         goto cleanup;
1749                 }
1750
1751                 if (DEV_SUPERSPEED(temp)) {
1752                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1753                         /* Set a flag to say the port signaled remote wakeup,
1754                          * so we can tell the difference between the end of
1755                          * device and host initiated resume.
1756                          */
1757                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1758                         xhci_test_and_clear_bit(xhci, port_array,
1759                                         faked_port_index, PORT_PLC);
1760                         xhci_set_link_state(xhci, port_array, faked_port_index,
1761                                                 XDEV_U0);
1762                         /* Need to wait until the next link state change
1763                          * indicates the device is actually in U0.
1764                          */
1765                         bogus_port_status = true;
1766                         goto cleanup;
1767                 } else {
1768                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1769                         bus_state->resume_done[faked_port_index] = jiffies +
1770                                 msecs_to_jiffies(20);
1771                         set_bit(faked_port_index, &bus_state->resuming_ports);
1772                         mod_timer(&hcd->rh_timer,
1773                                   bus_state->resume_done[faked_port_index]);
1774                         /* Do the rest in GetPortStatus */
1775                 }
1776         }
1777
1778         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1779                         DEV_SUPERSPEED(temp)) {
1780                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1781                 /* We've just brought the device into U0 through either the
1782                  * Resume state after a device remote wakeup, or through the
1783                  * U3Exit state after a host-initiated resume.  If it's a device
1784                  * initiated remote wake, don't pass up the link state change,
1785                  * so the roothub behavior is consistent with external
1786                  * USB 3.0 hub behavior.
1787                  */
1788                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1789                                 faked_port_index + 1);
1790                 if (slot_id && xhci->devs[slot_id])
1791                         xhci_ring_device(xhci, slot_id);
1792                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1793                         bus_state->port_remote_wakeup &=
1794                                 ~(1 << faked_port_index);
1795                         xhci_test_and_clear_bit(xhci, port_array,
1796                                         faked_port_index, PORT_PLC);
1797                         usb_wakeup_notification(hcd->self.root_hub,
1798                                         faked_port_index + 1);
1799                         bogus_port_status = true;
1800                         goto cleanup;
1801                 }
1802         }
1803
1804         /*
1805          * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1806          * RExit to a disconnect state).  If so, let the the driver know it's
1807          * out of the RExit state.
1808          */
1809         if (!DEV_SUPERSPEED(temp) &&
1810                         test_and_clear_bit(faked_port_index,
1811                                 &bus_state->rexit_ports)) {
1812                 complete(&bus_state->rexit_done[faked_port_index]);
1813                 bogus_port_status = true;
1814                 goto cleanup;
1815         }
1816
1817         if (hcd->speed != HCD_USB3)
1818                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1819                                         PORT_PLC);
1820
1821 cleanup:
1822         /* Update event ring dequeue pointer before dropping the lock */
1823         inc_deq(xhci, xhci->event_ring);
1824
1825         /* Don't make the USB core poll the roothub if we got a bad port status
1826          * change event.  Besides, at that point we can't tell which roothub
1827          * (USB 2.0 or USB 3.0) to kick.
1828          */
1829         if (bogus_port_status)
1830                 return;
1831
1832         /*
1833          * xHCI port-status-change events occur when the "or" of all the
1834          * status-change bits in the portsc register changes from 0 to 1.
1835          * New status changes won't cause an event if any other change
1836          * bits are still set.  When an event occurs, switch over to
1837          * polling to avoid losing status changes.
1838          */
1839         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1840         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1841         spin_unlock(&xhci->lock);
1842         /* Pass this up to the core */
1843         usb_hcd_poll_rh_status(hcd);
1844         spin_lock(&xhci->lock);
1845 }
1846
1847 /*
1848  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1849  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1850  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1851  * returns 0.
1852  */
1853 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1854                 union xhci_trb  *start_trb,
1855                 union xhci_trb  *end_trb,
1856                 dma_addr_t      suspect_dma)
1857 {
1858         dma_addr_t start_dma;
1859         dma_addr_t end_seg_dma;
1860         dma_addr_t end_trb_dma;
1861         struct xhci_segment *cur_seg;
1862
1863         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1864         cur_seg = start_seg;
1865
1866         do {
1867                 if (start_dma == 0)
1868                         return NULL;
1869                 /* We may get an event for a Link TRB in the middle of a TD */
1870                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1871                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1872                 /* If the end TRB isn't in this segment, this is set to 0 */
1873                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1874
1875                 if (end_trb_dma > 0) {
1876                         /* The end TRB is in this segment, so suspect should be here */
1877                         if (start_dma <= end_trb_dma) {
1878                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1879                                         return cur_seg;
1880                         } else {
1881                                 /* Case for one segment with
1882                                  * a TD wrapped around to the top
1883                                  */
1884                                 if ((suspect_dma >= start_dma &&
1885                                                         suspect_dma <= end_seg_dma) ||
1886                                                 (suspect_dma >= cur_seg->dma &&
1887                                                  suspect_dma <= end_trb_dma))
1888                                         return cur_seg;
1889                         }
1890                         return NULL;
1891                 } else {
1892                         /* Might still be somewhere in this segment */
1893                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1894                                 return cur_seg;
1895                 }
1896                 cur_seg = cur_seg->next;
1897                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1898         } while (cur_seg != start_seg);
1899
1900         return NULL;
1901 }
1902
1903 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1904                 unsigned int slot_id, unsigned int ep_index,
1905                 unsigned int stream_id,
1906                 struct xhci_td *td, union xhci_trb *event_trb)
1907 {
1908         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1909         ep->ep_state |= EP_HALTED;
1910         ep->stopped_td = td;
1911         ep->stopped_trb = event_trb;
1912         ep->stopped_stream = stream_id;
1913
1914         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1915         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1916
1917         ep->stopped_td = NULL;
1918         ep->stopped_trb = NULL;
1919         ep->stopped_stream = 0;
1920
1921         xhci_ring_cmd_db(xhci);
1922 }
1923
1924 /* Check if an error has halted the endpoint ring.  The class driver will
1925  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1926  * However, a babble and other errors also halt the endpoint ring, and the class
1927  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1928  * Ring Dequeue Pointer command manually.
1929  */
1930 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1931                 struct xhci_ep_ctx *ep_ctx,
1932                 unsigned int trb_comp_code)
1933 {
1934         /* TRB completion codes that may require a manual halt cleanup */
1935         if (trb_comp_code == COMP_TX_ERR ||
1936                         trb_comp_code == COMP_BABBLE ||
1937                         trb_comp_code == COMP_SPLIT_ERR)
1938                 /* The 0.96 spec says a babbling control endpoint
1939                  * is not halted. The 0.96 spec says it is.  Some HW
1940                  * claims to be 0.95 compliant, but it halts the control
1941                  * endpoint anyway.  Check if a babble halted the
1942                  * endpoint.
1943                  */
1944                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1945                     cpu_to_le32(EP_STATE_HALTED))
1946                         return 1;
1947
1948         return 0;
1949 }
1950
1951 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1952 {
1953         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1954                 /* Vendor defined "informational" completion code,
1955                  * treat as not-an-error.
1956                  */
1957                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1958                                 trb_comp_code);
1959                 xhci_dbg(xhci, "Treating code as success.\n");
1960                 return 1;
1961         }
1962         return 0;
1963 }
1964
1965 /*
1966  * Finish the td processing, remove the td from td list;
1967  * Return 1 if the urb can be given back.
1968  */
1969 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1970         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1971         struct xhci_virt_ep *ep, int *status, bool skip)
1972 {
1973         struct xhci_virt_device *xdev;
1974         struct xhci_ring *ep_ring;
1975         unsigned int slot_id;
1976         int ep_index;
1977         struct urb *urb = NULL;
1978         struct xhci_ep_ctx *ep_ctx;
1979         int ret = 0;
1980         struct urb_priv *urb_priv;
1981         u32 trb_comp_code;
1982
1983         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1984         xdev = xhci->devs[slot_id];
1985         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1986         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1987         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1988         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1989
1990         if (skip)
1991                 goto td_cleanup;
1992
1993         if (trb_comp_code == COMP_STOP_INVAL ||
1994                         trb_comp_code == COMP_STOP) {
1995                 /* The Endpoint Stop Command completion will take care of any
1996                  * stopped TDs.  A stopped TD may be restarted, so don't update
1997                  * the ring dequeue pointer or take this TD off any lists yet.
1998                  */
1999                 ep->stopped_td = td;
2000                 ep->stopped_trb = event_trb;
2001                 return 0;
2002         } else {
2003                 if (trb_comp_code == COMP_STALL) {
2004                         /* The transfer is completed from the driver's
2005                          * perspective, but we need to issue a set dequeue
2006                          * command for this stalled endpoint to move the dequeue
2007                          * pointer past the TD.  We can't do that here because
2008                          * the halt condition must be cleared first.  Let the
2009                          * USB class driver clear the stall later.
2010                          */
2011                         ep->stopped_td = td;
2012                         ep->stopped_trb = event_trb;
2013                         ep->stopped_stream = ep_ring->stream_id;
2014                 } else if (xhci_requires_manual_halt_cleanup(xhci,
2015                                         ep_ctx, trb_comp_code)) {
2016                         /* Other types of errors halt the endpoint, but the
2017                          * class driver doesn't call usb_reset_endpoint() unless
2018                          * the error is -EPIPE.  Clear the halted status in the
2019                          * xHCI hardware manually.
2020                          */
2021                         xhci_cleanup_halted_endpoint(xhci,
2022                                         slot_id, ep_index, ep_ring->stream_id,
2023                                         td, event_trb);
2024                 } else {
2025                         /* Update ring dequeue pointer */
2026                         while (ep_ring->dequeue != td->last_trb)
2027                                 inc_deq(xhci, ep_ring);
2028                         inc_deq(xhci, ep_ring);
2029                 }
2030
2031 td_cleanup:
2032                 /* Clean up the endpoint's TD list */
2033                 urb = td->urb;
2034                 urb_priv = urb->hcpriv;
2035
2036                 /* Do one last check of the actual transfer length.
2037                  * If the host controller said we transferred more data than
2038                  * the buffer length, urb->actual_length will be a very big
2039                  * number (since it's unsigned).  Play it safe and say we didn't
2040                  * transfer anything.
2041                  */
2042                 if (urb->actual_length > urb->transfer_buffer_length) {
2043                         xhci_warn(xhci, "URB transfer length is wrong, "
2044                                         "xHC issue? req. len = %u, "
2045                                         "act. len = %u\n",
2046                                         urb->transfer_buffer_length,
2047                                         urb->actual_length);
2048                         urb->actual_length = 0;
2049                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2050                                 *status = -EREMOTEIO;
2051                         else
2052                                 *status = 0;
2053                 }
2054                 list_del_init(&td->td_list);
2055                 /* Was this TD slated to be cancelled but completed anyway? */
2056                 if (!list_empty(&td->cancelled_td_list))
2057                         list_del_init(&td->cancelled_td_list);
2058
2059                 urb_priv->td_cnt++;
2060                 /* Giveback the urb when all the tds are completed */
2061                 if (urb_priv->td_cnt == urb_priv->length) {
2062                         ret = 1;
2063                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2064                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
2065                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
2066                                         == 0) {
2067                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
2068                                                 usb_amd_quirk_pll_enable();
2069                                 }
2070                         }
2071                 }
2072         }
2073
2074         return ret;
2075 }
2076
2077 /*
2078  * Process control tds, update urb status and actual_length.
2079  */
2080 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2081         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2082         struct xhci_virt_ep *ep, int *status)
2083 {
2084         struct xhci_virt_device *xdev;
2085         struct xhci_ring *ep_ring;
2086         unsigned int slot_id;
2087         int ep_index;
2088         struct xhci_ep_ctx *ep_ctx;
2089         u32 trb_comp_code;
2090
2091         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2092         xdev = xhci->devs[slot_id];
2093         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2094         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2095         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2096         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2097
2098         switch (trb_comp_code) {
2099         case COMP_SUCCESS:
2100                 if (event_trb == ep_ring->dequeue) {
2101                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2102                                         "without IOC set??\n");
2103                         *status = -ESHUTDOWN;
2104                 } else if (event_trb != td->last_trb) {
2105                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2106                                         "without IOC set??\n");
2107                         *status = -ESHUTDOWN;
2108                 } else {
2109                         *status = 0;
2110                 }
2111                 break;
2112         case COMP_SHORT_TX:
2113                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2114                         *status = -EREMOTEIO;
2115                 else
2116                         *status = 0;
2117                 break;
2118         case COMP_STOP_INVAL:
2119         case COMP_STOP:
2120                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2121         default:
2122                 if (!xhci_requires_manual_halt_cleanup(xhci,
2123                                         ep_ctx, trb_comp_code))
2124                         break;
2125                 xhci_dbg(xhci, "TRB error code %u, "
2126                                 "halted endpoint index = %u\n",
2127                                 trb_comp_code, ep_index);
2128                 /* else fall through */
2129         case COMP_STALL:
2130                 /* Did we transfer part of the data (middle) phase? */
2131                 if (event_trb != ep_ring->dequeue &&
2132                                 event_trb != td->last_trb)
2133                         td->urb->actual_length =
2134                                 td->urb->transfer_buffer_length -
2135                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2136                 else
2137                         td->urb->actual_length = 0;
2138
2139                 xhci_cleanup_halted_endpoint(xhci,
2140                         slot_id, ep_index, 0, td, event_trb);
2141                 return finish_td(xhci, td, event_trb, event, ep, status, true);
2142         }
2143         /*
2144          * Did we transfer any data, despite the errors that might have
2145          * happened?  I.e. did we get past the setup stage?
2146          */
2147         if (event_trb != ep_ring->dequeue) {
2148                 /* The event was for the status stage */
2149                 if (event_trb == td->last_trb) {
2150                         if (td->urb->actual_length != 0) {
2151                                 /* Don't overwrite a previously set error code
2152                                  */
2153                                 if ((*status == -EINPROGRESS || *status == 0) &&
2154                                                 (td->urb->transfer_flags
2155                                                  & URB_SHORT_NOT_OK))
2156                                         /* Did we already see a short data
2157                                          * stage? */
2158                                         *status = -EREMOTEIO;
2159                         } else {
2160                                 td->urb->actual_length =
2161                                         td->urb->transfer_buffer_length;
2162                         }
2163                 } else {
2164                 /* Maybe the event was for the data stage? */
2165                         td->urb->actual_length =
2166                                 td->urb->transfer_buffer_length -
2167                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2168                         xhci_dbg(xhci, "Waiting for status "
2169                                         "stage event\n");
2170                         return 0;
2171                 }
2172         }
2173
2174         return finish_td(xhci, td, event_trb, event, ep, status, false);
2175 }
2176
2177 /*
2178  * Process isochronous tds, update urb packet status and actual_length.
2179  */
2180 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2181         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2182         struct xhci_virt_ep *ep, int *status)
2183 {
2184         struct xhci_ring *ep_ring;
2185         struct urb_priv *urb_priv;
2186         int idx;
2187         int len = 0;
2188         union xhci_trb *cur_trb;
2189         struct xhci_segment *cur_seg;
2190         struct usb_iso_packet_descriptor *frame;
2191         u32 trb_comp_code;
2192         bool skip_td = false;
2193
2194         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2195         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2196         urb_priv = td->urb->hcpriv;
2197         idx = urb_priv->td_cnt;
2198         frame = &td->urb->iso_frame_desc[idx];
2199
2200         /* handle completion code */
2201         switch (trb_comp_code) {
2202         case COMP_SUCCESS:
2203                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2204                         frame->status = 0;
2205                         break;
2206                 }
2207                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2208                         trb_comp_code = COMP_SHORT_TX;
2209         case COMP_SHORT_TX:
2210                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2211                                 -EREMOTEIO : 0;
2212                 break;
2213         case COMP_BW_OVER:
2214                 frame->status = -ECOMM;
2215                 skip_td = true;
2216                 break;
2217         case COMP_BUFF_OVER:
2218         case COMP_BABBLE:
2219                 frame->status = -EOVERFLOW;
2220                 skip_td = true;
2221                 break;
2222         case COMP_DEV_ERR:
2223         case COMP_STALL:
2224         case COMP_TX_ERR:
2225                 frame->status = -EPROTO;
2226                 skip_td = true;
2227                 break;
2228         case COMP_STOP:
2229         case COMP_STOP_INVAL:
2230                 break;
2231         default:
2232                 frame->status = -1;
2233                 break;
2234         }
2235
2236         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2237                 frame->actual_length = frame->length;
2238                 td->urb->actual_length += frame->length;
2239         } else {
2240                 for (cur_trb = ep_ring->dequeue,
2241                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2242                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2243                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2244                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2245                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2246                 }
2247                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2248                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2249
2250                 if (trb_comp_code != COMP_STOP_INVAL) {
2251                         frame->actual_length = len;
2252                         td->urb->actual_length += len;
2253                 }
2254         }
2255
2256         return finish_td(xhci, td, event_trb, event, ep, status, false);
2257 }
2258
2259 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2260                         struct xhci_transfer_event *event,
2261                         struct xhci_virt_ep *ep, int *status)
2262 {
2263         struct xhci_ring *ep_ring;
2264         struct urb_priv *urb_priv;
2265         struct usb_iso_packet_descriptor *frame;
2266         int idx;
2267
2268         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2269         urb_priv = td->urb->hcpriv;
2270         idx = urb_priv->td_cnt;
2271         frame = &td->urb->iso_frame_desc[idx];
2272
2273         /* The transfer is partly done. */
2274         frame->status = -EXDEV;
2275
2276         /* calc actual length */
2277         frame->actual_length = 0;
2278
2279         /* Update ring dequeue pointer */
2280         while (ep_ring->dequeue != td->last_trb)
2281                 inc_deq(xhci, ep_ring);
2282         inc_deq(xhci, ep_ring);
2283
2284         return finish_td(xhci, td, NULL, event, ep, status, true);
2285 }
2286
2287 /*
2288  * Process bulk and interrupt tds, update urb status and actual_length.
2289  */
2290 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2291         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2292         struct xhci_virt_ep *ep, int *status)
2293 {
2294         struct xhci_ring *ep_ring;
2295         union xhci_trb *cur_trb;
2296         struct xhci_segment *cur_seg;
2297         u32 trb_comp_code;
2298
2299         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2300         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2301
2302         switch (trb_comp_code) {
2303         case COMP_SUCCESS:
2304                 /* Double check that the HW transferred everything. */
2305                 if (event_trb != td->last_trb ||
2306                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2307                         xhci_warn(xhci, "WARN Successful completion "
2308                                         "on short TX\n");
2309                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2310                                 *status = -EREMOTEIO;
2311                         else
2312                                 *status = 0;
2313                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2314                                 trb_comp_code = COMP_SHORT_TX;
2315                 } else {
2316                         *status = 0;
2317                 }
2318                 break;
2319         case COMP_SHORT_TX:
2320                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2321                         *status = -EREMOTEIO;
2322                 else
2323                         *status = 0;
2324                 break;
2325         default:
2326                 /* Others already handled above */
2327                 break;
2328         }
2329         if (trb_comp_code == COMP_SHORT_TX)
2330                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2331                                 "%d bytes untransferred\n",
2332                                 td->urb->ep->desc.bEndpointAddress,
2333                                 td->urb->transfer_buffer_length,
2334                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2335         /* Fast path - was this the last TRB in the TD for this URB? */
2336         if (event_trb == td->last_trb) {
2337                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2338                         td->urb->actual_length =
2339                                 td->urb->transfer_buffer_length -
2340                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2341                         if (td->urb->transfer_buffer_length <
2342                                         td->urb->actual_length) {
2343                                 xhci_warn(xhci, "HC gave bad length "
2344                                                 "of %d bytes left\n",
2345                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2346                                 td->urb->actual_length = 0;
2347                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2348                                         *status = -EREMOTEIO;
2349                                 else
2350                                         *status = 0;
2351                         }
2352                         /* Don't overwrite a previously set error code */
2353                         if (*status == -EINPROGRESS) {
2354                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2355                                         *status = -EREMOTEIO;
2356                                 else
2357                                         *status = 0;
2358                         }
2359                 } else {
2360                         td->urb->actual_length =
2361                                 td->urb->transfer_buffer_length;
2362                         /* Ignore a short packet completion if the
2363                          * untransferred length was zero.
2364                          */
2365                         if (*status == -EREMOTEIO)
2366                                 *status = 0;
2367                 }
2368         } else {
2369                 /* Slow path - walk the list, starting from the dequeue
2370                  * pointer, to get the actual length transferred.
2371                  */
2372                 td->urb->actual_length = 0;
2373                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2374                                 cur_trb != event_trb;
2375                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2376                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2377                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2378                                 td->urb->actual_length +=
2379                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2380                 }
2381                 /* If the ring didn't stop on a Link or No-op TRB, add
2382                  * in the actual bytes transferred from the Normal TRB
2383                  */
2384                 if (trb_comp_code != COMP_STOP_INVAL)
2385                         td->urb->actual_length +=
2386                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2387                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2388         }
2389
2390         return finish_td(xhci, td, event_trb, event, ep, status, false);
2391 }
2392
2393 /*
2394  * If this function returns an error condition, it means it got a Transfer
2395  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2396  * At this point, the host controller is probably hosed and should be reset.
2397  */
2398 static int handle_tx_event(struct xhci_hcd *xhci,
2399                 struct xhci_transfer_event *event)
2400         __releases(&xhci->lock)
2401         __acquires(&xhci->lock)
2402 {
2403         struct xhci_virt_device *xdev;
2404         struct xhci_virt_ep *ep;
2405         struct xhci_ring *ep_ring;
2406         unsigned int slot_id;
2407         int ep_index;
2408         struct xhci_td *td = NULL;
2409         dma_addr_t event_dma;
2410         struct xhci_segment *event_seg;
2411         union xhci_trb *event_trb;
2412         struct urb *urb = NULL;
2413         int status = -EINPROGRESS;
2414         struct urb_priv *urb_priv;
2415         struct xhci_ep_ctx *ep_ctx;
2416         struct list_head *tmp;
2417         u32 trb_comp_code;
2418         int ret = 0;
2419         int td_num = 0;
2420
2421         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2422         xdev = xhci->devs[slot_id];
2423         if (!xdev) {
2424                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2425                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2426                          (unsigned long long) xhci_trb_virt_to_dma(
2427                                  xhci->event_ring->deq_seg,
2428                                  xhci->event_ring->dequeue),
2429                          lower_32_bits(le64_to_cpu(event->buffer)),
2430                          upper_32_bits(le64_to_cpu(event->buffer)),
2431                          le32_to_cpu(event->transfer_len),
2432                          le32_to_cpu(event->flags));
2433                 xhci_dbg(xhci, "Event ring:\n");
2434                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2435                 return -ENODEV;
2436         }
2437
2438         /* Endpoint ID is 1 based, our index is zero based */
2439         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2440         ep = &xdev->eps[ep_index];
2441         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2442         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2443         if (!ep_ring ||
2444             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2445             EP_STATE_DISABLED) {
2446                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2447                                 "or incorrect stream ring\n");
2448                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2449                          (unsigned long long) xhci_trb_virt_to_dma(
2450                                  xhci->event_ring->deq_seg,
2451                                  xhci->event_ring->dequeue),
2452                          lower_32_bits(le64_to_cpu(event->buffer)),
2453                          upper_32_bits(le64_to_cpu(event->buffer)),
2454                          le32_to_cpu(event->transfer_len),
2455                          le32_to_cpu(event->flags));
2456                 xhci_dbg(xhci, "Event ring:\n");
2457                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2458                 return -ENODEV;
2459         }
2460
2461         /* Count current td numbers if ep->skip is set */
2462         if (ep->skip) {
2463                 list_for_each(tmp, &ep_ring->td_list)
2464                         td_num++;
2465         }
2466
2467         event_dma = le64_to_cpu(event->buffer);
2468         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2469         /* Look for common error cases */
2470         switch (trb_comp_code) {
2471         /* Skip codes that require special handling depending on
2472          * transfer type
2473          */
2474         case COMP_SUCCESS:
2475                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2476                         break;
2477                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2478                         trb_comp_code = COMP_SHORT_TX;
2479                 else
2480                         xhci_warn_ratelimited(xhci,
2481                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2482         case COMP_SHORT_TX:
2483                 break;
2484         case COMP_STOP:
2485                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2486                 break;
2487         case COMP_STOP_INVAL:
2488                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2489                 break;
2490         case COMP_STALL:
2491                 xhci_dbg(xhci, "Stalled endpoint\n");
2492                 ep->ep_state |= EP_HALTED;
2493                 status = -EPIPE;
2494                 break;
2495         case COMP_TRB_ERR:
2496                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2497                 status = -EILSEQ;
2498                 break;
2499         case COMP_SPLIT_ERR:
2500         case COMP_TX_ERR:
2501                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2502                 status = -EPROTO;
2503                 break;
2504         case COMP_BABBLE:
2505                 xhci_dbg(xhci, "Babble error on endpoint\n");
2506                 status = -EOVERFLOW;
2507                 break;
2508         case COMP_DB_ERR:
2509                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2510                 status = -ENOSR;
2511                 break;
2512         case COMP_BW_OVER:
2513                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2514                 break;
2515         case COMP_BUFF_OVER:
2516                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2517                 break;
2518         case COMP_UNDERRUN:
2519                 /*
2520                  * When the Isoch ring is empty, the xHC will generate
2521                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2522                  * Underrun Event for OUT Isoch endpoint.
2523                  */
2524                 xhci_dbg(xhci, "underrun event on endpoint\n");
2525                 if (!list_empty(&ep_ring->td_list))
2526                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2527                                         "still with TDs queued?\n",
2528                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2529                                  ep_index);
2530                 goto cleanup;
2531         case COMP_OVERRUN:
2532                 xhci_dbg(xhci, "overrun event on endpoint\n");
2533                 if (!list_empty(&ep_ring->td_list))
2534                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2535                                         "still with TDs queued?\n",
2536                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2537                                  ep_index);
2538                 goto cleanup;
2539         case COMP_DEV_ERR:
2540                 xhci_warn(xhci, "WARN: detect an incompatible device");
2541                 status = -EPROTO;
2542                 break;
2543         case COMP_MISSED_INT:
2544                 /*
2545                  * When encounter missed service error, one or more isoc tds
2546                  * may be missed by xHC.
2547                  * Set skip flag of the ep_ring; Complete the missed tds as
2548                  * short transfer when process the ep_ring next time.
2549                  */
2550                 ep->skip = true;
2551                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2552                 goto cleanup;
2553         default:
2554                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2555                         status = 0;
2556                         break;
2557                 }
2558                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2559                                 "busted\n");
2560                 goto cleanup;
2561         }
2562
2563         do {
2564                 /* This TRB should be in the TD at the head of this ring's
2565                  * TD list.
2566                  */
2567                 if (list_empty(&ep_ring->td_list)) {
2568                         /*
2569                          * A stopped endpoint may generate an extra completion
2570                          * event if the device was suspended.  Don't print
2571                          * warnings.
2572                          */
2573                         if (!(trb_comp_code == COMP_STOP ||
2574                                                 trb_comp_code == COMP_STOP_INVAL)) {
2575                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2576                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2577                                                 ep_index);
2578                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2579                                                 (le32_to_cpu(event->flags) &
2580                                                  TRB_TYPE_BITMASK)>>10);
2581                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2582                         }
2583                         if (ep->skip) {
2584                                 ep->skip = false;
2585                                 xhci_dbg(xhci, "td_list is empty while skip "
2586                                                 "flag set. Clear skip flag.\n");
2587                         }
2588                         ret = 0;
2589                         goto cleanup;
2590                 }
2591
2592                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2593                 if (ep->skip && td_num == 0) {
2594                         ep->skip = false;
2595                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2596                                                 "Clear skip flag.\n");
2597                         ret = 0;
2598                         goto cleanup;
2599                 }
2600
2601                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2602                 if (ep->skip)
2603                         td_num--;
2604
2605                 /* Is this a TRB in the currently executing TD? */
2606                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2607                                 td->last_trb, event_dma);
2608
2609                 /*
2610                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2611                  * is not in the current TD pointed by ep_ring->dequeue because
2612                  * that the hardware dequeue pointer still at the previous TRB
2613                  * of the current TD. The previous TRB maybe a Link TD or the
2614                  * last TRB of the previous TD. The command completion handle
2615                  * will take care the rest.
2616                  */
2617                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2618                         ret = 0;
2619                         goto cleanup;
2620                 }
2621
2622                 if (!event_seg) {
2623                         if (!ep->skip ||
2624                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2625                                 /* Some host controllers give a spurious
2626                                  * successful event after a short transfer.
2627                                  * Ignore it.
2628                                  */
2629                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2630                                                 ep_ring->last_td_was_short) {
2631                                         ep_ring->last_td_was_short = false;
2632                                         ret = 0;
2633                                         goto cleanup;
2634                                 }
2635                                 /* HC is busted, give up! */
2636                                 xhci_err(xhci,
2637                                         "ERROR Transfer event TRB DMA ptr not "
2638                                         "part of current TD\n");
2639                                 return -ESHUTDOWN;
2640                         }
2641
2642                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2643                         goto cleanup;
2644                 }
2645                 if (trb_comp_code == COMP_SHORT_TX)
2646                         ep_ring->last_td_was_short = true;
2647                 else
2648                         ep_ring->last_td_was_short = false;
2649
2650                 if (ep->skip) {
2651                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2652                         ep->skip = false;
2653                 }
2654
2655                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2656                                                 sizeof(*event_trb)];
2657                 /*
2658                  * No-op TRB should not trigger interrupts.
2659                  * If event_trb is a no-op TRB, it means the
2660                  * corresponding TD has been cancelled. Just ignore
2661                  * the TD.
2662                  */
2663                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2664                         xhci_dbg(xhci,
2665                                  "event_trb is a no-op TRB. Skip it\n");
2666                         goto cleanup;
2667                 }
2668
2669                 /* Now update the urb's actual_length and give back to
2670                  * the core
2671                  */
2672                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2673                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2674                                                  &status);
2675                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2676                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2677                                                  &status);
2678                 else
2679                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2680                                                  ep, &status);
2681
2682 cleanup:
2683                 /*
2684                  * Do not update event ring dequeue pointer if ep->skip is set.
2685                  * Will roll back to continue process missed tds.
2686                  */
2687                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2688                         inc_deq(xhci, xhci->event_ring);
2689                 }
2690
2691                 if (ret) {
2692                         urb = td->urb;
2693                         urb_priv = urb->hcpriv;
2694                         /* Leave the TD around for the reset endpoint function
2695                          * to use(but only if it's not a control endpoint,
2696                          * since we already queued the Set TR dequeue pointer
2697                          * command for stalled control endpoints).
2698                          */
2699                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2700                                 (trb_comp_code != COMP_STALL &&
2701                                         trb_comp_code != COMP_BABBLE))
2702                                 xhci_urb_free_priv(xhci, urb_priv);
2703                         else
2704                                 kfree(urb_priv);
2705
2706                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2707                         if ((urb->actual_length != urb->transfer_buffer_length &&
2708                                                 (urb->transfer_flags &
2709                                                  URB_SHORT_NOT_OK)) ||
2710                                         (status != 0 &&
2711                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2712                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2713                                                 "expected = %d, status = %d\n",
2714                                                 urb, urb->actual_length,
2715                                                 urb->transfer_buffer_length,
2716                                                 status);
2717                         spin_unlock(&xhci->lock);
2718                         /* EHCI, UHCI, and OHCI always unconditionally set the
2719                          * urb->status of an isochronous endpoint to 0.
2720                          */
2721                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2722                                 status = 0;
2723                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2724                         spin_lock(&xhci->lock);
2725                 }
2726
2727         /*
2728          * If ep->skip is set, it means there are missed tds on the
2729          * endpoint ring need to take care of.
2730          * Process them as short transfer until reach the td pointed by
2731          * the event.
2732          */
2733         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2734
2735         return 0;
2736 }
2737
2738 /*
2739  * This function handles all OS-owned events on the event ring.  It may drop
2740  * xhci->lock between event processing (e.g. to pass up port status changes).
2741  * Returns >0 for "possibly more events to process" (caller should call again),
2742  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2743  */
2744 static int xhci_handle_event(struct xhci_hcd *xhci)
2745 {
2746         union xhci_trb *event;
2747         int update_ptrs = 1;
2748         int ret;
2749
2750         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2751                 xhci->error_bitmask |= 1 << 1;
2752                 return 0;
2753         }
2754
2755         event = xhci->event_ring->dequeue;
2756         /* Does the HC or OS own the TRB? */
2757         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2758             xhci->event_ring->cycle_state) {
2759                 xhci->error_bitmask |= 1 << 2;
2760                 return 0;
2761         }
2762
2763         /*
2764          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2765          * speculative reads of the event's flags/data below.
2766          */
2767         rmb();
2768         /* FIXME: Handle more event types. */
2769         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2770         case TRB_TYPE(TRB_COMPLETION):
2771                 handle_cmd_completion(xhci, &event->event_cmd);
2772                 break;
2773         case TRB_TYPE(TRB_PORT_STATUS):
2774                 handle_port_status(xhci, event);
2775                 update_ptrs = 0;
2776                 break;
2777         case TRB_TYPE(TRB_TRANSFER):
2778                 ret = handle_tx_event(xhci, &event->trans_event);
2779                 if (ret < 0)
2780                         xhci->error_bitmask |= 1 << 9;
2781                 else
2782                         update_ptrs = 0;
2783                 break;
2784         case TRB_TYPE(TRB_DEV_NOTE):
2785                 handle_device_notification(xhci, event);
2786                 break;
2787         default:
2788                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2789                     TRB_TYPE(48))
2790                         handle_vendor_event(xhci, event);
2791                 else
2792                         xhci->error_bitmask |= 1 << 3;
2793         }
2794         /* Any of the above functions may drop and re-acquire the lock, so check
2795          * to make sure a watchdog timer didn't mark the host as non-responsive.
2796          */
2797         if (xhci->xhc_state & XHCI_STATE_DYING) {
2798                 xhci_dbg(xhci, "xHCI host dying, returning from "
2799                                 "event handler.\n");
2800                 return 0;
2801         }
2802
2803         if (update_ptrs)
2804                 /* Update SW event ring dequeue pointer */
2805                 inc_deq(xhci, xhci->event_ring);
2806
2807         /* Are there more items on the event ring?  Caller will call us again to
2808          * check.
2809          */
2810         return 1;
2811 }
2812
2813 /*
2814  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2815  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2816  * indicators of an event TRB error, but we check the status *first* to be safe.
2817  */
2818 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2819 {
2820         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2821         u32 status;
2822         u64 temp_64;
2823         union xhci_trb *event_ring_deq;
2824         dma_addr_t deq;
2825
2826         spin_lock(&xhci->lock);
2827         /* Check if the xHC generated the interrupt, or the irq is shared */
2828         status = readl(&xhci->op_regs->status);
2829         if (status == 0xffffffff)
2830                 goto hw_died;
2831
2832         if (!(status & STS_EINT)) {
2833                 spin_unlock(&xhci->lock);
2834                 return IRQ_NONE;
2835         }
2836         if (status & STS_FATAL) {
2837                 xhci_warn(xhci, "WARNING: Host System Error\n");
2838                 xhci_halt(xhci);
2839 hw_died:
2840                 spin_unlock(&xhci->lock);
2841                 return -ESHUTDOWN;
2842         }
2843
2844         /*
2845          * Clear the op reg interrupt status first,
2846          * so we can receive interrupts from other MSI-X interrupters.
2847          * Write 1 to clear the interrupt status.
2848          */
2849         status |= STS_EINT;
2850         writel(status, &xhci->op_regs->status);
2851         /* FIXME when MSI-X is supported and there are multiple vectors */
2852         /* Clear the MSI-X event interrupt status */
2853
2854         if (hcd->irq) {
2855                 u32 irq_pending;
2856                 /* Acknowledge the PCI interrupt */
2857                 irq_pending = readl(&xhci->ir_set->irq_pending);
2858                 irq_pending |= IMAN_IP;
2859                 writel(irq_pending, &xhci->ir_set->irq_pending);
2860         }
2861
2862         if (xhci->xhc_state & XHCI_STATE_DYING) {
2863                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2864                                 "Shouldn't IRQs be disabled?\n");
2865                 /* Clear the event handler busy flag (RW1C);
2866                  * the event ring should be empty.
2867                  */
2868                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2869                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2870                                 &xhci->ir_set->erst_dequeue);
2871                 spin_unlock(&xhci->lock);
2872
2873                 return IRQ_HANDLED;
2874         }
2875
2876         event_ring_deq = xhci->event_ring->dequeue;
2877         /* FIXME this should be a delayed service routine
2878          * that clears the EHB.
2879          */
2880         while (xhci_handle_event(xhci) > 0) {}
2881
2882         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2883         /* If necessary, update the HW's version of the event ring deq ptr. */
2884         if (event_ring_deq != xhci->event_ring->dequeue) {
2885                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2886                                 xhci->event_ring->dequeue);
2887                 if (deq == 0)
2888                         xhci_warn(xhci, "WARN something wrong with SW event "
2889                                         "ring dequeue ptr.\n");
2890                 /* Update HC event ring dequeue pointer */
2891                 temp_64 &= ERST_PTR_MASK;
2892                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2893         }
2894
2895         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2896         temp_64 |= ERST_EHB;
2897         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2898
2899         spin_unlock(&xhci->lock);
2900
2901         return IRQ_HANDLED;
2902 }
2903
2904 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2905 {
2906         return xhci_irq(hcd);
2907 }
2908
2909 /****           Endpoint Ring Operations        ****/
2910
2911 /*
2912  * Generic function for queueing a TRB on a ring.
2913  * The caller must have checked to make sure there's room on the ring.
2914  *
2915  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2916  *                      prepare_transfer()?
2917  */
2918 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2919                 bool more_trbs_coming,
2920                 u32 field1, u32 field2, u32 field3, u32 field4)
2921 {
2922         struct xhci_generic_trb *trb;
2923
2924         trb = &ring->enqueue->generic;
2925         trb->field[0] = cpu_to_le32(field1);
2926         trb->field[1] = cpu_to_le32(field2);
2927         trb->field[2] = cpu_to_le32(field3);
2928         trb->field[3] = cpu_to_le32(field4);
2929         inc_enq(xhci, ring, more_trbs_coming);
2930 }
2931
2932 /*
2933  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2934  * FIXME allocate segments if the ring is full.
2935  */
2936 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2937                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2938 {
2939         unsigned int num_trbs_needed;
2940
2941         /* Make sure the endpoint has been added to xHC schedule */
2942         switch (ep_state) {
2943         case EP_STATE_DISABLED:
2944                 /*
2945                  * USB core changed config/interfaces without notifying us,
2946                  * or hardware is reporting the wrong state.
2947                  */
2948                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2949                 return -ENOENT;
2950         case EP_STATE_ERROR:
2951                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2952                 /* FIXME event handling code for error needs to clear it */
2953                 /* XXX not sure if this should be -ENOENT or not */
2954                 return -EINVAL;
2955         case EP_STATE_HALTED:
2956                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2957         case EP_STATE_STOPPED:
2958         case EP_STATE_RUNNING:
2959                 break;
2960         default:
2961                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2962                 /*
2963                  * FIXME issue Configure Endpoint command to try to get the HC
2964                  * back into a known state.
2965                  */
2966                 return -EINVAL;
2967         }
2968
2969         while (1) {
2970                 if (room_on_ring(xhci, ep_ring, num_trbs))
2971                         break;
2972
2973                 if (ep_ring == xhci->cmd_ring) {
2974                         xhci_err(xhci, "Do not support expand command ring\n");
2975                         return -ENOMEM;
2976                 }
2977
2978                 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2979                                 "ERROR no room on ep ring, try ring expansion");
2980                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2981                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2982                                         mem_flags)) {
2983                         xhci_err(xhci, "Ring expansion failed\n");
2984                         return -ENOMEM;
2985                 }
2986         }
2987
2988         if (enqueue_is_link_trb(ep_ring)) {
2989                 struct xhci_ring *ring = ep_ring;
2990                 union xhci_trb *next;
2991
2992                 next = ring->enqueue;
2993
2994                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2995                         /* If we're not dealing with 0.95 hardware or isoc rings
2996                          * on AMD 0.96 host, clear the chain bit.
2997                          */
2998                         if (!xhci_link_trb_quirk(xhci) &&
2999                                         !(ring->type == TYPE_ISOC &&
3000                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
3001                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
3002                         else
3003                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
3004
3005                         wmb();
3006                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
3007
3008                         /* Toggle the cycle bit after the last ring segment. */
3009                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
3010                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
3011                         }
3012                         ring->enq_seg = ring->enq_seg->next;
3013                         ring->enqueue = ring->enq_seg->trbs;
3014                         next = ring->enqueue;
3015                 }
3016         }
3017
3018         return 0;
3019 }
3020
3021 static int prepare_transfer(struct xhci_hcd *xhci,
3022                 struct xhci_virt_device *xdev,
3023                 unsigned int ep_index,
3024                 unsigned int stream_id,
3025                 unsigned int num_trbs,
3026                 struct urb *urb,
3027                 unsigned int td_index,
3028                 gfp_t mem_flags)
3029 {
3030         int ret;
3031         struct urb_priv *urb_priv;
3032         struct xhci_td  *td;
3033         struct xhci_ring *ep_ring;
3034         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3035
3036         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3037         if (!ep_ring) {
3038                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3039                                 stream_id);
3040                 return -EINVAL;
3041         }
3042
3043         ret = prepare_ring(xhci, ep_ring,
3044                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3045                            num_trbs, mem_flags);
3046         if (ret)
3047                 return ret;
3048
3049         urb_priv = urb->hcpriv;
3050         td = urb_priv->td[td_index];
3051
3052         INIT_LIST_HEAD(&td->td_list);
3053         INIT_LIST_HEAD(&td->cancelled_td_list);
3054
3055         if (td_index == 0) {
3056                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3057                 if (unlikely(ret))
3058                         return ret;
3059         }
3060
3061         td->urb = urb;
3062         /* Add this TD to the tail of the endpoint ring's TD list */
3063         list_add_tail(&td->td_list, &ep_ring->td_list);
3064         td->start_seg = ep_ring->enq_seg;
3065         td->first_trb = ep_ring->enqueue;
3066
3067         urb_priv->td[td_index] = td;
3068
3069         return 0;
3070 }
3071
3072 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3073 {
3074         int num_sgs, num_trbs, running_total, temp, i;
3075         struct scatterlist *sg;
3076
3077         sg = NULL;
3078         num_sgs = urb->num_mapped_sgs;
3079         temp = urb->transfer_buffer_length;
3080
3081         num_trbs = 0;
3082         for_each_sg(urb->sg, sg, num_sgs, i) {
3083                 unsigned int len = sg_dma_len(sg);
3084
3085                 /* Scatter gather list entries may cross 64KB boundaries */
3086                 running_total = TRB_MAX_BUFF_SIZE -
3087                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3088                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3089                 if (running_total != 0)
3090                         num_trbs++;
3091
3092                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3093                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3094                         num_trbs++;
3095                         running_total += TRB_MAX_BUFF_SIZE;
3096                 }
3097                 len = min_t(int, len, temp);
3098                 temp -= len;
3099                 if (temp == 0)
3100                         break;
3101         }
3102         return num_trbs;
3103 }
3104
3105 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3106 {
3107         if (num_trbs != 0)
3108                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3109                                 "TRBs, %d left\n", __func__,
3110                                 urb->ep->desc.bEndpointAddress, num_trbs);
3111         if (running_total != urb->transfer_buffer_length)
3112                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3113                                 "queued %#x (%d), asked for %#x (%d)\n",
3114                                 __func__,
3115                                 urb->ep->desc.bEndpointAddress,
3116                                 running_total, running_total,
3117                                 urb->transfer_buffer_length,
3118                                 urb->transfer_buffer_length);
3119 }
3120
3121 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3122                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3123                 struct xhci_generic_trb *start_trb)
3124 {
3125         /*
3126          * Pass all the TRBs to the hardware at once and make sure this write
3127          * isn't reordered.
3128          */
3129         wmb();
3130         if (start_cycle)
3131                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3132         else
3133                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3134         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3135 }
3136
3137 /*
3138  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3139  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3140  * (comprised of sg list entries) can take several service intervals to
3141  * transmit.
3142  */
3143 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3144                 struct urb *urb, int slot_id, unsigned int ep_index)
3145 {
3146         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3147                         xhci->devs[slot_id]->out_ctx, ep_index);
3148         int xhci_interval;
3149         int ep_interval;
3150
3151         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3152         ep_interval = urb->interval;
3153         /* Convert to microframes */
3154         if (urb->dev->speed == USB_SPEED_LOW ||
3155                         urb->dev->speed == USB_SPEED_FULL)
3156                 ep_interval *= 8;
3157         /* FIXME change this to a warning and a suggestion to use the new API
3158          * to set the polling interval (once the API is added).
3159          */
3160         if (xhci_interval != ep_interval) {
3161                 dev_dbg_ratelimited(&urb->dev->dev,
3162                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3163                                 ep_interval, ep_interval == 1 ? "" : "s",
3164                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3165                 urb->interval = xhci_interval;
3166                 /* Convert back to frames for LS/FS devices */
3167                 if (urb->dev->speed == USB_SPEED_LOW ||
3168                                 urb->dev->speed == USB_SPEED_FULL)
3169                         urb->interval /= 8;
3170         }
3171         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3172 }
3173
3174 /*
3175  * The TD size is the number of bytes remaining in the TD (including this TRB),
3176  * right shifted by 10.
3177  * It must fit in bits 21:17, so it can't be bigger than 31.
3178  */
3179 static u32 xhci_td_remainder(unsigned int remainder)
3180 {
3181         u32 max = (1 << (21 - 17 + 1)) - 1;
3182
3183         if ((remainder >> 10) >= max)
3184                 return max << 17;
3185         else
3186                 return (remainder >> 10) << 17;
3187 }
3188
3189 /*
3190  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3191  * packets remaining in the TD (*not* including this TRB).
3192  *
3193  * Total TD packet count = total_packet_count =
3194  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3195  *
3196  * Packets transferred up to and including this TRB = packets_transferred =
3197  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3198  *
3199  * TD size = total_packet_count - packets_transferred
3200  *
3201  * It must fit in bits 21:17, so it can't be bigger than 31.
3202  * The last TRB in a TD must have the TD size set to zero.
3203  */
3204 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3205                 unsigned int total_packet_count, struct urb *urb,
3206                 unsigned int num_trbs_left)
3207 {
3208         int packets_transferred;
3209
3210         /* One TRB with a zero-length data packet. */
3211         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3212                 return 0;
3213
3214         /* All the TRB queueing functions don't count the current TRB in
3215          * running_total.
3216          */
3217         packets_transferred = (running_total + trb_buff_len) /
3218                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3219
3220         if ((total_packet_count - packets_transferred) > 31)
3221                 return 31 << 17;
3222         return (total_packet_count - packets_transferred) << 17;
3223 }
3224
3225 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3226                 struct urb *urb, int slot_id, unsigned int ep_index)
3227 {
3228         struct xhci_ring *ep_ring;
3229         unsigned int num_trbs;
3230         struct urb_priv *urb_priv;
3231         struct xhci_td *td;
3232         struct scatterlist *sg;
3233         int num_sgs;
3234         int trb_buff_len, this_sg_len, running_total;
3235         unsigned int total_packet_count;
3236         bool first_trb;
3237         u64 addr;
3238         bool more_trbs_coming;
3239
3240         struct xhci_generic_trb *start_trb;
3241         int start_cycle;
3242
3243         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3244         if (!ep_ring)
3245                 return -EINVAL;
3246
3247         num_trbs = count_sg_trbs_needed(xhci, urb);
3248         num_sgs = urb->num_mapped_sgs;
3249         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3250                         usb_endpoint_maxp(&urb->ep->desc));
3251
3252         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3253                         ep_index, urb->stream_id,
3254                         num_trbs, urb, 0, mem_flags);
3255         if (trb_buff_len < 0)
3256                 return trb_buff_len;
3257
3258         urb_priv = urb->hcpriv;
3259         td = urb_priv->td[0];
3260
3261         /*
3262          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3263          * until we've finished creating all the other TRBs.  The ring's cycle
3264          * state may change as we enqueue the other TRBs, so save it too.
3265          */
3266         start_trb = &ep_ring->enqueue->generic;
3267         start_cycle = ep_ring->cycle_state;
3268
3269         running_total = 0;
3270         /*
3271          * How much data is in the first TRB?
3272          *
3273          * There are three forces at work for TRB buffer pointers and lengths:
3274          * 1. We don't want to walk off the end of this sg-list entry buffer.
3275          * 2. The transfer length that the driver requested may be smaller than
3276          *    the amount of memory allocated for this scatter-gather list.
3277          * 3. TRBs buffers can't cross 64KB boundaries.
3278          */
3279         sg = urb->sg;
3280         addr = (u64) sg_dma_address(sg);
3281         this_sg_len = sg_dma_len(sg);
3282         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3283         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3284         if (trb_buff_len > urb->transfer_buffer_length)
3285                 trb_buff_len = urb->transfer_buffer_length;
3286
3287         first_trb = true;
3288         /* Queue the first TRB, even if it's zero-length */
3289         do {
3290                 u32 field = 0;
3291                 u32 length_field = 0;
3292                 u32 remainder = 0;
3293
3294                 /* Don't change the cycle bit of the first TRB until later */
3295                 if (first_trb) {
3296                         first_trb = false;
3297                         if (start_cycle == 0)
3298                                 field |= 0x1;
3299                 } else
3300                         field |= ep_ring->cycle_state;
3301
3302                 /* Chain all the TRBs together; clear the chain bit in the last
3303                  * TRB to indicate it's the last TRB in the chain.
3304                  */
3305                 if (num_trbs > 1) {
3306                         field |= TRB_CHAIN;
3307                 } else {
3308                         /* FIXME - add check for ZERO_PACKET flag before this */
3309                         td->last_trb = ep_ring->enqueue;
3310                         field |= TRB_IOC;
3311                 }
3312
3313                 /* Only set interrupt on short packet for IN endpoints */
3314                 if (usb_urb_dir_in(urb))
3315                         field |= TRB_ISP;
3316
3317                 if (TRB_MAX_BUFF_SIZE -
3318                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3319                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3320                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3321                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3322                                         (unsigned int) addr + trb_buff_len);
3323                 }
3324
3325                 /* Set the TRB length, TD size, and interrupter fields. */
3326                 if (xhci->hci_version < 0x100) {
3327                         remainder = xhci_td_remainder(
3328                                         urb->transfer_buffer_length -
3329                                         running_total);
3330                 } else {
3331                         remainder = xhci_v1_0_td_remainder(running_total,
3332                                         trb_buff_len, total_packet_count, urb,
3333                                         num_trbs - 1);
3334                 }
3335                 length_field = TRB_LEN(trb_buff_len) |
3336                         remainder |
3337                         TRB_INTR_TARGET(0);
3338
3339                 if (num_trbs > 1)
3340                         more_trbs_coming = true;
3341                 else
3342                         more_trbs_coming = false;
3343                 queue_trb(xhci, ep_ring, more_trbs_coming,
3344                                 lower_32_bits(addr),
3345                                 upper_32_bits(addr),
3346                                 length_field,
3347                                 field | TRB_TYPE(TRB_NORMAL));
3348                 --num_trbs;
3349                 running_total += trb_buff_len;
3350
3351                 /* Calculate length for next transfer --
3352                  * Are we done queueing all the TRBs for this sg entry?
3353                  */
3354                 this_sg_len -= trb_buff_len;
3355                 if (this_sg_len == 0) {
3356                         --num_sgs;
3357                         if (num_sgs == 0)
3358                                 break;
3359                         sg = sg_next(sg);
3360                         addr = (u64) sg_dma_address(sg);
3361                         this_sg_len = sg_dma_len(sg);
3362                 } else {
3363                         addr += trb_buff_len;
3364                 }
3365
3366                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3367                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3368                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3369                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3370                         trb_buff_len =
3371                                 urb->transfer_buffer_length - running_total;
3372         } while (running_total < urb->transfer_buffer_length);
3373
3374         check_trb_math(urb, num_trbs, running_total);
3375         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3376                         start_cycle, start_trb);
3377         return 0;
3378 }
3379
3380 /* This is very similar to what ehci-q.c qtd_fill() does */
3381 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3382                 struct urb *urb, int slot_id, unsigned int ep_index)
3383 {
3384         struct xhci_ring *ep_ring;
3385         struct urb_priv *urb_priv;
3386         struct xhci_td *td;
3387         int num_trbs;
3388         struct xhci_generic_trb *start_trb;
3389         bool first_trb;
3390         bool more_trbs_coming;
3391         int start_cycle;
3392         u32 field, length_field;
3393
3394         int running_total, trb_buff_len, ret;
3395         unsigned int total_packet_count;
3396         u64 addr;
3397
3398         if (urb->num_sgs)
3399                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3400
3401         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3402         if (!ep_ring)
3403                 return -EINVAL;
3404
3405         num_trbs = 0;
3406         /* How much data is (potentially) left before the 64KB boundary? */
3407         running_total = TRB_MAX_BUFF_SIZE -
3408                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3409         running_total &= TRB_MAX_BUFF_SIZE - 1;
3410
3411         /* If there's some data on this 64KB chunk, or we have to send a
3412          * zero-length transfer, we need at least one TRB
3413          */
3414         if (running_total != 0 || urb->transfer_buffer_length == 0)
3415                 num_trbs++;
3416         /* How many more 64KB chunks to transfer, how many more TRBs? */
3417         while (running_total < urb->transfer_buffer_length) {
3418                 num_trbs++;
3419                 running_total += TRB_MAX_BUFF_SIZE;
3420         }
3421         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3422
3423         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3424                         ep_index, urb->stream_id,
3425                         num_trbs, urb, 0, mem_flags);
3426         if (ret < 0)
3427                 return ret;
3428
3429         urb_priv = urb->hcpriv;
3430         td = urb_priv->td[0];
3431
3432         /*
3433          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3434          * until we've finished creating all the other TRBs.  The ring's cycle
3435          * state may change as we enqueue the other TRBs, so save it too.
3436          */
3437         start_trb = &ep_ring->enqueue->generic;
3438         start_cycle = ep_ring->cycle_state;
3439
3440         running_total = 0;
3441         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3442                         usb_endpoint_maxp(&urb->ep->desc));
3443         /* How much data is in the first TRB? */
3444         addr = (u64) urb->transfer_dma;
3445         trb_buff_len = TRB_MAX_BUFF_SIZE -
3446                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3447         if (trb_buff_len > urb->transfer_buffer_length)
3448                 trb_buff_len = urb->transfer_buffer_length;
3449
3450         first_trb = true;
3451
3452         /* Queue the first TRB, even if it's zero-length */
3453         do {
3454                 u32 remainder = 0;
3455                 field = 0;
3456
3457                 /* Don't change the cycle bit of the first TRB until later */
3458                 if (first_trb) {
3459                         first_trb = false;
3460                         if (start_cycle == 0)
3461                                 field |= 0x1;
3462                 } else
3463                         field |= ep_ring->cycle_state;
3464
3465                 /* Chain all the TRBs together; clear the chain bit in the last
3466                  * TRB to indicate it's the last TRB in the chain.
3467                  */
3468                 if (num_trbs > 1) {
3469                         field |= TRB_CHAIN;
3470                 } else {
3471                         /* FIXME - add check for ZERO_PACKET flag before this */
3472                         td->last_trb = ep_ring->enqueue;
3473                         field |= TRB_IOC;
3474                 }
3475
3476                 /* Only set interrupt on short packet for IN endpoints */
3477                 if (usb_urb_dir_in(urb))
3478                         field |= TRB_ISP;
3479
3480                 /* Set the TRB length, TD size, and interrupter fields. */
3481                 if (xhci->hci_version < 0x100) {
3482                         remainder = xhci_td_remainder(
3483                                         urb->transfer_buffer_length -
3484                                         running_total);
3485                 } else {
3486                         remainder = xhci_v1_0_td_remainder(running_total,
3487                                         trb_buff_len, total_packet_count, urb,
3488                                         num_trbs - 1);
3489                 }
3490                 length_field = TRB_LEN(trb_buff_len) |
3491                         remainder |
3492                         TRB_INTR_TARGET(0);
3493
3494                 if (num_trbs > 1)
3495                         more_trbs_coming = true;
3496                 else
3497                         more_trbs_coming = false;
3498                 queue_trb(xhci, ep_ring, more_trbs_coming,
3499                                 lower_32_bits(addr),
3500                                 upper_32_bits(addr),
3501                                 length_field,
3502                                 field | TRB_TYPE(TRB_NORMAL));
3503                 --num_trbs;
3504                 running_total += trb_buff_len;
3505
3506                 /* Calculate length for next transfer */
3507                 addr += trb_buff_len;
3508                 trb_buff_len = urb->transfer_buffer_length - running_total;
3509                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3510                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3511         } while (running_total < urb->transfer_buffer_length);
3512
3513         check_trb_math(urb, num_trbs, running_total);
3514         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3515                         start_cycle, start_trb);
3516         return 0;
3517 }
3518
3519 /* Caller must have locked xhci->lock */
3520 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3521                 struct urb *urb, int slot_id, unsigned int ep_index)
3522 {
3523         struct xhci_ring *ep_ring;
3524         int num_trbs;
3525         int ret;
3526         struct usb_ctrlrequest *setup;
3527         struct xhci_generic_trb *start_trb;
3528         int start_cycle;
3529         u32 field, length_field;
3530         struct urb_priv *urb_priv;
3531         struct xhci_td *td;
3532
3533         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3534         if (!ep_ring)
3535                 return -EINVAL;
3536
3537         /*
3538          * Need to copy setup packet into setup TRB, so we can't use the setup
3539          * DMA address.
3540          */
3541         if (!urb->setup_packet)
3542                 return -EINVAL;
3543
3544         /* 1 TRB for setup, 1 for status */
3545         num_trbs = 2;
3546         /*
3547          * Don't need to check if we need additional event data and normal TRBs,
3548          * since data in control transfers will never get bigger than 16MB
3549          * XXX: can we get a buffer that crosses 64KB boundaries?
3550          */
3551         if (urb->transfer_buffer_length > 0)
3552                 num_trbs++;
3553         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3554                         ep_index, urb->stream_id,
3555                         num_trbs, urb, 0, mem_flags);
3556         if (ret < 0)
3557                 return ret;
3558
3559         urb_priv = urb->hcpriv;
3560         td = urb_priv->td[0];
3561
3562         /*
3563          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3564          * until we've finished creating all the other TRBs.  The ring's cycle
3565          * state may change as we enqueue the other TRBs, so save it too.
3566          */
3567         start_trb = &ep_ring->enqueue->generic;
3568         start_cycle = ep_ring->cycle_state;
3569
3570         /* Queue setup TRB - see section 6.4.1.2.1 */
3571         /* FIXME better way to translate setup_packet into two u32 fields? */
3572         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3573         field = 0;
3574         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3575         if (start_cycle == 0)
3576                 field |= 0x1;
3577
3578         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3579         if (xhci->hci_version == 0x100) {
3580                 if (urb->transfer_buffer_length > 0) {
3581                         if (setup->bRequestType & USB_DIR_IN)
3582                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3583                         else
3584                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3585                 }
3586         }
3587
3588         queue_trb(xhci, ep_ring, true,
3589                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3590                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3591                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3592                   /* Immediate data in pointer */
3593                   field);
3594
3595         /* If there's data, queue data TRBs */
3596         /* Only set interrupt on short packet for IN endpoints */
3597         if (usb_urb_dir_in(urb))
3598                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3599         else
3600                 field = TRB_TYPE(TRB_DATA);
3601
3602         length_field = TRB_LEN(urb->transfer_buffer_length) |
3603                 xhci_td_remainder(urb->transfer_buffer_length) |
3604                 TRB_INTR_TARGET(0);
3605         if (urb->transfer_buffer_length > 0) {
3606                 if (setup->bRequestType & USB_DIR_IN)
3607                         field |= TRB_DIR_IN;
3608                 queue_trb(xhci, ep_ring, true,
3609                                 lower_32_bits(urb->transfer_dma),
3610                                 upper_32_bits(urb->transfer_dma),
3611                                 length_field,
3612                                 field | ep_ring->cycle_state);
3613         }
3614
3615         /* Save the DMA address of the last TRB in the TD */
3616         td->last_trb = ep_ring->enqueue;
3617
3618         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3619         /* If the device sent data, the status stage is an OUT transfer */
3620         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3621                 field = 0;
3622         else
3623                 field = TRB_DIR_IN;
3624         queue_trb(xhci, ep_ring, false,
3625                         0,
3626                         0,
3627                         TRB_INTR_TARGET(0),
3628                         /* Event on completion */
3629                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3630
3631         giveback_first_trb(xhci, slot_id, ep_index, 0,
3632                         start_cycle, start_trb);
3633         return 0;
3634 }
3635
3636 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3637                 struct urb *urb, int i)
3638 {
3639         int num_trbs = 0;
3640         u64 addr, td_len;
3641
3642         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3643         td_len = urb->iso_frame_desc[i].length;
3644
3645         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3646                         TRB_MAX_BUFF_SIZE);
3647         if (num_trbs == 0)
3648                 num_trbs++;
3649
3650         return num_trbs;
3651 }
3652
3653 /*
3654  * The transfer burst count field of the isochronous TRB defines the number of
3655  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3656  * devices can burst up to bMaxBurst number of packets per service interval.
3657  * This field is zero based, meaning a value of zero in the field means one
3658  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3659  * zero.  Only xHCI 1.0 host controllers support this field.
3660  */
3661 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3662                 struct usb_device *udev,
3663                 struct urb *urb, unsigned int total_packet_count)
3664 {
3665         unsigned int max_burst;
3666
3667         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3668                 return 0;
3669
3670         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3671         return roundup(total_packet_count, max_burst + 1) - 1;
3672 }
3673
3674 /*
3675  * Returns the number of packets in the last "burst" of packets.  This field is
3676  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3677  * the last burst packet count is equal to the total number of packets in the
3678  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3679  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3680  * contain 1 to (bMaxBurst + 1) packets.
3681  */
3682 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3683                 struct usb_device *udev,
3684                 struct urb *urb, unsigned int total_packet_count)
3685 {
3686         unsigned int max_burst;
3687         unsigned int residue;
3688
3689         if (xhci->hci_version < 0x100)
3690                 return 0;
3691
3692         switch (udev->speed) {
3693         case USB_SPEED_SUPER:
3694                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3695                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3696                 residue = total_packet_count % (max_burst + 1);
3697                 /* If residue is zero, the last burst contains (max_burst + 1)
3698                  * number of packets, but the TLBPC field is zero-based.
3699                  */
3700                 if (residue == 0)
3701                         return max_burst;
3702                 return residue - 1;
3703         default:
3704                 if (total_packet_count == 0)
3705                         return 0;
3706                 return total_packet_count - 1;
3707         }
3708 }
3709
3710 /* This is for isoc transfer */
3711 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3712                 struct urb *urb, int slot_id, unsigned int ep_index)
3713 {
3714         struct xhci_ring *ep_ring;
3715         struct urb_priv *urb_priv;
3716         struct xhci_td *td;
3717         int num_tds, trbs_per_td;
3718         struct xhci_generic_trb *start_trb;
3719         bool first_trb;
3720         int start_cycle;
3721         u32 field, length_field;
3722         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3723         u64 start_addr, addr;
3724         int i, j;
3725         bool more_trbs_coming;
3726
3727         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3728
3729         num_tds = urb->number_of_packets;
3730         if (num_tds < 1) {
3731                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3732                 return -EINVAL;
3733         }
3734
3735         start_addr = (u64) urb->transfer_dma;
3736         start_trb = &ep_ring->enqueue->generic;
3737         start_cycle = ep_ring->cycle_state;
3738
3739         urb_priv = urb->hcpriv;
3740         /* Queue the first TRB, even if it's zero-length */
3741         for (i = 0; i < num_tds; i++) {
3742                 unsigned int total_packet_count;
3743                 unsigned int burst_count;
3744                 unsigned int residue;
3745
3746                 first_trb = true;
3747                 running_total = 0;
3748                 addr = start_addr + urb->iso_frame_desc[i].offset;
3749                 td_len = urb->iso_frame_desc[i].length;
3750                 td_remain_len = td_len;
3751                 total_packet_count = DIV_ROUND_UP(td_len,
3752                                 GET_MAX_PACKET(
3753                                         usb_endpoint_maxp(&urb->ep->desc)));
3754                 /* A zero-length transfer still involves at least one packet. */
3755                 if (total_packet_count == 0)
3756                         total_packet_count++;
3757                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3758                                 total_packet_count);
3759                 residue = xhci_get_last_burst_packet_count(xhci,
3760                                 urb->dev, urb, total_packet_count);
3761
3762                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3763
3764                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3765                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3766                 if (ret < 0) {
3767                         if (i == 0)
3768                                 return ret;
3769                         goto cleanup;
3770                 }
3771
3772                 td = urb_priv->td[i];
3773                 for (j = 0; j < trbs_per_td; j++) {
3774                         u32 remainder = 0;
3775                         field = 0;
3776
3777                         if (first_trb) {
3778                                 field = TRB_TBC(burst_count) |
3779                                         TRB_TLBPC(residue);
3780                                 /* Queue the isoc TRB */
3781                                 field |= TRB_TYPE(TRB_ISOC);
3782                                 /* Assume URB_ISO_ASAP is set */
3783                                 field |= TRB_SIA;
3784                                 if (i == 0) {
3785                                         if (start_cycle == 0)
3786                                                 field |= 0x1;
3787                                 } else
3788                                         field |= ep_ring->cycle_state;
3789                                 first_trb = false;
3790                         } else {
3791                                 /* Queue other normal TRBs */
3792                                 field |= TRB_TYPE(TRB_NORMAL);
3793                                 field |= ep_ring->cycle_state;
3794                         }
3795
3796                         /* Only set interrupt on short packet for IN EPs */
3797                         if (usb_urb_dir_in(urb))
3798                                 field |= TRB_ISP;
3799
3800                         /* Chain all the TRBs together; clear the chain bit in
3801                          * the last TRB to indicate it's the last TRB in the
3802                          * chain.
3803                          */
3804                         if (j < trbs_per_td - 1) {
3805                                 field |= TRB_CHAIN;
3806                                 more_trbs_coming = true;
3807                         } else {
3808                                 td->last_trb = ep_ring->enqueue;
3809                                 field |= TRB_IOC;
3810                                 if (xhci->hci_version == 0x100 &&
3811                                                 !(xhci->quirks &
3812                                                         XHCI_AVOID_BEI)) {
3813                                         /* Set BEI bit except for the last td */
3814                                         if (i < num_tds - 1)
3815                                                 field |= TRB_BEI;
3816                                 }
3817                                 more_trbs_coming = false;
3818                         }
3819
3820                         /* Calculate TRB length */
3821                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3822                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3823                         if (trb_buff_len > td_remain_len)
3824                                 trb_buff_len = td_remain_len;
3825
3826                         /* Set the TRB length, TD size, & interrupter fields. */
3827                         if (xhci->hci_version < 0x100) {
3828                                 remainder = xhci_td_remainder(
3829                                                 td_len - running_total);
3830                         } else {
3831                                 remainder = xhci_v1_0_td_remainder(
3832                                                 running_total, trb_buff_len,
3833                                                 total_packet_count, urb,
3834                                                 (trbs_per_td - j - 1));
3835                         }
3836                         length_field = TRB_LEN(trb_buff_len) |
3837                                 remainder |
3838                                 TRB_INTR_TARGET(0);
3839
3840                         queue_trb(xhci, ep_ring, more_trbs_coming,
3841                                 lower_32_bits(addr),
3842                                 upper_32_bits(addr),
3843                                 length_field,
3844                                 field);
3845                         running_total += trb_buff_len;
3846
3847                         addr += trb_buff_len;
3848                         td_remain_len -= trb_buff_len;
3849                 }
3850
3851                 /* Check TD length */
3852                 if (running_total != td_len) {
3853                         xhci_err(xhci, "ISOC TD length unmatch\n");
3854                         ret = -EINVAL;
3855                         goto cleanup;
3856                 }
3857         }
3858
3859         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3860                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3861                         usb_amd_quirk_pll_disable();
3862         }
3863         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3864
3865         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3866                         start_cycle, start_trb);
3867         return 0;
3868 cleanup:
3869         /* Clean up a partially enqueued isoc transfer. */
3870
3871         for (i--; i >= 0; i--)
3872                 list_del_init(&urb_priv->td[i]->td_list);
3873
3874         /* Use the first TD as a temporary variable to turn the TDs we've queued
3875          * into No-ops with a software-owned cycle bit. That way the hardware
3876          * won't accidentally start executing bogus TDs when we partially
3877          * overwrite them.  td->first_trb and td->start_seg are already set.
3878          */
3879         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3880         /* Every TRB except the first & last will have its cycle bit flipped. */
3881         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3882
3883         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3884         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3885         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3886         ep_ring->cycle_state = start_cycle;
3887         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3888         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3889         return ret;
3890 }
3891
3892 /*
3893  * Check transfer ring to guarantee there is enough room for the urb.
3894  * Update ISO URB start_frame and interval.
3895  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3896  * update the urb->start_frame by now.
3897  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3898  */
3899 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3900                 struct urb *urb, int slot_id, unsigned int ep_index)
3901 {
3902         struct xhci_virt_device *xdev;
3903         struct xhci_ring *ep_ring;
3904         struct xhci_ep_ctx *ep_ctx;
3905         int start_frame;
3906         int xhci_interval;
3907         int ep_interval;
3908         int num_tds, num_trbs, i;
3909         int ret;
3910
3911         xdev = xhci->devs[slot_id];
3912         ep_ring = xdev->eps[ep_index].ring;
3913         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3914
3915         num_trbs = 0;
3916         num_tds = urb->number_of_packets;
3917         for (i = 0; i < num_tds; i++)
3918                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3919
3920         /* Check the ring to guarantee there is enough room for the whole urb.
3921          * Do not insert any td of the urb to the ring if the check failed.
3922          */
3923         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3924                            num_trbs, mem_flags);
3925         if (ret)
3926                 return ret;
3927
3928         start_frame = readl(&xhci->run_regs->microframe_index);
3929         start_frame &= 0x3fff;
3930
3931         urb->start_frame = start_frame;
3932         if (urb->dev->speed == USB_SPEED_LOW ||
3933                         urb->dev->speed == USB_SPEED_FULL)
3934                 urb->start_frame >>= 3;
3935
3936         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3937         ep_interval = urb->interval;
3938         /* Convert to microframes */
3939         if (urb->dev->speed == USB_SPEED_LOW ||
3940                         urb->dev->speed == USB_SPEED_FULL)
3941                 ep_interval *= 8;
3942         /* FIXME change this to a warning and a suggestion to use the new API
3943          * to set the polling interval (once the API is added).
3944          */
3945         if (xhci_interval != ep_interval) {
3946                 dev_dbg_ratelimited(&urb->dev->dev,
3947                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3948                                 ep_interval, ep_interval == 1 ? "" : "s",
3949                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3950                 urb->interval = xhci_interval;
3951                 /* Convert back to frames for LS/FS devices */
3952                 if (urb->dev->speed == USB_SPEED_LOW ||
3953                                 urb->dev->speed == USB_SPEED_FULL)
3954                         urb->interval /= 8;
3955         }
3956         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3957
3958         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3959 }
3960
3961 /****           Command Ring Operations         ****/
3962
3963 /* Generic function for queueing a command TRB on the command ring.
3964  * Check to make sure there's room on the command ring for one command TRB.
3965  * Also check that there's room reserved for commands that must not fail.
3966  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3967  * then only check for the number of reserved spots.
3968  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3969  * because the command event handler may want to resubmit a failed command.
3970  */
3971 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3972                 u32 field3, u32 field4, bool command_must_succeed)
3973 {
3974         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3975         int ret;
3976
3977         if (!command_must_succeed)
3978                 reserved_trbs++;
3979
3980         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3981                         reserved_trbs, GFP_ATOMIC);
3982         if (ret < 0) {
3983                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3984                 if (command_must_succeed)
3985                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3986                                         "unfailable commands failed.\n");
3987                 return ret;
3988         }
3989         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3990                         field4 | xhci->cmd_ring->cycle_state);
3991         return 0;
3992 }
3993
3994 /* Queue a slot enable or disable request on the command ring */
3995 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3996 {
3997         return queue_command(xhci, 0, 0, 0,
3998                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3999 }
4000
4001 /* Queue an address device command TRB */
4002 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4003                               u32 slot_id, enum xhci_setup_dev setup)
4004 {
4005         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4006                         upper_32_bits(in_ctx_ptr), 0,
4007                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4008                         | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4009 }
4010
4011 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
4012                 u32 field1, u32 field2, u32 field3, u32 field4)
4013 {
4014         return queue_command(xhci, field1, field2, field3, field4, false);
4015 }
4016
4017 /* Queue a reset device command TRB */
4018 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
4019 {
4020         return queue_command(xhci, 0, 0, 0,
4021                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4022                         false);
4023 }
4024
4025 /* Queue a configure endpoint command TRB */
4026 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4027                 u32 slot_id, bool command_must_succeed)
4028 {
4029         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4030                         upper_32_bits(in_ctx_ptr), 0,
4031                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4032                         command_must_succeed);
4033 }
4034
4035 /* Queue an evaluate context command TRB */
4036 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4037                 u32 slot_id, bool command_must_succeed)
4038 {
4039         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4040                         upper_32_bits(in_ctx_ptr), 0,
4041                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4042                         command_must_succeed);
4043 }
4044
4045 /*
4046  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4047  * activity on an endpoint that is about to be suspended.
4048  */
4049 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
4050                 unsigned int ep_index, int suspend)
4051 {
4052         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4053         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4054         u32 type = TRB_TYPE(TRB_STOP_RING);
4055         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4056
4057         return queue_command(xhci, 0, 0, 0,
4058                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
4059 }
4060
4061 /* Set Transfer Ring Dequeue Pointer command.
4062  * This should not be used for endpoints that have streams enabled.
4063  */
4064 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
4065                 unsigned int ep_index, unsigned int stream_id,
4066                 struct xhci_segment *deq_seg,
4067                 union xhci_trb *deq_ptr, u32 cycle_state)
4068 {
4069         dma_addr_t addr;
4070         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4071         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4072         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4073         u32 type = TRB_TYPE(TRB_SET_DEQ);
4074         struct xhci_virt_ep *ep;
4075
4076         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4077         if (addr == 0) {
4078                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4079                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4080                                 deq_seg, deq_ptr);
4081                 return 0;
4082         }
4083         ep = &xhci->devs[slot_id]->eps[ep_index];
4084         if ((ep->ep_state & SET_DEQ_PENDING)) {
4085                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4086                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4087                 return 0;
4088         }
4089         ep->queued_deq_seg = deq_seg;
4090         ep->queued_deq_ptr = deq_ptr;
4091         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4092                         upper_32_bits(addr), trb_stream_id,
4093                         trb_slot_id | trb_ep_index | type, false);
4094 }
4095
4096 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4097                 unsigned int ep_index)
4098 {
4099         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4100         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4101         u32 type = TRB_TYPE(TRB_RESET_EP);
4102
4103         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4104                         false);
4105 }