drivers/video/omap2/dss/hdmi4_core.c

   1 /*
   2  * ti_hdmi_4xxx_ip.c
   3  *
   4  * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   6  * Authors: Yong Zhi
   7  *      Mythri pk <mythripk@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mutex.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/string.h>
  31 #include <linux/seq_file.h>
  32 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
  33 #include <sound/asound.h>
  34 #include <sound/asoundef.h>
  35 #endif
  36
  37 #include "hdmi4_core.h"
  38 #include "dss_features.h"
  39
  40 #define HDMI_CORE_AV            0x500
  41
  42 static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core)
  43 {
  44         return core->base + HDMI_CORE_AV;
  45 }
  46
  47 static int hdmi_core_ddc_init(struct hdmi_core_data *core)
  48 {
  49         void __iomem *base = core->base;
  50
  51         /* Turn on CLK for DDC */
  52         REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
  53
  54         /* IN_PROG */
  55         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
  56                 /* Abort transaction */
  57                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
  58                 /* IN_PROG */
  59                 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
  60                                         4, 4, 0) != 0) {
  61                         DSSERR("Timeout aborting DDC transaction\n");
  62                         return -ETIMEDOUT;
  63                 }
  64         }
  65
  66         /* Clk SCL Devices */
  67         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
  68
  69         /* HDMI_CORE_DDC_STATUS_IN_PROG */
  70         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
  71                                 4, 4, 0) != 0) {
  72                 DSSERR("Timeout starting SCL clock\n");
  73                 return -ETIMEDOUT;
  74         }
  75
  76         /* Clear FIFO */
  77         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
  78
  79         /* HDMI_CORE_DDC_STATUS_IN_PROG */
  80         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
  81                                 4, 4, 0) != 0) {
  82                 DSSERR("Timeout clearing DDC fifo\n");
  83                 return -ETIMEDOUT;
  84         }
  85
  86         return 0;
  87 }
  88
  89 static int hdmi_core_ddc_edid(struct hdmi_core_data *core,
  90                 u8 *pedid, int ext)
  91 {
  92         void __iomem *base = core->base;
  93         u32 i;
  94         char checksum;
  95         u32 offset = 0;
  96
  97         /* HDMI_CORE_DDC_STATUS_IN_PROG */
  98         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
  99                                 4, 4, 0) != 0) {
 100                 DSSERR("Timeout waiting DDC to be ready\n");
 101                 return -ETIMEDOUT;
 102         }
 103
 104         if (ext % 2 != 0)
 105                 offset = 0x80;
 106
 107         /* Load Segment Address Register */
 108         REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
 109
 110         /* Load Slave Address Register */
 111         REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
 112
 113         /* Load Offset Address Register */
 114         REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
 115
 116         /* Load Byte Count */
 117         REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
 118         REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
 119
 120         /* Set DDC_CMD */
 121         if (ext)
 122                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
 123         else
 124                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
 125
 126         /* HDMI_CORE_DDC_STATUS_BUS_LOW */
 127         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
 128                 pr_err("I2C Bus Low?\n");
 129                 return -EIO;
 130         }
 131         /* HDMI_CORE_DDC_STATUS_NO_ACK */
 132         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
 133                 pr_err("I2C No Ack\n");
 134                 return -EIO;
 135         }
 136
 137         for (i = 0; i < 0x80; ++i) {
 138                 int t;
 139
 140                 /* IN_PROG */
 141                 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
 142                         DSSERR("operation stopped when reading edid\n");
 143                         return -EIO;
 144                 }
 145
 146                 t = 0;
 147                 /* FIFO_EMPTY */
 148                 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
 149                         if (t++ > 10000) {
 150                                 DSSERR("timeout reading edid\n");
 151                                 return -ETIMEDOUT;
 152                         }
 153                         udelay(1);
 154                 }
 155
 156                 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
 157         }
 158
 159         checksum = 0;
 160         for (i = 0; i < 0x80; ++i)
 161                 checksum += pedid[i];
 162
 163         if (checksum != 0) {
 164                 pr_err("E-EDID checksum failed!!\n");
 165                 return -EIO;
 166         }
 167
 168         return 0;
 169 }
 170
 171 int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
 172 {
 173         int r, l;
 174
 175         if (len < 128)
 176                 return -EINVAL;
 177
 178         r = hdmi_core_ddc_init(core);
 179         if (r)
 180                 return r;
 181
 182         r = hdmi_core_ddc_edid(core, edid, 0);
 183         if (r)
 184                 return r;
 185
 186         l = 128;
 187
 188         if (len >= 128 * 2 && edid[0x7e] > 0) {
 189                 r = hdmi_core_ddc_edid(core, edid + 0x80, 1);
 190                 if (r)
 191                         return r;
 192                 l += 128;
 193         }
 194
 195         return l;
 196 }
 197
 198 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
 199                         struct hdmi_core_infoframe_avi *avi_cfg,
 200                         struct hdmi_core_packet_enable_repeat *repeat_cfg)
 201 {
 202         pr_debug("Enter hdmi_core_init\n");
 203
 204         /* video core */
 205         video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
 206         video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
 207         video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
 208         video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
 209         video_cfg->hdmi_dvi = HDMI_DVI;
 210         video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
 211
 212         /* info frame */
 213         avi_cfg->db1_format = 0;
 214         avi_cfg->db1_active_info = 0;
 215         avi_cfg->db1_bar_info_dv = 0;
 216         avi_cfg->db1_scan_info = 0;
 217         avi_cfg->db2_colorimetry = 0;
 218         avi_cfg->db2_aspect_ratio = 0;
 219         avi_cfg->db2_active_fmt_ar = 0;
 220         avi_cfg->db3_itc = 0;
 221         avi_cfg->db3_ec = 0;
 222         avi_cfg->db3_q_range = 0;
 223         avi_cfg->db3_nup_scaling = 0;
 224         avi_cfg->db4_videocode = 0;
 225         avi_cfg->db5_pixel_repeat = 0;
 226         avi_cfg->db6_7_line_eoftop = 0;
 227         avi_cfg->db8_9_line_sofbottom = 0;
 228         avi_cfg->db10_11_pixel_eofleft = 0;
 229         avi_cfg->db12_13_pixel_sofright = 0;
 230
 231         /* packet enable and repeat */
 232         repeat_cfg->audio_pkt = 0;
 233         repeat_cfg->audio_pkt_repeat = 0;
 234         repeat_cfg->avi_infoframe = 0;
 235         repeat_cfg->avi_infoframe_repeat = 0;
 236         repeat_cfg->gen_cntrl_pkt = 0;
 237         repeat_cfg->gen_cntrl_pkt_repeat = 0;
 238         repeat_cfg->generic_pkt = 0;
 239         repeat_cfg->generic_pkt_repeat = 0;
 240 }
 241
 242 static void hdmi_core_powerdown_disable(struct hdmi_core_data *core)
 243 {
 244         pr_debug("Enter hdmi_core_powerdown_disable\n");
 245         REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0);
 246 }
 247
 248 static void hdmi_core_swreset_release(struct hdmi_core_data *core)
 249 {
 250         pr_debug("Enter hdmi_core_swreset_release\n");
 251         REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0);
 252 }
 253
 254 static void hdmi_core_swreset_assert(struct hdmi_core_data *core)
 255 {
 256         pr_debug("Enter hdmi_core_swreset_assert\n");
 257         REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0);
 258 }
 259
 260 /* HDMI_CORE_VIDEO_CONFIG */
 261 static void hdmi_core_video_config(struct hdmi_core_data *core,
 262                                 struct hdmi_core_video_config *cfg)
 263 {
 264         u32 r = 0;
 265         void __iomem *core_sys_base = core->base;
 266         void __iomem *core_av_base = hdmi_av_base(core);
 267
 268         /* sys_ctrl1 default configuration not tunable */
 269         r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1);
 270         r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
 271         r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
 272         r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2);
 273         r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1);
 274         hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r);
 275
 276         REG_FLD_MOD(core_sys_base,
 277                         HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
 278
 279         /* Vid_Mode */
 280         r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
 281
 282         /* dither truncation configuration */
 283         if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
 284                 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
 285                 r = FLD_MOD(r, 1, 5, 5);
 286         } else {
 287                 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
 288                 r = FLD_MOD(r, 0, 5, 5);
 289         }
 290         hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
 291
 292         /* HDMI_Ctrl */
 293         r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL);
 294         r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
 295         r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
 296         r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
 297         hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r);
 298
 299         /* TMDS_CTRL */
 300         REG_FLD_MOD(core_sys_base,
 301                         HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
 302 }
 303
 304 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core)
 305 {
 306         u32 val;
 307         char sum = 0, checksum = 0;
 308         void __iomem *av_base = hdmi_av_base(core);
 309         struct hdmi_core_infoframe_avi info_avi = core->avi_cfg;
 310
 311         sum += 0x82 + 0x002 + 0x00D;
 312         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
 313         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
 314         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
 315
 316         val = (info_avi.db1_format << 5) |
 317                 (info_avi.db1_active_info << 4) |
 318                 (info_avi.db1_bar_info_dv << 2) |
 319                 (info_avi.db1_scan_info);
 320         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
 321         sum += val;
 322
 323         val = (info_avi.db2_colorimetry << 6) |
 324                 (info_avi.db2_aspect_ratio << 4) |
 325                 (info_avi.db2_active_fmt_ar);
 326         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
 327         sum += val;
 328
 329         val = (info_avi.db3_itc << 7) |
 330                 (info_avi.db3_ec << 4) |
 331                 (info_avi.db3_q_range << 2) |
 332                 (info_avi.db3_nup_scaling);
 333         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
 334         sum += val;
 335
 336         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
 337                                         info_avi.db4_videocode);
 338         sum += info_avi.db4_videocode;
 339
 340         val = info_avi.db5_pixel_repeat;
 341         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
 342         sum += val;
 343
 344         val = info_avi.db6_7_line_eoftop & 0x00FF;
 345         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
 346         sum += val;
 347
 348         val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
 349         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
 350         sum += val;
 351
 352         val = info_avi.db8_9_line_sofbottom & 0x00FF;
 353         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
 354         sum += val;
 355
 356         val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
 357         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
 358         sum += val;
 359
 360         val = info_avi.db10_11_pixel_eofleft & 0x00FF;
 361         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
 362         sum += val;
 363
 364         val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
 365         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
 366         sum += val;
 367
 368         val = info_avi.db12_13_pixel_sofright & 0x00FF;
 369         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
 370         sum += val;
 371
 372         val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
 373         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
 374         sum += val;
 375
 376         checksum = 0x100 - sum;
 377         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
 378 }
 379
 380 static void hdmi_core_av_packet_config(struct hdmi_core_data *core,
 381                 struct hdmi_core_packet_enable_repeat repeat_cfg)
 382 {
 383         /* enable/repeat the infoframe */
 384         hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1,
 385                 (repeat_cfg.audio_pkt << 5) |
 386                 (repeat_cfg.audio_pkt_repeat << 4) |
 387                 (repeat_cfg.avi_infoframe << 1) |
 388                 (repeat_cfg.avi_infoframe_repeat));
 389
 390         /* enable/repeat the packet */
 391         hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2,
 392                 (repeat_cfg.gen_cntrl_pkt << 3) |
 393                 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
 394                 (repeat_cfg.generic_pkt << 1) |
 395                 (repeat_cfg.generic_pkt_repeat));
 396 }
 397
 398 void hdmi4_configure(struct hdmi_core_data *core,
 399         struct hdmi_wp_data *wp, struct hdmi_config *cfg)
 400 {
 401         /* HDMI */
 402         struct omap_video_timings video_timing;
 403         struct hdmi_video_format video_format;
 404         /* HDMI core */
 405         struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg;
 406         struct hdmi_core_video_config v_core_cfg;
 407         struct hdmi_core_packet_enable_repeat repeat_cfg;
 408
 409         hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg);
 410
 411         hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
 412
 413         hdmi_wp_video_config_timing(wp, &video_timing);
 414
 415         /* video config */
 416         video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
 417
 418         hdmi_wp_video_config_format(wp, &video_format);
 419
 420         hdmi_wp_video_config_interface(wp, &video_timing);
 421
 422         /*
 423          * configure core video part
 424          * set software reset in the core
 425          */
 426         hdmi_core_swreset_assert(core);
 427
 428         /* power down off */
 429         hdmi_core_powerdown_disable(core);
 430
 431         v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
 432         v_core_cfg.hdmi_dvi = cfg->cm.mode;
 433
 434         hdmi_core_video_config(core, &v_core_cfg);
 435
 436         /* release software reset in the core */
 437         hdmi_core_swreset_release(core);
 438
 439         /*
 440          * configure packet
 441          * info frame video see doc CEA861-D page 65
 442          */
 443         avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
 444         avi_cfg->db1_active_info =
 445                         HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
 446         avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
 447         avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
 448         avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
 449         avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
 450         avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
 451         avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
 452         avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
 453         avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
 454         avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
 455         avi_cfg->db4_videocode = cfg->cm.code;
 456         avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
 457         avi_cfg->db6_7_line_eoftop = 0;
 458         avi_cfg->db8_9_line_sofbottom = 0;
 459         avi_cfg->db10_11_pixel_eofleft = 0;
 460         avi_cfg->db12_13_pixel_sofright = 0;
 461
 462         hdmi_core_aux_infoframe_avi_config(core);
 463
 464         /* enable/repeat the infoframe */
 465         repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
 466         repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
 467         /* wakeup */
 468         repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
 469         repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
 470         hdmi_core_av_packet_config(core, repeat_cfg);
 471 }
 472
 473 void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s)
 474 {
 475         int i;
 476
 477 #define CORE_REG(i, name) name(i)
 478 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
 479                 hdmi_read_reg(core->base, r))
 480 #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
 481                 hdmi_read_reg(hdmi_av_base(core), r))
 482 #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
 483                 (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \
 484                 hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r)))
 485
 486         DUMPCORE(HDMI_CORE_SYS_VND_IDL);
 487         DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
 488         DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
 489         DUMPCORE(HDMI_CORE_SYS_DEV_REV);
 490         DUMPCORE(HDMI_CORE_SYS_SRST);
 491         DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1);
 492         DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
 493         DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3);
 494         DUMPCORE(HDMI_CORE_SYS_DE_DLY);
 495         DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
 496         DUMPCORE(HDMI_CORE_SYS_DE_TOP);
 497         DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
 498         DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
 499         DUMPCORE(HDMI_CORE_SYS_DE_LINL);
 500         DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
 501         DUMPCORE(HDMI_CORE_SYS_HRES_L);
 502         DUMPCORE(HDMI_CORE_SYS_HRES_H);
 503         DUMPCORE(HDMI_CORE_SYS_VRES_L);
 504         DUMPCORE(HDMI_CORE_SYS_VRES_H);
 505         DUMPCORE(HDMI_CORE_SYS_IADJUST);
 506         DUMPCORE(HDMI_CORE_SYS_POLDETECT);
 507         DUMPCORE(HDMI_CORE_SYS_HWIDTH1);
 508         DUMPCORE(HDMI_CORE_SYS_HWIDTH2);
 509         DUMPCORE(HDMI_CORE_SYS_VWIDTH);
 510         DUMPCORE(HDMI_CORE_SYS_VID_CTRL);
 511         DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
 512         DUMPCORE(HDMI_CORE_SYS_VID_MODE);
 513         DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
 514         DUMPCORE(HDMI_CORE_SYS_VID_BLANK3);
 515         DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
 516         DUMPCORE(HDMI_CORE_SYS_DC_HEADER);
 517         DUMPCORE(HDMI_CORE_SYS_VID_DITHER);
 518         DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT);
 519         DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW);
 520         DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP);
 521         DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW);
 522         DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP);
 523         DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW);
 524         DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP);
 525         DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW);
 526         DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP);
 527         DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW);
 528         DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP);
 529         DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW);
 530         DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP);
 531         DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW);
 532         DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP);
 533         DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW);
 534         DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP);
 535         DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW);
 536         DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP);
 537         DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW);
 538         DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP);
 539         DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW);
 540         DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP);
 541         DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW);
 542         DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP);
 543         DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
 544         DUMPCORE(HDMI_CORE_SYS_INTR1);
 545         DUMPCORE(HDMI_CORE_SYS_INTR2);
 546         DUMPCORE(HDMI_CORE_SYS_INTR3);
 547         DUMPCORE(HDMI_CORE_SYS_INTR4);
 548         DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1);
 549         DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2);
 550         DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3);
 551         DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4);
 552         DUMPCORE(HDMI_CORE_SYS_INTR_CTRL);
 553         DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
 554
 555         DUMPCORE(HDMI_CORE_DDC_ADDR);
 556         DUMPCORE(HDMI_CORE_DDC_SEGM);
 557         DUMPCORE(HDMI_CORE_DDC_OFFSET);
 558         DUMPCORE(HDMI_CORE_DDC_COUNT1);
 559         DUMPCORE(HDMI_CORE_DDC_COUNT2);
 560         DUMPCORE(HDMI_CORE_DDC_STATUS);
 561         DUMPCORE(HDMI_CORE_DDC_CMD);
 562         DUMPCORE(HDMI_CORE_DDC_DATA);
 563
 564         DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
 565         DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
 566         DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
 567         DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
 568         DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
 569         DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
 570         DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
 571         DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
 572         DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
 573         DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
 574         DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
 575         DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
 576         DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
 577         DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
 578         DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
 579         DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
 580         DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
 581         DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
 582         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
 583         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
 584         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
 585         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
 586         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
 587         DUMPCOREAV(HDMI_CORE_AV_ASRC);
 588         DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
 589         DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
 590         DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
 591         DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
 592         DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
 593         DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
 594         DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
 595         DUMPCOREAV(HDMI_CORE_AV_DPD);
 596         DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
 597         DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
 598         DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
 599         DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
 600         DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
 601         DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
 602
 603         for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
 604                 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
 605
 606         DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
 607         DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
 608         DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
 609         DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
 610
 611         for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
 612                 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
 613
 614         DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
 615         DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
 616         DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
 617         DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
 618
 619         for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
 620                 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
 621
 622         DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
 623         DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
 624         DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
 625         DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
 626
 627         for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
 628                 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
 629
 630         for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
 631                 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
 632
 633         DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
 634
 635         for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
 636                 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
 637
 638         DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
 639 }
 640
 641 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
 642 static void hdmi_core_audio_config(struct hdmi_core_data *core,
 643                                         struct hdmi_core_audio_config *cfg)
 644 {
 645         u32 r;
 646         void __iomem *av_base = hdmi_av_base(core);
 647
 648         /*
 649          * Parameters for generation of Audio Clock Recovery packets
 650          */
 651         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
 652         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
 653         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
 654
 655         if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
 656                 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
 657                 REG_FLD_MOD(av_base,
 658                                 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
 659                 REG_FLD_MOD(av_base,
 660                                 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
 661         } else {
 662                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
 663                                 cfg->aud_par_busclk, 7, 0);
 664                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
 665                                 (cfg->aud_par_busclk >> 8), 7, 0);
 666                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
 667                                 (cfg->aud_par_busclk >> 16), 7, 0);
 668         }
 669
 670         /* Set ACR clock divisor */
 671         REG_FLD_MOD(av_base,
 672                         HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
 673
 674         r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
 675         /*
 676          * Use TMDS clock for ACR packets. For devices that use
 677          * the MCLK, this is the first part of the MCLK initialization.
 678          */
 679         r = FLD_MOD(r, 0, 2, 2);
 680
 681         r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
 682         r = FLD_MOD(r, cfg->cts_mode, 0, 0);
 683         hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
 684
 685         /* For devices using MCLK, this completes its initialization. */
 686         if (cfg->use_mclk)
 687                 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
 688
 689         /* Override of SPDIF sample frequency with value in I2S_CHST4 */
 690         REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
 691                                                 cfg->fs_override, 1, 1);
 692
 693         /*
 694          * Set IEC-60958-3 channel status word. It is passed to the IP
 695          * just as it is received. The user of the driver is responsible
 696          * for its contents.
 697          */
 698         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
 699                        cfg->iec60958_cfg->status[0]);
 700         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
 701                        cfg->iec60958_cfg->status[1]);
 702         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
 703                        cfg->iec60958_cfg->status[2]);
 704         /* yes, this is correct: status[3] goes to CHST4 register */
 705         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
 706                        cfg->iec60958_cfg->status[3]);
 707         /* yes, this is correct: status[4] goes to CHST5 register */
 708         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
 709                        cfg->iec60958_cfg->status[4]);
 710
 711         /* set I2S parameters */
 712         r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
 713         r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
 714         r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
 715         r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
 716         r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
 717         r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
 718         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
 719
 720         REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
 721                         cfg->i2s_cfg.in_length_bits, 3, 0);
 722
 723         /* Audio channels and mode parameters */
 724         REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
 725         r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
 726         r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
 727         r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
 728         r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
 729         r = FLD_MOD(r, cfg->en_spdif, 1, 1);
 730         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
 731
 732         /* Audio channel mappings */
 733         /* TODO: Make channel mapping dynamic. For now, map channels
 734          * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as
 735          * HDMI speaker order is different. See CEA-861 Section 6.6.2.
 736          */
 737         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78);
 738         REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5);
 739 }
 740
 741 static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core,
 742                 struct snd_cea_861_aud_if *info_aud)
 743 {
 744         u8 sum = 0, checksum = 0;
 745         void __iomem *av_base = hdmi_av_base(core);
 746
 747         /*
 748          * Set audio info frame type, version and length as
 749          * described in HDMI 1.4a Section 8.2.2 specification.
 750          * Checksum calculation is defined in Section 5.3.5.
 751          */
 752         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
 753         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
 754         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
 755         sum += 0x84 + 0x001 + 0x00a;
 756
 757         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
 758                        info_aud->db1_ct_cc);
 759         sum += info_aud->db1_ct_cc;
 760
 761         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
 762                        info_aud->db2_sf_ss);
 763         sum += info_aud->db2_sf_ss;
 764
 765         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
 766         sum += info_aud->db3;
 767
 768         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
 769         sum += info_aud->db4_ca;
 770
 771         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
 772                        info_aud->db5_dminh_lsv);
 773         sum += info_aud->db5_dminh_lsv;
 774
 775         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
 776         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
 777         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
 778         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
 779         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
 780
 781         checksum = 0x100 - sum;
 782         hdmi_write_reg(av_base,
 783                                         HDMI_CORE_AV_AUDIO_CHSUM, checksum);
 784
 785         /*
 786          * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
 787          * is available.
 788          */
 789 }
 790
 791 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
 792                 struct omap_dss_audio *audio, u32 pclk)
 793 {
 794         struct hdmi_audio_format audio_format;
 795         struct hdmi_audio_dma audio_dma;
 796         struct hdmi_core_audio_config acore;
 797         int err, n, cts, channel_count;
 798         unsigned int fs_nr;
 799         bool word_length_16b = false;
 800
 801         if (!audio || !audio->iec || !audio->cea || !core)
 802                 return -EINVAL;
 803
 804         acore.iec60958_cfg = audio->iec;
 805         /*
 806          * In the IEC-60958 status word, check if the audio sample word length
 807          * is 16-bit as several optimizations can be performed in such case.
 808          */
 809         if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
 810                 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
 811                         word_length_16b = true;
 812
 813         /* I2S configuration. See Phillips' specification */
 814         if (word_length_16b)
 815                 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
 816         else
 817                 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
 818         /*
 819          * The I2S input word length is twice the lenght given in the IEC-60958
 820          * status word. If the word size is greater than
 821          * 20 bits, increment by one.
 822          */
 823         acore.i2s_cfg.in_length_bits = audio->iec->status[4]
 824                 & IEC958_AES4_CON_WORDLEN;
 825         if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
 826                 acore.i2s_cfg.in_length_bits++;
 827         acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
 828         acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
 829         acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
 830         acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
 831
 832         /* convert sample frequency to a number */
 833         switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
 834         case IEC958_AES3_CON_FS_32000:
 835                 fs_nr = 32000;
 836                 break;
 837         case IEC958_AES3_CON_FS_44100:
 838                 fs_nr = 44100;
 839                 break;
 840         case IEC958_AES3_CON_FS_48000:
 841                 fs_nr = 48000;
 842                 break;
 843         case IEC958_AES3_CON_FS_88200:
 844                 fs_nr = 88200;
 845                 break;
 846         case IEC958_AES3_CON_FS_96000:
 847                 fs_nr = 96000;
 848                 break;
 849         case IEC958_AES3_CON_FS_176400:
 850                 fs_nr = 176400;
 851                 break;
 852         case IEC958_AES3_CON_FS_192000:
 853                 fs_nr = 192000;
 854                 break;
 855         default:
 856                 return -EINVAL;
 857         }
 858
 859         err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
 860
 861         /* Audio clock regeneration settings */
 862         acore.n = n;
 863         acore.cts = cts;
 864         if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
 865                 acore.aud_par_busclk = 0;
 866                 acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
 867                 acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
 868         } else {
 869                 acore.aud_par_busclk = (((128 * 31) - 1) << 8);
 870                 acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
 871                 acore.use_mclk = true;
 872         }
 873
 874         if (acore.use_mclk)
 875                 acore.mclk_mode = HDMI_AUDIO_MCLK_128FS;
 876
 877         /* Audio channels settings */
 878         channel_count = (audio->cea->db1_ct_cc &
 879                          CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
 880
 881         switch (channel_count) {
 882         case 2:
 883                 audio_format.active_chnnls_msk = 0x03;
 884                 break;
 885         case 3:
 886                 audio_format.active_chnnls_msk = 0x07;
 887                 break;
 888         case 4:
 889                 audio_format.active_chnnls_msk = 0x0f;
 890                 break;
 891         case 5:
 892                 audio_format.active_chnnls_msk = 0x1f;
 893                 break;
 894         case 6:
 895                 audio_format.active_chnnls_msk = 0x3f;
 896                 break;
 897         case 7:
 898                 audio_format.active_chnnls_msk = 0x7f;
 899                 break;
 900         case 8:
 901                 audio_format.active_chnnls_msk = 0xff;
 902                 break;
 903         default:
 904                 return -EINVAL;
 905         }
 906
 907         /*
 908          * the HDMI IP needs to enable four stereo channels when transmitting
 909          * more than 2 audio channels
 910          */
 911         if (channel_count == 2) {
 912                 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
 913                 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
 914                 acore.layout = HDMI_AUDIO_LAYOUT_2CH;
 915         } else {
 916                 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
 917                 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
 918                                 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
 919                                 HDMI_AUDIO_I2S_SD3_EN;
 920                 acore.layout = HDMI_AUDIO_LAYOUT_8CH;
 921         }
 922
 923         acore.en_spdif = false;
 924         /* use sample frequency from channel status word */
 925         acore.fs_override = true;
 926         /* enable ACR packets */
 927         acore.en_acr_pkt = true;
 928         /* disable direct streaming digital audio */
 929         acore.en_dsd_audio = false;
 930         /* use parallel audio interface */
 931         acore.en_parallel_aud_input = true;
 932
 933         /* DMA settings */
 934         if (word_length_16b)
 935                 audio_dma.transfer_size = 0x10;
 936         else
 937                 audio_dma.transfer_size = 0x20;
 938         audio_dma.block_size = 0xC0;
 939         audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
 940         audio_dma.fifo_threshold = 0x20; /* in number of samples */
 941
 942         /* audio FIFO format settings */
 943         if (word_length_16b) {
 944                 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
 945                 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
 946                 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
 947         } else {
 948                 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
 949                 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
 950                 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
 951         }
 952         audio_format.type = HDMI_AUDIO_TYPE_LPCM;
 953         audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
 954         /* disable start/stop signals of IEC 60958 blocks */
 955         audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
 956
 957         /* configure DMA and audio FIFO format*/
 958         hdmi_wp_audio_config_dma(wp, &audio_dma);
 959         hdmi_wp_audio_config_format(wp, &audio_format);
 960
 961         /* configure the core*/
 962         hdmi_core_audio_config(core, &acore);
 963
 964         /* configure CEA 861 audio infoframe*/
 965         hdmi_core_audio_infoframe_cfg(core, audio->cea);
 966
 967         return 0;
 968 }
 969
 970 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
 971 {
 972         REG_FLD_MOD(hdmi_av_base(core),
 973                     HDMI_CORE_AV_AUD_MODE, true, 0, 0);
 974
 975         hdmi_wp_audio_core_req_enable(wp, true);
 976
 977         return 0;
 978 }
 979
 980 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
 981 {
 982         REG_FLD_MOD(hdmi_av_base(core),
 983                     HDMI_CORE_AV_AUD_MODE, false, 0, 0);
 984
 985         hdmi_wp_audio_core_req_enable(wp, false);
 986 }
 987
 988 int hdmi4_audio_get_dma_port(u32 *offset, u32 *size)
 989 {
 990         if (!offset || !size)
 991                 return -EINVAL;
 992         *offset = HDMI_WP_AUDIO_DATA;
 993         *size = 4;
 994         return 0;
 995 }
 996
 997 #endif
 998
 999 #define CORE_OFFSET             0x400
1000 #define CORE_SIZE               0xc00
1001
1002 int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
1003 {
1004         struct resource *res;
1005         struct resource temp_res;
1006
1007         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_core");
1008         if (!res) {
1009                 DSSDBG("can't get CORE mem resource by name\n");
1010                 /*
1011                  * if hwmod/DT doesn't have the memory resource information
1012                  * split into HDMI sub blocks by name, we try again by getting
1013                  * the platform's first resource. this code will be removed when
1014                  * the driver can get the mem resources by name
1015                  */
1016                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1017                 if (!res) {
1018                         DSSERR("can't get CORE mem resource\n");
1019                         return -EINVAL;
1020                 }
1021
1022                 temp_res.start = res->start + CORE_OFFSET;
1023                 temp_res.end = temp_res.start + CORE_SIZE - 1;
1024                 res = &temp_res;
1025         }
1026
1027         core->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1028         if (!core->base) {
1029                 DSSERR("can't ioremap CORE\n");
1030                 return -ENOMEM;
1031         }
1032
1033         return 0;
1034 }