drivers/watchdog/imx2_wdt.c

   1 /*
   2  * Watchdog driver for IMX2 and later processors
   3  *
   4  *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
   5  *  Copyright (C) 2014 Freescale Semiconductor, Inc.
   6  *
   7  * some parts adapted by similar drivers from Darius Augulis and Vladimir
   8  * Zapolskiy, additional improvements by Wim Van Sebroeck.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
  15  *
  16  *                      MX1:            MX2+:
  17  *                      ----            -----
  18  * Registers:           32-bit          16-bit
  19  * Stopable timer:      Yes             No
  20  * Need to enable clk:  No              Yes
  21  * Halt on suspend:     Manual          Can be automatic
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/io.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/of_address.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/regmap.h>
  34 #include <linux/watchdog.h>
  35
  36 #define DRIVER_NAME "imx2-wdt"
  37
  38 #define IMX2_WDT_WCR            0x00            /* Control Register */
  39 #define IMX2_WDT_WCR_WT         (0xFF << 8)     /* -> Watchdog Timeout Field */
  40 #define IMX2_WDT_WCR_WDA        (1 << 5)        /* -> External Reset WDOG_B */
  41 #define IMX2_WDT_WCR_SRS        (1 << 4)        /* -> Software Reset Signal */
  42 #define IMX2_WDT_WCR_WRE        (1 << 3)        /* -> WDOG Reset Enable */
  43 #define IMX2_WDT_WCR_WDE        (1 << 2)        /* -> Watchdog Enable */
  44 #define IMX2_WDT_WCR_WDZST      (1 << 0)        /* -> Watchdog timer Suspend */
  45
  46 #define IMX2_WDT_WSR            0x02            /* Service Register */
  47 #define IMX2_WDT_SEQ1           0x5555          /* -> service sequence 1 */
  48 #define IMX2_WDT_SEQ2           0xAAAA          /* -> service sequence 2 */
  49
  50 #define IMX2_WDT_WRSR           0x04            /* Reset Status Register */
  51 #define IMX2_WDT_WRSR_TOUT      (1 << 1)        /* -> Reset due to Timeout */
  52
  53 #define IMX2_WDT_WMCR           0x08            /* Misc Register */
  54
  55 #define IMX2_WDT_MAX_TIME       128
  56 #define IMX2_WDT_DEFAULT_TIME   60              /* in seconds */
  57
  58 #define WDOG_SEC_TO_COUNT(s)    ((s * 2 - 1) << 8)
  59
  60 struct imx2_wdt_device {
  61         struct clk *clk;
  62         struct regmap *regmap;
  63         struct watchdog_device wdog;
  64         bool ext_reset;
  65 };
  66
  67 static bool nowayout = WATCHDOG_NOWAYOUT;
  68 module_param(nowayout, bool, 0);
  69 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  70                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  71
  72
  73 static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
  74 module_param(timeout, uint, 0);
  75 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
  76                                 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
  77
  78 static const struct watchdog_info imx2_wdt_info = {
  79         .identity = "imx2+ watchdog",
  80         .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
  81 };
  82
  83 static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
  84                             void *data)
  85 {
  86         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  87         unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
  88
  89         /* Use internal reset or external - not both */
  90         if (wdev->ext_reset)
  91                 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
  92         else
  93                 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
  94
  95         /* Assert SRS signal */
  96         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  97         /*
  98          * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
  99          * written twice), we add another two writes to ensure there must be at
 100          * least two writes happen in the same one 32kHz clock period.  We save
 101          * the target check here, since the writes shouldn't be a huge burden
 102          * for other platforms.
 103          */
 104         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 105         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 106
 107         /* wait for reset to assert... */
 108         mdelay(500);
 109
 110         return 0;
 111 }
 112
 113 static inline void imx2_wdt_setup(struct watchdog_device *wdog)
 114 {
 115         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 116         u32 val;
 117
 118         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 119
 120         /* Suspend timer in low power mode, write once-only */
 121         val |= IMX2_WDT_WCR_WDZST;
 122         /* Strip the old watchdog Time-Out value */
 123         val &= ~IMX2_WDT_WCR_WT;
 124         /* Generate internal chip-level reset if WDOG times out */
 125         if (!wdev->ext_reset)
 126                 val &= ~IMX2_WDT_WCR_WRE;
 127         /* Or if external-reset assert WDOG_B reset only on time-out */
 128         else
 129                 val |= IMX2_WDT_WCR_WRE;
 130         /* Keep Watchdog Disabled */
 131         val &= ~IMX2_WDT_WCR_WDE;
 132         /* Set the watchdog's Time-Out value */
 133         val |= WDOG_SEC_TO_COUNT(wdog->timeout);
 134
 135         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 136
 137         /* enable the watchdog */
 138         val |= IMX2_WDT_WCR_WDE;
 139         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 140 }
 141
 142 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
 143 {
 144         u32 val;
 145
 146         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 147
 148         return val & IMX2_WDT_WCR_WDE;
 149 }
 150
 151 static int imx2_wdt_ping(struct watchdog_device *wdog)
 152 {
 153         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 154
 155         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
 156         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
 157         return 0;
 158 }
 159
 160 static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
 161                                 unsigned int new_timeout)
 162 {
 163         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 164
 165         wdog->timeout = new_timeout;
 166
 167         regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
 168                            WDOG_SEC_TO_COUNT(new_timeout));
 169         return 0;
 170 }
 171
 172 static int imx2_wdt_start(struct watchdog_device *wdog)
 173 {
 174         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 175
 176         if (imx2_wdt_is_running(wdev))
 177                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 178         else
 179                 imx2_wdt_setup(wdog);
 180
 181         set_bit(WDOG_HW_RUNNING, &wdog->status);
 182
 183         return imx2_wdt_ping(wdog);
 184 }
 185
 186 static const struct watchdog_ops imx2_wdt_ops = {
 187         .owner = THIS_MODULE,
 188         .start = imx2_wdt_start,
 189         .ping = imx2_wdt_ping,
 190         .set_timeout = imx2_wdt_set_timeout,
 191         .restart = imx2_wdt_restart,
 192 };
 193
 194 static const struct regmap_config imx2_wdt_regmap_config = {
 195         .reg_bits = 16,
 196         .reg_stride = 2,
 197         .val_bits = 16,
 198         .max_register = 0x8,
 199 };
 200
 201 static int __init imx2_wdt_probe(struct platform_device *pdev)
 202 {
 203         struct imx2_wdt_device *wdev;
 204         struct watchdog_device *wdog;
 205         struct resource *res;
 206         void __iomem *base;
 207         int ret;
 208         u32 val;
 209
 210         wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
 211         if (!wdev)
 212                 return -ENOMEM;
 213
 214         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 215         base = devm_ioremap_resource(&pdev->dev, res);
 216         if (IS_ERR(base))
 217                 return PTR_ERR(base);
 218
 219         wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
 220                                                  &imx2_wdt_regmap_config);
 221         if (IS_ERR(wdev->regmap)) {
 222                 dev_err(&pdev->dev, "regmap init failed\n");
 223                 return PTR_ERR(wdev->regmap);
 224         }
 225
 226         wdev->clk = devm_clk_get(&pdev->dev, NULL);
 227         if (IS_ERR(wdev->clk)) {
 228                 dev_err(&pdev->dev, "can't get Watchdog clock\n");
 229                 return PTR_ERR(wdev->clk);
 230         }
 231
 232         wdog                    = &wdev->wdog;
 233         wdog->info              = &imx2_wdt_info;
 234         wdog->ops               = &imx2_wdt_ops;
 235         wdog->min_timeout       = 1;
 236         wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
 237         wdog->parent            = &pdev->dev;
 238
 239         ret = clk_prepare_enable(wdev->clk);
 240         if (ret)
 241                 return ret;
 242
 243         regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
 244         wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
 245
 246         wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
 247                                                 "fsl,ext-reset-output");
 248         wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
 249         if (wdog->timeout != timeout)
 250                 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
 251                          timeout, wdog->timeout);
 252
 253         platform_set_drvdata(pdev, wdog);
 254         watchdog_set_drvdata(wdog, wdev);
 255         watchdog_set_nowayout(wdog, nowayout);
 256         watchdog_set_restart_priority(wdog, 128);
 257         watchdog_init_timeout(wdog, timeout, &pdev->dev);
 258
 259         if (imx2_wdt_is_running(wdev)) {
 260                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 261                 set_bit(WDOG_HW_RUNNING, &wdog->status);
 262         }
 263
 264         /*
 265          * Disable the watchdog power down counter at boot. Otherwise the power
 266          * down counter will pull down the #WDOG interrupt line for one clock
 267          * cycle.
 268          */
 269         regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
 270
 271         ret = watchdog_register_device(wdog);
 272         if (ret) {
 273                 dev_err(&pdev->dev, "cannot register watchdog device\n");
 274                 goto disable_clk;
 275         }
 276
 277         dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
 278                  wdog->timeout, nowayout);
 279
 280         return 0;
 281
 282 disable_clk:
 283         clk_disable_unprepare(wdev->clk);
 284         return ret;
 285 }
 286
 287 static int __exit imx2_wdt_remove(struct platform_device *pdev)
 288 {
 289         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 290         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 291
 292         watchdog_unregister_device(wdog);
 293
 294         if (imx2_wdt_is_running(wdev)) {
 295                 imx2_wdt_ping(wdog);
 296                 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
 297         }
 298         return 0;
 299 }
 300
 301 static void imx2_wdt_shutdown(struct platform_device *pdev)
 302 {
 303         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 304         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 305
 306         if (imx2_wdt_is_running(wdev)) {
 307                 /*
 308                  * We are running, configure max timeout before reboot
 309                  * will take place.
 310                  */
 311                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 312                 imx2_wdt_ping(wdog);
 313                 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
 314         }
 315 }
 316
 317 #ifdef CONFIG_PM_SLEEP
 318 /* Disable watchdog if it is active or non-active but still running */
 319 static int imx2_wdt_suspend(struct device *dev)
 320 {
 321         struct watchdog_device *wdog = dev_get_drvdata(dev);
 322         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 323
 324         /* The watchdog IP block is running */
 325         if (imx2_wdt_is_running(wdev)) {
 326                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 327                 imx2_wdt_ping(wdog);
 328         }
 329
 330         clk_disable_unprepare(wdev->clk);
 331
 332         return 0;
 333 }
 334
 335 /* Enable watchdog and configure it if necessary */
 336 static int imx2_wdt_resume(struct device *dev)
 337 {
 338         struct watchdog_device *wdog = dev_get_drvdata(dev);
 339         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 340         int ret;
 341
 342         ret = clk_prepare_enable(wdev->clk);
 343         if (ret)
 344                 return ret;
 345
 346         if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
 347                 /*
 348                  * If the watchdog is still active and resumes
 349                  * from deep sleep state, need to restart the
 350                  * watchdog again.
 351                  */
 352                 imx2_wdt_setup(wdog);
 353         }
 354         if (imx2_wdt_is_running(wdev)) {
 355                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 356                 imx2_wdt_ping(wdog);
 357         }
 358
 359         return 0;
 360 }
 361 #endif
 362
 363 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
 364                          imx2_wdt_resume);
 365
 366 static const struct of_device_id imx2_wdt_dt_ids[] = {
 367         { .compatible = "fsl,imx21-wdt", },
 368         { /* sentinel */ }
 369 };
 370 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
 371
 372 static struct platform_driver imx2_wdt_driver = {
 373         .remove         = __exit_p(imx2_wdt_remove),
 374         .shutdown       = imx2_wdt_shutdown,
 375         .driver         = {
 376                 .name   = DRIVER_NAME,
 377                 .pm     = &imx2_wdt_pm_ops,
 378                 .of_match_table = imx2_wdt_dt_ids,
 379         },
 380 };
 381
 382 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
 383
 384 MODULE_AUTHOR("Wolfram Sang");
 385 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
 386 MODULE_LICENSE("GPL v2");
 387 MODULE_ALIAS("platform:" DRIVER_NAME);