include/linux/mfd/palmas.h

   1 /*
   2  * TI Palmas
   3  *
   4  * Copyright 2011-2013 Texas Instruments Inc.
   5  *
   6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
   7  * Author: Ian Lartey <ian@slimlogic.co.uk>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under  the terms of the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the License, or (at your
  12  *  option) any later version.
  13  *
  14  */
  15
  16 #ifndef __LINUX_MFD_PALMAS_H
  17 #define __LINUX_MFD_PALMAS_H
  18
  19 #include <linux/usb/otg.h>
  20 #include <linux/leds.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/driver.h>
  23 #include <linux/extcon.h>
  24 #include <linux/usb/phy_companion.h>
  25
  26 #define PALMAS_NUM_CLIENTS              3
  27
  28 /* The ID_REVISION NUMBERS */
  29 #define PALMAS_CHIP_OLD_ID              0x0000
  30 #define PALMAS_CHIP_ID                  0xC035
  31 #define PALMAS_CHIP_CHARGER_ID          0xC036
  32
  33 #define is_palmas(a)    (((a) == PALMAS_CHIP_OLD_ID) || \
  34                         ((a) == PALMAS_CHIP_ID))
  35 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
  36
  37 struct palmas_pmic;
  38 struct palmas_gpadc;
  39 struct palmas_resource;
  40 struct palmas_usb;
  41
  42 enum palmas_usb_state {
  43         PALMAS_USB_STATE_DISCONNECT,
  44         PALMAS_USB_STATE_VBUS,
  45         PALMAS_USB_STATE_ID,
  46 };
  47
  48 struct palmas {
  49         struct device *dev;
  50
  51         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
  52         struct regmap *regmap[PALMAS_NUM_CLIENTS];
  53
  54         /* Stored chip id */
  55         int id;
  56
  57         /* IRQ Data */
  58         int irq;
  59         u32 irq_mask;
  60         struct mutex irq_lock;
  61         struct regmap_irq_chip_data *irq_data;
  62
  63         /* Child Devices */
  64         struct palmas_pmic *pmic;
  65         struct palmas_gpadc *gpadc;
  66         struct palmas_resource *resource;
  67         struct palmas_usb *usb;
  68
  69         /* GPIO MUXing */
  70         u8 gpio_muxed;
  71         u8 led_muxed;
  72         u8 pwm_muxed;
  73 };
  74
  75 struct palmas_gpadc_platform_data {
  76         /* Channel 3 current source is only enabled during conversion */
  77         int ch3_current;
  78
  79         /* Channel 0 current source can be used for battery detection.
  80          * If used for battery detection this will cause a permanent current
  81          * consumption depending on current level set here.
  82          */
  83         int ch0_current;
  84
  85         /* default BAT_REMOVAL_DAT setting on device probe */
  86         int bat_removal;
  87
  88         /* Sets the START_POLARITY bit in the RT_CTRL register */
  89         int start_polarity;
  90 };
  91
  92 struct palmas_reg_init {
  93         /* warm_rest controls the voltage levels after a warm reset
  94          *
  95          * 0: reload default values from OTP on warm reset
  96          * 1: maintain voltage from VSEL on warm reset
  97          */
  98         int warm_reset;
  99
 100         /* roof_floor controls whether the regulator uses the i2c style
 101          * of DVS or uses the method where a GPIO or other control method is
 102          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
 103          *
 104          * For SMPS
 105          *
 106          * 0: i2c selection of voltage
 107          * 1: pin selection of voltage.
 108          *
 109          * For LDO unused
 110          */
 111         int roof_floor;
 112
 113         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
 114          * the data sheet.
 115          *
 116          * For SMPS
 117          *
 118          * 0: Off
 119          * 1: AUTO
 120          * 2: ECO
 121          * 3: Forced PWM
 122          *
 123          * For LDO
 124          *
 125          * 0: Off
 126          * 1: On
 127          */
 128         int mode_sleep;
 129
 130         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
 131          * register. Set this is the default voltage set in OTP needs
 132          * to be overridden.
 133          */
 134         u8 vsel;
 135
 136 };
 137
 138 enum palmas_regulators {
 139         /* SMPS regulators */
 140         PALMAS_REG_SMPS12,
 141         PALMAS_REG_SMPS123,
 142         PALMAS_REG_SMPS3,
 143         PALMAS_REG_SMPS45,
 144         PALMAS_REG_SMPS457,
 145         PALMAS_REG_SMPS6,
 146         PALMAS_REG_SMPS7,
 147         PALMAS_REG_SMPS8,
 148         PALMAS_REG_SMPS9,
 149         PALMAS_REG_SMPS10,
 150         /* LDO regulators */
 151         PALMAS_REG_LDO1,
 152         PALMAS_REG_LDO2,
 153         PALMAS_REG_LDO3,
 154         PALMAS_REG_LDO4,
 155         PALMAS_REG_LDO5,
 156         PALMAS_REG_LDO6,
 157         PALMAS_REG_LDO7,
 158         PALMAS_REG_LDO8,
 159         PALMAS_REG_LDO9,
 160         PALMAS_REG_LDOLN,
 161         PALMAS_REG_LDOUSB,
 162         /* External regulators */
 163         PALMAS_REG_REGEN1,
 164         PALMAS_REG_REGEN2,
 165         PALMAS_REG_REGEN3,
 166         PALMAS_REG_SYSEN1,
 167         PALMAS_REG_SYSEN2,
 168         /* Total number of regulators */
 169         PALMAS_NUM_REGS,
 170 };
 171
 172 struct palmas_pmic_platform_data {
 173         /* An array of pointers to regulator init data indexed by regulator
 174          * ID
 175          */
 176         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
 177
 178         /* An array of pointers to structures containing sleep mode and DVS
 179          * configuration for regulators indexed by ID
 180          */
 181         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
 182
 183         /* use LDO6 for vibrator control */
 184         int ldo6_vibrator;
 185
 186         /* Enable tracking mode of LDO8 */
 187         bool enable_ldo8_tracking;
 188 };
 189
 190 struct palmas_usb_platform_data {
 191         /* Do we enable the wakeup comparator on probe */
 192         int wakeup;
 193 };
 194
 195 struct palmas_resource_platform_data {
 196         int regen1_mode_sleep;
 197         int regen2_mode_sleep;
 198         int sysen1_mode_sleep;
 199         int sysen2_mode_sleep;
 200
 201         /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
 202         u8 nsleep_res;
 203         /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
 204         u8 nsleep_smps;
 205         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
 206         u8 nsleep_ldo1;
 207         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
 208         u8 nsleep_ldo2;
 209
 210         /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
 211         u8 enable1_res;
 212         /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
 213         u8 enable1_smps;
 214         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
 215         u8 enable1_ldo1;
 216         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
 217         u8 enable1_ldo2;
 218
 219         /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
 220         u8 enable2_res;
 221         /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
 222         u8 enable2_smps;
 223         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
 224         u8 enable2_ldo1;
 225         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
 226         u8 enable2_ldo2;
 227 };
 228
 229 struct palmas_clk_platform_data {
 230         int clk32kg_mode_sleep;
 231         int clk32kgaudio_mode_sleep;
 232 };
 233
 234 struct palmas_platform_data {
 235         int irq_flags;
 236         int gpio_base;
 237
 238         /* bit value to be loaded to the POWER_CTRL register */
 239         u8 power_ctrl;
 240
 241         /*
 242          * boolean to select if we want to configure muxing here
 243          * then the two value to load into the registers if true
 244          */
 245         int mux_from_pdata;
 246         u8 pad1, pad2;
 247
 248         struct palmas_pmic_platform_data *pmic_pdata;
 249         struct palmas_gpadc_platform_data *gpadc_pdata;
 250         struct palmas_usb_platform_data *usb_pdata;
 251         struct palmas_resource_platform_data *resource_pdata;
 252         struct palmas_clk_platform_data *clk_pdata;
 253 };
 254
 255 struct palmas_gpadc_calibration {
 256         s32 gain;
 257         s32 gain_error;
 258         s32 offset_error;
 259 };
 260
 261 struct palmas_gpadc {
 262         struct device *dev;
 263         struct palmas *palmas;
 264
 265         int ch3_current;
 266         int ch0_current;
 267
 268         int gpadc_force;
 269
 270         int bat_removal;
 271
 272         struct mutex reading_lock;
 273         struct completion irq_complete;
 274
 275         int eoc_sw_irq;
 276
 277         struct palmas_gpadc_calibration *palmas_cal_tbl;
 278
 279         int conv0_channel;
 280         int conv1_channel;
 281         int rt_channel;
 282 };
 283
 284 struct palmas_gpadc_result {
 285         s32 raw_code;
 286         s32 corrected_code;
 287         s32 result;
 288 };
 289
 290 #define PALMAS_MAX_CHANNELS 16
 291
 292 /* Define the palmas IRQ numbers */
 293 enum palmas_irqs {
 294         /* INT1 registers */
 295         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
 296         PALMAS_PWRON_IRQ,
 297         PALMAS_LONG_PRESS_KEY_IRQ,
 298         PALMAS_RPWRON_IRQ,
 299         PALMAS_PWRDOWN_IRQ,
 300         PALMAS_HOTDIE_IRQ,
 301         PALMAS_VSYS_MON_IRQ,
 302         PALMAS_VBAT_MON_IRQ,
 303         /* INT2 registers */
 304         PALMAS_RTC_ALARM_IRQ,
 305         PALMAS_RTC_TIMER_IRQ,
 306         PALMAS_WDT_IRQ,
 307         PALMAS_BATREMOVAL_IRQ,
 308         PALMAS_RESET_IN_IRQ,
 309         PALMAS_FBI_BB_IRQ,
 310         PALMAS_SHORT_IRQ,
 311         PALMAS_VAC_ACOK_IRQ,
 312         /* INT3 registers */
 313         PALMAS_GPADC_AUTO_0_IRQ,
 314         PALMAS_GPADC_AUTO_1_IRQ,
 315         PALMAS_GPADC_EOC_SW_IRQ,
 316         PALMAS_GPADC_EOC_RT_IRQ,
 317         PALMAS_ID_OTG_IRQ,
 318         PALMAS_ID_IRQ,
 319         PALMAS_VBUS_OTG_IRQ,
 320         PALMAS_VBUS_IRQ,
 321         /* INT4 registers */
 322         PALMAS_GPIO_0_IRQ,
 323         PALMAS_GPIO_1_IRQ,
 324         PALMAS_GPIO_2_IRQ,
 325         PALMAS_GPIO_3_IRQ,
 326         PALMAS_GPIO_4_IRQ,
 327         PALMAS_GPIO_5_IRQ,
 328         PALMAS_GPIO_6_IRQ,
 329         PALMAS_GPIO_7_IRQ,
 330         /* Total Number IRQs */
 331         PALMAS_NUM_IRQ,
 332 };
 333
 334 struct palmas_pmic {
 335         struct palmas *palmas;
 336         struct device *dev;
 337         struct regulator_desc desc[PALMAS_NUM_REGS];
 338         struct regulator_dev *rdev[PALMAS_NUM_REGS];
 339         struct mutex mutex;
 340
 341         int smps123;
 342         int smps457;
 343
 344         int range[PALMAS_REG_SMPS10];
 345         unsigned int ramp_delay[PALMAS_REG_SMPS10];
 346         unsigned int current_reg_mode[PALMAS_REG_SMPS10];
 347 };
 348
 349 struct palmas_resource {
 350         struct palmas *palmas;
 351         struct device *dev;
 352 };
 353
 354 struct palmas_usb {
 355         struct palmas *palmas;
 356         struct device *dev;
 357
 358         struct extcon_dev edev;
 359
 360         /* used to set vbus, in atomic path */
 361         struct work_struct set_vbus_work;
 362
 363         int id_otg_irq;
 364         int id_irq;
 365         int vbus_otg_irq;
 366         int vbus_irq;
 367
 368         int vbus_enable;
 369
 370         enum palmas_usb_state linkstat;
 371 };
 372
 373 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
 374
 375 enum usb_irq_events {
 376         /* Wakeup events from INT3 */
 377         PALMAS_USB_ID_WAKEPUP,
 378         PALMAS_USB_VBUS_WAKEUP,
 379
 380         /* ID_OTG_EVENTS */
 381         PALMAS_USB_ID_GND,
 382         N_PALMAS_USB_ID_GND,
 383         PALMAS_USB_ID_C,
 384         N_PALMAS_USB_ID_C,
 385         PALMAS_USB_ID_B,
 386         N_PALMAS_USB_ID_B,
 387         PALMAS_USB_ID_A,
 388         N_PALMAS_USB_ID_A,
 389         PALMAS_USB_ID_FLOAT,
 390         N_PALMAS_USB_ID_FLOAT,
 391
 392         /* VBUS_OTG_EVENTS */
 393         PALMAS_USB_VB_SESS_END,
 394         N_PALMAS_USB_VB_SESS_END,
 395         PALMAS_USB_VB_SESS_VLD,
 396         N_PALMAS_USB_VB_SESS_VLD,
 397         PALMAS_USB_VA_SESS_VLD,
 398         N_PALMAS_USB_VA_SESS_VLD,
 399         PALMAS_USB_VA_VBUS_VLD,
 400         N_PALMAS_USB_VA_VBUS_VLD,
 401         PALMAS_USB_VADP_SNS,
 402         N_PALMAS_USB_VADP_SNS,
 403         PALMAS_USB_VADP_PRB,
 404         N_PALMAS_USB_VADP_PRB,
 405         PALMAS_USB_VOTG_SESS_VLD,
 406         N_PALMAS_USB_VOTG_SESS_VLD,
 407 };
 408
 409 /* defines so we can store the mux settings */
 410 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
 411 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
 412 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
 413 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
 414 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
 415 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
 416 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
 417 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
 418
 419 #define PALMAS_LED1_MUXED                                       (1 << 0)
 420 #define PALMAS_LED2_MUXED                                       (1 << 1)
 421
 422 #define PALMAS_PWM1_MUXED                                       (1 << 0)
 423 #define PALMAS_PWM2_MUXED                                       (1 << 1)
 424
 425 /* helper macro to get correct slave number */
 426 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
 427 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
 428
 429 /* Base addresses of IP blocks in Palmas */
 430 #define PALMAS_SMPS_DVS_BASE                                    0x20
 431 #define PALMAS_RTC_BASE                                         0x100
 432 #define PALMAS_VALIDITY_BASE                                    0x118
 433 #define PALMAS_SMPS_BASE                                        0x120
 434 #define PALMAS_LDO_BASE                                         0x150
 435 #define PALMAS_DVFS_BASE                                        0x180
 436 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
 437 #define PALMAS_RESOURCE_BASE                                    0x1D4
 438 #define PALMAS_PU_PD_OD_BASE                                    0x1F4
 439 #define PALMAS_LED_BASE                                         0x200
 440 #define PALMAS_INTERRUPT_BASE                                   0x210
 441 #define PALMAS_USB_OTG_BASE                                     0x250
 442 #define PALMAS_VIBRATOR_BASE                                    0x270
 443 #define PALMAS_GPIO_BASE                                        0x280
 444 #define PALMAS_USB_BASE                                         0x290
 445 #define PALMAS_GPADC_BASE                                       0x2C0
 446 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
 447
 448 /* Registers for function RTC */
 449 #define PALMAS_SECONDS_REG                                      0x0
 450 #define PALMAS_MINUTES_REG                                      0x1
 451 #define PALMAS_HOURS_REG                                        0x2
 452 #define PALMAS_DAYS_REG                                         0x3
 453 #define PALMAS_MONTHS_REG                                       0x4
 454 #define PALMAS_YEARS_REG                                        0x5
 455 #define PALMAS_WEEKS_REG                                        0x6
 456 #define PALMAS_ALARM_SECONDS_REG                                0x8
 457 #define PALMAS_ALARM_MINUTES_REG                                0x9
 458 #define PALMAS_ALARM_HOURS_REG                                  0xA
 459 #define PALMAS_ALARM_DAYS_REG                                   0xB
 460 #define PALMAS_ALARM_MONTHS_REG                                 0xC
 461 #define PALMAS_ALARM_YEARS_REG                                  0xD
 462 #define PALMAS_RTC_CTRL_REG                                     0x10
 463 #define PALMAS_RTC_STATUS_REG                                   0x11
 464 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
 465 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
 466 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
 467 #define PALMAS_RTC_RES_PROG_REG                                 0x15
 468 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
 469
 470 /* Bit definitions for SECONDS_REG */
 471 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
 472 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
 473 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
 474 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
 475
 476 /* Bit definitions for MINUTES_REG */
 477 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
 478 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
 479 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
 480 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
 481
 482 /* Bit definitions for HOURS_REG */
 483 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
 484 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
 485 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
 486 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
 487 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
 488 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
 489
 490 /* Bit definitions for DAYS_REG */
 491 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
 492 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
 493 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
 494 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
 495
 496 /* Bit definitions for MONTHS_REG */
 497 #define PALMAS_MONTHS_REG_MONTH1                                0x10
 498 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
 499 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
 500 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
 501
 502 /* Bit definitions for YEARS_REG */
 503 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
 504 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
 505 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
 506 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
 507
 508 /* Bit definitions for WEEKS_REG */
 509 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
 510 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
 511
 512 /* Bit definitions for ALARM_SECONDS_REG */
 513 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
 514 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
 515 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
 516 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
 517
 518 /* Bit definitions for ALARM_MINUTES_REG */
 519 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
 520 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
 521 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
 522 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
 523
 524 /* Bit definitions for ALARM_HOURS_REG */
 525 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
 526 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
 527 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
 528 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
 529 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
 530 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
 531
 532 /* Bit definitions for ALARM_DAYS_REG */
 533 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
 534 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
 535 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
 536 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
 537
 538 /* Bit definitions for ALARM_MONTHS_REG */
 539 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
 540 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
 541 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
 542 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
 543
 544 /* Bit definitions for ALARM_YEARS_REG */
 545 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
 546 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
 547 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
 548 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
 549
 550 /* Bit definitions for RTC_CTRL_REG */
 551 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
 552 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
 553 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
 554 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
 555 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
 556 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
 557 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
 558 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
 559 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
 560 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
 561 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
 562 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
 563 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
 564 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
 565 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
 566 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
 567
 568 /* Bit definitions for RTC_STATUS_REG */
 569 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
 570 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
 571 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
 572 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
 573 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
 574 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
 575 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
 576 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
 577 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
 578 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
 579 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
 580 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
 581 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
 582 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
 583
 584 /* Bit definitions for RTC_INTERRUPTS_REG */
 585 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
 586 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
 587 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
 588 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
 589 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
 590 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
 591 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
 592 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
 593
 594 /* Bit definitions for RTC_COMP_LSB_REG */
 595 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
 596 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
 597
 598 /* Bit definitions for RTC_COMP_MSB_REG */
 599 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
 600 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
 601
 602 /* Bit definitions for RTC_RES_PROG_REG */
 603 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
 604 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
 605
 606 /* Bit definitions for RTC_RESET_STATUS_REG */
 607 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
 608 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
 609
 610 /* Registers for function BACKUP */
 611 #define PALMAS_BACKUP0                                          0x0
 612 #define PALMAS_BACKUP1                                          0x1
 613 #define PALMAS_BACKUP2                                          0x2
 614 #define PALMAS_BACKUP3                                          0x3
 615 #define PALMAS_BACKUP4                                          0x4
 616 #define PALMAS_BACKUP5                                          0x5
 617 #define PALMAS_BACKUP6                                          0x6
 618 #define PALMAS_BACKUP7                                          0x7
 619
 620 /* Bit definitions for BACKUP0 */
 621 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
 622 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
 623
 624 /* Bit definitions for BACKUP1 */
 625 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
 626 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
 627
 628 /* Bit definitions for BACKUP2 */
 629 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
 630 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
 631
 632 /* Bit definitions for BACKUP3 */
 633 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
 634 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
 635
 636 /* Bit definitions for BACKUP4 */
 637 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
 638 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
 639
 640 /* Bit definitions for BACKUP5 */
 641 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
 642 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
 643
 644 /* Bit definitions for BACKUP6 */
 645 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
 646 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
 647
 648 /* Bit definitions for BACKUP7 */
 649 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
 650 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
 651
 652 /* Registers for function SMPS */
 653 #define PALMAS_SMPS12_CTRL                                      0x0
 654 #define PALMAS_SMPS12_TSTEP                                     0x1
 655 #define PALMAS_SMPS12_FORCE                                     0x2
 656 #define PALMAS_SMPS12_VOLTAGE                                   0x3
 657 #define PALMAS_SMPS3_CTRL                                       0x4
 658 #define PALMAS_SMPS3_VOLTAGE                                    0x7
 659 #define PALMAS_SMPS45_CTRL                                      0x8
 660 #define PALMAS_SMPS45_TSTEP                                     0x9
 661 #define PALMAS_SMPS45_FORCE                                     0xA
 662 #define PALMAS_SMPS45_VOLTAGE                                   0xB
 663 #define PALMAS_SMPS6_CTRL                                       0xC
 664 #define PALMAS_SMPS6_TSTEP                                      0xD
 665 #define PALMAS_SMPS6_FORCE                                      0xE
 666 #define PALMAS_SMPS6_VOLTAGE                                    0xF
 667 #define PALMAS_SMPS7_CTRL                                       0x10
 668 #define PALMAS_SMPS7_VOLTAGE                                    0x13
 669 #define PALMAS_SMPS8_CTRL                                       0x14
 670 #define PALMAS_SMPS8_TSTEP                                      0x15
 671 #define PALMAS_SMPS8_FORCE                                      0x16
 672 #define PALMAS_SMPS8_VOLTAGE                                    0x17
 673 #define PALMAS_SMPS9_CTRL                                       0x18
 674 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
 675 #define PALMAS_SMPS10_CTRL                                      0x1C
 676 #define PALMAS_SMPS10_STATUS                                    0x1F
 677 #define PALMAS_SMPS_CTRL                                        0x24
 678 #define PALMAS_SMPS_PD_CTRL                                     0x25
 679 #define PALMAS_SMPS_DITHER_EN                                   0x26
 680 #define PALMAS_SMPS_THERMAL_EN                                  0x27
 681 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
 682 #define PALMAS_SMPS_SHORT_STATUS                                0x29
 683 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
 684 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
 685 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
 686
 687 /* Bit definitions for SMPS12_CTRL */
 688 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
 689 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
 690 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
 691 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
 692 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
 693 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
 694 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
 695 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
 696 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
 697 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
 698
 699 /* Bit definitions for SMPS12_TSTEP */
 700 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
 701 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
 702
 703 /* Bit definitions for SMPS12_FORCE */
 704 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
 705 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
 706 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
 707 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
 708
 709 /* Bit definitions for SMPS12_VOLTAGE */
 710 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
 711 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
 712 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
 713 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
 714
 715 /* Bit definitions for SMPS3_CTRL */
 716 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
 717 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
 718 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
 719 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
 720 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
 721 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
 722 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
 723 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
 724
 725 /* Bit definitions for SMPS3_VOLTAGE */
 726 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
 727 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
 728 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
 729 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
 730
 731 /* Bit definitions for SMPS45_CTRL */
 732 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
 733 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
 734 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
 735 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
 736 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
 737 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
 738 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
 739 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
 740 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
 741 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
 742
 743 /* Bit definitions for SMPS45_TSTEP */
 744 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
 745 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
 746
 747 /* Bit definitions for SMPS45_FORCE */
 748 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
 749 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
 750 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
 751 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
 752
 753 /* Bit definitions for SMPS45_VOLTAGE */
 754 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
 755 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
 756 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
 757 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
 758
 759 /* Bit definitions for SMPS6_CTRL */
 760 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
 761 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
 762 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
 763 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
 764 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
 765 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
 766 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
 767 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
 768 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
 769 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
 770
 771 /* Bit definitions for SMPS6_TSTEP */
 772 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
 773 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
 774
 775 /* Bit definitions for SMPS6_FORCE */
 776 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
 777 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
 778 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
 779 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
 780
 781 /* Bit definitions for SMPS6_VOLTAGE */
 782 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
 783 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
 784 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
 785 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
 786
 787 /* Bit definitions for SMPS7_CTRL */
 788 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
 789 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
 790 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
 791 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
 792 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
 793 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
 794 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
 795 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
 796
 797 /* Bit definitions for SMPS7_VOLTAGE */
 798 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
 799 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
 800 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
 801 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
 802
 803 /* Bit definitions for SMPS8_CTRL */
 804 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
 805 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
 806 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
 807 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
 808 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
 809 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
 810 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
 811 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
 812 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
 813 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
 814
 815 /* Bit definitions for SMPS8_TSTEP */
 816 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
 817 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
 818
 819 /* Bit definitions for SMPS8_FORCE */
 820 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
 821 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
 822 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
 823 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
 824
 825 /* Bit definitions for SMPS8_VOLTAGE */
 826 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
 827 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
 828 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
 829 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
 830
 831 /* Bit definitions for SMPS9_CTRL */
 832 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
 833 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
 834 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
 835 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
 836 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
 837 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
 838 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
 839 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
 840
 841 /* Bit definitions for SMPS9_VOLTAGE */
 842 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
 843 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
 844 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
 845 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
 846
 847 /* Bit definitions for SMPS10_CTRL */
 848 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
 849 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
 850 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
 851 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
 852
 853 /* Bit definitions for SMPS10_STATUS */
 854 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
 855 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
 856
 857 /* Bit definitions for SMPS_CTRL */
 858 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
 859 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
 860 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
 861 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
 862 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
 863 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
 864 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
 865 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
 866
 867 /* Bit definitions for SMPS_PD_CTRL */
 868 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
 869 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
 870 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
 871 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
 872 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
 873 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
 874 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
 875 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
 876 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
 877 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
 878 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
 879 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
 880 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
 881 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
 882
 883 /* Bit definitions for SMPS_THERMAL_EN */
 884 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
 885 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
 886 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
 887 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
 888 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
 889 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
 890 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
 891 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
 892 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
 893 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
 894
 895 /* Bit definitions for SMPS_THERMAL_STATUS */
 896 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
 897 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
 898 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
 899 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
 900 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
 901 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
 902 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
 903 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
 904 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
 905 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
 906
 907 /* Bit definitions for SMPS_SHORT_STATUS */
 908 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
 909 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
 910 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
 911 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
 912 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
 913 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
 914 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
 915 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
 916 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
 917 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
 918 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
 919 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
 920 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
 921 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
 922 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
 923 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
 924
 925 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
 926 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
 927 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
 928 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
 929 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
 930 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
 931 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
 932 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
 933 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
 934 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
 935 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
 936 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
 937 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
 938 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
 939 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
 940
 941 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
 942 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
 943 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
 944 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
 945 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
 946 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
 947 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
 948 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
 949 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
 950 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
 951 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
 952 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
 953 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
 954 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
 955 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
 956 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
 957 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
 958
 959 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
 960 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
 961 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
 962 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
 963 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
 964 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
 965 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
 966 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
 967 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
 968
 969 /* Registers for function LDO */
 970 #define PALMAS_LDO1_CTRL                                        0x0
 971 #define PALMAS_LDO1_VOLTAGE                                     0x1
 972 #define PALMAS_LDO2_CTRL                                        0x2
 973 #define PALMAS_LDO2_VOLTAGE                                     0x3
 974 #define PALMAS_LDO3_CTRL                                        0x4
 975 #define PALMAS_LDO3_VOLTAGE                                     0x5
 976 #define PALMAS_LDO4_CTRL                                        0x6
 977 #define PALMAS_LDO4_VOLTAGE                                     0x7
 978 #define PALMAS_LDO5_CTRL                                        0x8
 979 #define PALMAS_LDO5_VOLTAGE                                     0x9
 980 #define PALMAS_LDO6_CTRL                                        0xA
 981 #define PALMAS_LDO6_VOLTAGE                                     0xB
 982 #define PALMAS_LDO7_CTRL                                        0xC
 983 #define PALMAS_LDO7_VOLTAGE                                     0xD
 984 #define PALMAS_LDO8_CTRL                                        0xE
 985 #define PALMAS_LDO8_VOLTAGE                                     0xF
 986 #define PALMAS_LDO9_CTRL                                        0x10
 987 #define PALMAS_LDO9_VOLTAGE                                     0x11
 988 #define PALMAS_LDOLN_CTRL                                       0x12
 989 #define PALMAS_LDOLN_VOLTAGE                                    0x13
 990 #define PALMAS_LDOUSB_CTRL                                      0x14
 991 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
 992 #define PALMAS_LDO_CTRL                                         0x1A
 993 #define PALMAS_LDO_PD_CTRL1                                     0x1B
 994 #define PALMAS_LDO_PD_CTRL2                                     0x1C
 995 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
 996 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
 997
 998 /* Bit definitions for LDO1_CTRL */
 999 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
1000 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
1001 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
1002 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
1003 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
1004 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
1005 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
1006 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
1007
1008 /* Bit definitions for LDO1_VOLTAGE */
1009 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
1010 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
1011
1012 /* Bit definitions for LDO2_CTRL */
1013 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
1014 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
1015 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
1016 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
1017 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
1018 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
1019 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
1020 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
1021
1022 /* Bit definitions for LDO2_VOLTAGE */
1023 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
1024 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
1025
1026 /* Bit definitions for LDO3_CTRL */
1027 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
1028 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
1029 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
1030 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
1031 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
1032 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
1033 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
1034 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
1035
1036 /* Bit definitions for LDO3_VOLTAGE */
1037 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
1038 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
1039
1040 /* Bit definitions for LDO4_CTRL */
1041 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
1042 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
1043 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
1044 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
1045 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
1046 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
1047 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
1048 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
1049
1050 /* Bit definitions for LDO4_VOLTAGE */
1051 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
1052 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
1053
1054 /* Bit definitions for LDO5_CTRL */
1055 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
1056 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
1057 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
1058 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
1059 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
1060 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
1061 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
1062 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
1063
1064 /* Bit definitions for LDO5_VOLTAGE */
1065 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
1066 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
1067
1068 /* Bit definitions for LDO6_CTRL */
1069 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
1070 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
1071 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
1072 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
1073 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
1074 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
1075 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
1076 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
1077 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
1078 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
1079
1080 /* Bit definitions for LDO6_VOLTAGE */
1081 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
1082 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
1083
1084 /* Bit definitions for LDO7_CTRL */
1085 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
1086 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
1087 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
1088 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
1089 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
1090 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
1091 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
1092 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
1093
1094 /* Bit definitions for LDO7_VOLTAGE */
1095 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
1096 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
1097
1098 /* Bit definitions for LDO8_CTRL */
1099 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
1100 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
1101 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
1102 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
1103 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
1104 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
1105 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
1106 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
1107 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
1108 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
1109
1110 /* Bit definitions for LDO8_VOLTAGE */
1111 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
1112 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
1113
1114 /* Bit definitions for LDO9_CTRL */
1115 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
1116 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
1117 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
1118 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
1119 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
1120 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
1121 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1122 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
1123 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1124 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
1125
1126 /* Bit definitions for LDO9_VOLTAGE */
1127 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
1128 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
1129
1130 /* Bit definitions for LDOLN_CTRL */
1131 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1132 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
1133 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1134 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
1135 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1136 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
1137 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1138 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
1139
1140 /* Bit definitions for LDOLN_VOLTAGE */
1141 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
1142 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
1143
1144 /* Bit definitions for LDOUSB_CTRL */
1145 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1146 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
1147 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1148 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
1149 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1150 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
1151 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1152 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
1153
1154 /* Bit definitions for LDOUSB_VOLTAGE */
1155 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
1156 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
1157
1158 /* Bit definitions for LDO_CTRL */
1159 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1160 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
1161
1162 /* Bit definitions for LDO_PD_CTRL1 */
1163 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1164 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
1165 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1166 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
1167 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1168 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
1169 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1170 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1171 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1172 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1173 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1174 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1175 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1176 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1177 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1178 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1179
1180 /* Bit definitions for LDO_PD_CTRL2 */
1181 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1182 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1183 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1184 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1185 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1186 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1187
1188 /* Bit definitions for LDO_SHORT_STATUS1 */
1189 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1190 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1191 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1192 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1193 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1194 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1195 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1196 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1197 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1198 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1199 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1200 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1201 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1202 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1203 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1204 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1205
1206 /* Bit definitions for LDO_SHORT_STATUS2 */
1207 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1208 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1209 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1210 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1211 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1212 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1213 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1214 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1215
1216 /* Registers for function PMU_CONTROL */
1217 #define PALMAS_DEV_CTRL                                         0x0
1218 #define PALMAS_POWER_CTRL                                       0x1
1219 #define PALMAS_VSYS_LO                                          0x2
1220 #define PALMAS_VSYS_MON                                         0x3
1221 #define PALMAS_VBAT_MON                                         0x4
1222 #define PALMAS_WATCHDOG                                         0x5
1223 #define PALMAS_BOOT_STATUS                                      0x6
1224 #define PALMAS_BATTERY_BOUNCE                                   0x7
1225 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1226 #define PALMAS_LONG_PRESS_KEY                                   0x9
1227 #define PALMAS_OSC_THERM_CTRL                                   0xA
1228 #define PALMAS_BATDEBOUNCING                                    0xB
1229 #define PALMAS_SWOFF_HWRST                                      0xF
1230 #define PALMAS_SWOFF_COLDRST                                    0x10
1231 #define PALMAS_SWOFF_STATUS                                     0x11
1232 #define PALMAS_PMU_CONFIG                                       0x12
1233 #define PALMAS_SPARE                                            0x14
1234 #define PALMAS_PMU_SECONDARY_INT                                0x15
1235 #define PALMAS_SW_REVISION                                      0x17
1236 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1237 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1238
1239 /* Bit definitions for DEV_CTRL */
1240 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1241 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1242 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1243 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1244 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1245 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1246
1247 /* Bit definitions for POWER_CTRL */
1248 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1249 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1250 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1251 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1252 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1253 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1254
1255 /* Bit definitions for VSYS_LO */
1256 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1257 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1258
1259 /* Bit definitions for VSYS_MON */
1260 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1261 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1262 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1263 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1264
1265 /* Bit definitions for VBAT_MON */
1266 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1267 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1268 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1269 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1270
1271 /* Bit definitions for WATCHDOG */
1272 #define PALMAS_WATCHDOG_LOCK                                    0x20
1273 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1274 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1275 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1276 #define PALMAS_WATCHDOG_MODE                                    0x08
1277 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1278 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1279 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1280
1281 /* Bit definitions for BOOT_STATUS */
1282 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1283 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1284 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1285 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1286
1287 /* Bit definitions for BATTERY_BOUNCE */
1288 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1289 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1290
1291 /* Bit definitions for BACKUP_BATTERY_CTRL */
1292 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1293 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1294 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1295 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1296 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1297 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1298 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1299 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1300 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1301 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1302 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1303 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1304 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1305 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1306
1307 /* Bit definitions for LONG_PRESS_KEY */
1308 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1309 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1310 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1311 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1312 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1313 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1314 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1315 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1316
1317 /* Bit definitions for OSC_THERM_CTRL */
1318 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1319 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1320 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1321 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1322 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1323 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1324 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1325 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1326 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1327 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1328 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1329 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1330 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1331 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1332
1333 /* Bit definitions for BATDEBOUNCING */
1334 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1335 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1336 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1337 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1338 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1339 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1340
1341 /* Bit definitions for SWOFF_HWRST */
1342 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1343 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1344 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1345 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1346 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1347 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1348 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1349 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1350 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1351 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1352 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1353 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1354 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1355 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1356 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1357 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1358
1359 /* Bit definitions for SWOFF_COLDRST */
1360 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1361 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1362 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1363 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1364 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1365 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1366 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1367 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1368 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1369 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1370 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1371 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1372 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1373 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1374 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1375 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1376
1377 /* Bit definitions for SWOFF_STATUS */
1378 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1379 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1380 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1381 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1382 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1383 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1384 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1385 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1386 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1387 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
1388 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1389 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
1390 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1391 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
1392 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1393 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
1394
1395 /* Bit definitions for PMU_CONFIG */
1396 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1397 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
1398 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1399 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
1400 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1401 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
1402 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1403 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
1404 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1405 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
1406
1407 /* Bit definitions for SPARE */
1408 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1409 #define PALMAS_SPARE_SPARE_SHIFT                                3
1410 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1411 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
1412 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1413 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
1414 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1415 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
1416
1417 /* Bit definitions for PMU_SECONDARY_INT */
1418 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1419 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
1420 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1421 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
1422 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1423 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
1424 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1425 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
1426 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
1427 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
1428 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
1429 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
1430 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
1431 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
1432 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
1433 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
1434
1435 /* Bit definitions for SW_REVISION */
1436 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
1437 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
1438
1439 /* Bit definitions for EXT_CHRG_CTRL */
1440 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
1441 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
1442 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
1443 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
1444 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
1445 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
1446 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
1447 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
1448 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
1449 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
1450 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
1451 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
1452
1453 /* Bit definitions for PMU_SECONDARY_INT2 */
1454 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
1455 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
1456 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
1457 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
1458 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
1459 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
1460 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
1461 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
1462
1463 /* Registers for function RESOURCE */
1464 #define PALMAS_CLK32KG_CTRL                                     0x0
1465 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
1466 #define PALMAS_REGEN1_CTRL                                      0x2
1467 #define PALMAS_REGEN2_CTRL                                      0x3
1468 #define PALMAS_SYSEN1_CTRL                                      0x4
1469 #define PALMAS_SYSEN2_CTRL                                      0x5
1470 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
1471 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
1472 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
1473 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
1474 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
1475 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
1476 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
1477 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
1478 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
1479 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
1480 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
1481 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
1482 #define PALMAS_REGEN3_CTRL                                      0x12
1483
1484 /* Bit definitions for CLK32KG_CTRL */
1485 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
1486 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
1487 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
1488 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
1489 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
1490 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
1491
1492 /* Bit definitions for CLK32KGAUDIO_CTRL */
1493 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
1494 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
1495 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
1496 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
1497 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
1498 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
1499 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
1500 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
1501
1502 /* Bit definitions for REGEN1_CTRL */
1503 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
1504 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
1505 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
1506 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
1507 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
1508 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1509
1510 /* Bit definitions for REGEN2_CTRL */
1511 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
1512 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
1513 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
1514 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
1515 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
1516 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1517
1518 /* Bit definitions for SYSEN1_CTRL */
1519 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
1520 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
1521 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
1522 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
1523 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
1524 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1525
1526 /* Bit definitions for SYSEN2_CTRL */
1527 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
1528 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
1529 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
1530 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
1531 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
1532 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1533
1534 /* Bit definitions for NSLEEP_RES_ASSIGN */
1535 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
1536 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
1537 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
1538 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
1539 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
1540 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
1541 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
1542 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
1543 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
1544 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
1545 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
1546 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
1547 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
1548 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
1549
1550 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1551 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
1552 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
1553 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
1554 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
1555 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
1556 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
1557 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
1558 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
1559 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
1560 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
1561 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
1562 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
1563 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
1564 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
1565 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
1566 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
1567
1568 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1569 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
1570 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
1571 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
1572 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
1573 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
1574 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
1575 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
1576 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
1577 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
1578 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
1579 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
1580 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
1581 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
1582 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
1583 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
1584 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
1585
1586 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1587 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
1588 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
1589 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
1590 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
1591 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
1592 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
1593
1594 /* Bit definitions for ENABLE1_RES_ASSIGN */
1595 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
1596 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
1597 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
1598 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1599 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
1600 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
1601 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
1602 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
1603 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
1604 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
1605 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
1606 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
1607 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
1608 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
1609
1610 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1611 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
1612 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
1613 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
1614 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
1615 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
1616 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
1617 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
1618 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
1619 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
1620 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
1621 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
1622 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
1623 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
1624 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
1625 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
1626 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
1627
1628 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1629 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
1630 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
1631 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
1632 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
1633 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
1634 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
1635 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
1636 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
1637 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
1638 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
1639 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
1640 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
1641 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
1642 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
1643 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
1644 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
1645
1646 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1647 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
1648 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1649 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
1650 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
1651 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
1652 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
1653
1654 /* Bit definitions for ENABLE2_RES_ASSIGN */
1655 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
1656 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
1657 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
1658 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1659 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
1660 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
1661 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
1662 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
1663 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
1664 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
1665 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
1666 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
1667 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
1668 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
1669
1670 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1671 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
1672 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
1673 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
1674 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
1675 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
1676 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
1677 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
1678 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
1679 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
1680 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
1681 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
1682 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
1683 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
1684 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
1685 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
1686 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
1687
1688 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1689 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
1690 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
1691 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
1692 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
1693 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
1694 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
1695 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
1696 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
1697 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
1698 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
1699 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
1700 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
1701 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
1702 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
1703 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
1704 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
1705
1706 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1707 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
1708 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1709 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
1710 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
1711 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
1712 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
1713
1714 /* Bit definitions for REGEN3_CTRL */
1715 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
1716 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
1717 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
1718 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
1719 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
1720 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
1721
1722 /* Registers for function PAD_CONTROL */
1723 #define PALMAS_PU_PD_INPUT_CTRL1                                0x0
1724 #define PALMAS_PU_PD_INPUT_CTRL2                                0x1
1725 #define PALMAS_PU_PD_INPUT_CTRL3                                0x2
1726 #define PALMAS_OD_OUTPUT_CTRL                                   0x4
1727 #define PALMAS_POLARITY_CTRL                                    0x5
1728 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0x6
1729 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0x7
1730 #define PALMAS_I2C_SPI                                          0x8
1731 #define PALMAS_PU_PD_INPUT_CTRL4                                0x9
1732 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xA
1733
1734 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1735 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
1736 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
1737 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
1738 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
1739 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
1740 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
1741 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
1742 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
1743 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
1744 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
1745
1746 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1747 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
1748 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
1749 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
1750 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
1751 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
1752 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
1753 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
1754 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
1755 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
1756 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
1757 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
1758 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
1759
1760 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1761 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
1762 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
1763 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
1764 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
1765 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
1766 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
1767 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
1768 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
1769
1770 /* Bit definitions for OD_OUTPUT_CTRL */
1771 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
1772 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
1773 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
1774 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
1775 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
1776 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
1777 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
1778 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
1779
1780 /* Bit definitions for POLARITY_CTRL */
1781 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
1782 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
1783 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
1784 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
1785 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
1786 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
1787 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
1788 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
1789 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
1790 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
1791 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
1792 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
1793 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
1794 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
1795 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
1796 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
1797
1798 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1799 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
1800 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
1801 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
1802 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
1803 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
1804 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
1805 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
1806 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
1807 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
1808 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
1809 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
1810 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
1811
1812 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1813 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
1814 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
1815 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
1816 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
1817 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
1818 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
1819 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
1820 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
1821
1822 /* Bit definitions for I2C_SPI */
1823 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
1824 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
1825 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
1826 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
1827 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
1828 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
1829 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
1830 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
1831 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
1832 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
1833
1834 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1835 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
1836 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
1837 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
1838 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
1839 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
1840 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
1841 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
1842 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
1843
1844 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1845 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
1846 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
1847 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
1848 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
1849
1850 /* Registers for function LED_PWM */
1851 #define PALMAS_LED_PERIOD_CTRL                                  0x0
1852 #define PALMAS_LED_CTRL                                         0x1
1853 #define PALMAS_PWM_CTRL1                                        0x2
1854 #define PALMAS_PWM_CTRL2                                        0x3
1855
1856 /* Bit definitions for LED_PERIOD_CTRL */
1857 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
1858 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
1859 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
1860 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
1861
1862 /* Bit definitions for LED_CTRL */
1863 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
1864 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
1865 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
1866 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
1867 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
1868 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
1869 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
1870 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
1871
1872 /* Bit definitions for PWM_CTRL1 */
1873 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
1874 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
1875 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
1876 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
1877
1878 /* Bit definitions for PWM_CTRL2 */
1879 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
1880 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
1881
1882 /* Registers for function INTERRUPT */
1883 #define PALMAS_INT1_STATUS                                      0x0
1884 #define PALMAS_INT1_MASK                                        0x1
1885 #define PALMAS_INT1_LINE_STATE                                  0x2
1886 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
1887 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
1888 #define PALMAS_INT2_STATUS                                      0x5
1889 #define PALMAS_INT2_MASK                                        0x6
1890 #define PALMAS_INT2_LINE_STATE                                  0x7
1891 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
1892 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
1893 #define PALMAS_INT3_STATUS                                      0xA
1894 #define PALMAS_INT3_MASK                                        0xB
1895 #define PALMAS_INT3_LINE_STATE                                  0xC
1896 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
1897 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
1898 #define PALMAS_INT4_STATUS                                      0xF
1899 #define PALMAS_INT4_MASK                                        0x10
1900 #define PALMAS_INT4_LINE_STATE                                  0x11
1901 #define PALMAS_INT4_EDGE_DETECT1                                0x12
1902 #define PALMAS_INT4_EDGE_DETECT2                                0x13
1903 #define PALMAS_INT_CTRL                                         0x14
1904
1905 /* Bit definitions for INT1_STATUS */
1906 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
1907 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
1908 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
1909 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
1910 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
1911 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
1912 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
1913 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
1914 #define PALMAS_INT1_STATUS_RPWRON                               0x08
1915 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
1916 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
1917 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
1918 #define PALMAS_INT1_STATUS_PWRON                                0x02
1919 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
1920 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
1921 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
1922
1923 /* Bit definitions for INT1_MASK */
1924 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
1925 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
1926 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
1927 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
1928 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
1929 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
1930 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
1931 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
1932 #define PALMAS_INT1_MASK_RPWRON                                 0x08
1933 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
1934 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
1935 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
1936 #define PALMAS_INT1_MASK_PWRON                                  0x02
1937 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
1938 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
1939 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
1940
1941 /* Bit definitions for INT1_LINE_STATE */
1942 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
1943 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
1944 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
1945 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
1946 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
1947 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
1948 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
1949 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
1950 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
1951 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
1952 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
1953 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
1954 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
1955 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
1956 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
1957 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
1958
1959 /* Bit definitions for INT2_STATUS */
1960 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
1961 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
1962 #define PALMAS_INT2_STATUS_SHORT                                0x40
1963 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
1964 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
1965 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
1966 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
1967 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
1968 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
1969 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
1970 #define PALMAS_INT2_STATUS_WDT                                  0x04
1971 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
1972 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
1973 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
1974 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
1975 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
1976
1977 /* Bit definitions for INT2_MASK */
1978 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
1979 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
1980 #define PALMAS_INT2_MASK_SHORT                                  0x40
1981 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
1982 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
1983 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
1984 #define PALMAS_INT2_MASK_RESET_IN                               0x10
1985 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
1986 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
1987 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
1988 #define PALMAS_INT2_MASK_WDT                                    0x04
1989 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
1990 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
1991 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
1992 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
1993 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
1994
1995 /* Bit definitions for INT2_LINE_STATE */
1996 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
1997 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
1998 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
1999 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
2000 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
2001 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
2002 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
2003 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
2004 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
2005 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
2006 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
2007 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
2008 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
2009 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
2010 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
2011 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
2012
2013 /* Bit definitions for INT3_STATUS */
2014 #define PALMAS_INT3_STATUS_VBUS                                 0x80
2015 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
2016 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
2017 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
2018 #define PALMAS_INT3_STATUS_ID                                   0x20
2019 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
2020 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
2021 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
2022 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
2023 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
2024 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
2025 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
2026 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
2027 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
2028 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
2029 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
2030
2031 /* Bit definitions for INT3_MASK */
2032 #define PALMAS_INT3_MASK_VBUS                                   0x80
2033 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
2034 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
2035 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
2036 #define PALMAS_INT3_MASK_ID                                     0x20
2037 #define PALMAS_INT3_MASK_ID_SHIFT                               5
2038 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
2039 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
2040 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
2041 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
2042 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
2043 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
2044 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
2045 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
2046 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
2047 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
2048
2049 /* Bit definitions for INT3_LINE_STATE */
2050 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
2051 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
2052 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
2053 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
2054 #define PALMAS_INT3_LINE_STATE_ID                               0x20
2055 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
2056 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
2057 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
2058 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
2059 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
2060 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
2061 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
2062 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
2063 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
2064 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
2065 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
2066
2067 /* Bit definitions for INT4_STATUS */
2068 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
2069 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
2070 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
2071 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
2072 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
2073 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
2074 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
2075 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
2076 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
2077 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
2078 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
2079 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
2080 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
2081 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
2082 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
2083 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
2084
2085 /* Bit definitions for INT4_MASK */
2086 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
2087 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
2088 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
2089 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
2090 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
2091 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
2092 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
2093 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
2094 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
2095 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
2096 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
2097 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
2098 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
2099 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
2100 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
2101 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
2102
2103 /* Bit definitions for INT4_LINE_STATE */
2104 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
2105 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
2106 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
2107 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
2108 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2109 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
2110 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2111 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
2112 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2113 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
2114 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2115 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
2116 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2117 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
2118 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2119 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
2120
2121 /* Bit definitions for INT4_EDGE_DETECT1 */
2122 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2123 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
2124 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2125 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
2126 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2127 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
2128 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2129 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
2130 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2131 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
2132 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2133 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
2134 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2135 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
2136 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2137 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
2138
2139 /* Bit definitions for INT4_EDGE_DETECT2 */
2140 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2141 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
2142 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2143 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
2144 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2145 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
2146 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2147 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
2148 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2149 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
2150 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2151 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
2152 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2153 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
2154 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2155 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
2156
2157 /* Bit definitions for INT_CTRL */
2158 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
2159 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
2160 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
2161 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
2162
2163 /* Registers for function USB_OTG */
2164 #define PALMAS_USB_WAKEUP                                       0x3
2165 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
2166 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
2167 #define PALMAS_USB_ID_CTRL_SET                                  0x6
2168 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
2169 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
2170 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
2171 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
2172 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
2173 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
2174 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
2175 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
2176 #define PALMAS_USB_ID_INT_SRC                                   0xF
2177 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
2178 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
2179 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
2180 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
2181 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
2182 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
2183 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
2184 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
2185 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
2186 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
2187 #define PALMAS_USB_OTG_REVISION                                 0x1A
2188
2189 /* Bit definitions for USB_WAKEUP */
2190 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
2191 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
2192
2193 /* Bit definitions for USB_VBUS_CTRL_SET */
2194 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
2195 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
2196 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
2197 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
2198 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
2199 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
2200 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
2201 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
2202 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
2203 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
2204
2205 /* Bit definitions for USB_VBUS_CTRL_CLR */
2206 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
2207 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
2208 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
2209 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
2210 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
2211 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
2212 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
2213 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
2214 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
2215 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
2216
2217 /* Bit definitions for USB_ID_CTRL_SET */
2218 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
2219 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
2220 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
2221 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
2222 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
2223 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
2224 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
2225 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
2226 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
2227 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
2228 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
2229 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
2230
2231 /* Bit definitions for USB_ID_CTRL_CLEAR */
2232 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
2233 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
2234 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
2235 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
2236 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
2237 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
2238 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
2239 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
2240 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
2241 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
2242 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
2243 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
2244
2245 /* Bit definitions for USB_VBUS_INT_SRC */
2246 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
2247 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
2248 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
2249 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
2250 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
2251 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
2252 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
2253 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
2254 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
2255 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
2256 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
2257 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
2258 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
2259 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
2260
2261 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2262 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
2263 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
2264 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
2265 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
2266 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
2267 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
2268 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
2269 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
2270 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
2271 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
2272 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
2273 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
2274 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
2275 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
2276 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
2277 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
2278
2279 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2280 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
2281 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
2282 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
2283 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
2284 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
2285 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
2286 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
2287 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
2288 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
2289 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
2290 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
2291 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
2292 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
2293 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
2294 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
2295 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
2296
2297 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2298 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
2299 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
2300 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
2301 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
2302 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
2303 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
2304 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
2305 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
2306 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
2307 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
2308 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
2309 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
2310 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
2311 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
2312
2313 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2314 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
2315 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
2316 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
2317 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
2318 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
2319 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
2320 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
2321 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
2322 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
2323 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
2324 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
2325 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
2326 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
2327 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
2328
2329 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2330 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
2331 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
2332 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
2333 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
2334 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
2335 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
2336 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
2337 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
2338 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
2339 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
2340 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
2341 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
2342 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
2343 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
2344 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
2345 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
2346
2347 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2348 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
2349 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
2350 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
2351 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
2352 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
2353 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
2354 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
2355 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
2356 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
2357 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
2358 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
2359 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
2360 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
2361 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
2362 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
2363 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
2364
2365 /* Bit definitions for USB_ID_INT_SRC */
2366 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
2367 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
2368 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
2369 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
2370 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
2371 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
2372 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
2373 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
2374 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
2375 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
2376
2377 /* Bit definitions for USB_ID_INT_LATCH_SET */
2378 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
2379 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
2380 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
2381 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
2382 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
2383 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
2384 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
2385 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
2386 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
2387 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
2388
2389 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2390 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
2391 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
2392 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
2393 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
2394 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
2395 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
2396 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
2397 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
2398 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
2399 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
2400
2401 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2402 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
2403 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
2404 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
2405 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
2406 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
2407 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
2408 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
2409 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
2410 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
2411 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
2412
2413 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2414 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
2415 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
2416 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
2417 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
2418 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
2419 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
2420 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
2421 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
2422 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
2423 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
2424
2425 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2426 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
2427 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
2428 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
2429 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
2430 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
2431 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
2432 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
2433 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
2434 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
2435 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
2436
2437 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2438 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
2439 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
2440 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
2441 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
2442 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
2443 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
2444 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
2445 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
2446 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
2447 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
2448
2449 /* Bit definitions for USB_OTG_ADP_CTRL */
2450 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
2451 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
2452 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
2453 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
2454
2455 /* Bit definitions for USB_OTG_ADP_HIGH */
2456 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
2457 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
2458
2459 /* Bit definitions for USB_OTG_ADP_LOW */
2460 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
2461 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
2462
2463 /* Bit definitions for USB_OTG_ADP_RISE */
2464 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
2465 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
2466
2467 /* Bit definitions for USB_OTG_REVISION */
2468 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
2469 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
2470
2471 /* Registers for function VIBRATOR */
2472 #define PALMAS_VIBRA_CTRL                                       0x0
2473
2474 /* Bit definitions for VIBRA_CTRL */
2475 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
2476 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
2477 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
2478 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
2479
2480 /* Registers for function GPIO */
2481 #define PALMAS_GPIO_DATA_IN                                     0x0
2482 #define PALMAS_GPIO_DATA_DIR                                    0x1
2483 #define PALMAS_GPIO_DATA_OUT                                    0x2
2484 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
2485 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
2486 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
2487 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
2488 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
2489 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
2490
2491 /* Bit definitions for GPIO_DATA_IN */
2492 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
2493 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
2494 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
2495 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
2496 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
2497 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
2498 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
2499 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
2500 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
2501 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
2502 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
2503 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
2504 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
2505 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
2506 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
2507 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
2508
2509 /* Bit definitions for GPIO_DATA_DIR */
2510 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
2511 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
2512 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
2513 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
2514 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
2515 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
2516 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
2517 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
2518 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
2519 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
2520 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
2521 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
2522 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
2523 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
2524 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
2525 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
2526
2527 /* Bit definitions for GPIO_DATA_OUT */
2528 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
2529 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
2530 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
2531 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
2532 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
2533 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
2534 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
2535 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
2536 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
2537 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
2538 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
2539 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
2540 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
2541 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
2542 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
2543 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
2544
2545 /* Bit definitions for GPIO_DEBOUNCE_EN */
2546 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
2547 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
2548 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
2549 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
2550 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
2551 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
2552 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
2553 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
2554 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
2555 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
2556 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
2557 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
2558 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
2559 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
2560 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
2561 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
2562
2563 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2564 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
2565 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
2566 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
2567 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
2568 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
2569 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
2570 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
2571 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
2572 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
2573 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
2574 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
2575 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
2576 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
2577 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
2578 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
2579 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
2580
2581 /* Bit definitions for GPIO_SET_DATA_OUT */
2582 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
2583 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
2584 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
2585 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
2586 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
2587 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
2588 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
2589 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
2590 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
2591 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
2592 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
2593 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
2594 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
2595 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
2596 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
2597 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
2598
2599 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2600 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
2601 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
2602 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
2603 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
2604 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
2605 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
2606 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
2607 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
2608 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
2609 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
2610 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
2611 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
2612
2613 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2614 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
2615 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
2616 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
2617 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
2618 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
2619 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
2620 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
2621 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
2622 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
2623 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
2624 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
2625 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
2626 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
2627 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
2628
2629 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2630 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
2631 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
2632 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
2633 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
2634 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
2635 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
2636
2637 /* Registers for function GPADC */
2638 #define PALMAS_GPADC_CTRL1                                      0x0
2639 #define PALMAS_GPADC_CTRL2                                      0x1
2640 #define PALMAS_GPADC_RT_CTRL                                    0x2
2641 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
2642 #define PALMAS_GPADC_STATUS                                     0x4
2643 #define PALMAS_GPADC_RT_SELECT                                  0x5
2644 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
2645 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
2646 #define PALMAS_GPADC_AUTO_SELECT                                0x8
2647 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
2648 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
2649 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
2650 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
2651 #define PALMAS_GPADC_SW_SELECT                                  0xD
2652 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
2653 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
2654 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
2655 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
2656 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
2657 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
2658 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
2659 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
2660
2661 /* Bit definitions for GPADC_CTRL1 */
2662 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
2663 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
2664 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
2665 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
2666 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
2667 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
2668 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
2669 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
2670 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
2671 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
2672
2673 /* Bit definitions for GPADC_CTRL2 */
2674 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
2675 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
2676
2677 /* Bit definitions for GPADC_RT_CTRL */
2678 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
2679 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
2680 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
2681 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
2682
2683 /* Bit definitions for GPADC_AUTO_CTRL */
2684 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
2685 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
2686 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
2687 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
2688 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
2689 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
2690 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
2691 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
2692 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
2693 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
2694
2695 /* Bit definitions for GPADC_STATUS */
2696 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
2697 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
2698
2699 /* Bit definitions for GPADC_RT_SELECT */
2700 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
2701 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
2702 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
2703 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
2704
2705 /* Bit definitions for GPADC_RT_CONV0_LSB */
2706 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
2707 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
2708
2709 /* Bit definitions for GPADC_RT_CONV0_MSB */
2710 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
2711 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
2712
2713 /* Bit definitions for GPADC_AUTO_SELECT */
2714 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
2715 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
2716 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
2717 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
2718
2719 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2720 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
2721 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
2722
2723 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2724 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
2725 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
2726
2727 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2728 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
2729 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
2730
2731 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2732 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
2733 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
2734
2735 /* Bit definitions for GPADC_SW_SELECT */
2736 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
2737 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
2738 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
2739 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
2740 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
2741 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
2742
2743 /* Bit definitions for GPADC_SW_CONV0_LSB */
2744 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
2745 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
2746
2747 /* Bit definitions for GPADC_SW_CONV0_MSB */
2748 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
2749 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
2750
2751 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2752 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
2753 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
2754
2755 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2756 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
2757 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
2758 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
2759 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
2760
2761 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2762 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
2763 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
2764
2765 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2766 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
2767 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
2768 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
2769 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
2770
2771 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2772 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
2773 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
2774 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
2775 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
2776 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
2777 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
2778
2779 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2780 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
2781 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
2782 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
2783 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
2784
2785 /* Registers for function GPADC */
2786 #define PALMAS_GPADC_TRIM1                                      0x0
2787 #define PALMAS_GPADC_TRIM2                                      0x1
2788 #define PALMAS_GPADC_TRIM3                                      0x2
2789 #define PALMAS_GPADC_TRIM4                                      0x3
2790 #define PALMAS_GPADC_TRIM5                                      0x4
2791 #define PALMAS_GPADC_TRIM6                                      0x5
2792 #define PALMAS_GPADC_TRIM7                                      0x6
2793 #define PALMAS_GPADC_TRIM8                                      0x7
2794 #define PALMAS_GPADC_TRIM9                                      0x8
2795 #define PALMAS_GPADC_TRIM10                                     0x9
2796 #define PALMAS_GPADC_TRIM11                                     0xA
2797 #define PALMAS_GPADC_TRIM12                                     0xB
2798 #define PALMAS_GPADC_TRIM13                                     0xC
2799 #define PALMAS_GPADC_TRIM14                                     0xD
2800 #define PALMAS_GPADC_TRIM15                                     0xE
2801 #define PALMAS_GPADC_TRIM16                                     0xF
2802
2803 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2804                 unsigned int reg, unsigned int *val)
2805 {
2806         unsigned int addr =  PALMAS_BASE_TO_REG(base, reg);
2807         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2808
2809         return regmap_read(palmas->regmap[slave_id], addr, val);
2810 }
2811
2812 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2813                 unsigned int reg, unsigned int value)
2814 {
2815         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2816         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2817
2818         return regmap_write(palmas->regmap[slave_id], addr, value);
2819 }
2820
2821 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2822         unsigned int reg, const void *val, size_t val_count)
2823 {
2824         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2825         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2826
2827         return regmap_bulk_write(palmas->regmap[slave_id], addr,
2828                         val, val_count);
2829 }
2830
2831 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2832                 unsigned int reg, void *val, size_t val_count)
2833 {
2834         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2835         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2836
2837         return regmap_bulk_read(palmas->regmap[slave_id], addr,
2838                 val, val_count);
2839 }
2840
2841 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2842         unsigned int reg, unsigned int mask, unsigned int val)
2843 {
2844         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2845         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2846
2847         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2848 }
2849
2850 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2851 {
2852         return regmap_irq_get_virq(palmas->irq_data, irq);
2853 }
2854
2855 #endif /*  __LINUX_MFD_PALMAS_H */