include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38 #include <linux/mlx5/mlx5_ifc.h>
  39
  40 #if defined(__LITTLE_ENDIAN)
  41 #define MLX5_SET_HOST_ENDIANNESS        0
  42 #elif defined(__BIG_ENDIAN)
  43 #define MLX5_SET_HOST_ENDIANNESS        0x80
  44 #else
  45 #error Host endianness not defined
  46 #endif
  47
  48 /* helper macros */
  49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
  52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  58
  59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  62 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
  63 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
  64 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  65 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
  66
  67 /* insert a value to a struct */
  68 #define MLX5_SET(typ, p, fld, v) do { \
  69         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  70         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  71         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  72                      (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
  73                      << __mlx5_dw_bit_off(typ, fld))); \
  74 } while (0)
  75
  76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
  77         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  78         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  79         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  80                      (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
  81                      << __mlx5_dw_bit_off(typ, fld))); \
  82 } while (0)
  83
  84 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  85 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  86 __mlx5_mask(typ, fld))
  87
  88 #define MLX5_GET_PR(typ, p, fld) ({ \
  89         u32 ___t = MLX5_GET(typ, p, fld); \
  90         pr_debug(#fld " = 0x%x\n", ___t); \
  91         ___t; \
  92 })
  93
  94 #define MLX5_SET64(typ, p, fld, v) do { \
  95         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
  96         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
  97         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
  98 } while (0)
  99
 100 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
 101
 102 #define MLX5_GET64_PR(typ, p, fld) ({ \
 103         u64 ___t = MLX5_GET64(typ, p, fld); \
 104         pr_debug(#fld " = 0x%llx\n", ___t); \
 105         ___t; \
 106 })
 107
 108 /* Big endian getters */
 109 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
 110         __mlx5_64_off(typ, fld)))
 111
 112 #define MLX5_GET_BE(type_t, typ, p, fld) ({                               \
 113                 type_t tmp;                                               \
 114                 switch (sizeof(tmp)) {                                    \
 115                 case sizeof(u8):                                          \
 116                         tmp = (__force type_t)MLX5_GET(typ, p, fld);      \
 117                         break;                                            \
 118                 case sizeof(u16):                                         \
 119                         tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
 120                         break;                                            \
 121                 case sizeof(u32):                                         \
 122                         tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
 123                         break;                                            \
 124                 case sizeof(u64):                                         \
 125                         tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
 126                         break;                                            \
 127                         }                                                 \
 128                 tmp;                                                      \
 129                 })
 130
 131 enum {
 132         MLX5_MAX_COMMANDS               = 32,
 133         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
 134         MLX5_PCI_CMD_XPORT              = 7,
 135         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
 136         MLX5_MAX_PSVS                   = 4,
 137 };
 138
 139 enum {
 140         MLX5_EXTENDED_UD_AV             = 0x80000000,
 141 };
 142
 143 enum {
 144         MLX5_CQ_STATE_ARMED             = 9,
 145         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
 146         MLX5_CQ_STATE_FIRED             = 0xa,
 147 };
 148
 149 enum {
 150         MLX5_STAT_RATE_OFFSET   = 5,
 151 };
 152
 153 enum {
 154         MLX5_INLINE_SEG = 0x80000000,
 155 };
 156
 157 enum {
 158         MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
 159 };
 160
 161 enum {
 162         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 163         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 164 };
 165
 166 enum {
 167         MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
 168 };
 169
 170 enum {
 171         MLX5_PFAULT_SUBTYPE_WQE = 0,
 172         MLX5_PFAULT_SUBTYPE_RDMA = 1,
 173 };
 174
 175 enum {
 176         MLX5_PERM_LOCAL_READ    = 1 << 2,
 177         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 178         MLX5_PERM_REMOTE_READ   = 1 << 4,
 179         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 180         MLX5_PERM_ATOMIC        = 1 << 6,
 181         MLX5_PERM_UMR_EN        = 1 << 7,
 182 };
 183
 184 enum {
 185         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 186         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 187         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 188         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 189         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 190 };
 191
 192 enum {
 193         MLX5_ACCESS_MODE_PA     = 0,
 194         MLX5_ACCESS_MODE_MTT    = 1,
 195         MLX5_ACCESS_MODE_KLM    = 2
 196 };
 197
 198 enum {
 199         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 200         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 201         MLX5_MKEY_BSF_EN        = 1 << 30,
 202         MLX5_MKEY_LEN64         = 1 << 31,
 203 };
 204
 205 enum {
 206         MLX5_EN_RD      = (u64)1,
 207         MLX5_EN_WR      = (u64)2
 208 };
 209
 210 enum {
 211         MLX5_BF_REGS_PER_PAGE           = 4,
 212         MLX5_MAX_UAR_PAGES              = 1 << 8,
 213         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 214         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 215 };
 216
 217 enum {
 218         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 219         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 220         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 221         MLX5_MKEY_MASK_PD               = 1ull << 7,
 222         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 223         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 224         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 225         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 226         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 227         MLX5_MKEY_MASK_LR               = 1ull << 17,
 228         MLX5_MKEY_MASK_LW               = 1ull << 18,
 229         MLX5_MKEY_MASK_RR               = 1ull << 19,
 230         MLX5_MKEY_MASK_RW               = 1ull << 20,
 231         MLX5_MKEY_MASK_A                = 1ull << 21,
 232         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 233         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 234 };
 235
 236 enum {
 237         MLX5_UMR_TRANSLATION_OFFSET_EN  = (1 << 4),
 238
 239         MLX5_UMR_CHECK_NOT_FREE         = (1 << 5),
 240         MLX5_UMR_CHECK_FREE             = (2 << 5),
 241
 242         MLX5_UMR_INLINE                 = (1 << 7),
 243 };
 244
 245 #define MLX5_UMR_MTT_ALIGNMENT 0x40
 246 #define MLX5_UMR_MTT_MASK      (MLX5_UMR_MTT_ALIGNMENT - 1)
 247 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
 248
 249 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
 250
 251 enum {
 252         MLX5_EVENT_QUEUE_TYPE_QP = 0,
 253         MLX5_EVENT_QUEUE_TYPE_RQ = 1,
 254         MLX5_EVENT_QUEUE_TYPE_SQ = 2,
 255 };
 256
 257 enum mlx5_event {
 258         MLX5_EVENT_TYPE_COMP               = 0x0,
 259
 260         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 261         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 262         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 263         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 264         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 265
 266         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 267         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 268         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 269         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 270         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 271         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 272
 273         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 274         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 275         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 276         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 277
 278         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 279         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 280
 281         MLX5_EVENT_TYPE_CMD                = 0x0a,
 282         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 283
 284         MLX5_EVENT_TYPE_PAGE_FAULT         = 0xc,
 285         MLX5_EVENT_TYPE_NIC_VPORT_CHANGE   = 0xd,
 286 };
 287
 288 enum {
 289         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 290         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 291         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 292         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 293         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 294         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 295         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 296 };
 297
 298 enum {
 299         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 300         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 301         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 302         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 303         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 304         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 305         MLX5_DEV_CAP_FLAG_ON_DMND_PG    = 1LL << 24,
 306         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 307         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 308         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 309         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 310         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 311 };
 312
 313 enum {
 314         MLX5_ROCE_VERSION_1             = 0,
 315         MLX5_ROCE_VERSION_2             = 2,
 316 };
 317
 318 enum {
 319         MLX5_ROCE_VERSION_1_CAP         = 1 << MLX5_ROCE_VERSION_1,
 320         MLX5_ROCE_VERSION_2_CAP         = 1 << MLX5_ROCE_VERSION_2,
 321 };
 322
 323 enum {
 324         MLX5_ROCE_L3_TYPE_IPV4          = 0,
 325         MLX5_ROCE_L3_TYPE_IPV6          = 1,
 326 };
 327
 328 enum {
 329         MLX5_ROCE_L3_TYPE_IPV4_CAP      = 1 << 1,
 330         MLX5_ROCE_L3_TYPE_IPV6_CAP      = 1 << 2,
 331 };
 332
 333 enum {
 334         MLX5_OPCODE_NOP                 = 0x00,
 335         MLX5_OPCODE_SEND_INVAL          = 0x01,
 336         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 337         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 338         MLX5_OPCODE_SEND                = 0x0a,
 339         MLX5_OPCODE_SEND_IMM            = 0x0b,
 340         MLX5_OPCODE_LSO                 = 0x0e,
 341         MLX5_OPCODE_RDMA_READ           = 0x10,
 342         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 343         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 344         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 345         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 346         MLX5_OPCODE_BIND_MW             = 0x18,
 347         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 348
 349         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 350         MLX5_RECV_OPCODE_SEND           = 0x01,
 351         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 352         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 353
 354         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 355         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 356
 357         MLX5_OPCODE_SET_PSV             = 0x20,
 358         MLX5_OPCODE_GET_PSV             = 0x21,
 359         MLX5_OPCODE_CHECK_PSV           = 0x22,
 360         MLX5_OPCODE_RGET_PSV            = 0x26,
 361         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 362
 363         MLX5_OPCODE_UMR                 = 0x25,
 364
 365 };
 366
 367 enum {
 368         MLX5_SET_PORT_RESET_QKEY        = 0,
 369         MLX5_SET_PORT_GUID0             = 16,
 370         MLX5_SET_PORT_NODE_GUID         = 17,
 371         MLX5_SET_PORT_SYS_GUID          = 18,
 372         MLX5_SET_PORT_GID_TABLE         = 19,
 373         MLX5_SET_PORT_PKEY_TABLE        = 20,
 374 };
 375
 376 enum {
 377         MLX5_BW_NO_LIMIT   = 0,
 378         MLX5_100_MBPS_UNIT = 3,
 379         MLX5_GBPS_UNIT     = 4,
 380 };
 381
 382 enum {
 383         MLX5_MAX_PAGE_SHIFT             = 31
 384 };
 385
 386 enum {
 387         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 388         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 389 };
 390
 391 enum {
 392         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 393 };
 394
 395 enum {
 396         /*
 397          * Max wqe size for rdma read is 512 bytes, so this
 398          * limits our max_sge_rd as the wqe needs to fit:
 399          * - ctrl segment (16 bytes)
 400          * - rdma segment (16 bytes)
 401          * - scatter elements (16 bytes each)
 402          */
 403         MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
 404 };
 405
 406 struct mlx5_inbox_hdr {
 407         __be16          opcode;
 408         u8              rsvd[4];
 409         __be16          opmod;
 410 };
 411
 412 struct mlx5_outbox_hdr {
 413         u8              status;
 414         u8              rsvd[3];
 415         __be32          syndrome;
 416 };
 417
 418 struct mlx5_cmd_query_adapter_mbox_in {
 419         struct mlx5_inbox_hdr   hdr;
 420         u8                      rsvd[8];
 421 };
 422
 423 struct mlx5_cmd_query_adapter_mbox_out {
 424         struct mlx5_outbox_hdr  hdr;
 425         u8                      rsvd0[24];
 426         u8                      intapin;
 427         u8                      rsvd1[13];
 428         __be16                  vsd_vendor_id;
 429         u8                      vsd[208];
 430         u8                      vsd_psid[16];
 431 };
 432
 433 enum mlx5_odp_transport_cap_bits {
 434         MLX5_ODP_SUPPORT_SEND    = 1 << 31,
 435         MLX5_ODP_SUPPORT_RECV    = 1 << 30,
 436         MLX5_ODP_SUPPORT_WRITE   = 1 << 29,
 437         MLX5_ODP_SUPPORT_READ    = 1 << 28,
 438 };
 439
 440 struct mlx5_odp_caps {
 441         char reserved[0x10];
 442         struct {
 443                 __be32                  rc_odp_caps;
 444                 __be32                  uc_odp_caps;
 445                 __be32                  ud_odp_caps;
 446         } per_transport_caps;
 447         char reserved2[0xe4];
 448 };
 449
 450 struct mlx5_cmd_init_hca_mbox_in {
 451         struct mlx5_inbox_hdr   hdr;
 452         u8                      rsvd0[2];
 453         __be16                  profile;
 454         u8                      rsvd1[4];
 455 };
 456
 457 struct mlx5_cmd_init_hca_mbox_out {
 458         struct mlx5_outbox_hdr  hdr;
 459         u8                      rsvd[8];
 460 };
 461
 462 struct mlx5_cmd_teardown_hca_mbox_in {
 463         struct mlx5_inbox_hdr   hdr;
 464         u8                      rsvd0[2];
 465         __be16                  profile;
 466         u8                      rsvd1[4];
 467 };
 468
 469 struct mlx5_cmd_teardown_hca_mbox_out {
 470         struct mlx5_outbox_hdr  hdr;
 471         u8                      rsvd[8];
 472 };
 473
 474 struct mlx5_cmd_layout {
 475         u8              type;
 476         u8              rsvd0[3];
 477         __be32          inlen;
 478         __be64          in_ptr;
 479         __be32          in[4];
 480         __be32          out[4];
 481         __be64          out_ptr;
 482         __be32          outlen;
 483         u8              token;
 484         u8              sig;
 485         u8              rsvd1;
 486         u8              status_own;
 487 };
 488
 489
 490 struct health_buffer {
 491         __be32          assert_var[5];
 492         __be32          rsvd0[3];
 493         __be32          assert_exit_ptr;
 494         __be32          assert_callra;
 495         __be32          rsvd1[2];
 496         __be32          fw_ver;
 497         __be32          hw_id;
 498         __be32          rsvd2;
 499         u8              irisc_index;
 500         u8              synd;
 501         __be16          ext_synd;
 502 };
 503
 504 struct mlx5_init_seg {
 505         __be32                  fw_rev;
 506         __be32                  cmdif_rev_fw_sub;
 507         __be32                  rsvd0[2];
 508         __be32                  cmdq_addr_h;
 509         __be32                  cmdq_addr_l_sz;
 510         __be32                  cmd_dbell;
 511         __be32                  rsvd1[120];
 512         __be32                  initializing;
 513         struct health_buffer    health;
 514         __be32                  rsvd2[880];
 515         __be32                  internal_timer_h;
 516         __be32                  internal_timer_l;
 517         __be32                  rsvd3[2];
 518         __be32                  health_counter;
 519         __be32                  rsvd4[1019];
 520         __be64                  ieee1588_clk;
 521         __be32                  ieee1588_clk_type;
 522         __be32                  clr_intx;
 523 };
 524
 525 struct mlx5_eqe_comp {
 526         __be32  reserved[6];
 527         __be32  cqn;
 528 };
 529
 530 struct mlx5_eqe_qp_srq {
 531         __be32  reserved1[5];
 532         u8      type;
 533         u8      reserved2[3];
 534         __be32  qp_srq_n;
 535 };
 536
 537 struct mlx5_eqe_cq_err {
 538         __be32  cqn;
 539         u8      reserved1[7];
 540         u8      syndrome;
 541 };
 542
 543 struct mlx5_eqe_port_state {
 544         u8      reserved0[8];
 545         u8      port;
 546 };
 547
 548 struct mlx5_eqe_gpio {
 549         __be32  reserved0[2];
 550         __be64  gpio_event;
 551 };
 552
 553 struct mlx5_eqe_congestion {
 554         u8      type;
 555         u8      rsvd0;
 556         u8      congestion_level;
 557 };
 558
 559 struct mlx5_eqe_stall_vl {
 560         u8      rsvd0[3];
 561         u8      port_vl;
 562 };
 563
 564 struct mlx5_eqe_cmd {
 565         __be32  vector;
 566         __be32  rsvd[6];
 567 };
 568
 569 struct mlx5_eqe_page_req {
 570         u8              rsvd0[2];
 571         __be16          func_id;
 572         __be32          num_pages;
 573         __be32          rsvd1[5];
 574 };
 575
 576 struct mlx5_eqe_page_fault {
 577         __be32 bytes_committed;
 578         union {
 579                 struct {
 580                         u16     reserved1;
 581                         __be16  wqe_index;
 582                         u16     reserved2;
 583                         __be16  packet_length;
 584                         u8      reserved3[12];
 585                 } __packed wqe;
 586                 struct {
 587                         __be32  r_key;
 588                         u16     reserved1;
 589                         __be16  packet_length;
 590                         __be32  rdma_op_len;
 591                         __be64  rdma_va;
 592                 } __packed rdma;
 593         } __packed;
 594         __be32 flags_qpn;
 595 } __packed;
 596
 597 struct mlx5_eqe_vport_change {
 598         u8              rsvd0[2];
 599         __be16          vport_num;
 600         __be32          rsvd1[6];
 601 } __packed;
 602
 603 union ev_data {
 604         __be32                          raw[7];
 605         struct mlx5_eqe_cmd             cmd;
 606         struct mlx5_eqe_comp            comp;
 607         struct mlx5_eqe_qp_srq          qp_srq;
 608         struct mlx5_eqe_cq_err          cq_err;
 609         struct mlx5_eqe_port_state      port;
 610         struct mlx5_eqe_gpio            gpio;
 611         struct mlx5_eqe_congestion      cong;
 612         struct mlx5_eqe_stall_vl        stall_vl;
 613         struct mlx5_eqe_page_req        req_pages;
 614         struct mlx5_eqe_page_fault      page_fault;
 615         struct mlx5_eqe_vport_change    vport_change;
 616 } __packed;
 617
 618 struct mlx5_eqe {
 619         u8              rsvd0;
 620         u8              type;
 621         u8              rsvd1;
 622         u8              sub_type;
 623         __be32          rsvd2[7];
 624         union ev_data   data;
 625         __be16          rsvd3;
 626         u8              signature;
 627         u8              owner;
 628 } __packed;
 629
 630 struct mlx5_cmd_prot_block {
 631         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 632         u8              rsvd0[48];
 633         __be64          next;
 634         __be32          block_num;
 635         u8              rsvd1;
 636         u8              token;
 637         u8              ctrl_sig;
 638         u8              sig;
 639 };
 640
 641 enum {
 642         MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
 643 };
 644
 645 struct mlx5_err_cqe {
 646         u8      rsvd0[32];
 647         __be32  srqn;
 648         u8      rsvd1[18];
 649         u8      vendor_err_synd;
 650         u8      syndrome;
 651         __be32  s_wqe_opcode_qpn;
 652         __be16  wqe_counter;
 653         u8      signature;
 654         u8      op_own;
 655 };
 656
 657 struct mlx5_cqe64 {
 658         u8              rsvd0[4];
 659         u8              lro_tcppsh_abort_dupack;
 660         u8              lro_min_ttl;
 661         __be16          lro_tcp_win;
 662         __be32          lro_ack_seq_num;
 663         __be32          rss_hash_result;
 664         u8              rss_hash_type;
 665         u8              ml_path;
 666         u8              rsvd20[2];
 667         __be16          check_sum;
 668         __be16          slid;
 669         __be32          flags_rqpn;
 670         u8              hds_ip_ext;
 671         u8              l4_hdr_type_etc;
 672         __be16          vlan_info;
 673         __be32          srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
 674         __be32          imm_inval_pkey;
 675         u8              rsvd40[4];
 676         __be32          byte_cnt;
 677         __be32          timestamp_h;
 678         __be32          timestamp_l;
 679         __be32          sop_drop_qpn;
 680         __be16          wqe_counter;
 681         u8              signature;
 682         u8              op_own;
 683 };
 684
 685 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
 686 {
 687         return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
 688 }
 689
 690 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
 691 {
 692         return (cqe->l4_hdr_type_etc >> 4) & 0x7;
 693 }
 694
 695 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
 696 {
 697         return !!(cqe->l4_hdr_type_etc & 0x1);
 698 }
 699
 700 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
 701 {
 702         u32 hi, lo;
 703
 704         hi = be32_to_cpu(cqe->timestamp_h);
 705         lo = be32_to_cpu(cqe->timestamp_l);
 706
 707         return (u64)lo | ((u64)hi << 32);
 708 }
 709
 710 enum {
 711         CQE_L4_HDR_TYPE_NONE                    = 0x0,
 712         CQE_L4_HDR_TYPE_TCP_NO_ACK              = 0x1,
 713         CQE_L4_HDR_TYPE_UDP                     = 0x2,
 714         CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA         = 0x3,
 715         CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA        = 0x4,
 716 };
 717
 718 enum {
 719         CQE_RSS_HTYPE_IP        = 0x3 << 6,
 720         CQE_RSS_HTYPE_L4        = 0x3 << 2,
 721 };
 722
 723 enum {
 724         MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH        = 0x0,
 725         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6       = 0x1,
 726         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4       = 0x2,
 727 };
 728
 729 enum {
 730         CQE_L2_OK       = 1 << 0,
 731         CQE_L3_OK       = 1 << 1,
 732         CQE_L4_OK       = 1 << 2,
 733 };
 734
 735 struct mlx5_sig_err_cqe {
 736         u8              rsvd0[16];
 737         __be32          expected_trans_sig;
 738         __be32          actual_trans_sig;
 739         __be32          expected_reftag;
 740         __be32          actual_reftag;
 741         __be16          syndrome;
 742         u8              rsvd22[2];
 743         __be32          mkey;
 744         __be64          err_offset;
 745         u8              rsvd30[8];
 746         __be32          qpn;
 747         u8              rsvd38[2];
 748         u8              signature;
 749         u8              op_own;
 750 };
 751
 752 struct mlx5_wqe_srq_next_seg {
 753         u8                      rsvd0[2];
 754         __be16                  next_wqe_index;
 755         u8                      signature;
 756         u8                      rsvd1[11];
 757 };
 758
 759 union mlx5_ext_cqe {
 760         struct ib_grh   grh;
 761         u8              inl[64];
 762 };
 763
 764 struct mlx5_cqe128 {
 765         union mlx5_ext_cqe      inl_grh;
 766         struct mlx5_cqe64       cqe64;
 767 };
 768
 769 struct mlx5_srq_ctx {
 770         u8                      state_log_sz;
 771         u8                      rsvd0[3];
 772         __be32                  flags_xrcd;
 773         __be32                  pgoff_cqn;
 774         u8                      rsvd1[4];
 775         u8                      log_pg_sz;
 776         u8                      rsvd2[7];
 777         __be32                  pd;
 778         __be16                  lwm;
 779         __be16                  wqe_cnt;
 780         u8                      rsvd3[8];
 781         __be64                  db_record;
 782 };
 783
 784 struct mlx5_create_srq_mbox_in {
 785         struct mlx5_inbox_hdr   hdr;
 786         __be32                  input_srqn;
 787         u8                      rsvd0[4];
 788         struct mlx5_srq_ctx     ctx;
 789         u8                      rsvd1[208];
 790         __be64                  pas[0];
 791 };
 792
 793 struct mlx5_create_srq_mbox_out {
 794         struct mlx5_outbox_hdr  hdr;
 795         __be32                  srqn;
 796         u8                      rsvd[4];
 797 };
 798
 799 struct mlx5_destroy_srq_mbox_in {
 800         struct mlx5_inbox_hdr   hdr;
 801         __be32                  srqn;
 802         u8                      rsvd[4];
 803 };
 804
 805 struct mlx5_destroy_srq_mbox_out {
 806         struct mlx5_outbox_hdr  hdr;
 807         u8                      rsvd[8];
 808 };
 809
 810 struct mlx5_query_srq_mbox_in {
 811         struct mlx5_inbox_hdr   hdr;
 812         __be32                  srqn;
 813         u8                      rsvd0[4];
 814 };
 815
 816 struct mlx5_query_srq_mbox_out {
 817         struct mlx5_outbox_hdr  hdr;
 818         u8                      rsvd0[8];
 819         struct mlx5_srq_ctx     ctx;
 820         u8                      rsvd1[32];
 821         __be64                  pas[0];
 822 };
 823
 824 struct mlx5_arm_srq_mbox_in {
 825         struct mlx5_inbox_hdr   hdr;
 826         __be32                  srqn;
 827         __be16                  rsvd;
 828         __be16                  lwm;
 829 };
 830
 831 struct mlx5_arm_srq_mbox_out {
 832         struct mlx5_outbox_hdr  hdr;
 833         u8                      rsvd[8];
 834 };
 835
 836 struct mlx5_cq_context {
 837         u8                      status;
 838         u8                      cqe_sz_flags;
 839         u8                      st;
 840         u8                      rsvd3;
 841         u8                      rsvd4[6];
 842         __be16                  page_offset;
 843         __be32                  log_sz_usr_page;
 844         __be16                  cq_period;
 845         __be16                  cq_max_count;
 846         __be16                  rsvd20;
 847         __be16                  c_eqn;
 848         u8                      log_pg_sz;
 849         u8                      rsvd25[7];
 850         __be32                  last_notified_index;
 851         __be32                  solicit_producer_index;
 852         __be32                  consumer_counter;
 853         __be32                  producer_counter;
 854         u8                      rsvd48[8];
 855         __be64                  db_record_addr;
 856 };
 857
 858 struct mlx5_create_cq_mbox_in {
 859         struct mlx5_inbox_hdr   hdr;
 860         __be32                  input_cqn;
 861         u8                      rsvdx[4];
 862         struct mlx5_cq_context  ctx;
 863         u8                      rsvd6[192];
 864         __be64                  pas[0];
 865 };
 866
 867 struct mlx5_create_cq_mbox_out {
 868         struct mlx5_outbox_hdr  hdr;
 869         __be32                  cqn;
 870         u8                      rsvd0[4];
 871 };
 872
 873 struct mlx5_destroy_cq_mbox_in {
 874         struct mlx5_inbox_hdr   hdr;
 875         __be32                  cqn;
 876         u8                      rsvd0[4];
 877 };
 878
 879 struct mlx5_destroy_cq_mbox_out {
 880         struct mlx5_outbox_hdr  hdr;
 881         u8                      rsvd0[8];
 882 };
 883
 884 struct mlx5_query_cq_mbox_in {
 885         struct mlx5_inbox_hdr   hdr;
 886         __be32                  cqn;
 887         u8                      rsvd0[4];
 888 };
 889
 890 struct mlx5_query_cq_mbox_out {
 891         struct mlx5_outbox_hdr  hdr;
 892         u8                      rsvd0[8];
 893         struct mlx5_cq_context  ctx;
 894         u8                      rsvd6[16];
 895         __be64                  pas[0];
 896 };
 897
 898 struct mlx5_modify_cq_mbox_in {
 899         struct mlx5_inbox_hdr   hdr;
 900         __be32                  cqn;
 901         __be32                  field_select;
 902         struct mlx5_cq_context  ctx;
 903         u8                      rsvd[192];
 904         __be64                  pas[0];
 905 };
 906
 907 struct mlx5_modify_cq_mbox_out {
 908         struct mlx5_outbox_hdr  hdr;
 909         u8                      rsvd[8];
 910 };
 911
 912 struct mlx5_enable_hca_mbox_in {
 913         struct mlx5_inbox_hdr   hdr;
 914         u8                      rsvd[8];
 915 };
 916
 917 struct mlx5_enable_hca_mbox_out {
 918         struct mlx5_outbox_hdr  hdr;
 919         u8                      rsvd[8];
 920 };
 921
 922 struct mlx5_disable_hca_mbox_in {
 923         struct mlx5_inbox_hdr   hdr;
 924         u8                      rsvd[8];
 925 };
 926
 927 struct mlx5_disable_hca_mbox_out {
 928         struct mlx5_outbox_hdr  hdr;
 929         u8                      rsvd[8];
 930 };
 931
 932 struct mlx5_eq_context {
 933         u8                      status;
 934         u8                      ec_oi;
 935         u8                      st;
 936         u8                      rsvd2[7];
 937         __be16                  page_pffset;
 938         __be32                  log_sz_usr_page;
 939         u8                      rsvd3[7];
 940         u8                      intr;
 941         u8                      log_page_size;
 942         u8                      rsvd4[15];
 943         __be32                  consumer_counter;
 944         __be32                  produser_counter;
 945         u8                      rsvd5[16];
 946 };
 947
 948 struct mlx5_create_eq_mbox_in {
 949         struct mlx5_inbox_hdr   hdr;
 950         u8                      rsvd0[3];
 951         u8                      input_eqn;
 952         u8                      rsvd1[4];
 953         struct mlx5_eq_context  ctx;
 954         u8                      rsvd2[8];
 955         __be64                  events_mask;
 956         u8                      rsvd3[176];
 957         __be64                  pas[0];
 958 };
 959
 960 struct mlx5_create_eq_mbox_out {
 961         struct mlx5_outbox_hdr  hdr;
 962         u8                      rsvd0[3];
 963         u8                      eq_number;
 964         u8                      rsvd1[4];
 965 };
 966
 967 struct mlx5_destroy_eq_mbox_in {
 968         struct mlx5_inbox_hdr   hdr;
 969         u8                      rsvd0[3];
 970         u8                      eqn;
 971         u8                      rsvd1[4];
 972 };
 973
 974 struct mlx5_destroy_eq_mbox_out {
 975         struct mlx5_outbox_hdr  hdr;
 976         u8                      rsvd[8];
 977 };
 978
 979 struct mlx5_map_eq_mbox_in {
 980         struct mlx5_inbox_hdr   hdr;
 981         __be64                  mask;
 982         u8                      mu;
 983         u8                      rsvd0[2];
 984         u8                      eqn;
 985         u8                      rsvd1[24];
 986 };
 987
 988 struct mlx5_map_eq_mbox_out {
 989         struct mlx5_outbox_hdr  hdr;
 990         u8                      rsvd[8];
 991 };
 992
 993 struct mlx5_query_eq_mbox_in {
 994         struct mlx5_inbox_hdr   hdr;
 995         u8                      rsvd0[3];
 996         u8                      eqn;
 997         u8                      rsvd1[4];
 998 };
 999
1000 struct mlx5_query_eq_mbox_out {
1001         struct mlx5_outbox_hdr  hdr;
1002         u8                      rsvd[8];
1003         struct mlx5_eq_context  ctx;
1004 };
1005
1006 enum {
1007         MLX5_MKEY_STATUS_FREE = 1 << 6,
1008 };
1009
1010 struct mlx5_mkey_seg {
1011         /* This is a two bit field occupying bits 31-30.
1012          * bit 31 is always 0,
1013          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
1014          */
1015         u8              status;
1016         u8              pcie_control;
1017         u8              flags;
1018         u8              version;
1019         __be32          qpn_mkey7_0;
1020         u8              rsvd1[4];
1021         __be32          flags_pd;
1022         __be64          start_addr;
1023         __be64          len;
1024         __be32          bsfs_octo_size;
1025         u8              rsvd2[16];
1026         __be32          xlt_oct_size;
1027         u8              rsvd3[3];
1028         u8              log2_page_size;
1029         u8              rsvd4[4];
1030 };
1031
1032 struct mlx5_query_special_ctxs_mbox_in {
1033         struct mlx5_inbox_hdr   hdr;
1034         u8                      rsvd[8];
1035 };
1036
1037 struct mlx5_query_special_ctxs_mbox_out {
1038         struct mlx5_outbox_hdr  hdr;
1039         __be32                  dump_fill_mkey;
1040         __be32                  reserved_lkey;
1041 };
1042
1043 struct mlx5_create_mkey_mbox_in {
1044         struct mlx5_inbox_hdr   hdr;
1045         __be32                  input_mkey_index;
1046         __be32                  flags;
1047         struct mlx5_mkey_seg    seg;
1048         u8                      rsvd1[16];
1049         __be32                  xlat_oct_act_size;
1050         __be32                  rsvd2;
1051         u8                      rsvd3[168];
1052         __be64                  pas[0];
1053 };
1054
1055 struct mlx5_create_mkey_mbox_out {
1056         struct mlx5_outbox_hdr  hdr;
1057         __be32                  mkey;
1058         u8                      rsvd[4];
1059 };
1060
1061 struct mlx5_destroy_mkey_mbox_in {
1062         struct mlx5_inbox_hdr   hdr;
1063         __be32                  mkey;
1064         u8                      rsvd[4];
1065 };
1066
1067 struct mlx5_destroy_mkey_mbox_out {
1068         struct mlx5_outbox_hdr  hdr;
1069         u8                      rsvd[8];
1070 };
1071
1072 struct mlx5_query_mkey_mbox_in {
1073         struct mlx5_inbox_hdr   hdr;
1074         __be32                  mkey;
1075 };
1076
1077 struct mlx5_query_mkey_mbox_out {
1078         struct mlx5_outbox_hdr  hdr;
1079         __be64                  pas[0];
1080 };
1081
1082 struct mlx5_modify_mkey_mbox_in {
1083         struct mlx5_inbox_hdr   hdr;
1084         __be32                  mkey;
1085         __be64                  pas[0];
1086 };
1087
1088 struct mlx5_modify_mkey_mbox_out {
1089         struct mlx5_outbox_hdr  hdr;
1090         u8                      rsvd[8];
1091 };
1092
1093 struct mlx5_dump_mkey_mbox_in {
1094         struct mlx5_inbox_hdr   hdr;
1095 };
1096
1097 struct mlx5_dump_mkey_mbox_out {
1098         struct mlx5_outbox_hdr  hdr;
1099         __be32                  mkey;
1100 };
1101
1102 struct mlx5_mad_ifc_mbox_in {
1103         struct mlx5_inbox_hdr   hdr;
1104         __be16                  remote_lid;
1105         u8                      rsvd0;
1106         u8                      port;
1107         u8                      rsvd1[4];
1108         u8                      data[256];
1109 };
1110
1111 struct mlx5_mad_ifc_mbox_out {
1112         struct mlx5_outbox_hdr  hdr;
1113         u8                      rsvd[8];
1114         u8                      data[256];
1115 };
1116
1117 struct mlx5_access_reg_mbox_in {
1118         struct mlx5_inbox_hdr           hdr;
1119         u8                              rsvd0[2];
1120         __be16                          register_id;
1121         __be32                          arg;
1122         __be32                          data[0];
1123 };
1124
1125 struct mlx5_access_reg_mbox_out {
1126         struct mlx5_outbox_hdr          hdr;
1127         u8                              rsvd[8];
1128         __be32                          data[0];
1129 };
1130
1131 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
1132
1133 enum {
1134         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
1135 };
1136
1137 struct mlx5_allocate_psv_in {
1138         struct mlx5_inbox_hdr   hdr;
1139         __be32                  npsv_pd;
1140         __be32                  rsvd_psv0;
1141 };
1142
1143 struct mlx5_allocate_psv_out {
1144         struct mlx5_outbox_hdr  hdr;
1145         u8                      rsvd[8];
1146         __be32                  psv_idx[4];
1147 };
1148
1149 struct mlx5_destroy_psv_in {
1150         struct mlx5_inbox_hdr   hdr;
1151         __be32                  psv_number;
1152         u8                      rsvd[4];
1153 };
1154
1155 struct mlx5_destroy_psv_out {
1156         struct mlx5_outbox_hdr  hdr;
1157         u8                      rsvd[8];
1158 };
1159
1160 #define MLX5_CMD_OP_MAX 0x920
1161
1162 enum {
1163         VPORT_STATE_DOWN                = 0x0,
1164         VPORT_STATE_UP                  = 0x1,
1165 };
1166
1167 enum {
1168         MLX5_ESW_VPORT_ADMIN_STATE_DOWN  = 0x0,
1169         MLX5_ESW_VPORT_ADMIN_STATE_UP    = 0x1,
1170         MLX5_ESW_VPORT_ADMIN_STATE_AUTO  = 0x2,
1171 };
1172
1173 enum {
1174         MLX5_L3_PROT_TYPE_IPV4          = 0,
1175         MLX5_L3_PROT_TYPE_IPV6          = 1,
1176 };
1177
1178 enum {
1179         MLX5_L4_PROT_TYPE_TCP           = 0,
1180         MLX5_L4_PROT_TYPE_UDP           = 1,
1181 };
1182
1183 enum {
1184         MLX5_HASH_FIELD_SEL_SRC_IP      = 1 << 0,
1185         MLX5_HASH_FIELD_SEL_DST_IP      = 1 << 1,
1186         MLX5_HASH_FIELD_SEL_L4_SPORT    = 1 << 2,
1187         MLX5_HASH_FIELD_SEL_L4_DPORT    = 1 << 3,
1188         MLX5_HASH_FIELD_SEL_IPSEC_SPI   = 1 << 4,
1189 };
1190
1191 enum {
1192         MLX5_MATCH_OUTER_HEADERS        = 1 << 0,
1193         MLX5_MATCH_MISC_PARAMETERS      = 1 << 1,
1194         MLX5_MATCH_INNER_HEADERS        = 1 << 2,
1195
1196 };
1197
1198 enum {
1199         MLX5_FLOW_TABLE_TYPE_NIC_RCV    = 0,
1200         MLX5_FLOW_TABLE_TYPE_ESWITCH    = 4,
1201 };
1202
1203 enum {
1204         MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT       = 0,
1205         MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE  = 1,
1206         MLX5_FLOW_CONTEXT_DEST_TYPE_TIR         = 2,
1207 };
1208
1209 enum mlx5_list_type {
1210         MLX5_NVPRT_LIST_TYPE_UC   = 0x0,
1211         MLX5_NVPRT_LIST_TYPE_MC   = 0x1,
1212         MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1213 };
1214
1215 enum {
1216         MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1217         MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM    = 0x1,
1218 };
1219
1220 enum mlx5_wol_mode {
1221         MLX5_WOL_DISABLE        = 0,
1222         MLX5_WOL_SECURED_MAGIC  = 1 << 1,
1223         MLX5_WOL_MAGIC          = 1 << 2,
1224         MLX5_WOL_ARP            = 1 << 3,
1225         MLX5_WOL_BROADCAST      = 1 << 4,
1226         MLX5_WOL_MULTICAST      = 1 << 5,
1227         MLX5_WOL_UNICAST        = 1 << 6,
1228         MLX5_WOL_PHY_ACTIVITY   = 1 << 7,
1229 };
1230
1231 /* MLX5 DEV CAPs */
1232
1233 /* TODO: EAT.ME */
1234 enum mlx5_cap_mode {
1235         HCA_CAP_OPMOD_GET_MAX   = 0,
1236         HCA_CAP_OPMOD_GET_CUR   = 1,
1237 };
1238
1239 enum mlx5_cap_type {
1240         MLX5_CAP_GENERAL = 0,
1241         MLX5_CAP_ETHERNET_OFFLOADS,
1242         MLX5_CAP_ODP,
1243         MLX5_CAP_ATOMIC,
1244         MLX5_CAP_ROCE,
1245         MLX5_CAP_IPOIB_OFFLOADS,
1246         MLX5_CAP_EOIB_OFFLOADS,
1247         MLX5_CAP_FLOW_TABLE,
1248         MLX5_CAP_ESWITCH_FLOW_TABLE,
1249         MLX5_CAP_ESWITCH,
1250         MLX5_CAP_RESERVED,
1251         MLX5_CAP_VECTOR_CALC,
1252         /* NUM OF CAP Types */
1253         MLX5_CAP_NUM
1254 };
1255
1256 /* GET Dev Caps macros */
1257 #define MLX5_CAP_GEN(mdev, cap) \
1258         MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1259
1260 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1261         MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1262
1263 #define MLX5_CAP_ETH(mdev, cap) \
1264         MLX5_GET(per_protocol_networking_offload_caps,\
1265                  mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1266
1267 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1268         MLX5_GET(per_protocol_networking_offload_caps,\
1269                  mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1270
1271 #define MLX5_CAP_ROCE(mdev, cap) \
1272         MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1273
1274 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1275         MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1276
1277 #define MLX5_CAP_ATOMIC(mdev, cap) \
1278         MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1279
1280 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1281         MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1282
1283 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1284         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1285
1286 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1287         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1288
1289 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1290         MLX5_GET(flow_table_eswitch_cap, \
1291                  mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1292
1293 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1294         MLX5_GET(flow_table_eswitch_cap, \
1295                  mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1296
1297 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1298         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1299
1300 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1301         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1302
1303 #define MLX5_CAP_ESW(mdev, cap) \
1304         MLX5_GET(e_switch_cap, \
1305                  mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1306
1307 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1308         MLX5_GET(e_switch_cap, \
1309                  mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1310
1311 #define MLX5_CAP_ODP(mdev, cap)\
1312         MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1313
1314 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1315         MLX5_GET(vector_calc_cap, \
1316                  mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1317
1318 enum {
1319         MLX5_CMD_STAT_OK                        = 0x0,
1320         MLX5_CMD_STAT_INT_ERR                   = 0x1,
1321         MLX5_CMD_STAT_BAD_OP_ERR                = 0x2,
1322         MLX5_CMD_STAT_BAD_PARAM_ERR             = 0x3,
1323         MLX5_CMD_STAT_BAD_SYS_STATE_ERR         = 0x4,
1324         MLX5_CMD_STAT_BAD_RES_ERR               = 0x5,
1325         MLX5_CMD_STAT_RES_BUSY                  = 0x6,
1326         MLX5_CMD_STAT_LIM_ERR                   = 0x8,
1327         MLX5_CMD_STAT_BAD_RES_STATE_ERR         = 0x9,
1328         MLX5_CMD_STAT_IX_ERR                    = 0xa,
1329         MLX5_CMD_STAT_NO_RES_ERR                = 0xf,
1330         MLX5_CMD_STAT_BAD_INP_LEN_ERR           = 0x50,
1331         MLX5_CMD_STAT_BAD_OUTP_LEN_ERR          = 0x51,
1332         MLX5_CMD_STAT_BAD_QP_STATE_ERR          = 0x10,
1333         MLX5_CMD_STAT_BAD_PKT_ERR               = 0x30,
1334         MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR    = 0x40,
1335 };
1336
1337 enum {
1338         MLX5_IEEE_802_3_COUNTERS_GROUP        = 0x0,
1339         MLX5_RFC_2863_COUNTERS_GROUP          = 0x1,
1340         MLX5_RFC_2819_COUNTERS_GROUP          = 0x2,
1341         MLX5_RFC_3635_COUNTERS_GROUP          = 0x3,
1342         MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1343         MLX5_PER_PRIORITY_COUNTERS_GROUP      = 0x10,
1344         MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1345         MLX5_INFINIBAND_PORT_COUNTERS_GROUP   = 0x20,
1346 };
1347
1348 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1349 {
1350         if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1351                 return 0;
1352         return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1353 }
1354
1355 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1356 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1357 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1358 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1359                                 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1360                                 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1361
1362 #endif /* MLX5_DEVICE_H */