2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
45 #include <linux/mlx5/device.h>
46 #include <linux/mlx5/doorbell.h>
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
64 CMD_STATUS_SUCCESS = 0,
70 MLX5_SQP_IEEE_1588 = 2,
72 MLX5_SQP_SYNC_UMR = 4,
80 MLX5_EQ_VEC_PAGES = 0,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
87 MLX5_MAX_IRQ_NAME = 32
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
106 MLX5_REG_PFCC = 0x5007,
107 MLX5_REG_PPCNT = 0x5008,
108 MLX5_REG_PMAOS = 0x5012,
109 MLX5_REG_PUDE = 0x5009,
110 MLX5_REG_PMPE = 0x5010,
111 MLX5_REG_PELC = 0x500e,
112 MLX5_REG_PVLC = 0x500f,
113 MLX5_REG_PMLP = 0, /* TBD */
114 MLX5_REG_NODE_DESC = 0x6001,
115 MLX5_REG_HOST_ENDIANNESS = 0x7004,
118 enum mlx5_page_fault_resume_flags {
119 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
120 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
121 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
122 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
131 struct mlx5_field_desc {
136 struct mlx5_rsc_debug {
137 struct mlx5_core_dev *dev;
139 enum dbg_rsc_type type;
141 struct mlx5_field_desc fields[0];
144 enum mlx5_dev_event {
145 MLX5_DEV_EVENT_SYS_ERROR,
146 MLX5_DEV_EVENT_PORT_UP,
147 MLX5_DEV_EVENT_PORT_DOWN,
148 MLX5_DEV_EVENT_PORT_INITIALIZED,
149 MLX5_DEV_EVENT_LID_CHANGE,
150 MLX5_DEV_EVENT_PKEY_CHANGE,
151 MLX5_DEV_EVENT_GUID_CHANGE,
152 MLX5_DEV_EVENT_CLIENT_REREG,
155 enum mlx5_port_status {
160 struct mlx5_uuar_info {
161 struct mlx5_uar *uars;
163 int num_low_latency_uuars;
164 unsigned long *bitmap;
169 * protect uuar allocation data structs
177 void __iomem *regreg;
179 struct mlx5_uar *uar;
180 unsigned long offset;
182 /* protect blue flame buffer selection when needed
186 /* serialize 64 bit writes when done as two 32 bit accesses
192 struct mlx5_cmd_first {
196 struct mlx5_cmd_msg {
197 struct list_head list;
198 struct cache_ent *cache;
200 struct mlx5_cmd_first first;
201 struct mlx5_cmd_mailbox *next;
204 struct mlx5_cmd_debug {
205 struct dentry *dbg_root;
206 struct dentry *dbg_in;
207 struct dentry *dbg_out;
208 struct dentry *dbg_outlen;
209 struct dentry *dbg_status;
210 struct dentry *dbg_run;
219 /* protect block chain allocations
222 struct list_head head;
225 struct cmd_msg_cache {
226 struct cache_ent large;
227 struct cache_ent med;
231 struct mlx5_cmd_stats {
236 struct dentry *count;
237 /* protect command average calculations */
243 dma_addr_t alloc_dma;
254 /* protect command queue allocations
256 spinlock_t alloc_lock;
258 /* protect token allocations
260 spinlock_t token_lock;
262 unsigned long bitmask;
263 char wq_name[MLX5_CMD_WQ_MAX_NAME];
264 struct workqueue_struct *wq;
265 struct semaphore sem;
266 struct semaphore pages_sem;
268 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
269 struct pci_pool *pool;
270 struct mlx5_cmd_debug dbg;
271 struct cmd_msg_cache cache;
272 int checksum_disabled;
273 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
276 struct mlx5_port_caps {
282 struct mlx5_cmd_mailbox {
285 struct mlx5_cmd_mailbox *next;
288 struct mlx5_buf_list {
294 struct mlx5_buf_list direct;
301 struct mlx5_core_dev *dev;
302 __be32 __iomem *doorbell;
310 struct list_head list;
312 struct mlx5_rsc_debug *dbg;
315 struct mlx5_core_psv {
327 struct mlx5_core_sig_ctx {
328 struct mlx5_core_psv psv_memory;
329 struct mlx5_core_psv psv_wire;
330 struct ib_sig_err err_item;
331 bool sig_status_checked;
336 struct mlx5_core_mr {
349 struct mlx5_core_rsc_common {
350 enum mlx5_res_type res;
352 struct completion free;
355 struct mlx5_core_srq {
356 struct mlx5_core_rsc_common common; /* must be first */
360 int max_avail_gather;
362 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
365 struct completion free;
368 struct mlx5_eq_table {
369 void __iomem *update_ci;
370 void __iomem *update_arm_ci;
371 struct list_head comp_eqs_list;
372 struct mlx5_eq pages_eq;
373 struct mlx5_eq async_eq;
374 struct mlx5_eq cmd_eq;
375 int num_comp_vectors;
383 struct list_head bf_list;
384 unsigned free_bf_bmap;
385 void __iomem *bf_map;
390 struct mlx5_core_health {
391 struct health_buffer __iomem *health;
392 __be32 __iomem *health_counter;
393 struct timer_list timer;
397 struct workqueue_struct *wq;
398 struct work_struct work;
401 struct mlx5_cq_table {
402 /* protect radix tree
405 struct radix_tree_root tree;
408 struct mlx5_qp_table {
409 /* protect radix tree
412 struct radix_tree_root tree;
415 struct mlx5_srq_table {
416 /* protect radix tree
419 struct radix_tree_root tree;
422 struct mlx5_mr_table {
423 /* protect radix tree
426 struct radix_tree_root tree;
429 struct mlx5_irq_info {
431 char name[MLX5_MAX_IRQ_NAME];
435 char name[MLX5_MAX_NAME_LEN];
436 struct mlx5_eq_table eq_table;
437 struct msix_entry *msix_arr;
438 struct mlx5_irq_info *irq_info;
439 struct mlx5_uuar_info uuari;
440 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
442 struct io_mapping *bf_mapping;
445 struct workqueue_struct *pg_wq;
446 struct rb_root page_root;
449 struct list_head free_list;
451 struct mlx5_core_health health;
453 struct mlx5_srq_table srq_table;
455 /* start: qp staff */
456 struct mlx5_qp_table qp_table;
457 struct dentry *qp_debugfs;
458 struct dentry *eq_debugfs;
459 struct dentry *cq_debugfs;
460 struct dentry *cmdif_debugfs;
463 /* start: cq staff */
464 struct mlx5_cq_table cq_table;
467 /* start: mr staff */
468 struct mlx5_mr_table mr_table;
471 /* start: alloc staff */
472 /* protect buffer alocation according to numa node */
473 struct mutex alloc_mutex;
476 struct mutex pgdir_mutex;
477 struct list_head pgdir_list;
478 /* end: alloc staff */
479 struct dentry *dbg_root;
481 /* protect mkey key part */
482 spinlock_t mkey_lock;
485 struct list_head dev_list;
486 struct list_head ctx_list;
490 struct mlx5_core_dev {
491 struct pci_dev *pdev;
493 char board_id[MLX5_BOARD_ID_LEN];
495 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
496 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
497 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
498 phys_addr_t iseg_base;
499 struct mlx5_init_seg __iomem *iseg;
500 void (*event) (struct mlx5_core_dev *dev,
501 enum mlx5_dev_event event,
502 unsigned long param);
503 struct mlx5_priv priv;
504 struct mlx5_profile *profile;
512 struct mlx5_db_pgdir *pgdir;
513 struct mlx5_ib_user_db_page *user_page;
520 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
524 MLX5_COMP_EQ_SIZE = 1024,
528 MLX5_PTYS_IB = 1 << 0,
529 MLX5_PTYS_EN = 1 << 2,
532 struct mlx5_db_pgdir {
533 struct list_head list;
534 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
539 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
541 struct mlx5_cmd_work_ent {
542 struct mlx5_cmd_msg *in;
543 struct mlx5_cmd_msg *out;
546 mlx5_cmd_cbk_t callback;
549 struct completion done;
550 struct mlx5_cmd *cmd;
551 struct work_struct work;
552 struct mlx5_cmd_layout *lay;
567 enum port_state_policy {
571 enum phy_port_state {
575 struct mlx5_hca_vport_context {
580 enum port_state_policy policy;
581 enum phy_port_state phys_state;
582 enum ib_port_state vport_state;
583 u8 port_physical_state;
592 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
597 u16 qkey_violation_counter;
598 u16 pkey_violation_counter;
602 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
604 return buf->direct.buf + offset;
607 extern struct workqueue_struct *mlx5_core_wq;
609 #define STRUCT_FIELD(header, field) \
610 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
611 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
614 size_t struct_offset_bytes;
615 size_t struct_size_bytes;
620 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
622 return pci_get_drvdata(pdev);
625 extern struct dentry *mlx5_debugfs_root;
627 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
629 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
632 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
634 return ioread32be(&dev->iseg->fw_rev) >> 16;
637 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
639 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
642 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
644 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
647 static inline void *mlx5_vzalloc(unsigned long size)
651 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
657 static inline u32 mlx5_base_mkey(const u32 key)
659 return key & 0xffffff00u;
662 int mlx5_cmd_init(struct mlx5_core_dev *dev);
663 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
664 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
665 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
666 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
667 int mlx5_cmd_status_to_err_v2(void *ptr);
668 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
669 enum mlx5_cap_mode cap_mode);
670 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
672 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
673 void *out, int out_size, mlx5_cmd_cbk_t callback,
675 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
676 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
677 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
678 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
679 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
680 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
681 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
682 int mlx5_health_init(struct mlx5_core_dev *dev);
683 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
684 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
685 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
686 struct mlx5_buf *buf, int node);
687 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
688 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
689 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
690 gfp_t flags, int npages);
691 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
692 struct mlx5_cmd_mailbox *head);
693 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
694 struct mlx5_create_srq_mbox_in *in, int inlen,
696 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
697 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
698 struct mlx5_query_srq_mbox_out *out);
699 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
700 u16 lwm, int is_srq);
701 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
702 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
703 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
704 struct mlx5_create_mkey_mbox_in *in, int inlen,
705 mlx5_cmd_cbk_t callback, void *context,
706 struct mlx5_create_mkey_mbox_out *out);
707 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
708 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
709 struct mlx5_query_mkey_mbox_out *out, int outlen);
710 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
712 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
713 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
714 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
716 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
717 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
718 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
719 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
720 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
722 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
723 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
724 void mlx5_register_debugfs(void);
725 void mlx5_unregister_debugfs(void);
726 int mlx5_eq_init(struct mlx5_core_dev *dev);
727 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
728 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
729 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
730 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
731 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
732 void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
734 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
735 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
736 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
737 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
738 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
739 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
740 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
741 int mlx5_start_eqs(struct mlx5_core_dev *dev);
742 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
743 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
744 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
745 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
747 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
748 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
749 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
750 int size_in, void *data_out, int size_out,
751 u16 reg_num, int arg, int write);
753 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
754 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
755 int ptys_size, int proto_mask, u8 local_port);
756 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
757 u32 *proto_cap, int proto_mask);
758 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
759 u32 *proto_admin, int proto_mask);
760 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
761 u8 *link_width_oper, u8 local_port);
762 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
763 u8 *proto_oper, int proto_mask,
765 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
767 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
768 enum mlx5_port_status status);
769 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
770 enum mlx5_port_status *status);
772 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port);
773 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port);
774 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
777 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
778 u8 *vl_hw_cap, u8 local_port);
780 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
781 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
782 u32 *rx_pause, u32 *tx_pause);
784 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
785 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
786 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
787 struct mlx5_query_eq_mbox_out *out, int outlen);
788 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
789 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
790 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
791 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
792 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
793 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
795 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
797 const char *mlx5_command_str(int command);
798 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
799 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
800 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
801 int npsvs, u32 *sig_index);
802 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
803 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
804 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
805 struct mlx5_odp_caps *odp_caps);
807 static inline u32 mlx5_mkey_to_idx(u32 mkey)
812 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
814 return mkey_idx << 8;
817 static inline u8 mlx5_mkey_variant(u32 mkey)
823 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
824 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
828 MAX_MR_CACHE_ENTRIES = 16,
832 MLX5_INTERFACE_PROTOCOL_IB = 0,
833 MLX5_INTERFACE_PROTOCOL_ETH = 1,
836 struct mlx5_interface {
837 void * (*add)(struct mlx5_core_dev *dev);
838 void (*remove)(struct mlx5_core_dev *dev, void *context);
839 void (*event)(struct mlx5_core_dev *dev, void *context,
840 enum mlx5_dev_event event, unsigned long param);
841 void * (*get_dev)(void *context);
843 struct list_head list;
846 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
847 int mlx5_register_interface(struct mlx5_interface *intf);
848 void mlx5_unregister_interface(struct mlx5_interface *intf);
849 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
851 struct mlx5_profile {
857 } mr_cache[MAX_MR_CACHE_ENTRIES];
860 static inline int mlx5_get_gid_table_len(u16 param)
863 pr_warn("gid table length is zero\n");
867 return 8 * (1 << param);
871 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
874 #endif /* MLX5_DRIVER_H */