include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  71         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  72         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  73         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  74         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  75         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  76         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  77         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  78         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  79         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  80         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  81         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  82         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  83         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  84         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  85         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  86         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  87         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  88         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  89         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  90         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  91         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  92         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  93         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  94         MLX5_CMD_OP_CREATE_QP                     = 0x500,
  95         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
  96         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
  97         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
  98         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
  99         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 100         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 101         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 102         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 103         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 104         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 105         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 106         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 107         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 108         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 109         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 110         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 111         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 112         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 113         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 114         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 115         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 116         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 117         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 118         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 119         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 120         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 121         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 122         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 123         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 124         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 125         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 126         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 127         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 128         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 129         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 130         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 131         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 132         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 133         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 134         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 135         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 136         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 137         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 138         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 139         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 140         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 141         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 142         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 143         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 144         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 145         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 146         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 147         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 148         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 149         MLX5_CMD_OP_NOP                           = 0x80d,
 150         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 151         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 152         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 153         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 154         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 155         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 156         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 157         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 158         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 159         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 160         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 161         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 162         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 163         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 164         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 165         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 166         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 167         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 168         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 169         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 170         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 171         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 172         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 173         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 174         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 175         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 176         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 177         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 178         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 179         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 180         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 181         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 182         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 183         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 184         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 185         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 186         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 187         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 188         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 189         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 190         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 191         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 192         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 193         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 194         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 195         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 196         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 197         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938
 198 };
 199
 200 struct mlx5_ifc_flow_table_fields_supported_bits {
 201         u8         outer_dmac[0x1];
 202         u8         outer_smac[0x1];
 203         u8         outer_ether_type[0x1];
 204         u8         reserved_0[0x1];
 205         u8         outer_first_prio[0x1];
 206         u8         outer_first_cfi[0x1];
 207         u8         outer_first_vid[0x1];
 208         u8         reserved_1[0x1];
 209         u8         outer_second_prio[0x1];
 210         u8         outer_second_cfi[0x1];
 211         u8         outer_second_vid[0x1];
 212         u8         reserved_2[0x1];
 213         u8         outer_sip[0x1];
 214         u8         outer_dip[0x1];
 215         u8         outer_frag[0x1];
 216         u8         outer_ip_protocol[0x1];
 217         u8         outer_ip_ecn[0x1];
 218         u8         outer_ip_dscp[0x1];
 219         u8         outer_udp_sport[0x1];
 220         u8         outer_udp_dport[0x1];
 221         u8         outer_tcp_sport[0x1];
 222         u8         outer_tcp_dport[0x1];
 223         u8         outer_tcp_flags[0x1];
 224         u8         outer_gre_protocol[0x1];
 225         u8         outer_gre_key[0x1];
 226         u8         outer_vxlan_vni[0x1];
 227         u8         reserved_3[0x5];
 228         u8         source_eswitch_port[0x1];
 229
 230         u8         inner_dmac[0x1];
 231         u8         inner_smac[0x1];
 232         u8         inner_ether_type[0x1];
 233         u8         reserved_4[0x1];
 234         u8         inner_first_prio[0x1];
 235         u8         inner_first_cfi[0x1];
 236         u8         inner_first_vid[0x1];
 237         u8         reserved_5[0x1];
 238         u8         inner_second_prio[0x1];
 239         u8         inner_second_cfi[0x1];
 240         u8         inner_second_vid[0x1];
 241         u8         reserved_6[0x1];
 242         u8         inner_sip[0x1];
 243         u8         inner_dip[0x1];
 244         u8         inner_frag[0x1];
 245         u8         inner_ip_protocol[0x1];
 246         u8         inner_ip_ecn[0x1];
 247         u8         inner_ip_dscp[0x1];
 248         u8         inner_udp_sport[0x1];
 249         u8         inner_udp_dport[0x1];
 250         u8         inner_tcp_sport[0x1];
 251         u8         inner_tcp_dport[0x1];
 252         u8         inner_tcp_flags[0x1];
 253         u8         reserved_7[0x9];
 254
 255         u8         reserved_8[0x40];
 256 };
 257
 258 struct mlx5_ifc_flow_table_prop_layout_bits {
 259         u8         ft_support[0x1];
 260         u8         reserved_0[0x2];
 261         u8         flow_modify_en[0x1];
 262         u8         modify_root[0x1];
 263         u8         reserved_1[0x1b];
 264
 265         u8         reserved_2[0x2];
 266         u8         log_max_ft_size[0x6];
 267         u8         reserved_3[0x10];
 268         u8         max_ft_level[0x8];
 269
 270         u8         reserved_4[0x20];
 271
 272         u8         reserved_5[0x18];
 273         u8         log_max_ft_num[0x8];
 274
 275         u8         reserved_6[0x18];
 276         u8         log_max_destination[0x8];
 277
 278         u8         reserved_7[0x18];
 279         u8         log_max_flow[0x8];
 280
 281         u8         reserved_8[0x40];
 282
 283         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 284
 285         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 286 };
 287
 288 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 289         u8         send[0x1];
 290         u8         receive[0x1];
 291         u8         write[0x1];
 292         u8         read[0x1];
 293         u8         reserved_0[0x1];
 294         u8         srq_receive[0x1];
 295         u8         reserved_1[0x1a];
 296 };
 297
 298 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 299         u8         smac_47_16[0x20];
 300
 301         u8         smac_15_0[0x10];
 302         u8         ethertype[0x10];
 303
 304         u8         dmac_47_16[0x20];
 305
 306         u8         dmac_15_0[0x10];
 307         u8         first_prio[0x3];
 308         u8         first_cfi[0x1];
 309         u8         first_vid[0xc];
 310
 311         u8         ip_protocol[0x8];
 312         u8         ip_dscp[0x6];
 313         u8         ip_ecn[0x2];
 314         u8         vlan_tag[0x1];
 315         u8         reserved_0[0x1];
 316         u8         frag[0x1];
 317         u8         reserved_1[0x4];
 318         u8         tcp_flags[0x9];
 319
 320         u8         tcp_sport[0x10];
 321         u8         tcp_dport[0x10];
 322
 323         u8         reserved_2[0x20];
 324
 325         u8         udp_sport[0x10];
 326         u8         udp_dport[0x10];
 327
 328         u8         src_ip[4][0x20];
 329
 330         u8         dst_ip[4][0x20];
 331 };
 332
 333 struct mlx5_ifc_fte_match_set_misc_bits {
 334         u8         reserved_0[0x20];
 335
 336         u8         reserved_1[0x10];
 337         u8         source_port[0x10];
 338
 339         u8         outer_second_prio[0x3];
 340         u8         outer_second_cfi[0x1];
 341         u8         outer_second_vid[0xc];
 342         u8         inner_second_prio[0x3];
 343         u8         inner_second_cfi[0x1];
 344         u8         inner_second_vid[0xc];
 345
 346         u8         outer_second_vlan_tag[0x1];
 347         u8         inner_second_vlan_tag[0x1];
 348         u8         reserved_2[0xe];
 349         u8         gre_protocol[0x10];
 350
 351         u8         gre_key_h[0x18];
 352         u8         gre_key_l[0x8];
 353
 354         u8         vxlan_vni[0x18];
 355         u8         reserved_3[0x8];
 356
 357         u8         reserved_4[0x20];
 358
 359         u8         reserved_5[0xc];
 360         u8         outer_ipv6_flow_label[0x14];
 361
 362         u8         reserved_6[0xc];
 363         u8         inner_ipv6_flow_label[0x14];
 364
 365         u8         reserved_7[0xe0];
 366 };
 367
 368 struct mlx5_ifc_cmd_pas_bits {
 369         u8         pa_h[0x20];
 370
 371         u8         pa_l[0x14];
 372         u8         reserved_0[0xc];
 373 };
 374
 375 struct mlx5_ifc_uint64_bits {
 376         u8         hi[0x20];
 377
 378         u8         lo[0x20];
 379 };
 380
 381 enum {
 382         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 383         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 384         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 385         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 386         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 387         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 388         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 389         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 390         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 391         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 392 };
 393
 394 struct mlx5_ifc_ads_bits {
 395         u8         fl[0x1];
 396         u8         free_ar[0x1];
 397         u8         reserved_0[0xe];
 398         u8         pkey_index[0x10];
 399
 400         u8         reserved_1[0x8];
 401         u8         grh[0x1];
 402         u8         mlid[0x7];
 403         u8         rlid[0x10];
 404
 405         u8         ack_timeout[0x5];
 406         u8         reserved_2[0x3];
 407         u8         src_addr_index[0x8];
 408         u8         reserved_3[0x4];
 409         u8         stat_rate[0x4];
 410         u8         hop_limit[0x8];
 411
 412         u8         reserved_4[0x4];
 413         u8         tclass[0x8];
 414         u8         flow_label[0x14];
 415
 416         u8         rgid_rip[16][0x8];
 417
 418         u8         reserved_5[0x4];
 419         u8         f_dscp[0x1];
 420         u8         f_ecn[0x1];
 421         u8         reserved_6[0x1];
 422         u8         f_eth_prio[0x1];
 423         u8         ecn[0x2];
 424         u8         dscp[0x6];
 425         u8         udp_sport[0x10];
 426
 427         u8         dei_cfi[0x1];
 428         u8         eth_prio[0x3];
 429         u8         sl[0x4];
 430         u8         port[0x8];
 431         u8         rmac_47_32[0x10];
 432
 433         u8         rmac_31_0[0x20];
 434 };
 435
 436 struct mlx5_ifc_flow_table_nic_cap_bits {
 437         u8         reserved_0[0x200];
 438
 439         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 440
 441         u8         reserved_1[0x200];
 442
 443         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 444
 445         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 446
 447         u8         reserved_2[0x200];
 448
 449         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 450
 451         u8         reserved_3[0x7200];
 452 };
 453
 454 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 455         u8     reserved_0[0x200];
 456
 457         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 458
 459         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 460
 461         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 462
 463         u8      reserved_1[0x7800];
 464 };
 465
 466 struct mlx5_ifc_e_switch_cap_bits {
 467         u8         vport_svlan_strip[0x1];
 468         u8         vport_cvlan_strip[0x1];
 469         u8         vport_svlan_insert[0x1];
 470         u8         vport_cvlan_insert_if_not_exist[0x1];
 471         u8         vport_cvlan_insert_overwrite[0x1];
 472         u8         reserved_0[0x1b];
 473
 474         u8         reserved_1[0x7e0];
 475 };
 476
 477 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 478         u8         csum_cap[0x1];
 479         u8         vlan_cap[0x1];
 480         u8         lro_cap[0x1];
 481         u8         lro_psh_flag[0x1];
 482         u8         lro_time_stamp[0x1];
 483         u8         reserved_0[0x3];
 484         u8         self_lb_en_modifiable[0x1];
 485         u8         reserved_1[0x2];
 486         u8         max_lso_cap[0x5];
 487         u8         reserved_2[0x4];
 488         u8         rss_ind_tbl_cap[0x4];
 489         u8         reserved_3[0x3];
 490         u8         tunnel_lso_const_out_ip_id[0x1];
 491         u8         reserved_4[0x2];
 492         u8         tunnel_statless_gre[0x1];
 493         u8         tunnel_stateless_vxlan[0x1];
 494
 495         u8         reserved_5[0x20];
 496
 497         u8         reserved_6[0x10];
 498         u8         lro_min_mss_size[0x10];
 499
 500         u8         reserved_7[0x120];
 501
 502         u8         lro_timer_supported_periods[4][0x20];
 503
 504         u8         reserved_8[0x600];
 505 };
 506
 507 struct mlx5_ifc_roce_cap_bits {
 508         u8         roce_apm[0x1];
 509         u8         reserved_0[0x1f];
 510
 511         u8         reserved_1[0x60];
 512
 513         u8         reserved_2[0xc];
 514         u8         l3_type[0x4];
 515         u8         reserved_3[0x8];
 516         u8         roce_version[0x8];
 517
 518         u8         reserved_4[0x10];
 519         u8         r_roce_dest_udp_port[0x10];
 520
 521         u8         r_roce_max_src_udp_port[0x10];
 522         u8         r_roce_min_src_udp_port[0x10];
 523
 524         u8         reserved_5[0x10];
 525         u8         roce_address_table_size[0x10];
 526
 527         u8         reserved_6[0x700];
 528 };
 529
 530 enum {
 531         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 532         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 533         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 534         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 535         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 536         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 537         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 538         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 539         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 540 };
 541
 542 enum {
 543         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 544         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 545         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 546         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 547         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 548         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 549         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 550         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 551         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 552 };
 553
 554 struct mlx5_ifc_atomic_caps_bits {
 555         u8         reserved_0[0x40];
 556
 557         u8         atomic_req_endianness[0x1];
 558         u8         reserved_1[0x1f];
 559
 560         u8         reserved_2[0x20];
 561
 562         u8         reserved_3[0x10];
 563         u8         atomic_operations[0x10];
 564
 565         u8         reserved_4[0x10];
 566         u8         atomic_size_qp[0x10];
 567
 568         u8         reserved_5[0x10];
 569         u8         atomic_size_dc[0x10];
 570
 571         u8         reserved_6[0x720];
 572 };
 573
 574 struct mlx5_ifc_odp_cap_bits {
 575         u8         reserved_0[0x40];
 576
 577         u8         sig[0x1];
 578         u8         reserved_1[0x1f];
 579
 580         u8         reserved_2[0x20];
 581
 582         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 583
 584         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 585
 586         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 587
 588         u8         reserved_3[0x720];
 589 };
 590
 591 enum {
 592         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 593         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 594         MLX5_WQ_TYPE_STRQ         = 0x2,
 595 };
 596
 597 enum {
 598         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 599         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 600 };
 601
 602 enum {
 603         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 604         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 605         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 606         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 607         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 608 };
 609
 610 enum {
 611         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 612         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 613         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 614         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 615         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 616         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 617 };
 618
 619 enum {
 620         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 621         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 622 };
 623
 624 enum {
 625         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 626         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 627         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 628 };
 629
 630 enum {
 631         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 632         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 633 };
 634
 635 struct mlx5_ifc_cmd_hca_cap_bits {
 636         u8         reserved_0[0x80];
 637
 638         u8         log_max_srq_sz[0x8];
 639         u8         log_max_qp_sz[0x8];
 640         u8         reserved_1[0xb];
 641         u8         log_max_qp[0x5];
 642
 643         u8         reserved_2[0xb];
 644         u8         log_max_srq[0x5];
 645         u8         reserved_3[0x10];
 646
 647         u8         reserved_4[0x8];
 648         u8         log_max_cq_sz[0x8];
 649         u8         reserved_5[0xb];
 650         u8         log_max_cq[0x5];
 651
 652         u8         log_max_eq_sz[0x8];
 653         u8         reserved_6[0x2];
 654         u8         log_max_mkey[0x6];
 655         u8         reserved_7[0xc];
 656         u8         log_max_eq[0x4];
 657
 658         u8         max_indirection[0x8];
 659         u8         reserved_8[0x1];
 660         u8         log_max_mrw_sz[0x7];
 661         u8         reserved_9[0x2];
 662         u8         log_max_bsf_list_size[0x6];
 663         u8         reserved_10[0x2];
 664         u8         log_max_klm_list_size[0x6];
 665
 666         u8         reserved_11[0xa];
 667         u8         log_max_ra_req_dc[0x6];
 668         u8         reserved_12[0xa];
 669         u8         log_max_ra_res_dc[0x6];
 670
 671         u8         reserved_13[0xa];
 672         u8         log_max_ra_req_qp[0x6];
 673         u8         reserved_14[0xa];
 674         u8         log_max_ra_res_qp[0x6];
 675
 676         u8         pad_cap[0x1];
 677         u8         cc_query_allowed[0x1];
 678         u8         cc_modify_allowed[0x1];
 679         u8         reserved_15[0xd];
 680         u8         gid_table_size[0x10];
 681
 682         u8         out_of_seq_cnt[0x1];
 683         u8         vport_counters[0x1];
 684         u8         reserved_16[0x4];
 685         u8         max_qp_cnt[0xa];
 686         u8         pkey_table_size[0x10];
 687
 688         u8         vport_group_manager[0x1];
 689         u8         vhca_group_manager[0x1];
 690         u8         ib_virt[0x1];
 691         u8         eth_virt[0x1];
 692         u8         reserved_17[0x1];
 693         u8         ets[0x1];
 694         u8         nic_flow_table[0x1];
 695         u8         eswitch_flow_table[0x1];
 696         u8         early_vf_enable;
 697         u8         reserved_18[0x2];
 698         u8         local_ca_ack_delay[0x5];
 699         u8         reserved_19[0x6];
 700         u8         port_type[0x2];
 701         u8         num_ports[0x8];
 702
 703         u8         reserved_20[0x3];
 704         u8         log_max_msg[0x5];
 705         u8         reserved_21[0x18];
 706
 707         u8         stat_rate_support[0x10];
 708         u8         reserved_22[0xc];
 709         u8         cqe_version[0x4];
 710
 711         u8         compact_address_vector[0x1];
 712         u8         reserved_23[0xe];
 713         u8         drain_sigerr[0x1];
 714         u8         cmdif_checksum[0x2];
 715         u8         sigerr_cqe[0x1];
 716         u8         reserved_24[0x1];
 717         u8         wq_signature[0x1];
 718         u8         sctr_data_cqe[0x1];
 719         u8         reserved_25[0x1];
 720         u8         sho[0x1];
 721         u8         tph[0x1];
 722         u8         rf[0x1];
 723         u8         dct[0x1];
 724         u8         reserved_26[0x1];
 725         u8         eth_net_offloads[0x1];
 726         u8         roce[0x1];
 727         u8         atomic[0x1];
 728         u8         reserved_27[0x1];
 729
 730         u8         cq_oi[0x1];
 731         u8         cq_resize[0x1];
 732         u8         cq_moderation[0x1];
 733         u8         reserved_28[0x3];
 734         u8         cq_eq_remap[0x1];
 735         u8         pg[0x1];
 736         u8         block_lb_mc[0x1];
 737         u8         reserved_29[0x1];
 738         u8         scqe_break_moderation[0x1];
 739         u8         reserved_30[0x1];
 740         u8         cd[0x1];
 741         u8         reserved_31[0x1];
 742         u8         apm[0x1];
 743         u8         reserved_32[0x7];
 744         u8         qkv[0x1];
 745         u8         pkv[0x1];
 746         u8         reserved_33[0x4];
 747         u8         xrc[0x1];
 748         u8         ud[0x1];
 749         u8         uc[0x1];
 750         u8         rc[0x1];
 751
 752         u8         reserved_34[0xa];
 753         u8         uar_sz[0x6];
 754         u8         reserved_35[0x8];
 755         u8         log_pg_sz[0x8];
 756
 757         u8         bf[0x1];
 758         u8         reserved_36[0x1];
 759         u8         pad_tx_eth_packet[0x1];
 760         u8         reserved_37[0x8];
 761         u8         log_bf_reg_size[0x5];
 762         u8         reserved_38[0x10];
 763
 764         u8         reserved_39[0x10];
 765         u8         max_wqe_sz_sq[0x10];
 766
 767         u8         reserved_40[0x10];
 768         u8         max_wqe_sz_rq[0x10];
 769
 770         u8         reserved_41[0x10];
 771         u8         max_wqe_sz_sq_dc[0x10];
 772
 773         u8         reserved_42[0x7];
 774         u8         max_qp_mcg[0x19];
 775
 776         u8         reserved_43[0x18];
 777         u8         log_max_mcg[0x8];
 778
 779         u8         reserved_44[0x3];
 780         u8         log_max_transport_domain[0x5];
 781         u8         reserved_45[0x3];
 782         u8         log_max_pd[0x5];
 783         u8         reserved_46[0xb];
 784         u8         log_max_xrcd[0x5];
 785
 786         u8         reserved_47[0x20];
 787
 788         u8         reserved_48[0x3];
 789         u8         log_max_rq[0x5];
 790         u8         reserved_49[0x3];
 791         u8         log_max_sq[0x5];
 792         u8         reserved_50[0x3];
 793         u8         log_max_tir[0x5];
 794         u8         reserved_51[0x3];
 795         u8         log_max_tis[0x5];
 796
 797         u8         basic_cyclic_rcv_wqe[0x1];
 798         u8         reserved_52[0x2];
 799         u8         log_max_rmp[0x5];
 800         u8         reserved_53[0x3];
 801         u8         log_max_rqt[0x5];
 802         u8         reserved_54[0x3];
 803         u8         log_max_rqt_size[0x5];
 804         u8         reserved_55[0x3];
 805         u8         log_max_tis_per_sq[0x5];
 806
 807         u8         reserved_56[0x3];
 808         u8         log_max_stride_sz_rq[0x5];
 809         u8         reserved_57[0x3];
 810         u8         log_min_stride_sz_rq[0x5];
 811         u8         reserved_58[0x3];
 812         u8         log_max_stride_sz_sq[0x5];
 813         u8         reserved_59[0x3];
 814         u8         log_min_stride_sz_sq[0x5];
 815
 816         u8         reserved_60[0x1b];
 817         u8         log_max_wq_sz[0x5];
 818
 819         u8         nic_vport_change_event[0x1];
 820         u8         reserved_61[0xa];
 821         u8         log_max_vlan_list[0x5];
 822         u8         reserved_62[0x3];
 823         u8         log_max_current_mc_list[0x5];
 824         u8         reserved_63[0x3];
 825         u8         log_max_current_uc_list[0x5];
 826
 827         u8         reserved_64[0x80];
 828
 829         u8         reserved_65[0x3];
 830         u8         log_max_l2_table[0x5];
 831         u8         reserved_66[0x8];
 832         u8         log_uar_page_sz[0x10];
 833
 834         u8         reserved_67[0x40];
 835         u8         device_frequency_khz[0x20];
 836         u8         reserved_68[0x5f];
 837         u8         cqe_zip[0x1];
 838
 839         u8         cqe_zip_timeout[0x10];
 840         u8         cqe_zip_max_num[0x10];
 841
 842         u8         reserved_69[0x220];
 843 };
 844
 845 enum mlx5_flow_destination_type {
 846         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 847         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 848         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 849 };
 850
 851 struct mlx5_ifc_dest_format_struct_bits {
 852         u8         destination_type[0x8];
 853         u8         destination_id[0x18];
 854
 855         u8         reserved_0[0x20];
 856 };
 857
 858 struct mlx5_ifc_fte_match_param_bits {
 859         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 860
 861         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 862
 863         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 864
 865         u8         reserved_0[0xa00];
 866 };
 867
 868 enum {
 869         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 870         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 871         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 872         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 873         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 874 };
 875
 876 struct mlx5_ifc_rx_hash_field_select_bits {
 877         u8         l3_prot_type[0x1];
 878         u8         l4_prot_type[0x1];
 879         u8         selected_fields[0x1e];
 880 };
 881
 882 enum {
 883         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 884         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 885 };
 886
 887 enum {
 888         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 889         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 890 };
 891
 892 struct mlx5_ifc_wq_bits {
 893         u8         wq_type[0x4];
 894         u8         wq_signature[0x1];
 895         u8         end_padding_mode[0x2];
 896         u8         cd_slave[0x1];
 897         u8         reserved_0[0x18];
 898
 899         u8         hds_skip_first_sge[0x1];
 900         u8         log2_hds_buf_size[0x3];
 901         u8         reserved_1[0x7];
 902         u8         page_offset[0x5];
 903         u8         lwm[0x10];
 904
 905         u8         reserved_2[0x8];
 906         u8         pd[0x18];
 907
 908         u8         reserved_3[0x8];
 909         u8         uar_page[0x18];
 910
 911         u8         dbr_addr[0x40];
 912
 913         u8         hw_counter[0x20];
 914
 915         u8         sw_counter[0x20];
 916
 917         u8         reserved_4[0xc];
 918         u8         log_wq_stride[0x4];
 919         u8         reserved_5[0x3];
 920         u8         log_wq_pg_sz[0x5];
 921         u8         reserved_6[0x3];
 922         u8         log_wq_sz[0x5];
 923
 924         u8         reserved_7[0x4e0];
 925
 926         struct mlx5_ifc_cmd_pas_bits pas[0];
 927 };
 928
 929 struct mlx5_ifc_rq_num_bits {
 930         u8         reserved_0[0x8];
 931         u8         rq_num[0x18];
 932 };
 933
 934 struct mlx5_ifc_mac_address_layout_bits {
 935         u8         reserved_0[0x10];
 936         u8         mac_addr_47_32[0x10];
 937
 938         u8         mac_addr_31_0[0x20];
 939 };
 940
 941 struct mlx5_ifc_vlan_layout_bits {
 942         u8         reserved_0[0x14];
 943         u8         vlan[0x0c];
 944
 945         u8         reserved_1[0x20];
 946 };
 947
 948 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 949         u8         reserved_0[0xa0];
 950
 951         u8         min_time_between_cnps[0x20];
 952
 953         u8         reserved_1[0x12];
 954         u8         cnp_dscp[0x6];
 955         u8         reserved_2[0x5];
 956         u8         cnp_802p_prio[0x3];
 957
 958         u8         reserved_3[0x720];
 959 };
 960
 961 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
 962         u8         reserved_0[0x60];
 963
 964         u8         reserved_1[0x4];
 965         u8         clamp_tgt_rate[0x1];
 966         u8         reserved_2[0x3];
 967         u8         clamp_tgt_rate_after_time_inc[0x1];
 968         u8         reserved_3[0x17];
 969
 970         u8         reserved_4[0x20];
 971
 972         u8         rpg_time_reset[0x20];
 973
 974         u8         rpg_byte_reset[0x20];
 975
 976         u8         rpg_threshold[0x20];
 977
 978         u8         rpg_max_rate[0x20];
 979
 980         u8         rpg_ai_rate[0x20];
 981
 982         u8         rpg_hai_rate[0x20];
 983
 984         u8         rpg_gd[0x20];
 985
 986         u8         rpg_min_dec_fac[0x20];
 987
 988         u8         rpg_min_rate[0x20];
 989
 990         u8         reserved_5[0xe0];
 991
 992         u8         rate_to_set_on_first_cnp[0x20];
 993
 994         u8         dce_tcp_g[0x20];
 995
 996         u8         dce_tcp_rtt[0x20];
 997
 998         u8         rate_reduce_monitor_period[0x20];
 999
1000         u8         reserved_6[0x20];
1001
1002         u8         initial_alpha_value[0x20];
1003
1004         u8         reserved_7[0x4a0];
1005 };
1006
1007 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1008         u8         reserved_0[0x80];
1009
1010         u8         rppp_max_rps[0x20];
1011
1012         u8         rpg_time_reset[0x20];
1013
1014         u8         rpg_byte_reset[0x20];
1015
1016         u8         rpg_threshold[0x20];
1017
1018         u8         rpg_max_rate[0x20];
1019
1020         u8         rpg_ai_rate[0x20];
1021
1022         u8         rpg_hai_rate[0x20];
1023
1024         u8         rpg_gd[0x20];
1025
1026         u8         rpg_min_dec_fac[0x20];
1027
1028         u8         rpg_min_rate[0x20];
1029
1030         u8         reserved_1[0x640];
1031 };
1032
1033 enum {
1034         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1035         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1036         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1037 };
1038
1039 struct mlx5_ifc_resize_field_select_bits {
1040         u8         resize_field_select[0x20];
1041 };
1042
1043 enum {
1044         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1045         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1046         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1047         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1048 };
1049
1050 struct mlx5_ifc_modify_field_select_bits {
1051         u8         modify_field_select[0x20];
1052 };
1053
1054 struct mlx5_ifc_field_select_r_roce_np_bits {
1055         u8         field_select_r_roce_np[0x20];
1056 };
1057
1058 struct mlx5_ifc_field_select_r_roce_rp_bits {
1059         u8         field_select_r_roce_rp[0x20];
1060 };
1061
1062 enum {
1063         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1064         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1065         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1066         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1067         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1068         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1069         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1070         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1071         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1072         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1073 };
1074
1075 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1076         u8         field_select_8021qaurp[0x20];
1077 };
1078
1079 struct mlx5_ifc_phys_layer_cntrs_bits {
1080         u8         time_since_last_clear_high[0x20];
1081
1082         u8         time_since_last_clear_low[0x20];
1083
1084         u8         symbol_errors_high[0x20];
1085
1086         u8         symbol_errors_low[0x20];
1087
1088         u8         sync_headers_errors_high[0x20];
1089
1090         u8         sync_headers_errors_low[0x20];
1091
1092         u8         edpl_bip_errors_lane0_high[0x20];
1093
1094         u8         edpl_bip_errors_lane0_low[0x20];
1095
1096         u8         edpl_bip_errors_lane1_high[0x20];
1097
1098         u8         edpl_bip_errors_lane1_low[0x20];
1099
1100         u8         edpl_bip_errors_lane2_high[0x20];
1101
1102         u8         edpl_bip_errors_lane2_low[0x20];
1103
1104         u8         edpl_bip_errors_lane3_high[0x20];
1105
1106         u8         edpl_bip_errors_lane3_low[0x20];
1107
1108         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1109
1110         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1111
1112         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1113
1114         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1115
1116         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1117
1118         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1119
1120         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1121
1122         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1123
1124         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1125
1126         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1127
1128         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1129
1130         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1131
1132         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1133
1134         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1135
1136         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1137
1138         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1139
1140         u8         rs_fec_corrected_blocks_high[0x20];
1141
1142         u8         rs_fec_corrected_blocks_low[0x20];
1143
1144         u8         rs_fec_uncorrectable_blocks_high[0x20];
1145
1146         u8         rs_fec_uncorrectable_blocks_low[0x20];
1147
1148         u8         rs_fec_no_errors_blocks_high[0x20];
1149
1150         u8         rs_fec_no_errors_blocks_low[0x20];
1151
1152         u8         rs_fec_single_error_blocks_high[0x20];
1153
1154         u8         rs_fec_single_error_blocks_low[0x20];
1155
1156         u8         rs_fec_corrected_symbols_total_high[0x20];
1157
1158         u8         rs_fec_corrected_symbols_total_low[0x20];
1159
1160         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1161
1162         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1163
1164         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1165
1166         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1167
1168         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1169
1170         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1171
1172         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1173
1174         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1175
1176         u8         link_down_events[0x20];
1177
1178         u8         successful_recovery_events[0x20];
1179
1180         u8         reserved_0[0x180];
1181 };
1182
1183 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1184         u8         transmit_queue_high[0x20];
1185
1186         u8         transmit_queue_low[0x20];
1187
1188         u8         reserved_0[0x780];
1189 };
1190
1191 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1192         u8         rx_octets_high[0x20];
1193
1194         u8         rx_octets_low[0x20];
1195
1196         u8         reserved_0[0xc0];
1197
1198         u8         rx_frames_high[0x20];
1199
1200         u8         rx_frames_low[0x20];
1201
1202         u8         tx_octets_high[0x20];
1203
1204         u8         tx_octets_low[0x20];
1205
1206         u8         reserved_1[0xc0];
1207
1208         u8         tx_frames_high[0x20];
1209
1210         u8         tx_frames_low[0x20];
1211
1212         u8         rx_pause_high[0x20];
1213
1214         u8         rx_pause_low[0x20];
1215
1216         u8         rx_pause_duration_high[0x20];
1217
1218         u8         rx_pause_duration_low[0x20];
1219
1220         u8         tx_pause_high[0x20];
1221
1222         u8         tx_pause_low[0x20];
1223
1224         u8         tx_pause_duration_high[0x20];
1225
1226         u8         tx_pause_duration_low[0x20];
1227
1228         u8         rx_pause_transition_high[0x20];
1229
1230         u8         rx_pause_transition_low[0x20];
1231
1232         u8         reserved_2[0x400];
1233 };
1234
1235 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1236         u8         port_transmit_wait_high[0x20];
1237
1238         u8         port_transmit_wait_low[0x20];
1239
1240         u8         reserved_0[0x780];
1241 };
1242
1243 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1244         u8         dot3stats_alignment_errors_high[0x20];
1245
1246         u8         dot3stats_alignment_errors_low[0x20];
1247
1248         u8         dot3stats_fcs_errors_high[0x20];
1249
1250         u8         dot3stats_fcs_errors_low[0x20];
1251
1252         u8         dot3stats_single_collision_frames_high[0x20];
1253
1254         u8         dot3stats_single_collision_frames_low[0x20];
1255
1256         u8         dot3stats_multiple_collision_frames_high[0x20];
1257
1258         u8         dot3stats_multiple_collision_frames_low[0x20];
1259
1260         u8         dot3stats_sqe_test_errors_high[0x20];
1261
1262         u8         dot3stats_sqe_test_errors_low[0x20];
1263
1264         u8         dot3stats_deferred_transmissions_high[0x20];
1265
1266         u8         dot3stats_deferred_transmissions_low[0x20];
1267
1268         u8         dot3stats_late_collisions_high[0x20];
1269
1270         u8         dot3stats_late_collisions_low[0x20];
1271
1272         u8         dot3stats_excessive_collisions_high[0x20];
1273
1274         u8         dot3stats_excessive_collisions_low[0x20];
1275
1276         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1277
1278         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1279
1280         u8         dot3stats_carrier_sense_errors_high[0x20];
1281
1282         u8         dot3stats_carrier_sense_errors_low[0x20];
1283
1284         u8         dot3stats_frame_too_longs_high[0x20];
1285
1286         u8         dot3stats_frame_too_longs_low[0x20];
1287
1288         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1289
1290         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1291
1292         u8         dot3stats_symbol_errors_high[0x20];
1293
1294         u8         dot3stats_symbol_errors_low[0x20];
1295
1296         u8         dot3control_in_unknown_opcodes_high[0x20];
1297
1298         u8         dot3control_in_unknown_opcodes_low[0x20];
1299
1300         u8         dot3in_pause_frames_high[0x20];
1301
1302         u8         dot3in_pause_frames_low[0x20];
1303
1304         u8         dot3out_pause_frames_high[0x20];
1305
1306         u8         dot3out_pause_frames_low[0x20];
1307
1308         u8         reserved_0[0x3c0];
1309 };
1310
1311 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1312         u8         ether_stats_drop_events_high[0x20];
1313
1314         u8         ether_stats_drop_events_low[0x20];
1315
1316         u8         ether_stats_octets_high[0x20];
1317
1318         u8         ether_stats_octets_low[0x20];
1319
1320         u8         ether_stats_pkts_high[0x20];
1321
1322         u8         ether_stats_pkts_low[0x20];
1323
1324         u8         ether_stats_broadcast_pkts_high[0x20];
1325
1326         u8         ether_stats_broadcast_pkts_low[0x20];
1327
1328         u8         ether_stats_multicast_pkts_high[0x20];
1329
1330         u8         ether_stats_multicast_pkts_low[0x20];
1331
1332         u8         ether_stats_crc_align_errors_high[0x20];
1333
1334         u8         ether_stats_crc_align_errors_low[0x20];
1335
1336         u8         ether_stats_undersize_pkts_high[0x20];
1337
1338         u8         ether_stats_undersize_pkts_low[0x20];
1339
1340         u8         ether_stats_oversize_pkts_high[0x20];
1341
1342         u8         ether_stats_oversize_pkts_low[0x20];
1343
1344         u8         ether_stats_fragments_high[0x20];
1345
1346         u8         ether_stats_fragments_low[0x20];
1347
1348         u8         ether_stats_jabbers_high[0x20];
1349
1350         u8         ether_stats_jabbers_low[0x20];
1351
1352         u8         ether_stats_collisions_high[0x20];
1353
1354         u8         ether_stats_collisions_low[0x20];
1355
1356         u8         ether_stats_pkts64octets_high[0x20];
1357
1358         u8         ether_stats_pkts64octets_low[0x20];
1359
1360         u8         ether_stats_pkts65to127octets_high[0x20];
1361
1362         u8         ether_stats_pkts65to127octets_low[0x20];
1363
1364         u8         ether_stats_pkts128to255octets_high[0x20];
1365
1366         u8         ether_stats_pkts128to255octets_low[0x20];
1367
1368         u8         ether_stats_pkts256to511octets_high[0x20];
1369
1370         u8         ether_stats_pkts256to511octets_low[0x20];
1371
1372         u8         ether_stats_pkts512to1023octets_high[0x20];
1373
1374         u8         ether_stats_pkts512to1023octets_low[0x20];
1375
1376         u8         ether_stats_pkts1024to1518octets_high[0x20];
1377
1378         u8         ether_stats_pkts1024to1518octets_low[0x20];
1379
1380         u8         ether_stats_pkts1519to2047octets_high[0x20];
1381
1382         u8         ether_stats_pkts1519to2047octets_low[0x20];
1383
1384         u8         ether_stats_pkts2048to4095octets_high[0x20];
1385
1386         u8         ether_stats_pkts2048to4095octets_low[0x20];
1387
1388         u8         ether_stats_pkts4096to8191octets_high[0x20];
1389
1390         u8         ether_stats_pkts4096to8191octets_low[0x20];
1391
1392         u8         ether_stats_pkts8192to10239octets_high[0x20];
1393
1394         u8         ether_stats_pkts8192to10239octets_low[0x20];
1395
1396         u8         reserved_0[0x280];
1397 };
1398
1399 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1400         u8         if_in_octets_high[0x20];
1401
1402         u8         if_in_octets_low[0x20];
1403
1404         u8         if_in_ucast_pkts_high[0x20];
1405
1406         u8         if_in_ucast_pkts_low[0x20];
1407
1408         u8         if_in_discards_high[0x20];
1409
1410         u8         if_in_discards_low[0x20];
1411
1412         u8         if_in_errors_high[0x20];
1413
1414         u8         if_in_errors_low[0x20];
1415
1416         u8         if_in_unknown_protos_high[0x20];
1417
1418         u8         if_in_unknown_protos_low[0x20];
1419
1420         u8         if_out_octets_high[0x20];
1421
1422         u8         if_out_octets_low[0x20];
1423
1424         u8         if_out_ucast_pkts_high[0x20];
1425
1426         u8         if_out_ucast_pkts_low[0x20];
1427
1428         u8         if_out_discards_high[0x20];
1429
1430         u8         if_out_discards_low[0x20];
1431
1432         u8         if_out_errors_high[0x20];
1433
1434         u8         if_out_errors_low[0x20];
1435
1436         u8         if_in_multicast_pkts_high[0x20];
1437
1438         u8         if_in_multicast_pkts_low[0x20];
1439
1440         u8         if_in_broadcast_pkts_high[0x20];
1441
1442         u8         if_in_broadcast_pkts_low[0x20];
1443
1444         u8         if_out_multicast_pkts_high[0x20];
1445
1446         u8         if_out_multicast_pkts_low[0x20];
1447
1448         u8         if_out_broadcast_pkts_high[0x20];
1449
1450         u8         if_out_broadcast_pkts_low[0x20];
1451
1452         u8         reserved_0[0x480];
1453 };
1454
1455 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1456         u8         a_frames_transmitted_ok_high[0x20];
1457
1458         u8         a_frames_transmitted_ok_low[0x20];
1459
1460         u8         a_frames_received_ok_high[0x20];
1461
1462         u8         a_frames_received_ok_low[0x20];
1463
1464         u8         a_frame_check_sequence_errors_high[0x20];
1465
1466         u8         a_frame_check_sequence_errors_low[0x20];
1467
1468         u8         a_alignment_errors_high[0x20];
1469
1470         u8         a_alignment_errors_low[0x20];
1471
1472         u8         a_octets_transmitted_ok_high[0x20];
1473
1474         u8         a_octets_transmitted_ok_low[0x20];
1475
1476         u8         a_octets_received_ok_high[0x20];
1477
1478         u8         a_octets_received_ok_low[0x20];
1479
1480         u8         a_multicast_frames_xmitted_ok_high[0x20];
1481
1482         u8         a_multicast_frames_xmitted_ok_low[0x20];
1483
1484         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1485
1486         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1487
1488         u8         a_multicast_frames_received_ok_high[0x20];
1489
1490         u8         a_multicast_frames_received_ok_low[0x20];
1491
1492         u8         a_broadcast_frames_received_ok_high[0x20];
1493
1494         u8         a_broadcast_frames_received_ok_low[0x20];
1495
1496         u8         a_in_range_length_errors_high[0x20];
1497
1498         u8         a_in_range_length_errors_low[0x20];
1499
1500         u8         a_out_of_range_length_field_high[0x20];
1501
1502         u8         a_out_of_range_length_field_low[0x20];
1503
1504         u8         a_frame_too_long_errors_high[0x20];
1505
1506         u8         a_frame_too_long_errors_low[0x20];
1507
1508         u8         a_symbol_error_during_carrier_high[0x20];
1509
1510         u8         a_symbol_error_during_carrier_low[0x20];
1511
1512         u8         a_mac_control_frames_transmitted_high[0x20];
1513
1514         u8         a_mac_control_frames_transmitted_low[0x20];
1515
1516         u8         a_mac_control_frames_received_high[0x20];
1517
1518         u8         a_mac_control_frames_received_low[0x20];
1519
1520         u8         a_unsupported_opcodes_received_high[0x20];
1521
1522         u8         a_unsupported_opcodes_received_low[0x20];
1523
1524         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1525
1526         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1527
1528         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1529
1530         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1531
1532         u8         reserved_0[0x300];
1533 };
1534
1535 struct mlx5_ifc_cmd_inter_comp_event_bits {
1536         u8         command_completion_vector[0x20];
1537
1538         u8         reserved_0[0xc0];
1539 };
1540
1541 struct mlx5_ifc_stall_vl_event_bits {
1542         u8         reserved_0[0x18];
1543         u8         port_num[0x1];
1544         u8         reserved_1[0x3];
1545         u8         vl[0x4];
1546
1547         u8         reserved_2[0xa0];
1548 };
1549
1550 struct mlx5_ifc_db_bf_congestion_event_bits {
1551         u8         event_subtype[0x8];
1552         u8         reserved_0[0x8];
1553         u8         congestion_level[0x8];
1554         u8         reserved_1[0x8];
1555
1556         u8         reserved_2[0xa0];
1557 };
1558
1559 struct mlx5_ifc_gpio_event_bits {
1560         u8         reserved_0[0x60];
1561
1562         u8         gpio_event_hi[0x20];
1563
1564         u8         gpio_event_lo[0x20];
1565
1566         u8         reserved_1[0x40];
1567 };
1568
1569 struct mlx5_ifc_port_state_change_event_bits {
1570         u8         reserved_0[0x40];
1571
1572         u8         port_num[0x4];
1573         u8         reserved_1[0x1c];
1574
1575         u8         reserved_2[0x80];
1576 };
1577
1578 struct mlx5_ifc_dropped_packet_logged_bits {
1579         u8         reserved_0[0xe0];
1580 };
1581
1582 enum {
1583         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1584         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1585 };
1586
1587 struct mlx5_ifc_cq_error_bits {
1588         u8         reserved_0[0x8];
1589         u8         cqn[0x18];
1590
1591         u8         reserved_1[0x20];
1592
1593         u8         reserved_2[0x18];
1594         u8         syndrome[0x8];
1595
1596         u8         reserved_3[0x80];
1597 };
1598
1599 struct mlx5_ifc_rdma_page_fault_event_bits {
1600         u8         bytes_committed[0x20];
1601
1602         u8         r_key[0x20];
1603
1604         u8         reserved_0[0x10];
1605         u8         packet_len[0x10];
1606
1607         u8         rdma_op_len[0x20];
1608
1609         u8         rdma_va[0x40];
1610
1611         u8         reserved_1[0x5];
1612         u8         rdma[0x1];
1613         u8         write[0x1];
1614         u8         requestor[0x1];
1615         u8         qp_number[0x18];
1616 };
1617
1618 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1619         u8         bytes_committed[0x20];
1620
1621         u8         reserved_0[0x10];
1622         u8         wqe_index[0x10];
1623
1624         u8         reserved_1[0x10];
1625         u8         len[0x10];
1626
1627         u8         reserved_2[0x60];
1628
1629         u8         reserved_3[0x5];
1630         u8         rdma[0x1];
1631         u8         write_read[0x1];
1632         u8         requestor[0x1];
1633         u8         qpn[0x18];
1634 };
1635
1636 struct mlx5_ifc_qp_events_bits {
1637         u8         reserved_0[0xa0];
1638
1639         u8         type[0x8];
1640         u8         reserved_1[0x18];
1641
1642         u8         reserved_2[0x8];
1643         u8         qpn_rqn_sqn[0x18];
1644 };
1645
1646 struct mlx5_ifc_dct_events_bits {
1647         u8         reserved_0[0xc0];
1648
1649         u8         reserved_1[0x8];
1650         u8         dct_number[0x18];
1651 };
1652
1653 struct mlx5_ifc_comp_event_bits {
1654         u8         reserved_0[0xc0];
1655
1656         u8         reserved_1[0x8];
1657         u8         cq_number[0x18];
1658 };
1659
1660 enum {
1661         MLX5_QPC_STATE_RST        = 0x0,
1662         MLX5_QPC_STATE_INIT       = 0x1,
1663         MLX5_QPC_STATE_RTR        = 0x2,
1664         MLX5_QPC_STATE_RTS        = 0x3,
1665         MLX5_QPC_STATE_SQER       = 0x4,
1666         MLX5_QPC_STATE_ERR        = 0x6,
1667         MLX5_QPC_STATE_SQD        = 0x7,
1668         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1669 };
1670
1671 enum {
1672         MLX5_QPC_ST_RC            = 0x0,
1673         MLX5_QPC_ST_UC            = 0x1,
1674         MLX5_QPC_ST_UD            = 0x2,
1675         MLX5_QPC_ST_XRC           = 0x3,
1676         MLX5_QPC_ST_DCI           = 0x5,
1677         MLX5_QPC_ST_QP0           = 0x7,
1678         MLX5_QPC_ST_QP1           = 0x8,
1679         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1680         MLX5_QPC_ST_REG_UMR       = 0xc,
1681 };
1682
1683 enum {
1684         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1685         MLX5_QPC_PM_STATE_REARM     = 0x1,
1686         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1687         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1688 };
1689
1690 enum {
1691         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1692         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1693 };
1694
1695 enum {
1696         MLX5_QPC_MTU_256_BYTES        = 0x1,
1697         MLX5_QPC_MTU_512_BYTES        = 0x2,
1698         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1699         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1700         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1701         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1702 };
1703
1704 enum {
1705         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1706         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1707         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1708         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1709         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1710         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1711         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1712         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1713 };
1714
1715 enum {
1716         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1717         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1718         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1719 };
1720
1721 enum {
1722         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1723         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1724         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1725 };
1726
1727 struct mlx5_ifc_qpc_bits {
1728         u8         state[0x4];
1729         u8         reserved_0[0x4];
1730         u8         st[0x8];
1731         u8         reserved_1[0x3];
1732         u8         pm_state[0x2];
1733         u8         reserved_2[0x7];
1734         u8         end_padding_mode[0x2];
1735         u8         reserved_3[0x2];
1736
1737         u8         wq_signature[0x1];
1738         u8         block_lb_mc[0x1];
1739         u8         atomic_like_write_en[0x1];
1740         u8         latency_sensitive[0x1];
1741         u8         reserved_4[0x1];
1742         u8         drain_sigerr[0x1];
1743         u8         reserved_5[0x2];
1744         u8         pd[0x18];
1745
1746         u8         mtu[0x3];
1747         u8         log_msg_max[0x5];
1748         u8         reserved_6[0x1];
1749         u8         log_rq_size[0x4];
1750         u8         log_rq_stride[0x3];
1751         u8         no_sq[0x1];
1752         u8         log_sq_size[0x4];
1753         u8         reserved_7[0x6];
1754         u8         rlky[0x1];
1755         u8         reserved_8[0x4];
1756
1757         u8         counter_set_id[0x8];
1758         u8         uar_page[0x18];
1759
1760         u8         reserved_9[0x8];
1761         u8         user_index[0x18];
1762
1763         u8         reserved_10[0x3];
1764         u8         log_page_size[0x5];
1765         u8         remote_qpn[0x18];
1766
1767         struct mlx5_ifc_ads_bits primary_address_path;
1768
1769         struct mlx5_ifc_ads_bits secondary_address_path;
1770
1771         u8         log_ack_req_freq[0x4];
1772         u8         reserved_11[0x4];
1773         u8         log_sra_max[0x3];
1774         u8         reserved_12[0x2];
1775         u8         retry_count[0x3];
1776         u8         rnr_retry[0x3];
1777         u8         reserved_13[0x1];
1778         u8         fre[0x1];
1779         u8         cur_rnr_retry[0x3];
1780         u8         cur_retry_count[0x3];
1781         u8         reserved_14[0x5];
1782
1783         u8         reserved_15[0x20];
1784
1785         u8         reserved_16[0x8];
1786         u8         next_send_psn[0x18];
1787
1788         u8         reserved_17[0x8];
1789         u8         cqn_snd[0x18];
1790
1791         u8         reserved_18[0x40];
1792
1793         u8         reserved_19[0x8];
1794         u8         last_acked_psn[0x18];
1795
1796         u8         reserved_20[0x8];
1797         u8         ssn[0x18];
1798
1799         u8         reserved_21[0x8];
1800         u8         log_rra_max[0x3];
1801         u8         reserved_22[0x1];
1802         u8         atomic_mode[0x4];
1803         u8         rre[0x1];
1804         u8         rwe[0x1];
1805         u8         rae[0x1];
1806         u8         reserved_23[0x1];
1807         u8         page_offset[0x6];
1808         u8         reserved_24[0x3];
1809         u8         cd_slave_receive[0x1];
1810         u8         cd_slave_send[0x1];
1811         u8         cd_master[0x1];
1812
1813         u8         reserved_25[0x3];
1814         u8         min_rnr_nak[0x5];
1815         u8         next_rcv_psn[0x18];
1816
1817         u8         reserved_26[0x8];
1818         u8         xrcd[0x18];
1819
1820         u8         reserved_27[0x8];
1821         u8         cqn_rcv[0x18];
1822
1823         u8         dbr_addr[0x40];
1824
1825         u8         q_key[0x20];
1826
1827         u8         reserved_28[0x5];
1828         u8         rq_type[0x3];
1829         u8         srqn_rmpn[0x18];
1830
1831         u8         reserved_29[0x8];
1832         u8         rmsn[0x18];
1833
1834         u8         hw_sq_wqebb_counter[0x10];
1835         u8         sw_sq_wqebb_counter[0x10];
1836
1837         u8         hw_rq_counter[0x20];
1838
1839         u8         sw_rq_counter[0x20];
1840
1841         u8         reserved_30[0x20];
1842
1843         u8         reserved_31[0xf];
1844         u8         cgs[0x1];
1845         u8         cs_req[0x8];
1846         u8         cs_res[0x8];
1847
1848         u8         dc_access_key[0x40];
1849
1850         u8         reserved_32[0xc0];
1851 };
1852
1853 struct mlx5_ifc_roce_addr_layout_bits {
1854         u8         source_l3_address[16][0x8];
1855
1856         u8         reserved_0[0x3];
1857         u8         vlan_valid[0x1];
1858         u8         vlan_id[0xc];
1859         u8         source_mac_47_32[0x10];
1860
1861         u8         source_mac_31_0[0x20];
1862
1863         u8         reserved_1[0x14];
1864         u8         roce_l3_type[0x4];
1865         u8         roce_version[0x8];
1866
1867         u8         reserved_2[0x20];
1868 };
1869
1870 union mlx5_ifc_hca_cap_union_bits {
1871         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1872         struct mlx5_ifc_odp_cap_bits odp_cap;
1873         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1874         struct mlx5_ifc_roce_cap_bits roce_cap;
1875         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1876         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1877         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1878         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1879         u8         reserved_0[0x8000];
1880 };
1881
1882 enum {
1883         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1884         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1885         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1886 };
1887
1888 struct mlx5_ifc_flow_context_bits {
1889         u8         reserved_0[0x20];
1890
1891         u8         group_id[0x20];
1892
1893         u8         reserved_1[0x8];
1894         u8         flow_tag[0x18];
1895
1896         u8         reserved_2[0x10];
1897         u8         action[0x10];
1898
1899         u8         reserved_3[0x8];
1900         u8         destination_list_size[0x18];
1901
1902         u8         reserved_4[0x160];
1903
1904         struct mlx5_ifc_fte_match_param_bits match_value;
1905
1906         u8         reserved_5[0x600];
1907
1908         struct mlx5_ifc_dest_format_struct_bits destination[0];
1909 };
1910
1911 enum {
1912         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1913         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1914 };
1915
1916 struct mlx5_ifc_xrc_srqc_bits {
1917         u8         state[0x4];
1918         u8         log_xrc_srq_size[0x4];
1919         u8         reserved_0[0x18];
1920
1921         u8         wq_signature[0x1];
1922         u8         cont_srq[0x1];
1923         u8         reserved_1[0x1];
1924         u8         rlky[0x1];
1925         u8         basic_cyclic_rcv_wqe[0x1];
1926         u8         log_rq_stride[0x3];
1927         u8         xrcd[0x18];
1928
1929         u8         page_offset[0x6];
1930         u8         reserved_2[0x2];
1931         u8         cqn[0x18];
1932
1933         u8         reserved_3[0x20];
1934
1935         u8         user_index_equal_xrc_srqn[0x1];
1936         u8         reserved_4[0x1];
1937         u8         log_page_size[0x6];
1938         u8         user_index[0x18];
1939
1940         u8         reserved_5[0x20];
1941
1942         u8         reserved_6[0x8];
1943         u8         pd[0x18];
1944
1945         u8         lwm[0x10];
1946         u8         wqe_cnt[0x10];
1947
1948         u8         reserved_7[0x40];
1949
1950         u8         db_record_addr_h[0x20];
1951
1952         u8         db_record_addr_l[0x1e];
1953         u8         reserved_8[0x2];
1954
1955         u8         reserved_9[0x80];
1956 };
1957
1958 struct mlx5_ifc_traffic_counter_bits {
1959         u8         packets[0x40];
1960
1961         u8         octets[0x40];
1962 };
1963
1964 struct mlx5_ifc_tisc_bits {
1965         u8         reserved_0[0xc];
1966         u8         prio[0x4];
1967         u8         reserved_1[0x10];
1968
1969         u8         reserved_2[0x100];
1970
1971         u8         reserved_3[0x8];
1972         u8         transport_domain[0x18];
1973
1974         u8         reserved_4[0x3c0];
1975 };
1976
1977 enum {
1978         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1979         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1980 };
1981
1982 enum {
1983         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1984         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1985 };
1986
1987 enum {
1988         MLX5_RX_HASH_FN_NONE           = 0x0,
1989         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
1990         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
1991 };
1992
1993 enum {
1994         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
1995         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
1996 };
1997
1998 struct mlx5_ifc_tirc_bits {
1999         u8         reserved_0[0x20];
2000
2001         u8         disp_type[0x4];
2002         u8         reserved_1[0x1c];
2003
2004         u8         reserved_2[0x40];
2005
2006         u8         reserved_3[0x4];
2007         u8         lro_timeout_period_usecs[0x10];
2008         u8         lro_enable_mask[0x4];
2009         u8         lro_max_ip_payload_size[0x8];
2010
2011         u8         reserved_4[0x40];
2012
2013         u8         reserved_5[0x8];
2014         u8         inline_rqn[0x18];
2015
2016         u8         rx_hash_symmetric[0x1];
2017         u8         reserved_6[0x1];
2018         u8         tunneled_offload_en[0x1];
2019         u8         reserved_7[0x5];
2020         u8         indirect_table[0x18];
2021
2022         u8         rx_hash_fn[0x4];
2023         u8         reserved_8[0x2];
2024         u8         self_lb_block[0x2];
2025         u8         transport_domain[0x18];
2026
2027         u8         rx_hash_toeplitz_key[10][0x20];
2028
2029         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2030
2031         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2032
2033         u8         reserved_9[0x4c0];
2034 };
2035
2036 enum {
2037         MLX5_SRQC_STATE_GOOD   = 0x0,
2038         MLX5_SRQC_STATE_ERROR  = 0x1,
2039 };
2040
2041 struct mlx5_ifc_srqc_bits {
2042         u8         state[0x4];
2043         u8         log_srq_size[0x4];
2044         u8         reserved_0[0x18];
2045
2046         u8         wq_signature[0x1];
2047         u8         cont_srq[0x1];
2048         u8         reserved_1[0x1];
2049         u8         rlky[0x1];
2050         u8         reserved_2[0x1];
2051         u8         log_rq_stride[0x3];
2052         u8         xrcd[0x18];
2053
2054         u8         page_offset[0x6];
2055         u8         reserved_3[0x2];
2056         u8         cqn[0x18];
2057
2058         u8         reserved_4[0x20];
2059
2060         u8         reserved_5[0x2];
2061         u8         log_page_size[0x6];
2062         u8         reserved_6[0x18];
2063
2064         u8         reserved_7[0x20];
2065
2066         u8         reserved_8[0x8];
2067         u8         pd[0x18];
2068
2069         u8         lwm[0x10];
2070         u8         wqe_cnt[0x10];
2071
2072         u8         reserved_9[0x40];
2073
2074         u8         dbr_addr[0x40];
2075
2076         u8         reserved_10[0x80];
2077 };
2078
2079 enum {
2080         MLX5_SQC_STATE_RST  = 0x0,
2081         MLX5_SQC_STATE_RDY  = 0x1,
2082         MLX5_SQC_STATE_ERR  = 0x3,
2083 };
2084
2085 struct mlx5_ifc_sqc_bits {
2086         u8         rlky[0x1];
2087         u8         cd_master[0x1];
2088         u8         fre[0x1];
2089         u8         flush_in_error_en[0x1];
2090         u8         reserved_0[0x4];
2091         u8         state[0x4];
2092         u8         reserved_1[0x14];
2093
2094         u8         reserved_2[0x8];
2095         u8         user_index[0x18];
2096
2097         u8         reserved_3[0x8];
2098         u8         cqn[0x18];
2099
2100         u8         reserved_4[0xa0];
2101
2102         u8         tis_lst_sz[0x10];
2103         u8         reserved_5[0x10];
2104
2105         u8         reserved_6[0x40];
2106
2107         u8         reserved_7[0x8];
2108         u8         tis_num_0[0x18];
2109
2110         struct mlx5_ifc_wq_bits wq;
2111 };
2112
2113 struct mlx5_ifc_rqtc_bits {
2114         u8         reserved_0[0xa0];
2115
2116         u8         reserved_1[0x10];
2117         u8         rqt_max_size[0x10];
2118
2119         u8         reserved_2[0x10];
2120         u8         rqt_actual_size[0x10];
2121
2122         u8         reserved_3[0x6a0];
2123
2124         struct mlx5_ifc_rq_num_bits rq_num[0];
2125 };
2126
2127 enum {
2128         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2129         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2130 };
2131
2132 enum {
2133         MLX5_RQC_STATE_RST  = 0x0,
2134         MLX5_RQC_STATE_RDY  = 0x1,
2135         MLX5_RQC_STATE_ERR  = 0x3,
2136 };
2137
2138 struct mlx5_ifc_rqc_bits {
2139         u8         rlky[0x1];
2140         u8         reserved_0[0x2];
2141         u8         vsd[0x1];
2142         u8         mem_rq_type[0x4];
2143         u8         state[0x4];
2144         u8         reserved_1[0x1];
2145         u8         flush_in_error_en[0x1];
2146         u8         reserved_2[0x12];
2147
2148         u8         reserved_3[0x8];
2149         u8         user_index[0x18];
2150
2151         u8         reserved_4[0x8];
2152         u8         cqn[0x18];
2153
2154         u8         counter_set_id[0x8];
2155         u8         reserved_5[0x18];
2156
2157         u8         reserved_6[0x8];
2158         u8         rmpn[0x18];
2159
2160         u8         reserved_7[0xe0];
2161
2162         struct mlx5_ifc_wq_bits wq;
2163 };
2164
2165 enum {
2166         MLX5_RMPC_STATE_RDY  = 0x1,
2167         MLX5_RMPC_STATE_ERR  = 0x3,
2168 };
2169
2170 struct mlx5_ifc_rmpc_bits {
2171         u8         reserved_0[0x8];
2172         u8         state[0x4];
2173         u8         reserved_1[0x14];
2174
2175         u8         basic_cyclic_rcv_wqe[0x1];
2176         u8         reserved_2[0x1f];
2177
2178         u8         reserved_3[0x140];
2179
2180         struct mlx5_ifc_wq_bits wq;
2181 };
2182
2183 struct mlx5_ifc_nic_vport_context_bits {
2184         u8         reserved_0[0x1f];
2185         u8         roce_en[0x1];
2186
2187         u8         arm_change_event[0x1];
2188         u8         reserved_1[0x1a];
2189         u8         event_on_mtu[0x1];
2190         u8         event_on_promisc_change[0x1];
2191         u8         event_on_vlan_change[0x1];
2192         u8         event_on_mc_address_change[0x1];
2193         u8         event_on_uc_address_change[0x1];
2194
2195         u8         reserved_2[0xf0];
2196
2197         u8         mtu[0x10];
2198
2199         u8         reserved_3[0x640];
2200
2201         u8         promisc_uc[0x1];
2202         u8         promisc_mc[0x1];
2203         u8         promisc_all[0x1];
2204         u8         reserved_4[0x2];
2205         u8         allowed_list_type[0x3];
2206         u8         reserved_5[0xc];
2207         u8         allowed_list_size[0xc];
2208
2209         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2210
2211         u8         reserved_6[0x20];
2212
2213         u8         current_uc_mac_address[0][0x40];
2214 };
2215
2216 enum {
2217         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2218         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2219         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2220 };
2221
2222 struct mlx5_ifc_mkc_bits {
2223         u8         reserved_0[0x1];
2224         u8         free[0x1];
2225         u8         reserved_1[0xd];
2226         u8         small_fence_on_rdma_read_response[0x1];
2227         u8         umr_en[0x1];
2228         u8         a[0x1];
2229         u8         rw[0x1];
2230         u8         rr[0x1];
2231         u8         lw[0x1];
2232         u8         lr[0x1];
2233         u8         access_mode[0x2];
2234         u8         reserved_2[0x8];
2235
2236         u8         qpn[0x18];
2237         u8         mkey_7_0[0x8];
2238
2239         u8         reserved_3[0x20];
2240
2241         u8         length64[0x1];
2242         u8         bsf_en[0x1];
2243         u8         sync_umr[0x1];
2244         u8         reserved_4[0x2];
2245         u8         expected_sigerr_count[0x1];
2246         u8         reserved_5[0x1];
2247         u8         en_rinval[0x1];
2248         u8         pd[0x18];
2249
2250         u8         start_addr[0x40];
2251
2252         u8         len[0x40];
2253
2254         u8         bsf_octword_size[0x20];
2255
2256         u8         reserved_6[0x80];
2257
2258         u8         translations_octword_size[0x20];
2259
2260         u8         reserved_7[0x1b];
2261         u8         log_page_size[0x5];
2262
2263         u8         reserved_8[0x20];
2264 };
2265
2266 struct mlx5_ifc_pkey_bits {
2267         u8         reserved_0[0x10];
2268         u8         pkey[0x10];
2269 };
2270
2271 struct mlx5_ifc_array128_auto_bits {
2272         u8         array128_auto[16][0x8];
2273 };
2274
2275 struct mlx5_ifc_hca_vport_context_bits {
2276         u8         field_select[0x20];
2277
2278         u8         reserved_0[0xe0];
2279
2280         u8         sm_virt_aware[0x1];
2281         u8         has_smi[0x1];
2282         u8         has_raw[0x1];
2283         u8         grh_required[0x1];
2284         u8         reserved_1[0xc];
2285         u8         port_physical_state[0x4];
2286         u8         vport_state_policy[0x4];
2287         u8         port_state[0x4];
2288         u8         vport_state[0x4];
2289
2290         u8         reserved_2[0x20];
2291
2292         u8         system_image_guid[0x40];
2293
2294         u8         port_guid[0x40];
2295
2296         u8         node_guid[0x40];
2297
2298         u8         cap_mask1[0x20];
2299
2300         u8         cap_mask1_field_select[0x20];
2301
2302         u8         cap_mask2[0x20];
2303
2304         u8         cap_mask2_field_select[0x20];
2305
2306         u8         reserved_3[0x80];
2307
2308         u8         lid[0x10];
2309         u8         reserved_4[0x4];
2310         u8         init_type_reply[0x4];
2311         u8         lmc[0x3];
2312         u8         subnet_timeout[0x5];
2313
2314         u8         sm_lid[0x10];
2315         u8         sm_sl[0x4];
2316         u8         reserved_5[0xc];
2317
2318         u8         qkey_violation_counter[0x10];
2319         u8         pkey_violation_counter[0x10];
2320
2321         u8         reserved_6[0xca0];
2322 };
2323
2324 struct mlx5_ifc_esw_vport_context_bits {
2325         u8         reserved_0[0x3];
2326         u8         vport_svlan_strip[0x1];
2327         u8         vport_cvlan_strip[0x1];
2328         u8         vport_svlan_insert[0x1];
2329         u8         vport_cvlan_insert[0x2];
2330         u8         reserved_1[0x18];
2331
2332         u8         reserved_2[0x20];
2333
2334         u8         svlan_cfi[0x1];
2335         u8         svlan_pcp[0x3];
2336         u8         svlan_id[0xc];
2337         u8         cvlan_cfi[0x1];
2338         u8         cvlan_pcp[0x3];
2339         u8         cvlan_id[0xc];
2340
2341         u8         reserved_3[0x7a0];
2342 };
2343
2344 enum {
2345         MLX5_EQC_STATUS_OK                = 0x0,
2346         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2347 };
2348
2349 enum {
2350         MLX5_EQC_ST_ARMED  = 0x9,
2351         MLX5_EQC_ST_FIRED  = 0xa,
2352 };
2353
2354 struct mlx5_ifc_eqc_bits {
2355         u8         status[0x4];
2356         u8         reserved_0[0x9];
2357         u8         ec[0x1];
2358         u8         oi[0x1];
2359         u8         reserved_1[0x5];
2360         u8         st[0x4];
2361         u8         reserved_2[0x8];
2362
2363         u8         reserved_3[0x20];
2364
2365         u8         reserved_4[0x14];
2366         u8         page_offset[0x6];
2367         u8         reserved_5[0x6];
2368
2369         u8         reserved_6[0x3];
2370         u8         log_eq_size[0x5];
2371         u8         uar_page[0x18];
2372
2373         u8         reserved_7[0x20];
2374
2375         u8         reserved_8[0x18];
2376         u8         intr[0x8];
2377
2378         u8         reserved_9[0x3];
2379         u8         log_page_size[0x5];
2380         u8         reserved_10[0x18];
2381
2382         u8         reserved_11[0x60];
2383
2384         u8         reserved_12[0x8];
2385         u8         consumer_counter[0x18];
2386
2387         u8         reserved_13[0x8];
2388         u8         producer_counter[0x18];
2389
2390         u8         reserved_14[0x80];
2391 };
2392
2393 enum {
2394         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2395         MLX5_DCTC_STATE_DRAINING  = 0x1,
2396         MLX5_DCTC_STATE_DRAINED   = 0x2,
2397 };
2398
2399 enum {
2400         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2401         MLX5_DCTC_CS_RES_NA         = 0x1,
2402         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2403 };
2404
2405 enum {
2406         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2407         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2408         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2409         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2410         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2411 };
2412
2413 struct mlx5_ifc_dctc_bits {
2414         u8         reserved_0[0x4];
2415         u8         state[0x4];
2416         u8         reserved_1[0x18];
2417
2418         u8         reserved_2[0x8];
2419         u8         user_index[0x18];
2420
2421         u8         reserved_3[0x8];
2422         u8         cqn[0x18];
2423
2424         u8         counter_set_id[0x8];
2425         u8         atomic_mode[0x4];
2426         u8         rre[0x1];
2427         u8         rwe[0x1];
2428         u8         rae[0x1];
2429         u8         atomic_like_write_en[0x1];
2430         u8         latency_sensitive[0x1];
2431         u8         rlky[0x1];
2432         u8         free_ar[0x1];
2433         u8         reserved_4[0xd];
2434
2435         u8         reserved_5[0x8];
2436         u8         cs_res[0x8];
2437         u8         reserved_6[0x3];
2438         u8         min_rnr_nak[0x5];
2439         u8         reserved_7[0x8];
2440
2441         u8         reserved_8[0x8];
2442         u8         srqn[0x18];
2443
2444         u8         reserved_9[0x8];
2445         u8         pd[0x18];
2446
2447         u8         tclass[0x8];
2448         u8         reserved_10[0x4];
2449         u8         flow_label[0x14];
2450
2451         u8         dc_access_key[0x40];
2452
2453         u8         reserved_11[0x5];
2454         u8         mtu[0x3];
2455         u8         port[0x8];
2456         u8         pkey_index[0x10];
2457
2458         u8         reserved_12[0x8];
2459         u8         my_addr_index[0x8];
2460         u8         reserved_13[0x8];
2461         u8         hop_limit[0x8];
2462
2463         u8         dc_access_key_violation_count[0x20];
2464
2465         u8         reserved_14[0x14];
2466         u8         dei_cfi[0x1];
2467         u8         eth_prio[0x3];
2468         u8         ecn[0x2];
2469         u8         dscp[0x6];
2470
2471         u8         reserved_15[0x40];
2472 };
2473
2474 enum {
2475         MLX5_CQC_STATUS_OK             = 0x0,
2476         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2477         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2478 };
2479
2480 enum {
2481         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2482         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2483 };
2484
2485 enum {
2486         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2487         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2488         MLX5_CQC_ST_FIRED                                 = 0xa,
2489 };
2490
2491 struct mlx5_ifc_cqc_bits {
2492         u8         status[0x4];
2493         u8         reserved_0[0x4];
2494         u8         cqe_sz[0x3];
2495         u8         cc[0x1];
2496         u8         reserved_1[0x1];
2497         u8         scqe_break_moderation_en[0x1];
2498         u8         oi[0x1];
2499         u8         reserved_2[0x2];
2500         u8         cqe_zip_en[0x1];
2501         u8         mini_cqe_res_format[0x2];
2502         u8         st[0x4];
2503         u8         reserved_3[0x8];
2504
2505         u8         reserved_4[0x20];
2506
2507         u8         reserved_5[0x14];
2508         u8         page_offset[0x6];
2509         u8         reserved_6[0x6];
2510
2511         u8         reserved_7[0x3];
2512         u8         log_cq_size[0x5];
2513         u8         uar_page[0x18];
2514
2515         u8         reserved_8[0x4];
2516         u8         cq_period[0xc];
2517         u8         cq_max_count[0x10];
2518
2519         u8         reserved_9[0x18];
2520         u8         c_eqn[0x8];
2521
2522         u8         reserved_10[0x3];
2523         u8         log_page_size[0x5];
2524         u8         reserved_11[0x18];
2525
2526         u8         reserved_12[0x20];
2527
2528         u8         reserved_13[0x8];
2529         u8         last_notified_index[0x18];
2530
2531         u8         reserved_14[0x8];
2532         u8         last_solicit_index[0x18];
2533
2534         u8         reserved_15[0x8];
2535         u8         consumer_counter[0x18];
2536
2537         u8         reserved_16[0x8];
2538         u8         producer_counter[0x18];
2539
2540         u8         reserved_17[0x40];
2541
2542         u8         dbr_addr[0x40];
2543 };
2544
2545 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2546         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2547         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2548         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2549         u8         reserved_0[0x800];
2550 };
2551
2552 struct mlx5_ifc_query_adapter_param_block_bits {
2553         u8         reserved_0[0xc0];
2554
2555         u8         reserved_1[0x8];
2556         u8         ieee_vendor_id[0x18];
2557
2558         u8         reserved_2[0x10];
2559         u8         vsd_vendor_id[0x10];
2560
2561         u8         vsd[208][0x8];
2562
2563         u8         vsd_contd_psid[16][0x8];
2564 };
2565
2566 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2567         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2568         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2569         u8         reserved_0[0x20];
2570 };
2571
2572 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2573         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2574         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2575         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2576         u8         reserved_0[0x20];
2577 };
2578
2579 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2580         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2581         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2582         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2583         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2584         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2585         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2586         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2587         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2588         u8         reserved_0[0x7c0];
2589 };
2590
2591 union mlx5_ifc_event_auto_bits {
2592         struct mlx5_ifc_comp_event_bits comp_event;
2593         struct mlx5_ifc_dct_events_bits dct_events;
2594         struct mlx5_ifc_qp_events_bits qp_events;
2595         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2596         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2597         struct mlx5_ifc_cq_error_bits cq_error;
2598         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2599         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2600         struct mlx5_ifc_gpio_event_bits gpio_event;
2601         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2602         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2603         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2604         u8         reserved_0[0xe0];
2605 };
2606
2607 struct mlx5_ifc_health_buffer_bits {
2608         u8         reserved_0[0x100];
2609
2610         u8         assert_existptr[0x20];
2611
2612         u8         assert_callra[0x20];
2613
2614         u8         reserved_1[0x40];
2615
2616         u8         fw_version[0x20];
2617
2618         u8         hw_id[0x20];
2619
2620         u8         reserved_2[0x20];
2621
2622         u8         irisc_index[0x8];
2623         u8         synd[0x8];
2624         u8         ext_synd[0x10];
2625 };
2626
2627 struct mlx5_ifc_register_loopback_control_bits {
2628         u8         no_lb[0x1];
2629         u8         reserved_0[0x7];
2630         u8         port[0x8];
2631         u8         reserved_1[0x10];
2632
2633         u8         reserved_2[0x60];
2634 };
2635
2636 struct mlx5_ifc_teardown_hca_out_bits {
2637         u8         status[0x8];
2638         u8         reserved_0[0x18];
2639
2640         u8         syndrome[0x20];
2641
2642         u8         reserved_1[0x40];
2643 };
2644
2645 enum {
2646         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2647         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2648 };
2649
2650 struct mlx5_ifc_teardown_hca_in_bits {
2651         u8         opcode[0x10];
2652         u8         reserved_0[0x10];
2653
2654         u8         reserved_1[0x10];
2655         u8         op_mod[0x10];
2656
2657         u8         reserved_2[0x10];
2658         u8         profile[0x10];
2659
2660         u8         reserved_3[0x20];
2661 };
2662
2663 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2664         u8         status[0x8];
2665         u8         reserved_0[0x18];
2666
2667         u8         syndrome[0x20];
2668
2669         u8         reserved_1[0x40];
2670 };
2671
2672 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2673         u8         opcode[0x10];
2674         u8         reserved_0[0x10];
2675
2676         u8         reserved_1[0x10];
2677         u8         op_mod[0x10];
2678
2679         u8         reserved_2[0x8];
2680         u8         qpn[0x18];
2681
2682         u8         reserved_3[0x20];
2683
2684         u8         opt_param_mask[0x20];
2685
2686         u8         reserved_4[0x20];
2687
2688         struct mlx5_ifc_qpc_bits qpc;
2689
2690         u8         reserved_5[0x80];
2691 };
2692
2693 struct mlx5_ifc_sqd2rts_qp_out_bits {
2694         u8         status[0x8];
2695         u8         reserved_0[0x18];
2696
2697         u8         syndrome[0x20];
2698
2699         u8         reserved_1[0x40];
2700 };
2701
2702 struct mlx5_ifc_sqd2rts_qp_in_bits {
2703         u8         opcode[0x10];
2704         u8         reserved_0[0x10];
2705
2706         u8         reserved_1[0x10];
2707         u8         op_mod[0x10];
2708
2709         u8         reserved_2[0x8];
2710         u8         qpn[0x18];
2711
2712         u8         reserved_3[0x20];
2713
2714         u8         opt_param_mask[0x20];
2715
2716         u8         reserved_4[0x20];
2717
2718         struct mlx5_ifc_qpc_bits qpc;
2719
2720         u8         reserved_5[0x80];
2721 };
2722
2723 struct mlx5_ifc_set_roce_address_out_bits {
2724         u8         status[0x8];
2725         u8         reserved_0[0x18];
2726
2727         u8         syndrome[0x20];
2728
2729         u8         reserved_1[0x40];
2730 };
2731
2732 struct mlx5_ifc_set_roce_address_in_bits {
2733         u8         opcode[0x10];
2734         u8         reserved_0[0x10];
2735
2736         u8         reserved_1[0x10];
2737         u8         op_mod[0x10];
2738
2739         u8         roce_address_index[0x10];
2740         u8         reserved_2[0x10];
2741
2742         u8         reserved_3[0x20];
2743
2744         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2745 };
2746
2747 struct mlx5_ifc_set_mad_demux_out_bits {
2748         u8         status[0x8];
2749         u8         reserved_0[0x18];
2750
2751         u8         syndrome[0x20];
2752
2753         u8         reserved_1[0x40];
2754 };
2755
2756 enum {
2757         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2758         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2759 };
2760
2761 struct mlx5_ifc_set_mad_demux_in_bits {
2762         u8         opcode[0x10];
2763         u8         reserved_0[0x10];
2764
2765         u8         reserved_1[0x10];
2766         u8         op_mod[0x10];
2767
2768         u8         reserved_2[0x20];
2769
2770         u8         reserved_3[0x6];
2771         u8         demux_mode[0x2];
2772         u8         reserved_4[0x18];
2773 };
2774
2775 struct mlx5_ifc_set_l2_table_entry_out_bits {
2776         u8         status[0x8];
2777         u8         reserved_0[0x18];
2778
2779         u8         syndrome[0x20];
2780
2781         u8         reserved_1[0x40];
2782 };
2783
2784 struct mlx5_ifc_set_l2_table_entry_in_bits {
2785         u8         opcode[0x10];
2786         u8         reserved_0[0x10];
2787
2788         u8         reserved_1[0x10];
2789         u8         op_mod[0x10];
2790
2791         u8         reserved_2[0x60];
2792
2793         u8         reserved_3[0x8];
2794         u8         table_index[0x18];
2795
2796         u8         reserved_4[0x20];
2797
2798         u8         reserved_5[0x13];
2799         u8         vlan_valid[0x1];
2800         u8         vlan[0xc];
2801
2802         struct mlx5_ifc_mac_address_layout_bits mac_address;
2803
2804         u8         reserved_6[0xc0];
2805 };
2806
2807 struct mlx5_ifc_set_issi_out_bits {
2808         u8         status[0x8];
2809         u8         reserved_0[0x18];
2810
2811         u8         syndrome[0x20];
2812
2813         u8         reserved_1[0x40];
2814 };
2815
2816 struct mlx5_ifc_set_issi_in_bits {
2817         u8         opcode[0x10];
2818         u8         reserved_0[0x10];
2819
2820         u8         reserved_1[0x10];
2821         u8         op_mod[0x10];
2822
2823         u8         reserved_2[0x10];
2824         u8         current_issi[0x10];
2825
2826         u8         reserved_3[0x20];
2827 };
2828
2829 struct mlx5_ifc_set_hca_cap_out_bits {
2830         u8         status[0x8];
2831         u8         reserved_0[0x18];
2832
2833         u8         syndrome[0x20];
2834
2835         u8         reserved_1[0x40];
2836 };
2837
2838 struct mlx5_ifc_set_hca_cap_in_bits {
2839         u8         opcode[0x10];
2840         u8         reserved_0[0x10];
2841
2842         u8         reserved_1[0x10];
2843         u8         op_mod[0x10];
2844
2845         u8         reserved_2[0x40];
2846
2847         union mlx5_ifc_hca_cap_union_bits capability;
2848 };
2849
2850 enum {
2851         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
2852         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
2853         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
2854         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
2855 };
2856
2857 struct mlx5_ifc_set_fte_out_bits {
2858         u8         status[0x8];
2859         u8         reserved_0[0x18];
2860
2861         u8         syndrome[0x20];
2862
2863         u8         reserved_1[0x40];
2864 };
2865
2866 struct mlx5_ifc_set_fte_in_bits {
2867         u8         opcode[0x10];
2868         u8         reserved_0[0x10];
2869
2870         u8         reserved_1[0x10];
2871         u8         op_mod[0x10];
2872
2873         u8         reserved_2[0x40];
2874
2875         u8         table_type[0x8];
2876         u8         reserved_3[0x18];
2877
2878         u8         reserved_4[0x8];
2879         u8         table_id[0x18];
2880
2881         u8         reserved_5[0x18];
2882         u8         modify_enable_mask[0x8];
2883
2884         u8         reserved_6[0x20];
2885
2886         u8         flow_index[0x20];
2887
2888         u8         reserved_7[0xe0];
2889
2890         struct mlx5_ifc_flow_context_bits flow_context;
2891 };
2892
2893 struct mlx5_ifc_rts2rts_qp_out_bits {
2894         u8         status[0x8];
2895         u8         reserved_0[0x18];
2896
2897         u8         syndrome[0x20];
2898
2899         u8         reserved_1[0x40];
2900 };
2901
2902 struct mlx5_ifc_rts2rts_qp_in_bits {
2903         u8         opcode[0x10];
2904         u8         reserved_0[0x10];
2905
2906         u8         reserved_1[0x10];
2907         u8         op_mod[0x10];
2908
2909         u8         reserved_2[0x8];
2910         u8         qpn[0x18];
2911
2912         u8         reserved_3[0x20];
2913
2914         u8         opt_param_mask[0x20];
2915
2916         u8         reserved_4[0x20];
2917
2918         struct mlx5_ifc_qpc_bits qpc;
2919
2920         u8         reserved_5[0x80];
2921 };
2922
2923 struct mlx5_ifc_rtr2rts_qp_out_bits {
2924         u8         status[0x8];
2925         u8         reserved_0[0x18];
2926
2927         u8         syndrome[0x20];
2928
2929         u8         reserved_1[0x40];
2930 };
2931
2932 struct mlx5_ifc_rtr2rts_qp_in_bits {
2933         u8         opcode[0x10];
2934         u8         reserved_0[0x10];
2935
2936         u8         reserved_1[0x10];
2937         u8         op_mod[0x10];
2938
2939         u8         reserved_2[0x8];
2940         u8         qpn[0x18];
2941
2942         u8         reserved_3[0x20];
2943
2944         u8         opt_param_mask[0x20];
2945
2946         u8         reserved_4[0x20];
2947
2948         struct mlx5_ifc_qpc_bits qpc;
2949
2950         u8         reserved_5[0x80];
2951 };
2952
2953 struct mlx5_ifc_rst2init_qp_out_bits {
2954         u8         status[0x8];
2955         u8         reserved_0[0x18];
2956
2957         u8         syndrome[0x20];
2958
2959         u8         reserved_1[0x40];
2960 };
2961
2962 struct mlx5_ifc_rst2init_qp_in_bits {
2963         u8         opcode[0x10];
2964         u8         reserved_0[0x10];
2965
2966         u8         reserved_1[0x10];
2967         u8         op_mod[0x10];
2968
2969         u8         reserved_2[0x8];
2970         u8         qpn[0x18];
2971
2972         u8         reserved_3[0x20];
2973
2974         u8         opt_param_mask[0x20];
2975
2976         u8         reserved_4[0x20];
2977
2978         struct mlx5_ifc_qpc_bits qpc;
2979
2980         u8         reserved_5[0x80];
2981 };
2982
2983 struct mlx5_ifc_query_xrc_srq_out_bits {
2984         u8         status[0x8];
2985         u8         reserved_0[0x18];
2986
2987         u8         syndrome[0x20];
2988
2989         u8         reserved_1[0x40];
2990
2991         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2992
2993         u8         reserved_2[0x600];
2994
2995         u8         pas[0][0x40];
2996 };
2997
2998 struct mlx5_ifc_query_xrc_srq_in_bits {
2999         u8         opcode[0x10];
3000         u8         reserved_0[0x10];
3001
3002         u8         reserved_1[0x10];
3003         u8         op_mod[0x10];
3004
3005         u8         reserved_2[0x8];
3006         u8         xrc_srqn[0x18];
3007
3008         u8         reserved_3[0x20];
3009 };
3010
3011 enum {
3012         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3013         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3014 };
3015
3016 struct mlx5_ifc_query_vport_state_out_bits {
3017         u8         status[0x8];
3018         u8         reserved_0[0x18];
3019
3020         u8         syndrome[0x20];
3021
3022         u8         reserved_1[0x20];
3023
3024         u8         reserved_2[0x18];
3025         u8         admin_state[0x4];
3026         u8         state[0x4];
3027 };
3028
3029 enum {
3030         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3031         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3032 };
3033
3034 struct mlx5_ifc_query_vport_state_in_bits {
3035         u8         opcode[0x10];
3036         u8         reserved_0[0x10];
3037
3038         u8         reserved_1[0x10];
3039         u8         op_mod[0x10];
3040
3041         u8         other_vport[0x1];
3042         u8         reserved_2[0xf];
3043         u8         vport_number[0x10];
3044
3045         u8         reserved_3[0x20];
3046 };
3047
3048 struct mlx5_ifc_query_vport_counter_out_bits {
3049         u8         status[0x8];
3050         u8         reserved_0[0x18];
3051
3052         u8         syndrome[0x20];
3053
3054         u8         reserved_1[0x40];
3055
3056         struct mlx5_ifc_traffic_counter_bits received_errors;
3057
3058         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3059
3060         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3061
3062         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3063
3064         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3065
3066         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3067
3068         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3069
3070         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3071
3072         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3073
3074         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3075
3076         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3077
3078         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3079
3080         u8         reserved_2[0xa00];
3081 };
3082
3083 enum {
3084         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3085 };
3086
3087 struct mlx5_ifc_query_vport_counter_in_bits {
3088         u8         opcode[0x10];
3089         u8         reserved_0[0x10];
3090
3091         u8         reserved_1[0x10];
3092         u8         op_mod[0x10];
3093
3094         u8         other_vport[0x1];
3095         u8         reserved_2[0xf];
3096         u8         vport_number[0x10];
3097
3098         u8         reserved_3[0x60];
3099
3100         u8         clear[0x1];
3101         u8         reserved_4[0x1f];
3102
3103         u8         reserved_5[0x20];
3104 };
3105
3106 struct mlx5_ifc_query_tis_out_bits {
3107         u8         status[0x8];
3108         u8         reserved_0[0x18];
3109
3110         u8         syndrome[0x20];
3111
3112         u8         reserved_1[0x40];
3113
3114         struct mlx5_ifc_tisc_bits tis_context;
3115 };
3116
3117 struct mlx5_ifc_query_tis_in_bits {
3118         u8         opcode[0x10];
3119         u8         reserved_0[0x10];
3120
3121         u8         reserved_1[0x10];
3122         u8         op_mod[0x10];
3123
3124         u8         reserved_2[0x8];
3125         u8         tisn[0x18];
3126
3127         u8         reserved_3[0x20];
3128 };
3129
3130 struct mlx5_ifc_query_tir_out_bits {
3131         u8         status[0x8];
3132         u8         reserved_0[0x18];
3133
3134         u8         syndrome[0x20];
3135
3136         u8         reserved_1[0xc0];
3137
3138         struct mlx5_ifc_tirc_bits tir_context;
3139 };
3140
3141 struct mlx5_ifc_query_tir_in_bits {
3142         u8         opcode[0x10];
3143         u8         reserved_0[0x10];
3144
3145         u8         reserved_1[0x10];
3146         u8         op_mod[0x10];
3147
3148         u8         reserved_2[0x8];
3149         u8         tirn[0x18];
3150
3151         u8         reserved_3[0x20];
3152 };
3153
3154 struct mlx5_ifc_query_srq_out_bits {
3155         u8         status[0x8];
3156         u8         reserved_0[0x18];
3157
3158         u8         syndrome[0x20];
3159
3160         u8         reserved_1[0x40];
3161
3162         struct mlx5_ifc_srqc_bits srq_context_entry;
3163
3164         u8         reserved_2[0x600];
3165
3166         u8         pas[0][0x40];
3167 };
3168
3169 struct mlx5_ifc_query_srq_in_bits {
3170         u8         opcode[0x10];
3171         u8         reserved_0[0x10];
3172
3173         u8         reserved_1[0x10];
3174         u8         op_mod[0x10];
3175
3176         u8         reserved_2[0x8];
3177         u8         srqn[0x18];
3178
3179         u8         reserved_3[0x20];
3180 };
3181
3182 struct mlx5_ifc_query_sq_out_bits {
3183         u8         status[0x8];
3184         u8         reserved_0[0x18];
3185
3186         u8         syndrome[0x20];
3187
3188         u8         reserved_1[0xc0];
3189
3190         struct mlx5_ifc_sqc_bits sq_context;
3191 };
3192
3193 struct mlx5_ifc_query_sq_in_bits {
3194         u8         opcode[0x10];
3195         u8         reserved_0[0x10];
3196
3197         u8         reserved_1[0x10];
3198         u8         op_mod[0x10];
3199
3200         u8         reserved_2[0x8];
3201         u8         sqn[0x18];
3202
3203         u8         reserved_3[0x20];
3204 };
3205
3206 struct mlx5_ifc_query_special_contexts_out_bits {
3207         u8         status[0x8];
3208         u8         reserved_0[0x18];
3209
3210         u8         syndrome[0x20];
3211
3212         u8         reserved_1[0x20];
3213
3214         u8         resd_lkey[0x20];
3215 };
3216
3217 struct mlx5_ifc_query_special_contexts_in_bits {
3218         u8         opcode[0x10];
3219         u8         reserved_0[0x10];
3220
3221         u8         reserved_1[0x10];
3222         u8         op_mod[0x10];
3223
3224         u8         reserved_2[0x40];
3225 };
3226
3227 struct mlx5_ifc_query_rqt_out_bits {
3228         u8         status[0x8];
3229         u8         reserved_0[0x18];
3230
3231         u8         syndrome[0x20];
3232
3233         u8         reserved_1[0xc0];
3234
3235         struct mlx5_ifc_rqtc_bits rqt_context;
3236 };
3237
3238 struct mlx5_ifc_query_rqt_in_bits {
3239         u8         opcode[0x10];
3240         u8         reserved_0[0x10];
3241
3242         u8         reserved_1[0x10];
3243         u8         op_mod[0x10];
3244
3245         u8         reserved_2[0x8];
3246         u8         rqtn[0x18];
3247
3248         u8         reserved_3[0x20];
3249 };
3250
3251 struct mlx5_ifc_query_rq_out_bits {
3252         u8         status[0x8];
3253         u8         reserved_0[0x18];
3254
3255         u8         syndrome[0x20];
3256
3257         u8         reserved_1[0xc0];
3258
3259         struct mlx5_ifc_rqc_bits rq_context;
3260 };
3261
3262 struct mlx5_ifc_query_rq_in_bits {
3263         u8         opcode[0x10];
3264         u8         reserved_0[0x10];
3265
3266         u8         reserved_1[0x10];
3267         u8         op_mod[0x10];
3268
3269         u8         reserved_2[0x8];
3270         u8         rqn[0x18];
3271
3272         u8         reserved_3[0x20];
3273 };
3274
3275 struct mlx5_ifc_query_roce_address_out_bits {
3276         u8         status[0x8];
3277         u8         reserved_0[0x18];
3278
3279         u8         syndrome[0x20];
3280
3281         u8         reserved_1[0x40];
3282
3283         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3284 };
3285
3286 struct mlx5_ifc_query_roce_address_in_bits {
3287         u8         opcode[0x10];
3288         u8         reserved_0[0x10];
3289
3290         u8         reserved_1[0x10];
3291         u8         op_mod[0x10];
3292
3293         u8         roce_address_index[0x10];
3294         u8         reserved_2[0x10];
3295
3296         u8         reserved_3[0x20];
3297 };
3298
3299 struct mlx5_ifc_query_rmp_out_bits {
3300         u8         status[0x8];
3301         u8         reserved_0[0x18];
3302
3303         u8         syndrome[0x20];
3304
3305         u8         reserved_1[0xc0];
3306
3307         struct mlx5_ifc_rmpc_bits rmp_context;
3308 };
3309
3310 struct mlx5_ifc_query_rmp_in_bits {
3311         u8         opcode[0x10];
3312         u8         reserved_0[0x10];
3313
3314         u8         reserved_1[0x10];
3315         u8         op_mod[0x10];
3316
3317         u8         reserved_2[0x8];
3318         u8         rmpn[0x18];
3319
3320         u8         reserved_3[0x20];
3321 };
3322
3323 struct mlx5_ifc_query_qp_out_bits {
3324         u8         status[0x8];
3325         u8         reserved_0[0x18];
3326
3327         u8         syndrome[0x20];
3328
3329         u8         reserved_1[0x40];
3330
3331         u8         opt_param_mask[0x20];
3332
3333         u8         reserved_2[0x20];
3334
3335         struct mlx5_ifc_qpc_bits qpc;
3336
3337         u8         reserved_3[0x80];
3338
3339         u8         pas[0][0x40];
3340 };
3341
3342 struct mlx5_ifc_query_qp_in_bits {
3343         u8         opcode[0x10];
3344         u8         reserved_0[0x10];
3345
3346         u8         reserved_1[0x10];
3347         u8         op_mod[0x10];
3348
3349         u8         reserved_2[0x8];
3350         u8         qpn[0x18];
3351
3352         u8         reserved_3[0x20];
3353 };
3354
3355 struct mlx5_ifc_query_q_counter_out_bits {
3356         u8         status[0x8];
3357         u8         reserved_0[0x18];
3358
3359         u8         syndrome[0x20];
3360
3361         u8         reserved_1[0x40];
3362
3363         u8         rx_write_requests[0x20];
3364
3365         u8         reserved_2[0x20];
3366
3367         u8         rx_read_requests[0x20];
3368
3369         u8         reserved_3[0x20];
3370
3371         u8         rx_atomic_requests[0x20];
3372
3373         u8         reserved_4[0x20];
3374
3375         u8         rx_dct_connect[0x20];
3376
3377         u8         reserved_5[0x20];
3378
3379         u8         out_of_buffer[0x20];
3380
3381         u8         reserved_6[0x20];
3382
3383         u8         out_of_sequence[0x20];
3384
3385         u8         reserved_7[0x620];
3386 };
3387
3388 struct mlx5_ifc_query_q_counter_in_bits {
3389         u8         opcode[0x10];
3390         u8         reserved_0[0x10];
3391
3392         u8         reserved_1[0x10];
3393         u8         op_mod[0x10];
3394
3395         u8         reserved_2[0x80];
3396
3397         u8         clear[0x1];
3398         u8         reserved_3[0x1f];
3399
3400         u8         reserved_4[0x18];
3401         u8         counter_set_id[0x8];
3402 };
3403
3404 struct mlx5_ifc_query_pages_out_bits {
3405         u8         status[0x8];
3406         u8         reserved_0[0x18];
3407
3408         u8         syndrome[0x20];
3409
3410         u8         reserved_1[0x10];
3411         u8         function_id[0x10];
3412
3413         u8         num_pages[0x20];
3414 };
3415
3416 enum {
3417         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3418         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3419         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3420 };
3421
3422 struct mlx5_ifc_query_pages_in_bits {
3423         u8         opcode[0x10];
3424         u8         reserved_0[0x10];
3425
3426         u8         reserved_1[0x10];
3427         u8         op_mod[0x10];
3428
3429         u8         reserved_2[0x10];
3430         u8         function_id[0x10];
3431
3432         u8         reserved_3[0x20];
3433 };
3434
3435 struct mlx5_ifc_query_nic_vport_context_out_bits {
3436         u8         status[0x8];
3437         u8         reserved_0[0x18];
3438
3439         u8         syndrome[0x20];
3440
3441         u8         reserved_1[0x40];
3442
3443         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3444 };
3445
3446 struct mlx5_ifc_query_nic_vport_context_in_bits {
3447         u8         opcode[0x10];
3448         u8         reserved_0[0x10];
3449
3450         u8         reserved_1[0x10];
3451         u8         op_mod[0x10];
3452
3453         u8         other_vport[0x1];
3454         u8         reserved_2[0xf];
3455         u8         vport_number[0x10];
3456
3457         u8         reserved_3[0x5];
3458         u8         allowed_list_type[0x3];
3459         u8         reserved_4[0x18];
3460 };
3461
3462 struct mlx5_ifc_query_mkey_out_bits {
3463         u8         status[0x8];
3464         u8         reserved_0[0x18];
3465
3466         u8         syndrome[0x20];
3467
3468         u8         reserved_1[0x40];
3469
3470         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3471
3472         u8         reserved_2[0x600];
3473
3474         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3475
3476         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3477 };
3478
3479 struct mlx5_ifc_query_mkey_in_bits {
3480         u8         opcode[0x10];
3481         u8         reserved_0[0x10];
3482
3483         u8         reserved_1[0x10];
3484         u8         op_mod[0x10];
3485
3486         u8         reserved_2[0x8];
3487         u8         mkey_index[0x18];
3488
3489         u8         pg_access[0x1];
3490         u8         reserved_3[0x1f];
3491 };
3492
3493 struct mlx5_ifc_query_mad_demux_out_bits {
3494         u8         status[0x8];
3495         u8         reserved_0[0x18];
3496
3497         u8         syndrome[0x20];
3498
3499         u8         reserved_1[0x40];
3500
3501         u8         mad_dumux_parameters_block[0x20];
3502 };
3503
3504 struct mlx5_ifc_query_mad_demux_in_bits {
3505         u8         opcode[0x10];
3506         u8         reserved_0[0x10];
3507
3508         u8         reserved_1[0x10];
3509         u8         op_mod[0x10];
3510
3511         u8         reserved_2[0x40];
3512 };
3513
3514 struct mlx5_ifc_query_l2_table_entry_out_bits {
3515         u8         status[0x8];
3516         u8         reserved_0[0x18];
3517
3518         u8         syndrome[0x20];
3519
3520         u8         reserved_1[0xa0];
3521
3522         u8         reserved_2[0x13];
3523         u8         vlan_valid[0x1];
3524         u8         vlan[0xc];
3525
3526         struct mlx5_ifc_mac_address_layout_bits mac_address;
3527
3528         u8         reserved_3[0xc0];
3529 };
3530
3531 struct mlx5_ifc_query_l2_table_entry_in_bits {
3532         u8         opcode[0x10];
3533         u8         reserved_0[0x10];
3534
3535         u8         reserved_1[0x10];
3536         u8         op_mod[0x10];
3537
3538         u8         reserved_2[0x60];
3539
3540         u8         reserved_3[0x8];
3541         u8         table_index[0x18];
3542
3543         u8         reserved_4[0x140];
3544 };
3545
3546 struct mlx5_ifc_query_issi_out_bits {
3547         u8         status[0x8];
3548         u8         reserved_0[0x18];
3549
3550         u8         syndrome[0x20];
3551
3552         u8         reserved_1[0x10];
3553         u8         current_issi[0x10];
3554
3555         u8         reserved_2[0xa0];
3556
3557         u8         supported_issi_reserved[76][0x8];
3558         u8         supported_issi_dw0[0x20];
3559 };
3560
3561 struct mlx5_ifc_query_issi_in_bits {
3562         u8         opcode[0x10];
3563         u8         reserved_0[0x10];
3564
3565         u8         reserved_1[0x10];
3566         u8         op_mod[0x10];
3567
3568         u8         reserved_2[0x40];
3569 };
3570
3571 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3572         u8         status[0x8];
3573         u8         reserved_0[0x18];
3574
3575         u8         syndrome[0x20];
3576
3577         u8         reserved_1[0x40];
3578
3579         struct mlx5_ifc_pkey_bits pkey[0];
3580 };
3581
3582 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3583         u8         opcode[0x10];
3584         u8         reserved_0[0x10];
3585
3586         u8         reserved_1[0x10];
3587         u8         op_mod[0x10];
3588
3589         u8         other_vport[0x1];
3590         u8         reserved_2[0xb];
3591         u8         port_num[0x4];
3592         u8         vport_number[0x10];
3593
3594         u8         reserved_3[0x10];
3595         u8         pkey_index[0x10];
3596 };
3597
3598 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3599         u8         status[0x8];
3600         u8         reserved_0[0x18];
3601
3602         u8         syndrome[0x20];
3603
3604         u8         reserved_1[0x20];
3605
3606         u8         gids_num[0x10];
3607         u8         reserved_2[0x10];
3608
3609         struct mlx5_ifc_array128_auto_bits gid[0];
3610 };
3611
3612 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3613         u8         opcode[0x10];
3614         u8         reserved_0[0x10];
3615
3616         u8         reserved_1[0x10];
3617         u8         op_mod[0x10];
3618
3619         u8         other_vport[0x1];
3620         u8         reserved_2[0xb];
3621         u8         port_num[0x4];
3622         u8         vport_number[0x10];
3623
3624         u8         reserved_3[0x10];
3625         u8         gid_index[0x10];
3626 };
3627
3628 struct mlx5_ifc_query_hca_vport_context_out_bits {
3629         u8         status[0x8];
3630         u8         reserved_0[0x18];
3631
3632         u8         syndrome[0x20];
3633
3634         u8         reserved_1[0x40];
3635
3636         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3637 };
3638
3639 struct mlx5_ifc_query_hca_vport_context_in_bits {
3640         u8         opcode[0x10];
3641         u8         reserved_0[0x10];
3642
3643         u8         reserved_1[0x10];
3644         u8         op_mod[0x10];
3645
3646         u8         other_vport[0x1];
3647         u8         reserved_2[0xb];
3648         u8         port_num[0x4];
3649         u8         vport_number[0x10];
3650
3651         u8         reserved_3[0x20];
3652 };
3653
3654 struct mlx5_ifc_query_hca_cap_out_bits {
3655         u8         status[0x8];
3656         u8         reserved_0[0x18];
3657
3658         u8         syndrome[0x20];
3659
3660         u8         reserved_1[0x40];
3661
3662         union mlx5_ifc_hca_cap_union_bits capability;
3663 };
3664
3665 struct mlx5_ifc_query_hca_cap_in_bits {
3666         u8         opcode[0x10];
3667         u8         reserved_0[0x10];
3668
3669         u8         reserved_1[0x10];
3670         u8         op_mod[0x10];
3671
3672         u8         reserved_2[0x40];
3673 };
3674
3675 struct mlx5_ifc_query_flow_table_out_bits {
3676         u8         status[0x8];
3677         u8         reserved_0[0x18];
3678
3679         u8         syndrome[0x20];
3680
3681         u8         reserved_1[0x80];
3682
3683         u8         reserved_2[0x8];
3684         u8         level[0x8];
3685         u8         reserved_3[0x8];
3686         u8         log_size[0x8];
3687
3688         u8         reserved_4[0x120];
3689 };
3690
3691 struct mlx5_ifc_query_flow_table_in_bits {
3692         u8         opcode[0x10];
3693         u8         reserved_0[0x10];
3694
3695         u8         reserved_1[0x10];
3696         u8         op_mod[0x10];
3697
3698         u8         reserved_2[0x40];
3699
3700         u8         table_type[0x8];
3701         u8         reserved_3[0x18];
3702
3703         u8         reserved_4[0x8];
3704         u8         table_id[0x18];
3705
3706         u8         reserved_5[0x140];
3707 };
3708
3709 struct mlx5_ifc_query_fte_out_bits {
3710         u8         status[0x8];
3711         u8         reserved_0[0x18];
3712
3713         u8         syndrome[0x20];
3714
3715         u8         reserved_1[0x1c0];
3716
3717         struct mlx5_ifc_flow_context_bits flow_context;
3718 };
3719
3720 struct mlx5_ifc_query_fte_in_bits {
3721         u8         opcode[0x10];
3722         u8         reserved_0[0x10];
3723
3724         u8         reserved_1[0x10];
3725         u8         op_mod[0x10];
3726
3727         u8         reserved_2[0x40];
3728
3729         u8         table_type[0x8];
3730         u8         reserved_3[0x18];
3731
3732         u8         reserved_4[0x8];
3733         u8         table_id[0x18];
3734
3735         u8         reserved_5[0x40];
3736
3737         u8         flow_index[0x20];
3738
3739         u8         reserved_6[0xe0];
3740 };
3741
3742 enum {
3743         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3744         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3745         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3746 };
3747
3748 struct mlx5_ifc_query_flow_group_out_bits {
3749         u8         status[0x8];
3750         u8         reserved_0[0x18];
3751
3752         u8         syndrome[0x20];
3753
3754         u8         reserved_1[0xa0];
3755
3756         u8         start_flow_index[0x20];
3757
3758         u8         reserved_2[0x20];
3759
3760         u8         end_flow_index[0x20];
3761
3762         u8         reserved_3[0xa0];
3763
3764         u8         reserved_4[0x18];
3765         u8         match_criteria_enable[0x8];
3766
3767         struct mlx5_ifc_fte_match_param_bits match_criteria;
3768
3769         u8         reserved_5[0xe00];
3770 };
3771
3772 struct mlx5_ifc_query_flow_group_in_bits {
3773         u8         opcode[0x10];
3774         u8         reserved_0[0x10];
3775
3776         u8         reserved_1[0x10];
3777         u8         op_mod[0x10];
3778
3779         u8         reserved_2[0x40];
3780
3781         u8         table_type[0x8];
3782         u8         reserved_3[0x18];
3783
3784         u8         reserved_4[0x8];
3785         u8         table_id[0x18];
3786
3787         u8         group_id[0x20];
3788
3789         u8         reserved_5[0x120];
3790 };
3791
3792 struct mlx5_ifc_query_esw_vport_context_out_bits {
3793         u8         status[0x8];
3794         u8         reserved_0[0x18];
3795
3796         u8         syndrome[0x20];
3797
3798         u8         reserved_1[0x40];
3799
3800         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3801 };
3802
3803 struct mlx5_ifc_query_esw_vport_context_in_bits {
3804         u8         opcode[0x10];
3805         u8         reserved_0[0x10];
3806
3807         u8         reserved_1[0x10];
3808         u8         op_mod[0x10];
3809
3810         u8         other_vport[0x1];
3811         u8         reserved_2[0xf];
3812         u8         vport_number[0x10];
3813
3814         u8         reserved_3[0x20];
3815 };
3816
3817 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3818         u8         status[0x8];
3819         u8         reserved_0[0x18];
3820
3821         u8         syndrome[0x20];
3822
3823         u8         reserved_1[0x40];
3824 };
3825
3826 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3827         u8         reserved[0x1c];
3828         u8         vport_cvlan_insert[0x1];
3829         u8         vport_svlan_insert[0x1];
3830         u8         vport_cvlan_strip[0x1];
3831         u8         vport_svlan_strip[0x1];
3832 };
3833
3834 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3835         u8         opcode[0x10];
3836         u8         reserved_0[0x10];
3837
3838         u8         reserved_1[0x10];
3839         u8         op_mod[0x10];
3840
3841         u8         other_vport[0x1];
3842         u8         reserved_2[0xf];
3843         u8         vport_number[0x10];
3844
3845         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3846
3847         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3848 };
3849
3850 struct mlx5_ifc_query_eq_out_bits {
3851         u8         status[0x8];
3852         u8         reserved_0[0x18];
3853
3854         u8         syndrome[0x20];
3855
3856         u8         reserved_1[0x40];
3857
3858         struct mlx5_ifc_eqc_bits eq_context_entry;
3859
3860         u8         reserved_2[0x40];
3861
3862         u8         event_bitmask[0x40];
3863
3864         u8         reserved_3[0x580];
3865
3866         u8         pas[0][0x40];
3867 };
3868
3869 struct mlx5_ifc_query_eq_in_bits {
3870         u8         opcode[0x10];
3871         u8         reserved_0[0x10];
3872
3873         u8         reserved_1[0x10];
3874         u8         op_mod[0x10];
3875
3876         u8         reserved_2[0x18];
3877         u8         eq_number[0x8];
3878
3879         u8         reserved_3[0x20];
3880 };
3881
3882 struct mlx5_ifc_query_dct_out_bits {
3883         u8         status[0x8];
3884         u8         reserved_0[0x18];
3885
3886         u8         syndrome[0x20];
3887
3888         u8         reserved_1[0x40];
3889
3890         struct mlx5_ifc_dctc_bits dct_context_entry;
3891
3892         u8         reserved_2[0x180];
3893 };
3894
3895 struct mlx5_ifc_query_dct_in_bits {
3896         u8         opcode[0x10];
3897         u8         reserved_0[0x10];
3898
3899         u8         reserved_1[0x10];
3900         u8         op_mod[0x10];
3901
3902         u8         reserved_2[0x8];
3903         u8         dctn[0x18];
3904
3905         u8         reserved_3[0x20];
3906 };
3907
3908 struct mlx5_ifc_query_cq_out_bits {
3909         u8         status[0x8];
3910         u8         reserved_0[0x18];
3911
3912         u8         syndrome[0x20];
3913
3914         u8         reserved_1[0x40];
3915
3916         struct mlx5_ifc_cqc_bits cq_context;
3917
3918         u8         reserved_2[0x600];
3919
3920         u8         pas[0][0x40];
3921 };
3922
3923 struct mlx5_ifc_query_cq_in_bits {
3924         u8         opcode[0x10];
3925         u8         reserved_0[0x10];
3926
3927         u8         reserved_1[0x10];
3928         u8         op_mod[0x10];
3929
3930         u8         reserved_2[0x8];
3931         u8         cqn[0x18];
3932
3933         u8         reserved_3[0x20];
3934 };
3935
3936 struct mlx5_ifc_query_cong_status_out_bits {
3937         u8         status[0x8];
3938         u8         reserved_0[0x18];
3939
3940         u8         syndrome[0x20];
3941
3942         u8         reserved_1[0x20];
3943
3944         u8         enable[0x1];
3945         u8         tag_enable[0x1];
3946         u8         reserved_2[0x1e];
3947 };
3948
3949 struct mlx5_ifc_query_cong_status_in_bits {
3950         u8         opcode[0x10];
3951         u8         reserved_0[0x10];
3952
3953         u8         reserved_1[0x10];
3954         u8         op_mod[0x10];
3955
3956         u8         reserved_2[0x18];
3957         u8         priority[0x4];
3958         u8         cong_protocol[0x4];
3959
3960         u8         reserved_3[0x20];
3961 };
3962
3963 struct mlx5_ifc_query_cong_statistics_out_bits {
3964         u8         status[0x8];
3965         u8         reserved_0[0x18];
3966
3967         u8         syndrome[0x20];
3968
3969         u8         reserved_1[0x40];
3970
3971         u8         cur_flows[0x20];
3972
3973         u8         sum_flows[0x20];
3974
3975         u8         cnp_ignored_high[0x20];
3976
3977         u8         cnp_ignored_low[0x20];
3978
3979         u8         cnp_handled_high[0x20];
3980
3981         u8         cnp_handled_low[0x20];
3982
3983         u8         reserved_2[0x100];
3984
3985         u8         time_stamp_high[0x20];
3986
3987         u8         time_stamp_low[0x20];
3988
3989         u8         accumulators_period[0x20];
3990
3991         u8         ecn_marked_roce_packets_high[0x20];
3992
3993         u8         ecn_marked_roce_packets_low[0x20];
3994
3995         u8         cnps_sent_high[0x20];
3996
3997         u8         cnps_sent_low[0x20];
3998
3999         u8         reserved_3[0x560];
4000 };
4001
4002 struct mlx5_ifc_query_cong_statistics_in_bits {
4003         u8         opcode[0x10];
4004         u8         reserved_0[0x10];
4005
4006         u8         reserved_1[0x10];
4007         u8         op_mod[0x10];
4008
4009         u8         clear[0x1];
4010         u8         reserved_2[0x1f];
4011
4012         u8         reserved_3[0x20];
4013 };
4014
4015 struct mlx5_ifc_query_cong_params_out_bits {
4016         u8         status[0x8];
4017         u8         reserved_0[0x18];
4018
4019         u8         syndrome[0x20];
4020
4021         u8         reserved_1[0x40];
4022
4023         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4024 };
4025
4026 struct mlx5_ifc_query_cong_params_in_bits {
4027         u8         opcode[0x10];
4028         u8         reserved_0[0x10];
4029
4030         u8         reserved_1[0x10];
4031         u8         op_mod[0x10];
4032
4033         u8         reserved_2[0x1c];
4034         u8         cong_protocol[0x4];
4035
4036         u8         reserved_3[0x20];
4037 };
4038
4039 struct mlx5_ifc_query_adapter_out_bits {
4040         u8         status[0x8];
4041         u8         reserved_0[0x18];
4042
4043         u8         syndrome[0x20];
4044
4045         u8         reserved_1[0x40];
4046
4047         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4048 };
4049
4050 struct mlx5_ifc_query_adapter_in_bits {
4051         u8         opcode[0x10];
4052         u8         reserved_0[0x10];
4053
4054         u8         reserved_1[0x10];
4055         u8         op_mod[0x10];
4056
4057         u8         reserved_2[0x40];
4058 };
4059
4060 struct mlx5_ifc_qp_2rst_out_bits {
4061         u8         status[0x8];
4062         u8         reserved_0[0x18];
4063
4064         u8         syndrome[0x20];
4065
4066         u8         reserved_1[0x40];
4067 };
4068
4069 struct mlx5_ifc_qp_2rst_in_bits {
4070         u8         opcode[0x10];
4071         u8         reserved_0[0x10];
4072
4073         u8         reserved_1[0x10];
4074         u8         op_mod[0x10];
4075
4076         u8         reserved_2[0x8];
4077         u8         qpn[0x18];
4078
4079         u8         reserved_3[0x20];
4080 };
4081
4082 struct mlx5_ifc_qp_2err_out_bits {
4083         u8         status[0x8];
4084         u8         reserved_0[0x18];
4085
4086         u8         syndrome[0x20];
4087
4088         u8         reserved_1[0x40];
4089 };
4090
4091 struct mlx5_ifc_qp_2err_in_bits {
4092         u8         opcode[0x10];
4093         u8         reserved_0[0x10];
4094
4095         u8         reserved_1[0x10];
4096         u8         op_mod[0x10];
4097
4098         u8         reserved_2[0x8];
4099         u8         qpn[0x18];
4100
4101         u8         reserved_3[0x20];
4102 };
4103
4104 struct mlx5_ifc_page_fault_resume_out_bits {
4105         u8         status[0x8];
4106         u8         reserved_0[0x18];
4107
4108         u8         syndrome[0x20];
4109
4110         u8         reserved_1[0x40];
4111 };
4112
4113 struct mlx5_ifc_page_fault_resume_in_bits {
4114         u8         opcode[0x10];
4115         u8         reserved_0[0x10];
4116
4117         u8         reserved_1[0x10];
4118         u8         op_mod[0x10];
4119
4120         u8         error[0x1];
4121         u8         reserved_2[0x4];
4122         u8         rdma[0x1];
4123         u8         read_write[0x1];
4124         u8         req_res[0x1];
4125         u8         qpn[0x18];
4126
4127         u8         reserved_3[0x20];
4128 };
4129
4130 struct mlx5_ifc_nop_out_bits {
4131         u8         status[0x8];
4132         u8         reserved_0[0x18];
4133
4134         u8         syndrome[0x20];
4135
4136         u8         reserved_1[0x40];
4137 };
4138
4139 struct mlx5_ifc_nop_in_bits {
4140         u8         opcode[0x10];
4141         u8         reserved_0[0x10];
4142
4143         u8         reserved_1[0x10];
4144         u8         op_mod[0x10];
4145
4146         u8         reserved_2[0x40];
4147 };
4148
4149 struct mlx5_ifc_modify_vport_state_out_bits {
4150         u8         status[0x8];
4151         u8         reserved_0[0x18];
4152
4153         u8         syndrome[0x20];
4154
4155         u8         reserved_1[0x40];
4156 };
4157
4158 struct mlx5_ifc_modify_vport_state_in_bits {
4159         u8         opcode[0x10];
4160         u8         reserved_0[0x10];
4161
4162         u8         reserved_1[0x10];
4163         u8         op_mod[0x10];
4164
4165         u8         other_vport[0x1];
4166         u8         reserved_2[0xf];
4167         u8         vport_number[0x10];
4168
4169         u8         reserved_3[0x18];
4170         u8         admin_state[0x4];
4171         u8         reserved_4[0x4];
4172 };
4173
4174 struct mlx5_ifc_modify_tis_out_bits {
4175         u8         status[0x8];
4176         u8         reserved_0[0x18];
4177
4178         u8         syndrome[0x20];
4179
4180         u8         reserved_1[0x40];
4181 };
4182
4183 struct mlx5_ifc_modify_tis_in_bits {
4184         u8         opcode[0x10];
4185         u8         reserved_0[0x10];
4186
4187         u8         reserved_1[0x10];
4188         u8         op_mod[0x10];
4189
4190         u8         reserved_2[0x8];
4191         u8         tisn[0x18];
4192
4193         u8         reserved_3[0x20];
4194
4195         u8         modify_bitmask[0x40];
4196
4197         u8         reserved_4[0x40];
4198
4199         struct mlx5_ifc_tisc_bits ctx;
4200 };
4201
4202 struct mlx5_ifc_modify_tir_bitmask_bits {
4203         u8         reserved_0[0x20];
4204
4205         u8         reserved_1[0x1b];
4206         u8         self_lb_en[0x1];
4207         u8         reserved_2[0x3];
4208         u8         lro[0x1];
4209 };
4210
4211 struct mlx5_ifc_modify_tir_out_bits {
4212         u8         status[0x8];
4213         u8         reserved_0[0x18];
4214
4215         u8         syndrome[0x20];
4216
4217         u8         reserved_1[0x40];
4218 };
4219
4220 struct mlx5_ifc_modify_tir_in_bits {
4221         u8         opcode[0x10];
4222         u8         reserved_0[0x10];
4223
4224         u8         reserved_1[0x10];
4225         u8         op_mod[0x10];
4226
4227         u8         reserved_2[0x8];
4228         u8         tirn[0x18];
4229
4230         u8         reserved_3[0x20];
4231
4232         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4233
4234         u8         reserved_4[0x40];
4235
4236         struct mlx5_ifc_tirc_bits ctx;
4237 };
4238
4239 struct mlx5_ifc_modify_sq_out_bits {
4240         u8         status[0x8];
4241         u8         reserved_0[0x18];
4242
4243         u8         syndrome[0x20];
4244
4245         u8         reserved_1[0x40];
4246 };
4247
4248 struct mlx5_ifc_modify_sq_in_bits {
4249         u8         opcode[0x10];
4250         u8         reserved_0[0x10];
4251
4252         u8         reserved_1[0x10];
4253         u8         op_mod[0x10];
4254
4255         u8         sq_state[0x4];
4256         u8         reserved_2[0x4];
4257         u8         sqn[0x18];
4258
4259         u8         reserved_3[0x20];
4260
4261         u8         modify_bitmask[0x40];
4262
4263         u8         reserved_4[0x40];
4264
4265         struct mlx5_ifc_sqc_bits ctx;
4266 };
4267
4268 struct mlx5_ifc_modify_rqt_out_bits {
4269         u8         status[0x8];
4270         u8         reserved_0[0x18];
4271
4272         u8         syndrome[0x20];
4273
4274         u8         reserved_1[0x40];
4275 };
4276
4277 struct mlx5_ifc_rqt_bitmask_bits {
4278         u8         reserved[0x20];
4279
4280         u8         reserved1[0x1f];
4281         u8         rqn_list[0x1];
4282 };
4283
4284 struct mlx5_ifc_modify_rqt_in_bits {
4285         u8         opcode[0x10];
4286         u8         reserved_0[0x10];
4287
4288         u8         reserved_1[0x10];
4289         u8         op_mod[0x10];
4290
4291         u8         reserved_2[0x8];
4292         u8         rqtn[0x18];
4293
4294         u8         reserved_3[0x20];
4295
4296         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4297
4298         u8         reserved_4[0x40];
4299
4300         struct mlx5_ifc_rqtc_bits ctx;
4301 };
4302
4303 struct mlx5_ifc_modify_rq_out_bits {
4304         u8         status[0x8];
4305         u8         reserved_0[0x18];
4306
4307         u8         syndrome[0x20];
4308
4309         u8         reserved_1[0x40];
4310 };
4311
4312 struct mlx5_ifc_modify_rq_in_bits {
4313         u8         opcode[0x10];
4314         u8         reserved_0[0x10];
4315
4316         u8         reserved_1[0x10];
4317         u8         op_mod[0x10];
4318
4319         u8         rq_state[0x4];
4320         u8         reserved_2[0x4];
4321         u8         rqn[0x18];
4322
4323         u8         reserved_3[0x20];
4324
4325         u8         modify_bitmask[0x40];
4326
4327         u8         reserved_4[0x40];
4328
4329         struct mlx5_ifc_rqc_bits ctx;
4330 };
4331
4332 struct mlx5_ifc_modify_rmp_out_bits {
4333         u8         status[0x8];
4334         u8         reserved_0[0x18];
4335
4336         u8         syndrome[0x20];
4337
4338         u8         reserved_1[0x40];
4339 };
4340
4341 struct mlx5_ifc_rmp_bitmask_bits {
4342         u8         reserved[0x20];
4343
4344         u8         reserved1[0x1f];
4345         u8         lwm[0x1];
4346 };
4347
4348 struct mlx5_ifc_modify_rmp_in_bits {
4349         u8         opcode[0x10];
4350         u8         reserved_0[0x10];
4351
4352         u8         reserved_1[0x10];
4353         u8         op_mod[0x10];
4354
4355         u8         rmp_state[0x4];
4356         u8         reserved_2[0x4];
4357         u8         rmpn[0x18];
4358
4359         u8         reserved_3[0x20];
4360
4361         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4362
4363         u8         reserved_4[0x40];
4364
4365         struct mlx5_ifc_rmpc_bits ctx;
4366 };
4367
4368 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4369         u8         status[0x8];
4370         u8         reserved_0[0x18];
4371
4372         u8         syndrome[0x20];
4373
4374         u8         reserved_1[0x40];
4375 };
4376
4377 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4378         u8         reserved_0[0x19];
4379         u8         mtu[0x1];
4380         u8         change_event[0x1];
4381         u8         promisc[0x1];
4382         u8         permanent_address[0x1];
4383         u8         addresses_list[0x1];
4384         u8         roce_en[0x1];
4385         u8         reserved_1[0x1];
4386 };
4387
4388 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4389         u8         opcode[0x10];
4390         u8         reserved_0[0x10];
4391
4392         u8         reserved_1[0x10];
4393         u8         op_mod[0x10];
4394
4395         u8         other_vport[0x1];
4396         u8         reserved_2[0xf];
4397         u8         vport_number[0x10];
4398
4399         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4400
4401         u8         reserved_3[0x780];
4402
4403         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4404 };
4405
4406 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4407         u8         status[0x8];
4408         u8         reserved_0[0x18];
4409
4410         u8         syndrome[0x20];
4411
4412         u8         reserved_1[0x40];
4413 };
4414
4415 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4416         u8         opcode[0x10];
4417         u8         reserved_0[0x10];
4418
4419         u8         reserved_1[0x10];
4420         u8         op_mod[0x10];
4421
4422         u8         other_vport[0x1];
4423         u8         reserved_2[0xb];
4424         u8         port_num[0x4];
4425         u8         vport_number[0x10];
4426
4427         u8         reserved_3[0x20];
4428
4429         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4430 };
4431
4432 struct mlx5_ifc_modify_cq_out_bits {
4433         u8         status[0x8];
4434         u8         reserved_0[0x18];
4435
4436         u8         syndrome[0x20];
4437
4438         u8         reserved_1[0x40];
4439 };
4440
4441 enum {
4442         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4443         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4444 };
4445
4446 struct mlx5_ifc_modify_cq_in_bits {
4447         u8         opcode[0x10];
4448         u8         reserved_0[0x10];
4449
4450         u8         reserved_1[0x10];
4451         u8         op_mod[0x10];
4452
4453         u8         reserved_2[0x8];
4454         u8         cqn[0x18];
4455
4456         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4457
4458         struct mlx5_ifc_cqc_bits cq_context;
4459
4460         u8         reserved_3[0x600];
4461
4462         u8         pas[0][0x40];
4463 };
4464
4465 struct mlx5_ifc_modify_cong_status_out_bits {
4466         u8         status[0x8];
4467         u8         reserved_0[0x18];
4468
4469         u8         syndrome[0x20];
4470
4471         u8         reserved_1[0x40];
4472 };
4473
4474 struct mlx5_ifc_modify_cong_status_in_bits {
4475         u8         opcode[0x10];
4476         u8         reserved_0[0x10];
4477
4478         u8         reserved_1[0x10];
4479         u8         op_mod[0x10];
4480
4481         u8         reserved_2[0x18];
4482         u8         priority[0x4];
4483         u8         cong_protocol[0x4];
4484
4485         u8         enable[0x1];
4486         u8         tag_enable[0x1];
4487         u8         reserved_3[0x1e];
4488 };
4489
4490 struct mlx5_ifc_modify_cong_params_out_bits {
4491         u8         status[0x8];
4492         u8         reserved_0[0x18];
4493
4494         u8         syndrome[0x20];
4495
4496         u8         reserved_1[0x40];
4497 };
4498
4499 struct mlx5_ifc_modify_cong_params_in_bits {
4500         u8         opcode[0x10];
4501         u8         reserved_0[0x10];
4502
4503         u8         reserved_1[0x10];
4504         u8         op_mod[0x10];
4505
4506         u8         reserved_2[0x1c];
4507         u8         cong_protocol[0x4];
4508
4509         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4510
4511         u8         reserved_3[0x80];
4512
4513         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4514 };
4515
4516 struct mlx5_ifc_manage_pages_out_bits {
4517         u8         status[0x8];
4518         u8         reserved_0[0x18];
4519
4520         u8         syndrome[0x20];
4521
4522         u8         output_num_entries[0x20];
4523
4524         u8         reserved_1[0x20];
4525
4526         u8         pas[0][0x40];
4527 };
4528
4529 enum {
4530         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4531         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4532         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4533 };
4534
4535 struct mlx5_ifc_manage_pages_in_bits {
4536         u8         opcode[0x10];
4537         u8         reserved_0[0x10];
4538
4539         u8         reserved_1[0x10];
4540         u8         op_mod[0x10];
4541
4542         u8         reserved_2[0x10];
4543         u8         function_id[0x10];
4544
4545         u8         input_num_entries[0x20];
4546
4547         u8         pas[0][0x40];
4548 };
4549
4550 struct mlx5_ifc_mad_ifc_out_bits {
4551         u8         status[0x8];
4552         u8         reserved_0[0x18];
4553
4554         u8         syndrome[0x20];
4555
4556         u8         reserved_1[0x40];
4557
4558         u8         response_mad_packet[256][0x8];
4559 };
4560
4561 struct mlx5_ifc_mad_ifc_in_bits {
4562         u8         opcode[0x10];
4563         u8         reserved_0[0x10];
4564
4565         u8         reserved_1[0x10];
4566         u8         op_mod[0x10];
4567
4568         u8         remote_lid[0x10];
4569         u8         reserved_2[0x8];
4570         u8         port[0x8];
4571
4572         u8         reserved_3[0x20];
4573
4574         u8         mad[256][0x8];
4575 };
4576
4577 struct mlx5_ifc_init_hca_out_bits {
4578         u8         status[0x8];
4579         u8         reserved_0[0x18];
4580
4581         u8         syndrome[0x20];
4582
4583         u8         reserved_1[0x40];
4584 };
4585
4586 struct mlx5_ifc_init_hca_in_bits {
4587         u8         opcode[0x10];
4588         u8         reserved_0[0x10];
4589
4590         u8         reserved_1[0x10];
4591         u8         op_mod[0x10];
4592
4593         u8         reserved_2[0x40];
4594 };
4595
4596 struct mlx5_ifc_init2rtr_qp_out_bits {
4597         u8         status[0x8];
4598         u8         reserved_0[0x18];
4599
4600         u8         syndrome[0x20];
4601
4602         u8         reserved_1[0x40];
4603 };
4604
4605 struct mlx5_ifc_init2rtr_qp_in_bits {
4606         u8         opcode[0x10];
4607         u8         reserved_0[0x10];
4608
4609         u8         reserved_1[0x10];
4610         u8         op_mod[0x10];
4611
4612         u8         reserved_2[0x8];
4613         u8         qpn[0x18];
4614
4615         u8         reserved_3[0x20];
4616
4617         u8         opt_param_mask[0x20];
4618
4619         u8         reserved_4[0x20];
4620
4621         struct mlx5_ifc_qpc_bits qpc;
4622
4623         u8         reserved_5[0x80];
4624 };
4625
4626 struct mlx5_ifc_init2init_qp_out_bits {
4627         u8         status[0x8];
4628         u8         reserved_0[0x18];
4629
4630         u8         syndrome[0x20];
4631
4632         u8         reserved_1[0x40];
4633 };
4634
4635 struct mlx5_ifc_init2init_qp_in_bits {
4636         u8         opcode[0x10];
4637         u8         reserved_0[0x10];
4638
4639         u8         reserved_1[0x10];
4640         u8         op_mod[0x10];
4641
4642         u8         reserved_2[0x8];
4643         u8         qpn[0x18];
4644
4645         u8         reserved_3[0x20];
4646
4647         u8         opt_param_mask[0x20];
4648
4649         u8         reserved_4[0x20];
4650
4651         struct mlx5_ifc_qpc_bits qpc;
4652
4653         u8         reserved_5[0x80];
4654 };
4655
4656 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4657         u8         status[0x8];
4658         u8         reserved_0[0x18];
4659
4660         u8         syndrome[0x20];
4661
4662         u8         reserved_1[0x40];
4663
4664         u8         packet_headers_log[128][0x8];
4665
4666         u8         packet_syndrome[64][0x8];
4667 };
4668
4669 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4670         u8         opcode[0x10];
4671         u8         reserved_0[0x10];
4672
4673         u8         reserved_1[0x10];
4674         u8         op_mod[0x10];
4675
4676         u8         reserved_2[0x40];
4677 };
4678
4679 struct mlx5_ifc_gen_eqe_in_bits {
4680         u8         opcode[0x10];
4681         u8         reserved_0[0x10];
4682
4683         u8         reserved_1[0x10];
4684         u8         op_mod[0x10];
4685
4686         u8         reserved_2[0x18];
4687         u8         eq_number[0x8];
4688
4689         u8         reserved_3[0x20];
4690
4691         u8         eqe[64][0x8];
4692 };
4693
4694 struct mlx5_ifc_gen_eq_out_bits {
4695         u8         status[0x8];
4696         u8         reserved_0[0x18];
4697
4698         u8         syndrome[0x20];
4699
4700         u8         reserved_1[0x40];
4701 };
4702
4703 struct mlx5_ifc_enable_hca_out_bits {
4704         u8         status[0x8];
4705         u8         reserved_0[0x18];
4706
4707         u8         syndrome[0x20];
4708
4709         u8         reserved_1[0x20];
4710 };
4711
4712 struct mlx5_ifc_enable_hca_in_bits {
4713         u8         opcode[0x10];
4714         u8         reserved_0[0x10];
4715
4716         u8         reserved_1[0x10];
4717         u8         op_mod[0x10];
4718
4719         u8         reserved_2[0x10];
4720         u8         function_id[0x10];
4721
4722         u8         reserved_3[0x20];
4723 };
4724
4725 struct mlx5_ifc_drain_dct_out_bits {
4726         u8         status[0x8];
4727         u8         reserved_0[0x18];
4728
4729         u8         syndrome[0x20];
4730
4731         u8         reserved_1[0x40];
4732 };
4733
4734 struct mlx5_ifc_drain_dct_in_bits {
4735         u8         opcode[0x10];
4736         u8         reserved_0[0x10];
4737
4738         u8         reserved_1[0x10];
4739         u8         op_mod[0x10];
4740
4741         u8         reserved_2[0x8];
4742         u8         dctn[0x18];
4743
4744         u8         reserved_3[0x20];
4745 };
4746
4747 struct mlx5_ifc_disable_hca_out_bits {
4748         u8         status[0x8];
4749         u8         reserved_0[0x18];
4750
4751         u8         syndrome[0x20];
4752
4753         u8         reserved_1[0x20];
4754 };
4755
4756 struct mlx5_ifc_disable_hca_in_bits {
4757         u8         opcode[0x10];
4758         u8         reserved_0[0x10];
4759
4760         u8         reserved_1[0x10];
4761         u8         op_mod[0x10];
4762
4763         u8         reserved_2[0x10];
4764         u8         function_id[0x10];
4765
4766         u8         reserved_3[0x20];
4767 };
4768
4769 struct mlx5_ifc_detach_from_mcg_out_bits {
4770         u8         status[0x8];
4771         u8         reserved_0[0x18];
4772
4773         u8         syndrome[0x20];
4774
4775         u8         reserved_1[0x40];
4776 };
4777
4778 struct mlx5_ifc_detach_from_mcg_in_bits {
4779         u8         opcode[0x10];
4780         u8         reserved_0[0x10];
4781
4782         u8         reserved_1[0x10];
4783         u8         op_mod[0x10];
4784
4785         u8         reserved_2[0x8];
4786         u8         qpn[0x18];
4787
4788         u8         reserved_3[0x20];
4789
4790         u8         multicast_gid[16][0x8];
4791 };
4792
4793 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4794         u8         status[0x8];
4795         u8         reserved_0[0x18];
4796
4797         u8         syndrome[0x20];
4798
4799         u8         reserved_1[0x40];
4800 };
4801
4802 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4803         u8         opcode[0x10];
4804         u8         reserved_0[0x10];
4805
4806         u8         reserved_1[0x10];
4807         u8         op_mod[0x10];
4808
4809         u8         reserved_2[0x8];
4810         u8         xrc_srqn[0x18];
4811
4812         u8         reserved_3[0x20];
4813 };
4814
4815 struct mlx5_ifc_destroy_tis_out_bits {
4816         u8         status[0x8];
4817         u8         reserved_0[0x18];
4818
4819         u8         syndrome[0x20];
4820
4821         u8         reserved_1[0x40];
4822 };
4823
4824 struct mlx5_ifc_destroy_tis_in_bits {
4825         u8         opcode[0x10];
4826         u8         reserved_0[0x10];
4827
4828         u8         reserved_1[0x10];
4829         u8         op_mod[0x10];
4830
4831         u8         reserved_2[0x8];
4832         u8         tisn[0x18];
4833
4834         u8         reserved_3[0x20];
4835 };
4836
4837 struct mlx5_ifc_destroy_tir_out_bits {
4838         u8         status[0x8];
4839         u8         reserved_0[0x18];
4840
4841         u8         syndrome[0x20];
4842
4843         u8         reserved_1[0x40];
4844 };
4845
4846 struct mlx5_ifc_destroy_tir_in_bits {
4847         u8         opcode[0x10];
4848         u8         reserved_0[0x10];
4849
4850         u8         reserved_1[0x10];
4851         u8         op_mod[0x10];
4852
4853         u8         reserved_2[0x8];
4854         u8         tirn[0x18];
4855
4856         u8         reserved_3[0x20];
4857 };
4858
4859 struct mlx5_ifc_destroy_srq_out_bits {
4860         u8         status[0x8];
4861         u8         reserved_0[0x18];
4862
4863         u8         syndrome[0x20];
4864
4865         u8         reserved_1[0x40];
4866 };
4867
4868 struct mlx5_ifc_destroy_srq_in_bits {
4869         u8         opcode[0x10];
4870         u8         reserved_0[0x10];
4871
4872         u8         reserved_1[0x10];
4873         u8         op_mod[0x10];
4874
4875         u8         reserved_2[0x8];
4876         u8         srqn[0x18];
4877
4878         u8         reserved_3[0x20];
4879 };
4880
4881 struct mlx5_ifc_destroy_sq_out_bits {
4882         u8         status[0x8];
4883         u8         reserved_0[0x18];
4884
4885         u8         syndrome[0x20];
4886
4887         u8         reserved_1[0x40];
4888 };
4889
4890 struct mlx5_ifc_destroy_sq_in_bits {
4891         u8         opcode[0x10];
4892         u8         reserved_0[0x10];
4893
4894         u8         reserved_1[0x10];
4895         u8         op_mod[0x10];
4896
4897         u8         reserved_2[0x8];
4898         u8         sqn[0x18];
4899
4900         u8         reserved_3[0x20];
4901 };
4902
4903 struct mlx5_ifc_destroy_rqt_out_bits {
4904         u8         status[0x8];
4905         u8         reserved_0[0x18];
4906
4907         u8         syndrome[0x20];
4908
4909         u8         reserved_1[0x40];
4910 };
4911
4912 struct mlx5_ifc_destroy_rqt_in_bits {
4913         u8         opcode[0x10];
4914         u8         reserved_0[0x10];
4915
4916         u8         reserved_1[0x10];
4917         u8         op_mod[0x10];
4918
4919         u8         reserved_2[0x8];
4920         u8         rqtn[0x18];
4921
4922         u8         reserved_3[0x20];
4923 };
4924
4925 struct mlx5_ifc_destroy_rq_out_bits {
4926         u8         status[0x8];
4927         u8         reserved_0[0x18];
4928
4929         u8         syndrome[0x20];
4930
4931         u8         reserved_1[0x40];
4932 };
4933
4934 struct mlx5_ifc_destroy_rq_in_bits {
4935         u8         opcode[0x10];
4936         u8         reserved_0[0x10];
4937
4938         u8         reserved_1[0x10];
4939         u8         op_mod[0x10];
4940
4941         u8         reserved_2[0x8];
4942         u8         rqn[0x18];
4943
4944         u8         reserved_3[0x20];
4945 };
4946
4947 struct mlx5_ifc_destroy_rmp_out_bits {
4948         u8         status[0x8];
4949         u8         reserved_0[0x18];
4950
4951         u8         syndrome[0x20];
4952
4953         u8         reserved_1[0x40];
4954 };
4955
4956 struct mlx5_ifc_destroy_rmp_in_bits {
4957         u8         opcode[0x10];
4958         u8         reserved_0[0x10];
4959
4960         u8         reserved_1[0x10];
4961         u8         op_mod[0x10];
4962
4963         u8         reserved_2[0x8];
4964         u8         rmpn[0x18];
4965
4966         u8         reserved_3[0x20];
4967 };
4968
4969 struct mlx5_ifc_destroy_qp_out_bits {
4970         u8         status[0x8];
4971         u8         reserved_0[0x18];
4972
4973         u8         syndrome[0x20];
4974
4975         u8         reserved_1[0x40];
4976 };
4977
4978 struct mlx5_ifc_destroy_qp_in_bits {
4979         u8         opcode[0x10];
4980         u8         reserved_0[0x10];
4981
4982         u8         reserved_1[0x10];
4983         u8         op_mod[0x10];
4984
4985         u8         reserved_2[0x8];
4986         u8         qpn[0x18];
4987
4988         u8         reserved_3[0x20];
4989 };
4990
4991 struct mlx5_ifc_destroy_psv_out_bits {
4992         u8         status[0x8];
4993         u8         reserved_0[0x18];
4994
4995         u8         syndrome[0x20];
4996
4997         u8         reserved_1[0x40];
4998 };
4999
5000 struct mlx5_ifc_destroy_psv_in_bits {
5001         u8         opcode[0x10];
5002         u8         reserved_0[0x10];
5003
5004         u8         reserved_1[0x10];
5005         u8         op_mod[0x10];
5006
5007         u8         reserved_2[0x8];
5008         u8         psvn[0x18];
5009
5010         u8         reserved_3[0x20];
5011 };
5012
5013 struct mlx5_ifc_destroy_mkey_out_bits {
5014         u8         status[0x8];
5015         u8         reserved_0[0x18];
5016
5017         u8         syndrome[0x20];
5018
5019         u8         reserved_1[0x40];
5020 };
5021
5022 struct mlx5_ifc_destroy_mkey_in_bits {
5023         u8         opcode[0x10];
5024         u8         reserved_0[0x10];
5025
5026         u8         reserved_1[0x10];
5027         u8         op_mod[0x10];
5028
5029         u8         reserved_2[0x8];
5030         u8         mkey_index[0x18];
5031
5032         u8         reserved_3[0x20];
5033 };
5034
5035 struct mlx5_ifc_destroy_flow_table_out_bits {
5036         u8         status[0x8];
5037         u8         reserved_0[0x18];
5038
5039         u8         syndrome[0x20];
5040
5041         u8         reserved_1[0x40];
5042 };
5043
5044 struct mlx5_ifc_destroy_flow_table_in_bits {
5045         u8         opcode[0x10];
5046         u8         reserved_0[0x10];
5047
5048         u8         reserved_1[0x10];
5049         u8         op_mod[0x10];
5050
5051         u8         reserved_2[0x40];
5052
5053         u8         table_type[0x8];
5054         u8         reserved_3[0x18];
5055
5056         u8         reserved_4[0x8];
5057         u8         table_id[0x18];
5058
5059         u8         reserved_5[0x140];
5060 };
5061
5062 struct mlx5_ifc_destroy_flow_group_out_bits {
5063         u8         status[0x8];
5064         u8         reserved_0[0x18];
5065
5066         u8         syndrome[0x20];
5067
5068         u8         reserved_1[0x40];
5069 };
5070
5071 struct mlx5_ifc_destroy_flow_group_in_bits {
5072         u8         opcode[0x10];
5073         u8         reserved_0[0x10];
5074
5075         u8         reserved_1[0x10];
5076         u8         op_mod[0x10];
5077
5078         u8         reserved_2[0x40];
5079
5080         u8         table_type[0x8];
5081         u8         reserved_3[0x18];
5082
5083         u8         reserved_4[0x8];
5084         u8         table_id[0x18];
5085
5086         u8         group_id[0x20];
5087
5088         u8         reserved_5[0x120];
5089 };
5090
5091 struct mlx5_ifc_destroy_eq_out_bits {
5092         u8         status[0x8];
5093         u8         reserved_0[0x18];
5094
5095         u8         syndrome[0x20];
5096
5097         u8         reserved_1[0x40];
5098 };
5099
5100 struct mlx5_ifc_destroy_eq_in_bits {
5101         u8         opcode[0x10];
5102         u8         reserved_0[0x10];
5103
5104         u8         reserved_1[0x10];
5105         u8         op_mod[0x10];
5106
5107         u8         reserved_2[0x18];
5108         u8         eq_number[0x8];
5109
5110         u8         reserved_3[0x20];
5111 };
5112
5113 struct mlx5_ifc_destroy_dct_out_bits {
5114         u8         status[0x8];
5115         u8         reserved_0[0x18];
5116
5117         u8         syndrome[0x20];
5118
5119         u8         reserved_1[0x40];
5120 };
5121
5122 struct mlx5_ifc_destroy_dct_in_bits {
5123         u8         opcode[0x10];
5124         u8         reserved_0[0x10];
5125
5126         u8         reserved_1[0x10];
5127         u8         op_mod[0x10];
5128
5129         u8         reserved_2[0x8];
5130         u8         dctn[0x18];
5131
5132         u8         reserved_3[0x20];
5133 };
5134
5135 struct mlx5_ifc_destroy_cq_out_bits {
5136         u8         status[0x8];
5137         u8         reserved_0[0x18];
5138
5139         u8         syndrome[0x20];
5140
5141         u8         reserved_1[0x40];
5142 };
5143
5144 struct mlx5_ifc_destroy_cq_in_bits {
5145         u8         opcode[0x10];
5146         u8         reserved_0[0x10];
5147
5148         u8         reserved_1[0x10];
5149         u8         op_mod[0x10];
5150
5151         u8         reserved_2[0x8];
5152         u8         cqn[0x18];
5153
5154         u8         reserved_3[0x20];
5155 };
5156
5157 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5158         u8         status[0x8];
5159         u8         reserved_0[0x18];
5160
5161         u8         syndrome[0x20];
5162
5163         u8         reserved_1[0x40];
5164 };
5165
5166 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5167         u8         opcode[0x10];
5168         u8         reserved_0[0x10];
5169
5170         u8         reserved_1[0x10];
5171         u8         op_mod[0x10];
5172
5173         u8         reserved_2[0x20];
5174
5175         u8         reserved_3[0x10];
5176         u8         vxlan_udp_port[0x10];
5177 };
5178
5179 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5180         u8         status[0x8];
5181         u8         reserved_0[0x18];
5182
5183         u8         syndrome[0x20];
5184
5185         u8         reserved_1[0x40];
5186 };
5187
5188 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5189         u8         opcode[0x10];
5190         u8         reserved_0[0x10];
5191
5192         u8         reserved_1[0x10];
5193         u8         op_mod[0x10];
5194
5195         u8         reserved_2[0x60];
5196
5197         u8         reserved_3[0x8];
5198         u8         table_index[0x18];
5199
5200         u8         reserved_4[0x140];
5201 };
5202
5203 struct mlx5_ifc_delete_fte_out_bits {
5204         u8         status[0x8];
5205         u8         reserved_0[0x18];
5206
5207         u8         syndrome[0x20];
5208
5209         u8         reserved_1[0x40];
5210 };
5211
5212 struct mlx5_ifc_delete_fte_in_bits {
5213         u8         opcode[0x10];
5214         u8         reserved_0[0x10];
5215
5216         u8         reserved_1[0x10];
5217         u8         op_mod[0x10];
5218
5219         u8         reserved_2[0x40];
5220
5221         u8         table_type[0x8];
5222         u8         reserved_3[0x18];
5223
5224         u8         reserved_4[0x8];
5225         u8         table_id[0x18];
5226
5227         u8         reserved_5[0x40];
5228
5229         u8         flow_index[0x20];
5230
5231         u8         reserved_6[0xe0];
5232 };
5233
5234 struct mlx5_ifc_dealloc_xrcd_out_bits {
5235         u8         status[0x8];
5236         u8         reserved_0[0x18];
5237
5238         u8         syndrome[0x20];
5239
5240         u8         reserved_1[0x40];
5241 };
5242
5243 struct mlx5_ifc_dealloc_xrcd_in_bits {
5244         u8         opcode[0x10];
5245         u8         reserved_0[0x10];
5246
5247         u8         reserved_1[0x10];
5248         u8         op_mod[0x10];
5249
5250         u8         reserved_2[0x8];
5251         u8         xrcd[0x18];
5252
5253         u8         reserved_3[0x20];
5254 };
5255
5256 struct mlx5_ifc_dealloc_uar_out_bits {
5257         u8         status[0x8];
5258         u8         reserved_0[0x18];
5259
5260         u8         syndrome[0x20];
5261
5262         u8         reserved_1[0x40];
5263 };
5264
5265 struct mlx5_ifc_dealloc_uar_in_bits {
5266         u8         opcode[0x10];
5267         u8         reserved_0[0x10];
5268
5269         u8         reserved_1[0x10];
5270         u8         op_mod[0x10];
5271
5272         u8         reserved_2[0x8];
5273         u8         uar[0x18];
5274
5275         u8         reserved_3[0x20];
5276 };
5277
5278 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5279         u8         status[0x8];
5280         u8         reserved_0[0x18];
5281
5282         u8         syndrome[0x20];
5283
5284         u8         reserved_1[0x40];
5285 };
5286
5287 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5288         u8         opcode[0x10];
5289         u8         reserved_0[0x10];
5290
5291         u8         reserved_1[0x10];
5292         u8         op_mod[0x10];
5293
5294         u8         reserved_2[0x8];
5295         u8         transport_domain[0x18];
5296
5297         u8         reserved_3[0x20];
5298 };
5299
5300 struct mlx5_ifc_dealloc_q_counter_out_bits {
5301         u8         status[0x8];
5302         u8         reserved_0[0x18];
5303
5304         u8         syndrome[0x20];
5305
5306         u8         reserved_1[0x40];
5307 };
5308
5309 struct mlx5_ifc_dealloc_q_counter_in_bits {
5310         u8         opcode[0x10];
5311         u8         reserved_0[0x10];
5312
5313         u8         reserved_1[0x10];
5314         u8         op_mod[0x10];
5315
5316         u8         reserved_2[0x18];
5317         u8         counter_set_id[0x8];
5318
5319         u8         reserved_3[0x20];
5320 };
5321
5322 struct mlx5_ifc_dealloc_pd_out_bits {
5323         u8         status[0x8];
5324         u8         reserved_0[0x18];
5325
5326         u8         syndrome[0x20];
5327
5328         u8         reserved_1[0x40];
5329 };
5330
5331 struct mlx5_ifc_dealloc_pd_in_bits {
5332         u8         opcode[0x10];
5333         u8         reserved_0[0x10];
5334
5335         u8         reserved_1[0x10];
5336         u8         op_mod[0x10];
5337
5338         u8         reserved_2[0x8];
5339         u8         pd[0x18];
5340
5341         u8         reserved_3[0x20];
5342 };
5343
5344 struct mlx5_ifc_create_xrc_srq_out_bits {
5345         u8         status[0x8];
5346         u8         reserved_0[0x18];
5347
5348         u8         syndrome[0x20];
5349
5350         u8         reserved_1[0x8];
5351         u8         xrc_srqn[0x18];
5352
5353         u8         reserved_2[0x20];
5354 };
5355
5356 struct mlx5_ifc_create_xrc_srq_in_bits {
5357         u8         opcode[0x10];
5358         u8         reserved_0[0x10];
5359
5360         u8         reserved_1[0x10];
5361         u8         op_mod[0x10];
5362
5363         u8         reserved_2[0x40];
5364
5365         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5366
5367         u8         reserved_3[0x600];
5368
5369         u8         pas[0][0x40];
5370 };
5371
5372 struct mlx5_ifc_create_tis_out_bits {
5373         u8         status[0x8];
5374         u8         reserved_0[0x18];
5375
5376         u8         syndrome[0x20];
5377
5378         u8         reserved_1[0x8];
5379         u8         tisn[0x18];
5380
5381         u8         reserved_2[0x20];
5382 };
5383
5384 struct mlx5_ifc_create_tis_in_bits {
5385         u8         opcode[0x10];
5386         u8         reserved_0[0x10];
5387
5388         u8         reserved_1[0x10];
5389         u8         op_mod[0x10];
5390
5391         u8         reserved_2[0xc0];
5392
5393         struct mlx5_ifc_tisc_bits ctx;
5394 };
5395
5396 struct mlx5_ifc_create_tir_out_bits {
5397         u8         status[0x8];
5398         u8         reserved_0[0x18];
5399
5400         u8         syndrome[0x20];
5401
5402         u8         reserved_1[0x8];
5403         u8         tirn[0x18];
5404
5405         u8         reserved_2[0x20];
5406 };
5407
5408 struct mlx5_ifc_create_tir_in_bits {
5409         u8         opcode[0x10];
5410         u8         reserved_0[0x10];
5411
5412         u8         reserved_1[0x10];
5413         u8         op_mod[0x10];
5414
5415         u8         reserved_2[0xc0];
5416
5417         struct mlx5_ifc_tirc_bits ctx;
5418 };
5419
5420 struct mlx5_ifc_create_srq_out_bits {
5421         u8         status[0x8];
5422         u8         reserved_0[0x18];
5423
5424         u8         syndrome[0x20];
5425
5426         u8         reserved_1[0x8];
5427         u8         srqn[0x18];
5428
5429         u8         reserved_2[0x20];
5430 };
5431
5432 struct mlx5_ifc_create_srq_in_bits {
5433         u8         opcode[0x10];
5434         u8         reserved_0[0x10];
5435
5436         u8         reserved_1[0x10];
5437         u8         op_mod[0x10];
5438
5439         u8         reserved_2[0x40];
5440
5441         struct mlx5_ifc_srqc_bits srq_context_entry;
5442
5443         u8         reserved_3[0x600];
5444
5445         u8         pas[0][0x40];
5446 };
5447
5448 struct mlx5_ifc_create_sq_out_bits {
5449         u8         status[0x8];
5450         u8         reserved_0[0x18];
5451
5452         u8         syndrome[0x20];
5453
5454         u8         reserved_1[0x8];
5455         u8         sqn[0x18];
5456
5457         u8         reserved_2[0x20];
5458 };
5459
5460 struct mlx5_ifc_create_sq_in_bits {
5461         u8         opcode[0x10];
5462         u8         reserved_0[0x10];
5463
5464         u8         reserved_1[0x10];
5465         u8         op_mod[0x10];
5466
5467         u8         reserved_2[0xc0];
5468
5469         struct mlx5_ifc_sqc_bits ctx;
5470 };
5471
5472 struct mlx5_ifc_create_rqt_out_bits {
5473         u8         status[0x8];
5474         u8         reserved_0[0x18];
5475
5476         u8         syndrome[0x20];
5477
5478         u8         reserved_1[0x8];
5479         u8         rqtn[0x18];
5480
5481         u8         reserved_2[0x20];
5482 };
5483
5484 struct mlx5_ifc_create_rqt_in_bits {
5485         u8         opcode[0x10];
5486         u8         reserved_0[0x10];
5487
5488         u8         reserved_1[0x10];
5489         u8         op_mod[0x10];
5490
5491         u8         reserved_2[0xc0];
5492
5493         struct mlx5_ifc_rqtc_bits rqt_context;
5494 };
5495
5496 struct mlx5_ifc_create_rq_out_bits {
5497         u8         status[0x8];
5498         u8         reserved_0[0x18];
5499
5500         u8         syndrome[0x20];
5501
5502         u8         reserved_1[0x8];
5503         u8         rqn[0x18];
5504
5505         u8         reserved_2[0x20];
5506 };
5507
5508 struct mlx5_ifc_create_rq_in_bits {
5509         u8         opcode[0x10];
5510         u8         reserved_0[0x10];
5511
5512         u8         reserved_1[0x10];
5513         u8         op_mod[0x10];
5514
5515         u8         reserved_2[0xc0];
5516
5517         struct mlx5_ifc_rqc_bits ctx;
5518 };
5519
5520 struct mlx5_ifc_create_rmp_out_bits {
5521         u8         status[0x8];
5522         u8         reserved_0[0x18];
5523
5524         u8         syndrome[0x20];
5525
5526         u8         reserved_1[0x8];
5527         u8         rmpn[0x18];
5528
5529         u8         reserved_2[0x20];
5530 };
5531
5532 struct mlx5_ifc_create_rmp_in_bits {
5533         u8         opcode[0x10];
5534         u8         reserved_0[0x10];
5535
5536         u8         reserved_1[0x10];
5537         u8         op_mod[0x10];
5538
5539         u8         reserved_2[0xc0];
5540
5541         struct mlx5_ifc_rmpc_bits ctx;
5542 };
5543
5544 struct mlx5_ifc_create_qp_out_bits {
5545         u8         status[0x8];
5546         u8         reserved_0[0x18];
5547
5548         u8         syndrome[0x20];
5549
5550         u8         reserved_1[0x8];
5551         u8         qpn[0x18];
5552
5553         u8         reserved_2[0x20];
5554 };
5555
5556 struct mlx5_ifc_create_qp_in_bits {
5557         u8         opcode[0x10];
5558         u8         reserved_0[0x10];
5559
5560         u8         reserved_1[0x10];
5561         u8         op_mod[0x10];
5562
5563         u8         reserved_2[0x40];
5564
5565         u8         opt_param_mask[0x20];
5566
5567         u8         reserved_3[0x20];
5568
5569         struct mlx5_ifc_qpc_bits qpc;
5570
5571         u8         reserved_4[0x80];
5572
5573         u8         pas[0][0x40];
5574 };
5575
5576 struct mlx5_ifc_create_psv_out_bits {
5577         u8         status[0x8];
5578         u8         reserved_0[0x18];
5579
5580         u8         syndrome[0x20];
5581
5582         u8         reserved_1[0x40];
5583
5584         u8         reserved_2[0x8];
5585         u8         psv0_index[0x18];
5586
5587         u8         reserved_3[0x8];
5588         u8         psv1_index[0x18];
5589
5590         u8         reserved_4[0x8];
5591         u8         psv2_index[0x18];
5592
5593         u8         reserved_5[0x8];
5594         u8         psv3_index[0x18];
5595 };
5596
5597 struct mlx5_ifc_create_psv_in_bits {
5598         u8         opcode[0x10];
5599         u8         reserved_0[0x10];
5600
5601         u8         reserved_1[0x10];
5602         u8         op_mod[0x10];
5603
5604         u8         num_psv[0x4];
5605         u8         reserved_2[0x4];
5606         u8         pd[0x18];
5607
5608         u8         reserved_3[0x20];
5609 };
5610
5611 struct mlx5_ifc_create_mkey_out_bits {
5612         u8         status[0x8];
5613         u8         reserved_0[0x18];
5614
5615         u8         syndrome[0x20];
5616
5617         u8         reserved_1[0x8];
5618         u8         mkey_index[0x18];
5619
5620         u8         reserved_2[0x20];
5621 };
5622
5623 struct mlx5_ifc_create_mkey_in_bits {
5624         u8         opcode[0x10];
5625         u8         reserved_0[0x10];
5626
5627         u8         reserved_1[0x10];
5628         u8         op_mod[0x10];
5629
5630         u8         reserved_2[0x20];
5631
5632         u8         pg_access[0x1];
5633         u8         reserved_3[0x1f];
5634
5635         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5636
5637         u8         reserved_4[0x80];
5638
5639         u8         translations_octword_actual_size[0x20];
5640
5641         u8         reserved_5[0x560];
5642
5643         u8         klm_pas_mtt[0][0x20];
5644 };
5645
5646 struct mlx5_ifc_create_flow_table_out_bits {
5647         u8         status[0x8];
5648         u8         reserved_0[0x18];
5649
5650         u8         syndrome[0x20];
5651
5652         u8         reserved_1[0x8];
5653         u8         table_id[0x18];
5654
5655         u8         reserved_2[0x20];
5656 };
5657
5658 struct mlx5_ifc_create_flow_table_in_bits {
5659         u8         opcode[0x10];
5660         u8         reserved_0[0x10];
5661
5662         u8         reserved_1[0x10];
5663         u8         op_mod[0x10];
5664
5665         u8         reserved_2[0x40];
5666
5667         u8         table_type[0x8];
5668         u8         reserved_3[0x18];
5669
5670         u8         reserved_4[0x20];
5671
5672         u8         reserved_5[0x8];
5673         u8         level[0x8];
5674         u8         reserved_6[0x8];
5675         u8         log_size[0x8];
5676
5677         u8         reserved_7[0x120];
5678 };
5679
5680 struct mlx5_ifc_create_flow_group_out_bits {
5681         u8         status[0x8];
5682         u8         reserved_0[0x18];
5683
5684         u8         syndrome[0x20];
5685
5686         u8         reserved_1[0x8];
5687         u8         group_id[0x18];
5688
5689         u8         reserved_2[0x20];
5690 };
5691
5692 enum {
5693         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5694         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5695         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5696 };
5697
5698 struct mlx5_ifc_create_flow_group_in_bits {
5699         u8         opcode[0x10];
5700         u8         reserved_0[0x10];
5701
5702         u8         reserved_1[0x10];
5703         u8         op_mod[0x10];
5704
5705         u8         reserved_2[0x40];
5706
5707         u8         table_type[0x8];
5708         u8         reserved_3[0x18];
5709
5710         u8         reserved_4[0x8];
5711         u8         table_id[0x18];
5712
5713         u8         reserved_5[0x20];
5714
5715         u8         start_flow_index[0x20];
5716
5717         u8         reserved_6[0x20];
5718
5719         u8         end_flow_index[0x20];
5720
5721         u8         reserved_7[0xa0];
5722
5723         u8         reserved_8[0x18];
5724         u8         match_criteria_enable[0x8];
5725
5726         struct mlx5_ifc_fte_match_param_bits match_criteria;
5727
5728         u8         reserved_9[0xe00];
5729 };
5730
5731 struct mlx5_ifc_create_eq_out_bits {
5732         u8         status[0x8];
5733         u8         reserved_0[0x18];
5734
5735         u8         syndrome[0x20];
5736
5737         u8         reserved_1[0x18];
5738         u8         eq_number[0x8];
5739
5740         u8         reserved_2[0x20];
5741 };
5742
5743 struct mlx5_ifc_create_eq_in_bits {
5744         u8         opcode[0x10];
5745         u8         reserved_0[0x10];
5746
5747         u8         reserved_1[0x10];
5748         u8         op_mod[0x10];
5749
5750         u8         reserved_2[0x40];
5751
5752         struct mlx5_ifc_eqc_bits eq_context_entry;
5753
5754         u8         reserved_3[0x40];
5755
5756         u8         event_bitmask[0x40];
5757
5758         u8         reserved_4[0x580];
5759
5760         u8         pas[0][0x40];
5761 };
5762
5763 struct mlx5_ifc_create_dct_out_bits {
5764         u8         status[0x8];
5765         u8         reserved_0[0x18];
5766
5767         u8         syndrome[0x20];
5768
5769         u8         reserved_1[0x8];
5770         u8         dctn[0x18];
5771
5772         u8         reserved_2[0x20];
5773 };
5774
5775 struct mlx5_ifc_create_dct_in_bits {
5776         u8         opcode[0x10];
5777         u8         reserved_0[0x10];
5778
5779         u8         reserved_1[0x10];
5780         u8         op_mod[0x10];
5781
5782         u8         reserved_2[0x40];
5783
5784         struct mlx5_ifc_dctc_bits dct_context_entry;
5785
5786         u8         reserved_3[0x180];
5787 };
5788
5789 struct mlx5_ifc_create_cq_out_bits {
5790         u8         status[0x8];
5791         u8         reserved_0[0x18];
5792
5793         u8         syndrome[0x20];
5794
5795         u8         reserved_1[0x8];
5796         u8         cqn[0x18];
5797
5798         u8         reserved_2[0x20];
5799 };
5800
5801 struct mlx5_ifc_create_cq_in_bits {
5802         u8         opcode[0x10];
5803         u8         reserved_0[0x10];
5804
5805         u8         reserved_1[0x10];
5806         u8         op_mod[0x10];
5807
5808         u8         reserved_2[0x40];
5809
5810         struct mlx5_ifc_cqc_bits cq_context;
5811
5812         u8         reserved_3[0x600];
5813
5814         u8         pas[0][0x40];
5815 };
5816
5817 struct mlx5_ifc_config_int_moderation_out_bits {
5818         u8         status[0x8];
5819         u8         reserved_0[0x18];
5820
5821         u8         syndrome[0x20];
5822
5823         u8         reserved_1[0x4];
5824         u8         min_delay[0xc];
5825         u8         int_vector[0x10];
5826
5827         u8         reserved_2[0x20];
5828 };
5829
5830 enum {
5831         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5832         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5833 };
5834
5835 struct mlx5_ifc_config_int_moderation_in_bits {
5836         u8         opcode[0x10];
5837         u8         reserved_0[0x10];
5838
5839         u8         reserved_1[0x10];
5840         u8         op_mod[0x10];
5841
5842         u8         reserved_2[0x4];
5843         u8         min_delay[0xc];
5844         u8         int_vector[0x10];
5845
5846         u8         reserved_3[0x20];
5847 };
5848
5849 struct mlx5_ifc_attach_to_mcg_out_bits {
5850         u8         status[0x8];
5851         u8         reserved_0[0x18];
5852
5853         u8         syndrome[0x20];
5854
5855         u8         reserved_1[0x40];
5856 };
5857
5858 struct mlx5_ifc_attach_to_mcg_in_bits {
5859         u8         opcode[0x10];
5860         u8         reserved_0[0x10];
5861
5862         u8         reserved_1[0x10];
5863         u8         op_mod[0x10];
5864
5865         u8         reserved_2[0x8];
5866         u8         qpn[0x18];
5867
5868         u8         reserved_3[0x20];
5869
5870         u8         multicast_gid[16][0x8];
5871 };
5872
5873 struct mlx5_ifc_arm_xrc_srq_out_bits {
5874         u8         status[0x8];
5875         u8         reserved_0[0x18];
5876
5877         u8         syndrome[0x20];
5878
5879         u8         reserved_1[0x40];
5880 };
5881
5882 enum {
5883         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
5884 };
5885
5886 struct mlx5_ifc_arm_xrc_srq_in_bits {
5887         u8         opcode[0x10];
5888         u8         reserved_0[0x10];
5889
5890         u8         reserved_1[0x10];
5891         u8         op_mod[0x10];
5892
5893         u8         reserved_2[0x8];
5894         u8         xrc_srqn[0x18];
5895
5896         u8         reserved_3[0x10];
5897         u8         lwm[0x10];
5898 };
5899
5900 struct mlx5_ifc_arm_rq_out_bits {
5901         u8         status[0x8];
5902         u8         reserved_0[0x18];
5903
5904         u8         syndrome[0x20];
5905
5906         u8         reserved_1[0x40];
5907 };
5908
5909 enum {
5910         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
5911 };
5912
5913 struct mlx5_ifc_arm_rq_in_bits {
5914         u8         opcode[0x10];
5915         u8         reserved_0[0x10];
5916
5917         u8         reserved_1[0x10];
5918         u8         op_mod[0x10];
5919
5920         u8         reserved_2[0x8];
5921         u8         srq_number[0x18];
5922
5923         u8         reserved_3[0x10];
5924         u8         lwm[0x10];
5925 };
5926
5927 struct mlx5_ifc_arm_dct_out_bits {
5928         u8         status[0x8];
5929         u8         reserved_0[0x18];
5930
5931         u8         syndrome[0x20];
5932
5933         u8         reserved_1[0x40];
5934 };
5935
5936 struct mlx5_ifc_arm_dct_in_bits {
5937         u8         opcode[0x10];
5938         u8         reserved_0[0x10];
5939
5940         u8         reserved_1[0x10];
5941         u8         op_mod[0x10];
5942
5943         u8         reserved_2[0x8];
5944         u8         dct_number[0x18];
5945
5946         u8         reserved_3[0x20];
5947 };
5948
5949 struct mlx5_ifc_alloc_xrcd_out_bits {
5950         u8         status[0x8];
5951         u8         reserved_0[0x18];
5952
5953         u8         syndrome[0x20];
5954
5955         u8         reserved_1[0x8];
5956         u8         xrcd[0x18];
5957
5958         u8         reserved_2[0x20];
5959 };
5960
5961 struct mlx5_ifc_alloc_xrcd_in_bits {
5962         u8         opcode[0x10];
5963         u8         reserved_0[0x10];
5964
5965         u8         reserved_1[0x10];
5966         u8         op_mod[0x10];
5967
5968         u8         reserved_2[0x40];
5969 };
5970
5971 struct mlx5_ifc_alloc_uar_out_bits {
5972         u8         status[0x8];
5973         u8         reserved_0[0x18];
5974
5975         u8         syndrome[0x20];
5976
5977         u8         reserved_1[0x8];
5978         u8         uar[0x18];
5979
5980         u8         reserved_2[0x20];
5981 };
5982
5983 struct mlx5_ifc_alloc_uar_in_bits {
5984         u8         opcode[0x10];
5985         u8         reserved_0[0x10];
5986
5987         u8         reserved_1[0x10];
5988         u8         op_mod[0x10];
5989
5990         u8         reserved_2[0x40];
5991 };
5992
5993 struct mlx5_ifc_alloc_transport_domain_out_bits {
5994         u8         status[0x8];
5995         u8         reserved_0[0x18];
5996
5997         u8         syndrome[0x20];
5998
5999         u8         reserved_1[0x8];
6000         u8         transport_domain[0x18];
6001
6002         u8         reserved_2[0x20];
6003 };
6004
6005 struct mlx5_ifc_alloc_transport_domain_in_bits {
6006         u8         opcode[0x10];
6007         u8         reserved_0[0x10];
6008
6009         u8         reserved_1[0x10];
6010         u8         op_mod[0x10];
6011
6012         u8         reserved_2[0x40];
6013 };
6014
6015 struct mlx5_ifc_alloc_q_counter_out_bits {
6016         u8         status[0x8];
6017         u8         reserved_0[0x18];
6018
6019         u8         syndrome[0x20];
6020
6021         u8         reserved_1[0x18];
6022         u8         counter_set_id[0x8];
6023
6024         u8         reserved_2[0x20];
6025 };
6026
6027 struct mlx5_ifc_alloc_q_counter_in_bits {
6028         u8         opcode[0x10];
6029         u8         reserved_0[0x10];
6030
6031         u8         reserved_1[0x10];
6032         u8         op_mod[0x10];
6033
6034         u8         reserved_2[0x40];
6035 };
6036
6037 struct mlx5_ifc_alloc_pd_out_bits {
6038         u8         status[0x8];
6039         u8         reserved_0[0x18];
6040
6041         u8         syndrome[0x20];
6042
6043         u8         reserved_1[0x8];
6044         u8         pd[0x18];
6045
6046         u8         reserved_2[0x20];
6047 };
6048
6049 struct mlx5_ifc_alloc_pd_in_bits {
6050         u8         opcode[0x10];
6051         u8         reserved_0[0x10];
6052
6053         u8         reserved_1[0x10];
6054         u8         op_mod[0x10];
6055
6056         u8         reserved_2[0x40];
6057 };
6058
6059 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6060         u8         status[0x8];
6061         u8         reserved_0[0x18];
6062
6063         u8         syndrome[0x20];
6064
6065         u8         reserved_1[0x40];
6066 };
6067
6068 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6069         u8         opcode[0x10];
6070         u8         reserved_0[0x10];
6071
6072         u8         reserved_1[0x10];
6073         u8         op_mod[0x10];
6074
6075         u8         reserved_2[0x20];
6076
6077         u8         reserved_3[0x10];
6078         u8         vxlan_udp_port[0x10];
6079 };
6080
6081 struct mlx5_ifc_access_register_out_bits {
6082         u8         status[0x8];
6083         u8         reserved_0[0x18];
6084
6085         u8         syndrome[0x20];
6086
6087         u8         reserved_1[0x40];
6088
6089         u8         register_data[0][0x20];
6090 };
6091
6092 enum {
6093         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6094         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6095 };
6096
6097 struct mlx5_ifc_access_register_in_bits {
6098         u8         opcode[0x10];
6099         u8         reserved_0[0x10];
6100
6101         u8         reserved_1[0x10];
6102         u8         op_mod[0x10];
6103
6104         u8         reserved_2[0x10];
6105         u8         register_id[0x10];
6106
6107         u8         argument[0x20];
6108
6109         u8         register_data[0][0x20];
6110 };
6111
6112 struct mlx5_ifc_sltp_reg_bits {
6113         u8         status[0x4];
6114         u8         version[0x4];
6115         u8         local_port[0x8];
6116         u8         pnat[0x2];
6117         u8         reserved_0[0x2];
6118         u8         lane[0x4];
6119         u8         reserved_1[0x8];
6120
6121         u8         reserved_2[0x20];
6122
6123         u8         reserved_3[0x7];
6124         u8         polarity[0x1];
6125         u8         ob_tap0[0x8];
6126         u8         ob_tap1[0x8];
6127         u8         ob_tap2[0x8];
6128
6129         u8         reserved_4[0xc];
6130         u8         ob_preemp_mode[0x4];
6131         u8         ob_reg[0x8];
6132         u8         ob_bias[0x8];
6133
6134         u8         reserved_5[0x20];
6135 };
6136
6137 struct mlx5_ifc_slrg_reg_bits {
6138         u8         status[0x4];
6139         u8         version[0x4];
6140         u8         local_port[0x8];
6141         u8         pnat[0x2];
6142         u8         reserved_0[0x2];
6143         u8         lane[0x4];
6144         u8         reserved_1[0x8];
6145
6146         u8         time_to_link_up[0x10];
6147         u8         reserved_2[0xc];
6148         u8         grade_lane_speed[0x4];
6149
6150         u8         grade_version[0x8];
6151         u8         grade[0x18];
6152
6153         u8         reserved_3[0x4];
6154         u8         height_grade_type[0x4];
6155         u8         height_grade[0x18];
6156
6157         u8         height_dz[0x10];
6158         u8         height_dv[0x10];
6159
6160         u8         reserved_4[0x10];
6161         u8         height_sigma[0x10];
6162
6163         u8         reserved_5[0x20];
6164
6165         u8         reserved_6[0x4];
6166         u8         phase_grade_type[0x4];
6167         u8         phase_grade[0x18];
6168
6169         u8         reserved_7[0x8];
6170         u8         phase_eo_pos[0x8];
6171         u8         reserved_8[0x8];
6172         u8         phase_eo_neg[0x8];
6173
6174         u8         ffe_set_tested[0x10];
6175         u8         test_errors_per_lane[0x10];
6176 };
6177
6178 struct mlx5_ifc_pvlc_reg_bits {
6179         u8         reserved_0[0x8];
6180         u8         local_port[0x8];
6181         u8         reserved_1[0x10];
6182
6183         u8         reserved_2[0x1c];
6184         u8         vl_hw_cap[0x4];
6185
6186         u8         reserved_3[0x1c];
6187         u8         vl_admin[0x4];
6188
6189         u8         reserved_4[0x1c];
6190         u8         vl_operational[0x4];
6191 };
6192
6193 struct mlx5_ifc_pude_reg_bits {
6194         u8         swid[0x8];
6195         u8         local_port[0x8];
6196         u8         reserved_0[0x4];
6197         u8         admin_status[0x4];
6198         u8         reserved_1[0x4];
6199         u8         oper_status[0x4];
6200
6201         u8         reserved_2[0x60];
6202 };
6203
6204 struct mlx5_ifc_ptys_reg_bits {
6205         u8         reserved_0[0x8];
6206         u8         local_port[0x8];
6207         u8         reserved_1[0xd];
6208         u8         proto_mask[0x3];
6209
6210         u8         reserved_2[0x40];
6211
6212         u8         eth_proto_capability[0x20];
6213
6214         u8         ib_link_width_capability[0x10];
6215         u8         ib_proto_capability[0x10];
6216
6217         u8         reserved_3[0x20];
6218
6219         u8         eth_proto_admin[0x20];
6220
6221         u8         ib_link_width_admin[0x10];
6222         u8         ib_proto_admin[0x10];
6223
6224         u8         reserved_4[0x20];
6225
6226         u8         eth_proto_oper[0x20];
6227
6228         u8         ib_link_width_oper[0x10];
6229         u8         ib_proto_oper[0x10];
6230
6231         u8         reserved_5[0x20];
6232
6233         u8         eth_proto_lp_advertise[0x20];
6234
6235         u8         reserved_6[0x60];
6236 };
6237
6238 struct mlx5_ifc_ptas_reg_bits {
6239         u8         reserved_0[0x20];
6240
6241         u8         algorithm_options[0x10];
6242         u8         reserved_1[0x4];
6243         u8         repetitions_mode[0x4];
6244         u8         num_of_repetitions[0x8];
6245
6246         u8         grade_version[0x8];
6247         u8         height_grade_type[0x4];
6248         u8         phase_grade_type[0x4];
6249         u8         height_grade_weight[0x8];
6250         u8         phase_grade_weight[0x8];
6251
6252         u8         gisim_measure_bits[0x10];
6253         u8         adaptive_tap_measure_bits[0x10];
6254
6255         u8         ber_bath_high_error_threshold[0x10];
6256         u8         ber_bath_mid_error_threshold[0x10];
6257
6258         u8         ber_bath_low_error_threshold[0x10];
6259         u8         one_ratio_high_threshold[0x10];
6260
6261         u8         one_ratio_high_mid_threshold[0x10];
6262         u8         one_ratio_low_mid_threshold[0x10];
6263
6264         u8         one_ratio_low_threshold[0x10];
6265         u8         ndeo_error_threshold[0x10];
6266
6267         u8         mixer_offset_step_size[0x10];
6268         u8         reserved_2[0x8];
6269         u8         mix90_phase_for_voltage_bath[0x8];
6270
6271         u8         mixer_offset_start[0x10];
6272         u8         mixer_offset_end[0x10];
6273
6274         u8         reserved_3[0x15];
6275         u8         ber_test_time[0xb];
6276 };
6277
6278 struct mlx5_ifc_pspa_reg_bits {
6279         u8         swid[0x8];
6280         u8         local_port[0x8];
6281         u8         sub_port[0x8];
6282         u8         reserved_0[0x8];
6283
6284         u8         reserved_1[0x20];
6285 };
6286
6287 struct mlx5_ifc_pqdr_reg_bits {
6288         u8         reserved_0[0x8];
6289         u8         local_port[0x8];
6290         u8         reserved_1[0x5];
6291         u8         prio[0x3];
6292         u8         reserved_2[0x6];
6293         u8         mode[0x2];
6294
6295         u8         reserved_3[0x20];
6296
6297         u8         reserved_4[0x10];
6298         u8         min_threshold[0x10];
6299
6300         u8         reserved_5[0x10];
6301         u8         max_threshold[0x10];
6302
6303         u8         reserved_6[0x10];
6304         u8         mark_probability_denominator[0x10];
6305
6306         u8         reserved_7[0x60];
6307 };
6308
6309 struct mlx5_ifc_ppsc_reg_bits {
6310         u8         reserved_0[0x8];
6311         u8         local_port[0x8];
6312         u8         reserved_1[0x10];
6313
6314         u8         reserved_2[0x60];
6315
6316         u8         reserved_3[0x1c];
6317         u8         wrps_admin[0x4];
6318
6319         u8         reserved_4[0x1c];
6320         u8         wrps_status[0x4];
6321
6322         u8         reserved_5[0x8];
6323         u8         up_threshold[0x8];
6324         u8         reserved_6[0x8];
6325         u8         down_threshold[0x8];
6326
6327         u8         reserved_7[0x20];
6328
6329         u8         reserved_8[0x1c];
6330         u8         srps_admin[0x4];
6331
6332         u8         reserved_9[0x1c];
6333         u8         srps_status[0x4];
6334
6335         u8         reserved_10[0x40];
6336 };
6337
6338 struct mlx5_ifc_pplr_reg_bits {
6339         u8         reserved_0[0x8];
6340         u8         local_port[0x8];
6341         u8         reserved_1[0x10];
6342
6343         u8         reserved_2[0x8];
6344         u8         lb_cap[0x8];
6345         u8         reserved_3[0x8];
6346         u8         lb_en[0x8];
6347 };
6348
6349 struct mlx5_ifc_pplm_reg_bits {
6350         u8         reserved_0[0x8];
6351         u8         local_port[0x8];
6352         u8         reserved_1[0x10];
6353
6354         u8         reserved_2[0x20];
6355
6356         u8         port_profile_mode[0x8];
6357         u8         static_port_profile[0x8];
6358         u8         active_port_profile[0x8];
6359         u8         reserved_3[0x8];
6360
6361         u8         retransmission_active[0x8];
6362         u8         fec_mode_active[0x18];
6363
6364         u8         reserved_4[0x20];
6365 };
6366
6367 struct mlx5_ifc_ppcnt_reg_bits {
6368         u8         swid[0x8];
6369         u8         local_port[0x8];
6370         u8         pnat[0x2];
6371         u8         reserved_0[0x8];
6372         u8         grp[0x6];
6373
6374         u8         clr[0x1];
6375         u8         reserved_1[0x1c];
6376         u8         prio_tc[0x3];
6377
6378         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6379 };
6380
6381 struct mlx5_ifc_ppad_reg_bits {
6382         u8         reserved_0[0x3];
6383         u8         single_mac[0x1];
6384         u8         reserved_1[0x4];
6385         u8         local_port[0x8];
6386         u8         mac_47_32[0x10];
6387
6388         u8         mac_31_0[0x20];
6389
6390         u8         reserved_2[0x40];
6391 };
6392
6393 struct mlx5_ifc_pmtu_reg_bits {
6394         u8         reserved_0[0x8];
6395         u8         local_port[0x8];
6396         u8         reserved_1[0x10];
6397
6398         u8         max_mtu[0x10];
6399         u8         reserved_2[0x10];
6400
6401         u8         admin_mtu[0x10];
6402         u8         reserved_3[0x10];
6403
6404         u8         oper_mtu[0x10];
6405         u8         reserved_4[0x10];
6406 };
6407
6408 struct mlx5_ifc_pmpr_reg_bits {
6409         u8         reserved_0[0x8];
6410         u8         module[0x8];
6411         u8         reserved_1[0x10];
6412
6413         u8         reserved_2[0x18];
6414         u8         attenuation_5g[0x8];
6415
6416         u8         reserved_3[0x18];
6417         u8         attenuation_7g[0x8];
6418
6419         u8         reserved_4[0x18];
6420         u8         attenuation_12g[0x8];
6421 };
6422
6423 struct mlx5_ifc_pmpe_reg_bits {
6424         u8         reserved_0[0x8];
6425         u8         module[0x8];
6426         u8         reserved_1[0xc];
6427         u8         module_status[0x4];
6428
6429         u8         reserved_2[0x60];
6430 };
6431
6432 struct mlx5_ifc_pmpc_reg_bits {
6433         u8         module_state_updated[32][0x8];
6434 };
6435
6436 struct mlx5_ifc_pmlpn_reg_bits {
6437         u8         reserved_0[0x4];
6438         u8         mlpn_status[0x4];
6439         u8         local_port[0x8];
6440         u8         reserved_1[0x10];
6441
6442         u8         e[0x1];
6443         u8         reserved_2[0x1f];
6444 };
6445
6446 struct mlx5_ifc_pmlp_reg_bits {
6447         u8         rxtx[0x1];
6448         u8         reserved_0[0x7];
6449         u8         local_port[0x8];
6450         u8         reserved_1[0x8];
6451         u8         width[0x8];
6452
6453         u8         lane0_module_mapping[0x20];
6454
6455         u8         lane1_module_mapping[0x20];
6456
6457         u8         lane2_module_mapping[0x20];
6458
6459         u8         lane3_module_mapping[0x20];
6460
6461         u8         reserved_2[0x160];
6462 };
6463
6464 struct mlx5_ifc_pmaos_reg_bits {
6465         u8         reserved_0[0x8];
6466         u8         module[0x8];
6467         u8         reserved_1[0x4];
6468         u8         admin_status[0x4];
6469         u8         reserved_2[0x4];
6470         u8         oper_status[0x4];
6471
6472         u8         ase[0x1];
6473         u8         ee[0x1];
6474         u8         reserved_3[0x1c];
6475         u8         e[0x2];
6476
6477         u8         reserved_4[0x40];
6478 };
6479
6480 struct mlx5_ifc_plpc_reg_bits {
6481         u8         reserved_0[0x4];
6482         u8         profile_id[0xc];
6483         u8         reserved_1[0x4];
6484         u8         proto_mask[0x4];
6485         u8         reserved_2[0x8];
6486
6487         u8         reserved_3[0x10];
6488         u8         lane_speed[0x10];
6489
6490         u8         reserved_4[0x17];
6491         u8         lpbf[0x1];
6492         u8         fec_mode_policy[0x8];
6493
6494         u8         retransmission_capability[0x8];
6495         u8         fec_mode_capability[0x18];
6496
6497         u8         retransmission_support_admin[0x8];
6498         u8         fec_mode_support_admin[0x18];
6499
6500         u8         retransmission_request_admin[0x8];
6501         u8         fec_mode_request_admin[0x18];
6502
6503         u8         reserved_5[0x80];
6504 };
6505
6506 struct mlx5_ifc_plib_reg_bits {
6507         u8         reserved_0[0x8];
6508         u8         local_port[0x8];
6509         u8         reserved_1[0x8];
6510         u8         ib_port[0x8];
6511
6512         u8         reserved_2[0x60];
6513 };
6514
6515 struct mlx5_ifc_plbf_reg_bits {
6516         u8         reserved_0[0x8];
6517         u8         local_port[0x8];
6518         u8         reserved_1[0xd];
6519         u8         lbf_mode[0x3];
6520
6521         u8         reserved_2[0x20];
6522 };
6523
6524 struct mlx5_ifc_pipg_reg_bits {
6525         u8         reserved_0[0x8];
6526         u8         local_port[0x8];
6527         u8         reserved_1[0x10];
6528
6529         u8         dic[0x1];
6530         u8         reserved_2[0x19];
6531         u8         ipg[0x4];
6532         u8         reserved_3[0x2];
6533 };
6534
6535 struct mlx5_ifc_pifr_reg_bits {
6536         u8         reserved_0[0x8];
6537         u8         local_port[0x8];
6538         u8         reserved_1[0x10];
6539
6540         u8         reserved_2[0xe0];
6541
6542         u8         port_filter[8][0x20];
6543
6544         u8         port_filter_update_en[8][0x20];
6545 };
6546
6547 struct mlx5_ifc_pfcc_reg_bits {
6548         u8         reserved_0[0x8];
6549         u8         local_port[0x8];
6550         u8         reserved_1[0x10];
6551
6552         u8         ppan[0x4];
6553         u8         reserved_2[0x4];
6554         u8         prio_mask_tx[0x8];
6555         u8         reserved_3[0x8];
6556         u8         prio_mask_rx[0x8];
6557
6558         u8         pptx[0x1];
6559         u8         aptx[0x1];
6560         u8         reserved_4[0x6];
6561         u8         pfctx[0x8];
6562         u8         reserved_5[0x10];
6563
6564         u8         pprx[0x1];
6565         u8         aprx[0x1];
6566         u8         reserved_6[0x6];
6567         u8         pfcrx[0x8];
6568         u8         reserved_7[0x10];
6569
6570         u8         reserved_8[0x80];
6571 };
6572
6573 struct mlx5_ifc_pelc_reg_bits {
6574         u8         op[0x4];
6575         u8         reserved_0[0x4];
6576         u8         local_port[0x8];
6577         u8         reserved_1[0x10];
6578
6579         u8         op_admin[0x8];
6580         u8         op_capability[0x8];
6581         u8         op_request[0x8];
6582         u8         op_active[0x8];
6583
6584         u8         admin[0x40];
6585
6586         u8         capability[0x40];
6587
6588         u8         request[0x40];
6589
6590         u8         active[0x40];
6591
6592         u8         reserved_2[0x80];
6593 };
6594
6595 struct mlx5_ifc_peir_reg_bits {
6596         u8         reserved_0[0x8];
6597         u8         local_port[0x8];
6598         u8         reserved_1[0x10];
6599
6600         u8         reserved_2[0xc];
6601         u8         error_count[0x4];
6602         u8         reserved_3[0x10];
6603
6604         u8         reserved_4[0xc];
6605         u8         lane[0x4];
6606         u8         reserved_5[0x8];
6607         u8         error_type[0x8];
6608 };
6609
6610 struct mlx5_ifc_pcap_reg_bits {
6611         u8         reserved_0[0x8];
6612         u8         local_port[0x8];
6613         u8         reserved_1[0x10];
6614
6615         u8         port_capability_mask[4][0x20];
6616 };
6617
6618 struct mlx5_ifc_paos_reg_bits {
6619         u8         swid[0x8];
6620         u8         local_port[0x8];
6621         u8         reserved_0[0x4];
6622         u8         admin_status[0x4];
6623         u8         reserved_1[0x4];
6624         u8         oper_status[0x4];
6625
6626         u8         ase[0x1];
6627         u8         ee[0x1];
6628         u8         reserved_2[0x1c];
6629         u8         e[0x2];
6630
6631         u8         reserved_3[0x40];
6632 };
6633
6634 struct mlx5_ifc_pamp_reg_bits {
6635         u8         reserved_0[0x8];
6636         u8         opamp_group[0x8];
6637         u8         reserved_1[0xc];
6638         u8         opamp_group_type[0x4];
6639
6640         u8         start_index[0x10];
6641         u8         reserved_2[0x4];
6642         u8         num_of_indices[0xc];
6643
6644         u8         index_data[18][0x10];
6645 };
6646
6647 struct mlx5_ifc_lane_2_module_mapping_bits {
6648         u8         reserved_0[0x6];
6649         u8         rx_lane[0x2];
6650         u8         reserved_1[0x6];
6651         u8         tx_lane[0x2];
6652         u8         reserved_2[0x8];
6653         u8         module[0x8];
6654 };
6655
6656 struct mlx5_ifc_bufferx_reg_bits {
6657         u8         reserved_0[0x6];
6658         u8         lossy[0x1];
6659         u8         epsb[0x1];
6660         u8         reserved_1[0xc];
6661         u8         size[0xc];
6662
6663         u8         xoff_threshold[0x10];
6664         u8         xon_threshold[0x10];
6665 };
6666
6667 struct mlx5_ifc_set_node_in_bits {
6668         u8         node_description[64][0x8];
6669 };
6670
6671 struct mlx5_ifc_register_power_settings_bits {
6672         u8         reserved_0[0x18];
6673         u8         power_settings_level[0x8];
6674
6675         u8         reserved_1[0x60];
6676 };
6677
6678 struct mlx5_ifc_register_host_endianness_bits {
6679         u8         he[0x1];
6680         u8         reserved_0[0x1f];
6681
6682         u8         reserved_1[0x60];
6683 };
6684
6685 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6686         u8         reserved_0[0x20];
6687
6688         u8         mkey[0x20];
6689
6690         u8         addressh_63_32[0x20];
6691
6692         u8         addressl_31_0[0x20];
6693 };
6694
6695 struct mlx5_ifc_ud_adrs_vector_bits {
6696         u8         dc_key[0x40];
6697
6698         u8         ext[0x1];
6699         u8         reserved_0[0x7];
6700         u8         destination_qp_dct[0x18];
6701
6702         u8         static_rate[0x4];
6703         u8         sl_eth_prio[0x4];
6704         u8         fl[0x1];
6705         u8         mlid[0x7];
6706         u8         rlid_udp_sport[0x10];
6707
6708         u8         reserved_1[0x20];
6709
6710         u8         rmac_47_16[0x20];
6711
6712         u8         rmac_15_0[0x10];
6713         u8         tclass[0x8];
6714         u8         hop_limit[0x8];
6715
6716         u8         reserved_2[0x1];
6717         u8         grh[0x1];
6718         u8         reserved_3[0x2];
6719         u8         src_addr_index[0x8];
6720         u8         flow_label[0x14];
6721
6722         u8         rgid_rip[16][0x8];
6723 };
6724
6725 struct mlx5_ifc_pages_req_event_bits {
6726         u8         reserved_0[0x10];
6727         u8         function_id[0x10];
6728
6729         u8         num_pages[0x20];
6730
6731         u8         reserved_1[0xa0];
6732 };
6733
6734 struct mlx5_ifc_eqe_bits {
6735         u8         reserved_0[0x8];
6736         u8         event_type[0x8];
6737         u8         reserved_1[0x8];
6738         u8         event_sub_type[0x8];
6739
6740         u8         reserved_2[0xe0];
6741
6742         union mlx5_ifc_event_auto_bits event_data;
6743
6744         u8         reserved_3[0x10];
6745         u8         signature[0x8];
6746         u8         reserved_4[0x7];
6747         u8         owner[0x1];
6748 };
6749
6750 enum {
6751         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6752 };
6753
6754 struct mlx5_ifc_cmd_queue_entry_bits {
6755         u8         type[0x8];
6756         u8         reserved_0[0x18];
6757
6758         u8         input_length[0x20];
6759
6760         u8         input_mailbox_pointer_63_32[0x20];
6761
6762         u8         input_mailbox_pointer_31_9[0x17];
6763         u8         reserved_1[0x9];
6764
6765         u8         command_input_inline_data[16][0x8];
6766
6767         u8         command_output_inline_data[16][0x8];
6768
6769         u8         output_mailbox_pointer_63_32[0x20];
6770
6771         u8         output_mailbox_pointer_31_9[0x17];
6772         u8         reserved_2[0x9];
6773
6774         u8         output_length[0x20];
6775
6776         u8         token[0x8];
6777         u8         signature[0x8];
6778         u8         reserved_3[0x8];
6779         u8         status[0x7];
6780         u8         ownership[0x1];
6781 };
6782
6783 struct mlx5_ifc_cmd_out_bits {
6784         u8         status[0x8];
6785         u8         reserved_0[0x18];
6786
6787         u8         syndrome[0x20];
6788
6789         u8         command_output[0x20];
6790 };
6791
6792 struct mlx5_ifc_cmd_in_bits {
6793         u8         opcode[0x10];
6794         u8         reserved_0[0x10];
6795
6796         u8         reserved_1[0x10];
6797         u8         op_mod[0x10];
6798
6799         u8         command[0][0x20];
6800 };
6801
6802 struct mlx5_ifc_cmd_if_box_bits {
6803         u8         mailbox_data[512][0x8];
6804
6805         u8         reserved_0[0x180];
6806
6807         u8         next_pointer_63_32[0x20];
6808
6809         u8         next_pointer_31_10[0x16];
6810         u8         reserved_1[0xa];
6811
6812         u8         block_number[0x20];
6813
6814         u8         reserved_2[0x8];
6815         u8         token[0x8];
6816         u8         ctrl_signature[0x8];
6817         u8         signature[0x8];
6818 };
6819
6820 struct mlx5_ifc_mtt_bits {
6821         u8         ptag_63_32[0x20];
6822
6823         u8         ptag_31_8[0x18];
6824         u8         reserved_0[0x6];
6825         u8         wr_en[0x1];
6826         u8         rd_en[0x1];
6827 };
6828
6829 enum {
6830         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
6831         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
6832         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
6833 };
6834
6835 enum {
6836         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
6837         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
6838         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
6839 };
6840
6841 enum {
6842         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
6843         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
6844         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
6845         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
6846         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
6847         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
6848         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
6849         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
6850         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
6851         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
6852         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
6853 };
6854
6855 struct mlx5_ifc_initial_seg_bits {
6856         u8         fw_rev_minor[0x10];
6857         u8         fw_rev_major[0x10];
6858
6859         u8         cmd_interface_rev[0x10];
6860         u8         fw_rev_subminor[0x10];
6861
6862         u8         reserved_0[0x40];
6863
6864         u8         cmdq_phy_addr_63_32[0x20];
6865
6866         u8         cmdq_phy_addr_31_12[0x14];
6867         u8         reserved_1[0x2];
6868         u8         nic_interface[0x2];
6869         u8         log_cmdq_size[0x4];
6870         u8         log_cmdq_stride[0x4];
6871
6872         u8         command_doorbell_vector[0x20];
6873
6874         u8         reserved_2[0xf00];
6875
6876         u8         initializing[0x1];
6877         u8         reserved_3[0x4];
6878         u8         nic_interface_supported[0x3];
6879         u8         reserved_4[0x18];
6880
6881         struct mlx5_ifc_health_buffer_bits health_buffer;
6882
6883         u8         no_dram_nic_offset[0x20];
6884
6885         u8         reserved_5[0x6e40];
6886
6887         u8         reserved_6[0x1f];
6888         u8         clear_int[0x1];
6889
6890         u8         health_syndrome[0x8];
6891         u8         health_counter[0x18];
6892
6893         u8         reserved_7[0x17fc0];
6894 };
6895
6896 union mlx5_ifc_ports_control_registers_document_bits {
6897         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6898         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6899         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6900         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6901         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6902         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6903         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6904         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6905         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6906         struct mlx5_ifc_pamp_reg_bits pamp_reg;
6907         struct mlx5_ifc_paos_reg_bits paos_reg;
6908         struct mlx5_ifc_pcap_reg_bits pcap_reg;
6909         struct mlx5_ifc_peir_reg_bits peir_reg;
6910         struct mlx5_ifc_pelc_reg_bits pelc_reg;
6911         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6912         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6913         struct mlx5_ifc_pifr_reg_bits pifr_reg;
6914         struct mlx5_ifc_pipg_reg_bits pipg_reg;
6915         struct mlx5_ifc_plbf_reg_bits plbf_reg;
6916         struct mlx5_ifc_plib_reg_bits plib_reg;
6917         struct mlx5_ifc_plpc_reg_bits plpc_reg;
6918         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6919         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6920         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6921         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6922         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6923         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6924         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6925         struct mlx5_ifc_ppad_reg_bits ppad_reg;
6926         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6927         struct mlx5_ifc_pplm_reg_bits pplm_reg;
6928         struct mlx5_ifc_pplr_reg_bits pplr_reg;
6929         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6930         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6931         struct mlx5_ifc_pspa_reg_bits pspa_reg;
6932         struct mlx5_ifc_ptas_reg_bits ptas_reg;
6933         struct mlx5_ifc_ptys_reg_bits ptys_reg;
6934         struct mlx5_ifc_pude_reg_bits pude_reg;
6935         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6936         struct mlx5_ifc_slrg_reg_bits slrg_reg;
6937         struct mlx5_ifc_sltp_reg_bits sltp_reg;
6938         u8         reserved_0[0x60e0];
6939 };
6940
6941 union mlx5_ifc_debug_enhancements_document_bits {
6942         struct mlx5_ifc_health_buffer_bits health_buffer;
6943         u8         reserved_0[0x200];
6944 };
6945
6946 union mlx5_ifc_uplink_pci_interface_document_bits {
6947         struct mlx5_ifc_initial_seg_bits initial_seg;
6948         u8         reserved_0[0x20060];
6949 };
6950
6951 struct mlx5_ifc_set_flow_table_root_out_bits {
6952         u8         status[0x8];
6953         u8         reserved_0[0x18];
6954
6955         u8         syndrome[0x20];
6956
6957         u8         reserved_1[0x40];
6958 };
6959
6960 struct mlx5_ifc_set_flow_table_root_in_bits {
6961         u8         opcode[0x10];
6962         u8         reserved_0[0x10];
6963
6964         u8         reserved_1[0x10];
6965         u8         op_mod[0x10];
6966
6967         u8         reserved_2[0x40];
6968
6969         u8         table_type[0x8];
6970         u8         reserved_3[0x18];
6971
6972         u8         reserved_4[0x8];
6973         u8         table_id[0x18];
6974
6975         u8         reserved_5[0x140];
6976 };
6977
6978 #endif /* MLX5_IFC_H */