include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 enum {
  36         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  37         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  38         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  39         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  40         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  41         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  42         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  43         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  44         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  45         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  46         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  47         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  48         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  49         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  50         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  51         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  52         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  53         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  54         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  55         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  56         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  57         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  58         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  59         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
  60 };
  61
  62 enum {
  63         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  64         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  65         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  66         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  67 };
  68
  69 enum {
  70         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  71         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  72         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  73         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  74         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  75         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  76         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  77         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  78         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  79         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  80         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  81         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  82         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  83         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  84         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  85         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  86         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  87         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  88         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  89         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  90         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
  91         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
  92         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
  93         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
  94         MLX5_CMD_OP_CREATE_QP                     = 0x500,
  95         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
  96         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
  97         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
  98         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
  99         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 100         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 101         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 102         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 103         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 104         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 105         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 106         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 107         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 108         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 109         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 110         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 111         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 112         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 113         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 114         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 115         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 116         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 117         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 118         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 119         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 120         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 121         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 122         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 123         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 124         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 125         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 126         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 127         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 128         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 129         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 130         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 131         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 132         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 133         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 134         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 135         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 136         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 137         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 138         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 139         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 140         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 141         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 142         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 143         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 144         MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
 145         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 146         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 147         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 148         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 149         MLX5_CMD_OP_NOP                           = 0x80d,
 150         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 151         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 152         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 153         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 154         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 155         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 156         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 157         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 158         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 159         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 160         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 161         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 162         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 163         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 164         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 165         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 166         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 167         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 168         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 169         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 170         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 171         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 172         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 173         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 174         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 175         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 176         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 177         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 178         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 179         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 180         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 181         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 182         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 183         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 184         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 185         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 186         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 187         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 188         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 189         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 190         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 191         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 192         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 193         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 194         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 195         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 196         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 197         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 198         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c
 199 };
 200
 201 struct mlx5_ifc_flow_table_fields_supported_bits {
 202         u8         outer_dmac[0x1];
 203         u8         outer_smac[0x1];
 204         u8         outer_ether_type[0x1];
 205         u8         reserved_0[0x1];
 206         u8         outer_first_prio[0x1];
 207         u8         outer_first_cfi[0x1];
 208         u8         outer_first_vid[0x1];
 209         u8         reserved_1[0x1];
 210         u8         outer_second_prio[0x1];
 211         u8         outer_second_cfi[0x1];
 212         u8         outer_second_vid[0x1];
 213         u8         reserved_2[0x1];
 214         u8         outer_sip[0x1];
 215         u8         outer_dip[0x1];
 216         u8         outer_frag[0x1];
 217         u8         outer_ip_protocol[0x1];
 218         u8         outer_ip_ecn[0x1];
 219         u8         outer_ip_dscp[0x1];
 220         u8         outer_udp_sport[0x1];
 221         u8         outer_udp_dport[0x1];
 222         u8         outer_tcp_sport[0x1];
 223         u8         outer_tcp_dport[0x1];
 224         u8         outer_tcp_flags[0x1];
 225         u8         outer_gre_protocol[0x1];
 226         u8         outer_gre_key[0x1];
 227         u8         outer_vxlan_vni[0x1];
 228         u8         reserved_3[0x5];
 229         u8         source_eswitch_port[0x1];
 230
 231         u8         inner_dmac[0x1];
 232         u8         inner_smac[0x1];
 233         u8         inner_ether_type[0x1];
 234         u8         reserved_4[0x1];
 235         u8         inner_first_prio[0x1];
 236         u8         inner_first_cfi[0x1];
 237         u8         inner_first_vid[0x1];
 238         u8         reserved_5[0x1];
 239         u8         inner_second_prio[0x1];
 240         u8         inner_second_cfi[0x1];
 241         u8         inner_second_vid[0x1];
 242         u8         reserved_6[0x1];
 243         u8         inner_sip[0x1];
 244         u8         inner_dip[0x1];
 245         u8         inner_frag[0x1];
 246         u8         inner_ip_protocol[0x1];
 247         u8         inner_ip_ecn[0x1];
 248         u8         inner_ip_dscp[0x1];
 249         u8         inner_udp_sport[0x1];
 250         u8         inner_udp_dport[0x1];
 251         u8         inner_tcp_sport[0x1];
 252         u8         inner_tcp_dport[0x1];
 253         u8         inner_tcp_flags[0x1];
 254         u8         reserved_7[0x9];
 255
 256         u8         reserved_8[0x40];
 257 };
 258
 259 struct mlx5_ifc_flow_table_prop_layout_bits {
 260         u8         ft_support[0x1];
 261         u8         reserved_0[0x2];
 262         u8         flow_modify_en[0x1];
 263         u8         modify_root[0x1];
 264         u8         identified_miss_table_mode[0x1];
 265         u8         flow_table_modify[0x1];
 266         u8         reserved_1[0x19];
 267
 268         u8         reserved_2[0x2];
 269         u8         log_max_ft_size[0x6];
 270         u8         reserved_3[0x10];
 271         u8         max_ft_level[0x8];
 272
 273         u8         reserved_4[0x20];
 274
 275         u8         reserved_5[0x18];
 276         u8         log_max_ft_num[0x8];
 277
 278         u8         reserved_6[0x18];
 279         u8         log_max_destination[0x8];
 280
 281         u8         reserved_7[0x18];
 282         u8         log_max_flow[0x8];
 283
 284         u8         reserved_8[0x40];
 285
 286         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 287
 288         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 289 };
 290
 291 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 292         u8         send[0x1];
 293         u8         receive[0x1];
 294         u8         write[0x1];
 295         u8         read[0x1];
 296         u8         reserved_0[0x1];
 297         u8         srq_receive[0x1];
 298         u8         reserved_1[0x1a];
 299 };
 300
 301 struct mlx5_ifc_ipv4_layout_bits {
 302         u8         reserved_0[0x60];
 303
 304         u8         ipv4[0x20];
 305 };
 306
 307 struct mlx5_ifc_ipv6_layout_bits {
 308         u8         ipv6[16][0x8];
 309 };
 310
 311 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 312         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 313         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 314         u8         reserved_0[0x80];
 315 };
 316
 317 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 318         u8         smac_47_16[0x20];
 319
 320         u8         smac_15_0[0x10];
 321         u8         ethertype[0x10];
 322
 323         u8         dmac_47_16[0x20];
 324
 325         u8         dmac_15_0[0x10];
 326         u8         first_prio[0x3];
 327         u8         first_cfi[0x1];
 328         u8         first_vid[0xc];
 329
 330         u8         ip_protocol[0x8];
 331         u8         ip_dscp[0x6];
 332         u8         ip_ecn[0x2];
 333         u8         vlan_tag[0x1];
 334         u8         reserved_0[0x1];
 335         u8         frag[0x1];
 336         u8         reserved_1[0x4];
 337         u8         tcp_flags[0x9];
 338
 339         u8         tcp_sport[0x10];
 340         u8         tcp_dport[0x10];
 341
 342         u8         reserved_2[0x20];
 343
 344         u8         udp_sport[0x10];
 345         u8         udp_dport[0x10];
 346
 347         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 348
 349         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 350 };
 351
 352 struct mlx5_ifc_fte_match_set_misc_bits {
 353         u8         reserved_0[0x20];
 354
 355         u8         reserved_1[0x10];
 356         u8         source_port[0x10];
 357
 358         u8         outer_second_prio[0x3];
 359         u8         outer_second_cfi[0x1];
 360         u8         outer_second_vid[0xc];
 361         u8         inner_second_prio[0x3];
 362         u8         inner_second_cfi[0x1];
 363         u8         inner_second_vid[0xc];
 364
 365         u8         outer_second_vlan_tag[0x1];
 366         u8         inner_second_vlan_tag[0x1];
 367         u8         reserved_2[0xe];
 368         u8         gre_protocol[0x10];
 369
 370         u8         gre_key_h[0x18];
 371         u8         gre_key_l[0x8];
 372
 373         u8         vxlan_vni[0x18];
 374         u8         reserved_3[0x8];
 375
 376         u8         reserved_4[0x20];
 377
 378         u8         reserved_5[0xc];
 379         u8         outer_ipv6_flow_label[0x14];
 380
 381         u8         reserved_6[0xc];
 382         u8         inner_ipv6_flow_label[0x14];
 383
 384         u8         reserved_7[0xe0];
 385 };
 386
 387 struct mlx5_ifc_cmd_pas_bits {
 388         u8         pa_h[0x20];
 389
 390         u8         pa_l[0x14];
 391         u8         reserved_0[0xc];
 392 };
 393
 394 struct mlx5_ifc_uint64_bits {
 395         u8         hi[0x20];
 396
 397         u8         lo[0x20];
 398 };
 399
 400 enum {
 401         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 402         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 403         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 404         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 405         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 406         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 407         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 408         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 409         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 410         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 411 };
 412
 413 struct mlx5_ifc_ads_bits {
 414         u8         fl[0x1];
 415         u8         free_ar[0x1];
 416         u8         reserved_0[0xe];
 417         u8         pkey_index[0x10];
 418
 419         u8         reserved_1[0x8];
 420         u8         grh[0x1];
 421         u8         mlid[0x7];
 422         u8         rlid[0x10];
 423
 424         u8         ack_timeout[0x5];
 425         u8         reserved_2[0x3];
 426         u8         src_addr_index[0x8];
 427         u8         reserved_3[0x4];
 428         u8         stat_rate[0x4];
 429         u8         hop_limit[0x8];
 430
 431         u8         reserved_4[0x4];
 432         u8         tclass[0x8];
 433         u8         flow_label[0x14];
 434
 435         u8         rgid_rip[16][0x8];
 436
 437         u8         reserved_5[0x4];
 438         u8         f_dscp[0x1];
 439         u8         f_ecn[0x1];
 440         u8         reserved_6[0x1];
 441         u8         f_eth_prio[0x1];
 442         u8         ecn[0x2];
 443         u8         dscp[0x6];
 444         u8         udp_sport[0x10];
 445
 446         u8         dei_cfi[0x1];
 447         u8         eth_prio[0x3];
 448         u8         sl[0x4];
 449         u8         port[0x8];
 450         u8         rmac_47_32[0x10];
 451
 452         u8         rmac_31_0[0x20];
 453 };
 454
 455 struct mlx5_ifc_flow_table_nic_cap_bits {
 456         u8         reserved_0[0x200];
 457
 458         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 459
 460         u8         reserved_1[0x200];
 461
 462         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 463
 464         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 465
 466         u8         reserved_2[0x200];
 467
 468         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 469
 470         u8         reserved_3[0x7200];
 471 };
 472
 473 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 474         u8     reserved_0[0x200];
 475
 476         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 477
 478         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 479
 480         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 481
 482         u8      reserved_1[0x7800];
 483 };
 484
 485 struct mlx5_ifc_e_switch_cap_bits {
 486         u8         vport_svlan_strip[0x1];
 487         u8         vport_cvlan_strip[0x1];
 488         u8         vport_svlan_insert[0x1];
 489         u8         vport_cvlan_insert_if_not_exist[0x1];
 490         u8         vport_cvlan_insert_overwrite[0x1];
 491         u8         reserved_0[0x1b];
 492
 493         u8         reserved_1[0x7e0];
 494 };
 495
 496 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 497         u8         csum_cap[0x1];
 498         u8         vlan_cap[0x1];
 499         u8         lro_cap[0x1];
 500         u8         lro_psh_flag[0x1];
 501         u8         lro_time_stamp[0x1];
 502         u8         reserved_0[0x3];
 503         u8         self_lb_en_modifiable[0x1];
 504         u8         reserved_1[0x2];
 505         u8         max_lso_cap[0x5];
 506         u8         reserved_2[0x4];
 507         u8         rss_ind_tbl_cap[0x4];
 508         u8         reserved_3[0x3];
 509         u8         tunnel_lso_const_out_ip_id[0x1];
 510         u8         reserved_4[0x2];
 511         u8         tunnel_statless_gre[0x1];
 512         u8         tunnel_stateless_vxlan[0x1];
 513
 514         u8         reserved_5[0x20];
 515
 516         u8         reserved_6[0x10];
 517         u8         lro_min_mss_size[0x10];
 518
 519         u8         reserved_7[0x120];
 520
 521         u8         lro_timer_supported_periods[4][0x20];
 522
 523         u8         reserved_8[0x600];
 524 };
 525
 526 struct mlx5_ifc_roce_cap_bits {
 527         u8         roce_apm[0x1];
 528         u8         reserved_0[0x1f];
 529
 530         u8         reserved_1[0x60];
 531
 532         u8         reserved_2[0xc];
 533         u8         l3_type[0x4];
 534         u8         reserved_3[0x8];
 535         u8         roce_version[0x8];
 536
 537         u8         reserved_4[0x10];
 538         u8         r_roce_dest_udp_port[0x10];
 539
 540         u8         r_roce_max_src_udp_port[0x10];
 541         u8         r_roce_min_src_udp_port[0x10];
 542
 543         u8         reserved_5[0x10];
 544         u8         roce_address_table_size[0x10];
 545
 546         u8         reserved_6[0x700];
 547 };
 548
 549 enum {
 550         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 551         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 552         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 553         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 554         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 555         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 556         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 557         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 558         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 559 };
 560
 561 enum {
 562         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 563         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 564         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 565         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 566         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 567         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 568         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 569         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 570         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 571 };
 572
 573 struct mlx5_ifc_atomic_caps_bits {
 574         u8         reserved_0[0x40];
 575
 576         u8         atomic_req_endianness[0x1];
 577         u8         reserved_1[0x1f];
 578
 579         u8         reserved_2[0x20];
 580
 581         u8         reserved_3[0x10];
 582         u8         atomic_operations[0x10];
 583
 584         u8         reserved_4[0x10];
 585         u8         atomic_size_qp[0x10];
 586
 587         u8         reserved_5[0x10];
 588         u8         atomic_size_dc[0x10];
 589
 590         u8         reserved_6[0x720];
 591 };
 592
 593 struct mlx5_ifc_odp_cap_bits {
 594         u8         reserved_0[0x40];
 595
 596         u8         sig[0x1];
 597         u8         reserved_1[0x1f];
 598
 599         u8         reserved_2[0x20];
 600
 601         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 602
 603         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 604
 605         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 606
 607         u8         reserved_3[0x720];
 608 };
 609
 610 enum {
 611         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 612         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 613         MLX5_WQ_TYPE_STRQ         = 0x2,
 614 };
 615
 616 enum {
 617         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 618         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 619 };
 620
 621 enum {
 622         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 623         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 624         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 625         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 626         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 627 };
 628
 629 enum {
 630         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 631         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 632         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 633         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 634         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 635         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 636 };
 637
 638 enum {
 639         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 640         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 641 };
 642
 643 enum {
 644         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 645         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 646         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 647 };
 648
 649 enum {
 650         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 651         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 652 };
 653
 654 struct mlx5_ifc_cmd_hca_cap_bits {
 655         u8         reserved_0[0x80];
 656
 657         u8         log_max_srq_sz[0x8];
 658         u8         log_max_qp_sz[0x8];
 659         u8         reserved_1[0xb];
 660         u8         log_max_qp[0x5];
 661
 662         u8         reserved_2[0xb];
 663         u8         log_max_srq[0x5];
 664         u8         reserved_3[0x10];
 665
 666         u8         reserved_4[0x8];
 667         u8         log_max_cq_sz[0x8];
 668         u8         reserved_5[0xb];
 669         u8         log_max_cq[0x5];
 670
 671         u8         log_max_eq_sz[0x8];
 672         u8         reserved_6[0x2];
 673         u8         log_max_mkey[0x6];
 674         u8         reserved_7[0xc];
 675         u8         log_max_eq[0x4];
 676
 677         u8         max_indirection[0x8];
 678         u8         reserved_8[0x1];
 679         u8         log_max_mrw_sz[0x7];
 680         u8         reserved_9[0x2];
 681         u8         log_max_bsf_list_size[0x6];
 682         u8         reserved_10[0x2];
 683         u8         log_max_klm_list_size[0x6];
 684
 685         u8         reserved_11[0xa];
 686         u8         log_max_ra_req_dc[0x6];
 687         u8         reserved_12[0xa];
 688         u8         log_max_ra_res_dc[0x6];
 689
 690         u8         reserved_13[0xa];
 691         u8         log_max_ra_req_qp[0x6];
 692         u8         reserved_14[0xa];
 693         u8         log_max_ra_res_qp[0x6];
 694
 695         u8         pad_cap[0x1];
 696         u8         cc_query_allowed[0x1];
 697         u8         cc_modify_allowed[0x1];
 698         u8         reserved_15[0xd];
 699         u8         gid_table_size[0x10];
 700
 701         u8         out_of_seq_cnt[0x1];
 702         u8         vport_counters[0x1];
 703         u8         reserved_16[0x4];
 704         u8         max_qp_cnt[0xa];
 705         u8         pkey_table_size[0x10];
 706
 707         u8         vport_group_manager[0x1];
 708         u8         vhca_group_manager[0x1];
 709         u8         ib_virt[0x1];
 710         u8         eth_virt[0x1];
 711         u8         reserved_17[0x1];
 712         u8         ets[0x1];
 713         u8         nic_flow_table[0x1];
 714         u8         eswitch_flow_table[0x1];
 715         u8         early_vf_enable;
 716         u8         reserved_18[0x2];
 717         u8         local_ca_ack_delay[0x5];
 718         u8         reserved_19[0x6];
 719         u8         port_type[0x2];
 720         u8         num_ports[0x8];
 721
 722         u8         reserved_20[0x3];
 723         u8         log_max_msg[0x5];
 724         u8         reserved_21[0x18];
 725
 726         u8         stat_rate_support[0x10];
 727         u8         reserved_22[0xc];
 728         u8         cqe_version[0x4];
 729
 730         u8         compact_address_vector[0x1];
 731         u8         reserved_23[0xe];
 732         u8         drain_sigerr[0x1];
 733         u8         cmdif_checksum[0x2];
 734         u8         sigerr_cqe[0x1];
 735         u8         reserved_24[0x1];
 736         u8         wq_signature[0x1];
 737         u8         sctr_data_cqe[0x1];
 738         u8         reserved_25[0x1];
 739         u8         sho[0x1];
 740         u8         tph[0x1];
 741         u8         rf[0x1];
 742         u8         dct[0x1];
 743         u8         reserved_26[0x1];
 744         u8         eth_net_offloads[0x1];
 745         u8         roce[0x1];
 746         u8         atomic[0x1];
 747         u8         reserved_27[0x1];
 748
 749         u8         cq_oi[0x1];
 750         u8         cq_resize[0x1];
 751         u8         cq_moderation[0x1];
 752         u8         reserved_28[0x3];
 753         u8         cq_eq_remap[0x1];
 754         u8         pg[0x1];
 755         u8         block_lb_mc[0x1];
 756         u8         reserved_29[0x1];
 757         u8         scqe_break_moderation[0x1];
 758         u8         reserved_30[0x1];
 759         u8         cd[0x1];
 760         u8         reserved_31[0x1];
 761         u8         apm[0x1];
 762         u8         reserved_32[0x7];
 763         u8         qkv[0x1];
 764         u8         pkv[0x1];
 765         u8         reserved_33[0x4];
 766         u8         xrc[0x1];
 767         u8         ud[0x1];
 768         u8         uc[0x1];
 769         u8         rc[0x1];
 770
 771         u8         reserved_34[0xa];
 772         u8         uar_sz[0x6];
 773         u8         reserved_35[0x8];
 774         u8         log_pg_sz[0x8];
 775
 776         u8         bf[0x1];
 777         u8         reserved_36[0x1];
 778         u8         pad_tx_eth_packet[0x1];
 779         u8         reserved_37[0x8];
 780         u8         log_bf_reg_size[0x5];
 781         u8         reserved_38[0x10];
 782
 783         u8         reserved_39[0x10];
 784         u8         max_wqe_sz_sq[0x10];
 785
 786         u8         reserved_40[0x10];
 787         u8         max_wqe_sz_rq[0x10];
 788
 789         u8         reserved_41[0x10];
 790         u8         max_wqe_sz_sq_dc[0x10];
 791
 792         u8         reserved_42[0x7];
 793         u8         max_qp_mcg[0x19];
 794
 795         u8         reserved_43[0x18];
 796         u8         log_max_mcg[0x8];
 797
 798         u8         reserved_44[0x3];
 799         u8         log_max_transport_domain[0x5];
 800         u8         reserved_45[0x3];
 801         u8         log_max_pd[0x5];
 802         u8         reserved_46[0xb];
 803         u8         log_max_xrcd[0x5];
 804
 805         u8         reserved_47[0x20];
 806
 807         u8         reserved_48[0x3];
 808         u8         log_max_rq[0x5];
 809         u8         reserved_49[0x3];
 810         u8         log_max_sq[0x5];
 811         u8         reserved_50[0x3];
 812         u8         log_max_tir[0x5];
 813         u8         reserved_51[0x3];
 814         u8         log_max_tis[0x5];
 815
 816         u8         basic_cyclic_rcv_wqe[0x1];
 817         u8         reserved_52[0x2];
 818         u8         log_max_rmp[0x5];
 819         u8         reserved_53[0x3];
 820         u8         log_max_rqt[0x5];
 821         u8         reserved_54[0x3];
 822         u8         log_max_rqt_size[0x5];
 823         u8         reserved_55[0x3];
 824         u8         log_max_tis_per_sq[0x5];
 825
 826         u8         reserved_56[0x3];
 827         u8         log_max_stride_sz_rq[0x5];
 828         u8         reserved_57[0x3];
 829         u8         log_min_stride_sz_rq[0x5];
 830         u8         reserved_58[0x3];
 831         u8         log_max_stride_sz_sq[0x5];
 832         u8         reserved_59[0x3];
 833         u8         log_min_stride_sz_sq[0x5];
 834
 835         u8         reserved_60[0x1b];
 836         u8         log_max_wq_sz[0x5];
 837
 838         u8         nic_vport_change_event[0x1];
 839         u8         reserved_61[0xa];
 840         u8         log_max_vlan_list[0x5];
 841         u8         reserved_62[0x3];
 842         u8         log_max_current_mc_list[0x5];
 843         u8         reserved_63[0x3];
 844         u8         log_max_current_uc_list[0x5];
 845
 846         u8         reserved_64[0x80];
 847
 848         u8         reserved_65[0x3];
 849         u8         log_max_l2_table[0x5];
 850         u8         reserved_66[0x8];
 851         u8         log_uar_page_sz[0x10];
 852
 853         u8         reserved_67[0x40];
 854         u8         device_frequency_khz[0x20];
 855         u8         reserved_68[0x5f];
 856         u8         cqe_zip[0x1];
 857
 858         u8         cqe_zip_timeout[0x10];
 859         u8         cqe_zip_max_num[0x10];
 860
 861         u8         reserved_69[0x220];
 862 };
 863
 864 enum mlx5_flow_destination_type {
 865         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
 866         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
 867         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
 868 };
 869
 870 struct mlx5_ifc_dest_format_struct_bits {
 871         u8         destination_type[0x8];
 872         u8         destination_id[0x18];
 873
 874         u8         reserved_0[0x20];
 875 };
 876
 877 struct mlx5_ifc_fte_match_param_bits {
 878         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 879
 880         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 881
 882         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 883
 884         u8         reserved_0[0xa00];
 885 };
 886
 887 enum {
 888         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 889         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 890         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 891         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 892         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 893 };
 894
 895 struct mlx5_ifc_rx_hash_field_select_bits {
 896         u8         l3_prot_type[0x1];
 897         u8         l4_prot_type[0x1];
 898         u8         selected_fields[0x1e];
 899 };
 900
 901 enum {
 902         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
 903         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
 904 };
 905
 906 enum {
 907         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
 908         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
 909 };
 910
 911 struct mlx5_ifc_wq_bits {
 912         u8         wq_type[0x4];
 913         u8         wq_signature[0x1];
 914         u8         end_padding_mode[0x2];
 915         u8         cd_slave[0x1];
 916         u8         reserved_0[0x18];
 917
 918         u8         hds_skip_first_sge[0x1];
 919         u8         log2_hds_buf_size[0x3];
 920         u8         reserved_1[0x7];
 921         u8         page_offset[0x5];
 922         u8         lwm[0x10];
 923
 924         u8         reserved_2[0x8];
 925         u8         pd[0x18];
 926
 927         u8         reserved_3[0x8];
 928         u8         uar_page[0x18];
 929
 930         u8         dbr_addr[0x40];
 931
 932         u8         hw_counter[0x20];
 933
 934         u8         sw_counter[0x20];
 935
 936         u8         reserved_4[0xc];
 937         u8         log_wq_stride[0x4];
 938         u8         reserved_5[0x3];
 939         u8         log_wq_pg_sz[0x5];
 940         u8         reserved_6[0x3];
 941         u8         log_wq_sz[0x5];
 942
 943         u8         reserved_7[0x4e0];
 944
 945         struct mlx5_ifc_cmd_pas_bits pas[0];
 946 };
 947
 948 struct mlx5_ifc_rq_num_bits {
 949         u8         reserved_0[0x8];
 950         u8         rq_num[0x18];
 951 };
 952
 953 struct mlx5_ifc_mac_address_layout_bits {
 954         u8         reserved_0[0x10];
 955         u8         mac_addr_47_32[0x10];
 956
 957         u8         mac_addr_31_0[0x20];
 958 };
 959
 960 struct mlx5_ifc_vlan_layout_bits {
 961         u8         reserved_0[0x14];
 962         u8         vlan[0x0c];
 963
 964         u8         reserved_1[0x20];
 965 };
 966
 967 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 968         u8         reserved_0[0xa0];
 969
 970         u8         min_time_between_cnps[0x20];
 971
 972         u8         reserved_1[0x12];
 973         u8         cnp_dscp[0x6];
 974         u8         reserved_2[0x5];
 975         u8         cnp_802p_prio[0x3];
 976
 977         u8         reserved_3[0x720];
 978 };
 979
 980 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
 981         u8         reserved_0[0x60];
 982
 983         u8         reserved_1[0x4];
 984         u8         clamp_tgt_rate[0x1];
 985         u8         reserved_2[0x3];
 986         u8         clamp_tgt_rate_after_time_inc[0x1];
 987         u8         reserved_3[0x17];
 988
 989         u8         reserved_4[0x20];
 990
 991         u8         rpg_time_reset[0x20];
 992
 993         u8         rpg_byte_reset[0x20];
 994
 995         u8         rpg_threshold[0x20];
 996
 997         u8         rpg_max_rate[0x20];
 998
 999         u8         rpg_ai_rate[0x20];
1000
1001         u8         rpg_hai_rate[0x20];
1002
1003         u8         rpg_gd[0x20];
1004
1005         u8         rpg_min_dec_fac[0x20];
1006
1007         u8         rpg_min_rate[0x20];
1008
1009         u8         reserved_5[0xe0];
1010
1011         u8         rate_to_set_on_first_cnp[0x20];
1012
1013         u8         dce_tcp_g[0x20];
1014
1015         u8         dce_tcp_rtt[0x20];
1016
1017         u8         rate_reduce_monitor_period[0x20];
1018
1019         u8         reserved_6[0x20];
1020
1021         u8         initial_alpha_value[0x20];
1022
1023         u8         reserved_7[0x4a0];
1024 };
1025
1026 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1027         u8         reserved_0[0x80];
1028
1029         u8         rppp_max_rps[0x20];
1030
1031         u8         rpg_time_reset[0x20];
1032
1033         u8         rpg_byte_reset[0x20];
1034
1035         u8         rpg_threshold[0x20];
1036
1037         u8         rpg_max_rate[0x20];
1038
1039         u8         rpg_ai_rate[0x20];
1040
1041         u8         rpg_hai_rate[0x20];
1042
1043         u8         rpg_gd[0x20];
1044
1045         u8         rpg_min_dec_fac[0x20];
1046
1047         u8         rpg_min_rate[0x20];
1048
1049         u8         reserved_1[0x640];
1050 };
1051
1052 enum {
1053         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1054         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1055         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1056 };
1057
1058 struct mlx5_ifc_resize_field_select_bits {
1059         u8         resize_field_select[0x20];
1060 };
1061
1062 enum {
1063         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1064         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1065         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1066         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1067 };
1068
1069 struct mlx5_ifc_modify_field_select_bits {
1070         u8         modify_field_select[0x20];
1071 };
1072
1073 struct mlx5_ifc_field_select_r_roce_np_bits {
1074         u8         field_select_r_roce_np[0x20];
1075 };
1076
1077 struct mlx5_ifc_field_select_r_roce_rp_bits {
1078         u8         field_select_r_roce_rp[0x20];
1079 };
1080
1081 enum {
1082         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1083         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1084         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1085         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1086         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1087         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1088         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1089         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1090         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1091         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1092 };
1093
1094 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1095         u8         field_select_8021qaurp[0x20];
1096 };
1097
1098 struct mlx5_ifc_phys_layer_cntrs_bits {
1099         u8         time_since_last_clear_high[0x20];
1100
1101         u8         time_since_last_clear_low[0x20];
1102
1103         u8         symbol_errors_high[0x20];
1104
1105         u8         symbol_errors_low[0x20];
1106
1107         u8         sync_headers_errors_high[0x20];
1108
1109         u8         sync_headers_errors_low[0x20];
1110
1111         u8         edpl_bip_errors_lane0_high[0x20];
1112
1113         u8         edpl_bip_errors_lane0_low[0x20];
1114
1115         u8         edpl_bip_errors_lane1_high[0x20];
1116
1117         u8         edpl_bip_errors_lane1_low[0x20];
1118
1119         u8         edpl_bip_errors_lane2_high[0x20];
1120
1121         u8         edpl_bip_errors_lane2_low[0x20];
1122
1123         u8         edpl_bip_errors_lane3_high[0x20];
1124
1125         u8         edpl_bip_errors_lane3_low[0x20];
1126
1127         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1128
1129         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1130
1131         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1132
1133         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1134
1135         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1136
1137         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1138
1139         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1140
1141         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1142
1143         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1144
1145         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1146
1147         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1148
1149         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1150
1151         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1152
1153         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1154
1155         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1156
1157         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1158
1159         u8         rs_fec_corrected_blocks_high[0x20];
1160
1161         u8         rs_fec_corrected_blocks_low[0x20];
1162
1163         u8         rs_fec_uncorrectable_blocks_high[0x20];
1164
1165         u8         rs_fec_uncorrectable_blocks_low[0x20];
1166
1167         u8         rs_fec_no_errors_blocks_high[0x20];
1168
1169         u8         rs_fec_no_errors_blocks_low[0x20];
1170
1171         u8         rs_fec_single_error_blocks_high[0x20];
1172
1173         u8         rs_fec_single_error_blocks_low[0x20];
1174
1175         u8         rs_fec_corrected_symbols_total_high[0x20];
1176
1177         u8         rs_fec_corrected_symbols_total_low[0x20];
1178
1179         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1180
1181         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1182
1183         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1184
1185         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1186
1187         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1188
1189         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1190
1191         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1192
1193         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1194
1195         u8         link_down_events[0x20];
1196
1197         u8         successful_recovery_events[0x20];
1198
1199         u8         reserved_0[0x180];
1200 };
1201
1202 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1203         u8         transmit_queue_high[0x20];
1204
1205         u8         transmit_queue_low[0x20];
1206
1207         u8         reserved_0[0x780];
1208 };
1209
1210 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1211         u8         rx_octets_high[0x20];
1212
1213         u8         rx_octets_low[0x20];
1214
1215         u8         reserved_0[0xc0];
1216
1217         u8         rx_frames_high[0x20];
1218
1219         u8         rx_frames_low[0x20];
1220
1221         u8         tx_octets_high[0x20];
1222
1223         u8         tx_octets_low[0x20];
1224
1225         u8         reserved_1[0xc0];
1226
1227         u8         tx_frames_high[0x20];
1228
1229         u8         tx_frames_low[0x20];
1230
1231         u8         rx_pause_high[0x20];
1232
1233         u8         rx_pause_low[0x20];
1234
1235         u8         rx_pause_duration_high[0x20];
1236
1237         u8         rx_pause_duration_low[0x20];
1238
1239         u8         tx_pause_high[0x20];
1240
1241         u8         tx_pause_low[0x20];
1242
1243         u8         tx_pause_duration_high[0x20];
1244
1245         u8         tx_pause_duration_low[0x20];
1246
1247         u8         rx_pause_transition_high[0x20];
1248
1249         u8         rx_pause_transition_low[0x20];
1250
1251         u8         reserved_2[0x400];
1252 };
1253
1254 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1255         u8         port_transmit_wait_high[0x20];
1256
1257         u8         port_transmit_wait_low[0x20];
1258
1259         u8         reserved_0[0x780];
1260 };
1261
1262 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1263         u8         dot3stats_alignment_errors_high[0x20];
1264
1265         u8         dot3stats_alignment_errors_low[0x20];
1266
1267         u8         dot3stats_fcs_errors_high[0x20];
1268
1269         u8         dot3stats_fcs_errors_low[0x20];
1270
1271         u8         dot3stats_single_collision_frames_high[0x20];
1272
1273         u8         dot3stats_single_collision_frames_low[0x20];
1274
1275         u8         dot3stats_multiple_collision_frames_high[0x20];
1276
1277         u8         dot3stats_multiple_collision_frames_low[0x20];
1278
1279         u8         dot3stats_sqe_test_errors_high[0x20];
1280
1281         u8         dot3stats_sqe_test_errors_low[0x20];
1282
1283         u8         dot3stats_deferred_transmissions_high[0x20];
1284
1285         u8         dot3stats_deferred_transmissions_low[0x20];
1286
1287         u8         dot3stats_late_collisions_high[0x20];
1288
1289         u8         dot3stats_late_collisions_low[0x20];
1290
1291         u8         dot3stats_excessive_collisions_high[0x20];
1292
1293         u8         dot3stats_excessive_collisions_low[0x20];
1294
1295         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1296
1297         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1298
1299         u8         dot3stats_carrier_sense_errors_high[0x20];
1300
1301         u8         dot3stats_carrier_sense_errors_low[0x20];
1302
1303         u8         dot3stats_frame_too_longs_high[0x20];
1304
1305         u8         dot3stats_frame_too_longs_low[0x20];
1306
1307         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1308
1309         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1310
1311         u8         dot3stats_symbol_errors_high[0x20];
1312
1313         u8         dot3stats_symbol_errors_low[0x20];
1314
1315         u8         dot3control_in_unknown_opcodes_high[0x20];
1316
1317         u8         dot3control_in_unknown_opcodes_low[0x20];
1318
1319         u8         dot3in_pause_frames_high[0x20];
1320
1321         u8         dot3in_pause_frames_low[0x20];
1322
1323         u8         dot3out_pause_frames_high[0x20];
1324
1325         u8         dot3out_pause_frames_low[0x20];
1326
1327         u8         reserved_0[0x3c0];
1328 };
1329
1330 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1331         u8         ether_stats_drop_events_high[0x20];
1332
1333         u8         ether_stats_drop_events_low[0x20];
1334
1335         u8         ether_stats_octets_high[0x20];
1336
1337         u8         ether_stats_octets_low[0x20];
1338
1339         u8         ether_stats_pkts_high[0x20];
1340
1341         u8         ether_stats_pkts_low[0x20];
1342
1343         u8         ether_stats_broadcast_pkts_high[0x20];
1344
1345         u8         ether_stats_broadcast_pkts_low[0x20];
1346
1347         u8         ether_stats_multicast_pkts_high[0x20];
1348
1349         u8         ether_stats_multicast_pkts_low[0x20];
1350
1351         u8         ether_stats_crc_align_errors_high[0x20];
1352
1353         u8         ether_stats_crc_align_errors_low[0x20];
1354
1355         u8         ether_stats_undersize_pkts_high[0x20];
1356
1357         u8         ether_stats_undersize_pkts_low[0x20];
1358
1359         u8         ether_stats_oversize_pkts_high[0x20];
1360
1361         u8         ether_stats_oversize_pkts_low[0x20];
1362
1363         u8         ether_stats_fragments_high[0x20];
1364
1365         u8         ether_stats_fragments_low[0x20];
1366
1367         u8         ether_stats_jabbers_high[0x20];
1368
1369         u8         ether_stats_jabbers_low[0x20];
1370
1371         u8         ether_stats_collisions_high[0x20];
1372
1373         u8         ether_stats_collisions_low[0x20];
1374
1375         u8         ether_stats_pkts64octets_high[0x20];
1376
1377         u8         ether_stats_pkts64octets_low[0x20];
1378
1379         u8         ether_stats_pkts65to127octets_high[0x20];
1380
1381         u8         ether_stats_pkts65to127octets_low[0x20];
1382
1383         u8         ether_stats_pkts128to255octets_high[0x20];
1384
1385         u8         ether_stats_pkts128to255octets_low[0x20];
1386
1387         u8         ether_stats_pkts256to511octets_high[0x20];
1388
1389         u8         ether_stats_pkts256to511octets_low[0x20];
1390
1391         u8         ether_stats_pkts512to1023octets_high[0x20];
1392
1393         u8         ether_stats_pkts512to1023octets_low[0x20];
1394
1395         u8         ether_stats_pkts1024to1518octets_high[0x20];
1396
1397         u8         ether_stats_pkts1024to1518octets_low[0x20];
1398
1399         u8         ether_stats_pkts1519to2047octets_high[0x20];
1400
1401         u8         ether_stats_pkts1519to2047octets_low[0x20];
1402
1403         u8         ether_stats_pkts2048to4095octets_high[0x20];
1404
1405         u8         ether_stats_pkts2048to4095octets_low[0x20];
1406
1407         u8         ether_stats_pkts4096to8191octets_high[0x20];
1408
1409         u8         ether_stats_pkts4096to8191octets_low[0x20];
1410
1411         u8         ether_stats_pkts8192to10239octets_high[0x20];
1412
1413         u8         ether_stats_pkts8192to10239octets_low[0x20];
1414
1415         u8         reserved_0[0x280];
1416 };
1417
1418 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1419         u8         if_in_octets_high[0x20];
1420
1421         u8         if_in_octets_low[0x20];
1422
1423         u8         if_in_ucast_pkts_high[0x20];
1424
1425         u8         if_in_ucast_pkts_low[0x20];
1426
1427         u8         if_in_discards_high[0x20];
1428
1429         u8         if_in_discards_low[0x20];
1430
1431         u8         if_in_errors_high[0x20];
1432
1433         u8         if_in_errors_low[0x20];
1434
1435         u8         if_in_unknown_protos_high[0x20];
1436
1437         u8         if_in_unknown_protos_low[0x20];
1438
1439         u8         if_out_octets_high[0x20];
1440
1441         u8         if_out_octets_low[0x20];
1442
1443         u8         if_out_ucast_pkts_high[0x20];
1444
1445         u8         if_out_ucast_pkts_low[0x20];
1446
1447         u8         if_out_discards_high[0x20];
1448
1449         u8         if_out_discards_low[0x20];
1450
1451         u8         if_out_errors_high[0x20];
1452
1453         u8         if_out_errors_low[0x20];
1454
1455         u8         if_in_multicast_pkts_high[0x20];
1456
1457         u8         if_in_multicast_pkts_low[0x20];
1458
1459         u8         if_in_broadcast_pkts_high[0x20];
1460
1461         u8         if_in_broadcast_pkts_low[0x20];
1462
1463         u8         if_out_multicast_pkts_high[0x20];
1464
1465         u8         if_out_multicast_pkts_low[0x20];
1466
1467         u8         if_out_broadcast_pkts_high[0x20];
1468
1469         u8         if_out_broadcast_pkts_low[0x20];
1470
1471         u8         reserved_0[0x480];
1472 };
1473
1474 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1475         u8         a_frames_transmitted_ok_high[0x20];
1476
1477         u8         a_frames_transmitted_ok_low[0x20];
1478
1479         u8         a_frames_received_ok_high[0x20];
1480
1481         u8         a_frames_received_ok_low[0x20];
1482
1483         u8         a_frame_check_sequence_errors_high[0x20];
1484
1485         u8         a_frame_check_sequence_errors_low[0x20];
1486
1487         u8         a_alignment_errors_high[0x20];
1488
1489         u8         a_alignment_errors_low[0x20];
1490
1491         u8         a_octets_transmitted_ok_high[0x20];
1492
1493         u8         a_octets_transmitted_ok_low[0x20];
1494
1495         u8         a_octets_received_ok_high[0x20];
1496
1497         u8         a_octets_received_ok_low[0x20];
1498
1499         u8         a_multicast_frames_xmitted_ok_high[0x20];
1500
1501         u8         a_multicast_frames_xmitted_ok_low[0x20];
1502
1503         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1504
1505         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1506
1507         u8         a_multicast_frames_received_ok_high[0x20];
1508
1509         u8         a_multicast_frames_received_ok_low[0x20];
1510
1511         u8         a_broadcast_frames_received_ok_high[0x20];
1512
1513         u8         a_broadcast_frames_received_ok_low[0x20];
1514
1515         u8         a_in_range_length_errors_high[0x20];
1516
1517         u8         a_in_range_length_errors_low[0x20];
1518
1519         u8         a_out_of_range_length_field_high[0x20];
1520
1521         u8         a_out_of_range_length_field_low[0x20];
1522
1523         u8         a_frame_too_long_errors_high[0x20];
1524
1525         u8         a_frame_too_long_errors_low[0x20];
1526
1527         u8         a_symbol_error_during_carrier_high[0x20];
1528
1529         u8         a_symbol_error_during_carrier_low[0x20];
1530
1531         u8         a_mac_control_frames_transmitted_high[0x20];
1532
1533         u8         a_mac_control_frames_transmitted_low[0x20];
1534
1535         u8         a_mac_control_frames_received_high[0x20];
1536
1537         u8         a_mac_control_frames_received_low[0x20];
1538
1539         u8         a_unsupported_opcodes_received_high[0x20];
1540
1541         u8         a_unsupported_opcodes_received_low[0x20];
1542
1543         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1544
1545         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1546
1547         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1548
1549         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1550
1551         u8         reserved_0[0x300];
1552 };
1553
1554 struct mlx5_ifc_cmd_inter_comp_event_bits {
1555         u8         command_completion_vector[0x20];
1556
1557         u8         reserved_0[0xc0];
1558 };
1559
1560 struct mlx5_ifc_stall_vl_event_bits {
1561         u8         reserved_0[0x18];
1562         u8         port_num[0x1];
1563         u8         reserved_1[0x3];
1564         u8         vl[0x4];
1565
1566         u8         reserved_2[0xa0];
1567 };
1568
1569 struct mlx5_ifc_db_bf_congestion_event_bits {
1570         u8         event_subtype[0x8];
1571         u8         reserved_0[0x8];
1572         u8         congestion_level[0x8];
1573         u8         reserved_1[0x8];
1574
1575         u8         reserved_2[0xa0];
1576 };
1577
1578 struct mlx5_ifc_gpio_event_bits {
1579         u8         reserved_0[0x60];
1580
1581         u8         gpio_event_hi[0x20];
1582
1583         u8         gpio_event_lo[0x20];
1584
1585         u8         reserved_1[0x40];
1586 };
1587
1588 struct mlx5_ifc_port_state_change_event_bits {
1589         u8         reserved_0[0x40];
1590
1591         u8         port_num[0x4];
1592         u8         reserved_1[0x1c];
1593
1594         u8         reserved_2[0x80];
1595 };
1596
1597 struct mlx5_ifc_dropped_packet_logged_bits {
1598         u8         reserved_0[0xe0];
1599 };
1600
1601 enum {
1602         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1603         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1604 };
1605
1606 struct mlx5_ifc_cq_error_bits {
1607         u8         reserved_0[0x8];
1608         u8         cqn[0x18];
1609
1610         u8         reserved_1[0x20];
1611
1612         u8         reserved_2[0x18];
1613         u8         syndrome[0x8];
1614
1615         u8         reserved_3[0x80];
1616 };
1617
1618 struct mlx5_ifc_rdma_page_fault_event_bits {
1619         u8         bytes_committed[0x20];
1620
1621         u8         r_key[0x20];
1622
1623         u8         reserved_0[0x10];
1624         u8         packet_len[0x10];
1625
1626         u8         rdma_op_len[0x20];
1627
1628         u8         rdma_va[0x40];
1629
1630         u8         reserved_1[0x5];
1631         u8         rdma[0x1];
1632         u8         write[0x1];
1633         u8         requestor[0x1];
1634         u8         qp_number[0x18];
1635 };
1636
1637 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1638         u8         bytes_committed[0x20];
1639
1640         u8         reserved_0[0x10];
1641         u8         wqe_index[0x10];
1642
1643         u8         reserved_1[0x10];
1644         u8         len[0x10];
1645
1646         u8         reserved_2[0x60];
1647
1648         u8         reserved_3[0x5];
1649         u8         rdma[0x1];
1650         u8         write_read[0x1];
1651         u8         requestor[0x1];
1652         u8         qpn[0x18];
1653 };
1654
1655 struct mlx5_ifc_qp_events_bits {
1656         u8         reserved_0[0xa0];
1657
1658         u8         type[0x8];
1659         u8         reserved_1[0x18];
1660
1661         u8         reserved_2[0x8];
1662         u8         qpn_rqn_sqn[0x18];
1663 };
1664
1665 struct mlx5_ifc_dct_events_bits {
1666         u8         reserved_0[0xc0];
1667
1668         u8         reserved_1[0x8];
1669         u8         dct_number[0x18];
1670 };
1671
1672 struct mlx5_ifc_comp_event_bits {
1673         u8         reserved_0[0xc0];
1674
1675         u8         reserved_1[0x8];
1676         u8         cq_number[0x18];
1677 };
1678
1679 enum {
1680         MLX5_QPC_STATE_RST        = 0x0,
1681         MLX5_QPC_STATE_INIT       = 0x1,
1682         MLX5_QPC_STATE_RTR        = 0x2,
1683         MLX5_QPC_STATE_RTS        = 0x3,
1684         MLX5_QPC_STATE_SQER       = 0x4,
1685         MLX5_QPC_STATE_ERR        = 0x6,
1686         MLX5_QPC_STATE_SQD        = 0x7,
1687         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1688 };
1689
1690 enum {
1691         MLX5_QPC_ST_RC            = 0x0,
1692         MLX5_QPC_ST_UC            = 0x1,
1693         MLX5_QPC_ST_UD            = 0x2,
1694         MLX5_QPC_ST_XRC           = 0x3,
1695         MLX5_QPC_ST_DCI           = 0x5,
1696         MLX5_QPC_ST_QP0           = 0x7,
1697         MLX5_QPC_ST_QP1           = 0x8,
1698         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1699         MLX5_QPC_ST_REG_UMR       = 0xc,
1700 };
1701
1702 enum {
1703         MLX5_QPC_PM_STATE_ARMED     = 0x0,
1704         MLX5_QPC_PM_STATE_REARM     = 0x1,
1705         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
1706         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
1707 };
1708
1709 enum {
1710         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
1711         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
1712 };
1713
1714 enum {
1715         MLX5_QPC_MTU_256_BYTES        = 0x1,
1716         MLX5_QPC_MTU_512_BYTES        = 0x2,
1717         MLX5_QPC_MTU_1K_BYTES         = 0x3,
1718         MLX5_QPC_MTU_2K_BYTES         = 0x4,
1719         MLX5_QPC_MTU_4K_BYTES         = 0x5,
1720         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
1721 };
1722
1723 enum {
1724         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
1725         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
1726         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
1727         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
1728         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
1729         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
1730         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
1731         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
1732 };
1733
1734 enum {
1735         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
1736         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
1737         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
1738 };
1739
1740 enum {
1741         MLX5_QPC_CS_RES_DISABLE    = 0x0,
1742         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
1743         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
1744 };
1745
1746 struct mlx5_ifc_qpc_bits {
1747         u8         state[0x4];
1748         u8         reserved_0[0x4];
1749         u8         st[0x8];
1750         u8         reserved_1[0x3];
1751         u8         pm_state[0x2];
1752         u8         reserved_2[0x7];
1753         u8         end_padding_mode[0x2];
1754         u8         reserved_3[0x2];
1755
1756         u8         wq_signature[0x1];
1757         u8         block_lb_mc[0x1];
1758         u8         atomic_like_write_en[0x1];
1759         u8         latency_sensitive[0x1];
1760         u8         reserved_4[0x1];
1761         u8         drain_sigerr[0x1];
1762         u8         reserved_5[0x2];
1763         u8         pd[0x18];
1764
1765         u8         mtu[0x3];
1766         u8         log_msg_max[0x5];
1767         u8         reserved_6[0x1];
1768         u8         log_rq_size[0x4];
1769         u8         log_rq_stride[0x3];
1770         u8         no_sq[0x1];
1771         u8         log_sq_size[0x4];
1772         u8         reserved_7[0x6];
1773         u8         rlky[0x1];
1774         u8         reserved_8[0x4];
1775
1776         u8         counter_set_id[0x8];
1777         u8         uar_page[0x18];
1778
1779         u8         reserved_9[0x8];
1780         u8         user_index[0x18];
1781
1782         u8         reserved_10[0x3];
1783         u8         log_page_size[0x5];
1784         u8         remote_qpn[0x18];
1785
1786         struct mlx5_ifc_ads_bits primary_address_path;
1787
1788         struct mlx5_ifc_ads_bits secondary_address_path;
1789
1790         u8         log_ack_req_freq[0x4];
1791         u8         reserved_11[0x4];
1792         u8         log_sra_max[0x3];
1793         u8         reserved_12[0x2];
1794         u8         retry_count[0x3];
1795         u8         rnr_retry[0x3];
1796         u8         reserved_13[0x1];
1797         u8         fre[0x1];
1798         u8         cur_rnr_retry[0x3];
1799         u8         cur_retry_count[0x3];
1800         u8         reserved_14[0x5];
1801
1802         u8         reserved_15[0x20];
1803
1804         u8         reserved_16[0x8];
1805         u8         next_send_psn[0x18];
1806
1807         u8         reserved_17[0x8];
1808         u8         cqn_snd[0x18];
1809
1810         u8         reserved_18[0x40];
1811
1812         u8         reserved_19[0x8];
1813         u8         last_acked_psn[0x18];
1814
1815         u8         reserved_20[0x8];
1816         u8         ssn[0x18];
1817
1818         u8         reserved_21[0x8];
1819         u8         log_rra_max[0x3];
1820         u8         reserved_22[0x1];
1821         u8         atomic_mode[0x4];
1822         u8         rre[0x1];
1823         u8         rwe[0x1];
1824         u8         rae[0x1];
1825         u8         reserved_23[0x1];
1826         u8         page_offset[0x6];
1827         u8         reserved_24[0x3];
1828         u8         cd_slave_receive[0x1];
1829         u8         cd_slave_send[0x1];
1830         u8         cd_master[0x1];
1831
1832         u8         reserved_25[0x3];
1833         u8         min_rnr_nak[0x5];
1834         u8         next_rcv_psn[0x18];
1835
1836         u8         reserved_26[0x8];
1837         u8         xrcd[0x18];
1838
1839         u8         reserved_27[0x8];
1840         u8         cqn_rcv[0x18];
1841
1842         u8         dbr_addr[0x40];
1843
1844         u8         q_key[0x20];
1845
1846         u8         reserved_28[0x5];
1847         u8         rq_type[0x3];
1848         u8         srqn_rmpn[0x18];
1849
1850         u8         reserved_29[0x8];
1851         u8         rmsn[0x18];
1852
1853         u8         hw_sq_wqebb_counter[0x10];
1854         u8         sw_sq_wqebb_counter[0x10];
1855
1856         u8         hw_rq_counter[0x20];
1857
1858         u8         sw_rq_counter[0x20];
1859
1860         u8         reserved_30[0x20];
1861
1862         u8         reserved_31[0xf];
1863         u8         cgs[0x1];
1864         u8         cs_req[0x8];
1865         u8         cs_res[0x8];
1866
1867         u8         dc_access_key[0x40];
1868
1869         u8         reserved_32[0xc0];
1870 };
1871
1872 struct mlx5_ifc_roce_addr_layout_bits {
1873         u8         source_l3_address[16][0x8];
1874
1875         u8         reserved_0[0x3];
1876         u8         vlan_valid[0x1];
1877         u8         vlan_id[0xc];
1878         u8         source_mac_47_32[0x10];
1879
1880         u8         source_mac_31_0[0x20];
1881
1882         u8         reserved_1[0x14];
1883         u8         roce_l3_type[0x4];
1884         u8         roce_version[0x8];
1885
1886         u8         reserved_2[0x20];
1887 };
1888
1889 union mlx5_ifc_hca_cap_union_bits {
1890         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1891         struct mlx5_ifc_odp_cap_bits odp_cap;
1892         struct mlx5_ifc_atomic_caps_bits atomic_caps;
1893         struct mlx5_ifc_roce_cap_bits roce_cap;
1894         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1895         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1896         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1897         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1898         u8         reserved_0[0x8000];
1899 };
1900
1901 enum {
1902         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
1903         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
1904         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
1905 };
1906
1907 struct mlx5_ifc_flow_context_bits {
1908         u8         reserved_0[0x20];
1909
1910         u8         group_id[0x20];
1911
1912         u8         reserved_1[0x8];
1913         u8         flow_tag[0x18];
1914
1915         u8         reserved_2[0x10];
1916         u8         action[0x10];
1917
1918         u8         reserved_3[0x8];
1919         u8         destination_list_size[0x18];
1920
1921         u8         reserved_4[0x160];
1922
1923         struct mlx5_ifc_fte_match_param_bits match_value;
1924
1925         u8         reserved_5[0x600];
1926
1927         struct mlx5_ifc_dest_format_struct_bits destination[0];
1928 };
1929
1930 enum {
1931         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
1932         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
1933 };
1934
1935 struct mlx5_ifc_xrc_srqc_bits {
1936         u8         state[0x4];
1937         u8         log_xrc_srq_size[0x4];
1938         u8         reserved_0[0x18];
1939
1940         u8         wq_signature[0x1];
1941         u8         cont_srq[0x1];
1942         u8         reserved_1[0x1];
1943         u8         rlky[0x1];
1944         u8         basic_cyclic_rcv_wqe[0x1];
1945         u8         log_rq_stride[0x3];
1946         u8         xrcd[0x18];
1947
1948         u8         page_offset[0x6];
1949         u8         reserved_2[0x2];
1950         u8         cqn[0x18];
1951
1952         u8         reserved_3[0x20];
1953
1954         u8         user_index_equal_xrc_srqn[0x1];
1955         u8         reserved_4[0x1];
1956         u8         log_page_size[0x6];
1957         u8         user_index[0x18];
1958
1959         u8         reserved_5[0x20];
1960
1961         u8         reserved_6[0x8];
1962         u8         pd[0x18];
1963
1964         u8         lwm[0x10];
1965         u8         wqe_cnt[0x10];
1966
1967         u8         reserved_7[0x40];
1968
1969         u8         db_record_addr_h[0x20];
1970
1971         u8         db_record_addr_l[0x1e];
1972         u8         reserved_8[0x2];
1973
1974         u8         reserved_9[0x80];
1975 };
1976
1977 struct mlx5_ifc_traffic_counter_bits {
1978         u8         packets[0x40];
1979
1980         u8         octets[0x40];
1981 };
1982
1983 struct mlx5_ifc_tisc_bits {
1984         u8         reserved_0[0xc];
1985         u8         prio[0x4];
1986         u8         reserved_1[0x10];
1987
1988         u8         reserved_2[0x100];
1989
1990         u8         reserved_3[0x8];
1991         u8         transport_domain[0x18];
1992
1993         u8         reserved_4[0x3c0];
1994 };
1995
1996 enum {
1997         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1998         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1999 };
2000
2001 enum {
2002         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2003         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2004 };
2005
2006 enum {
2007         MLX5_RX_HASH_FN_NONE           = 0x0,
2008         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2009         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2010 };
2011
2012 enum {
2013         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2014         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2015 };
2016
2017 struct mlx5_ifc_tirc_bits {
2018         u8         reserved_0[0x20];
2019
2020         u8         disp_type[0x4];
2021         u8         reserved_1[0x1c];
2022
2023         u8         reserved_2[0x40];
2024
2025         u8         reserved_3[0x4];
2026         u8         lro_timeout_period_usecs[0x10];
2027         u8         lro_enable_mask[0x4];
2028         u8         lro_max_ip_payload_size[0x8];
2029
2030         u8         reserved_4[0x40];
2031
2032         u8         reserved_5[0x8];
2033         u8         inline_rqn[0x18];
2034
2035         u8         rx_hash_symmetric[0x1];
2036         u8         reserved_6[0x1];
2037         u8         tunneled_offload_en[0x1];
2038         u8         reserved_7[0x5];
2039         u8         indirect_table[0x18];
2040
2041         u8         rx_hash_fn[0x4];
2042         u8         reserved_8[0x2];
2043         u8         self_lb_block[0x2];
2044         u8         transport_domain[0x18];
2045
2046         u8         rx_hash_toeplitz_key[10][0x20];
2047
2048         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2049
2050         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2051
2052         u8         reserved_9[0x4c0];
2053 };
2054
2055 enum {
2056         MLX5_SRQC_STATE_GOOD   = 0x0,
2057         MLX5_SRQC_STATE_ERROR  = 0x1,
2058 };
2059
2060 struct mlx5_ifc_srqc_bits {
2061         u8         state[0x4];
2062         u8         log_srq_size[0x4];
2063         u8         reserved_0[0x18];
2064
2065         u8         wq_signature[0x1];
2066         u8         cont_srq[0x1];
2067         u8         reserved_1[0x1];
2068         u8         rlky[0x1];
2069         u8         reserved_2[0x1];
2070         u8         log_rq_stride[0x3];
2071         u8         xrcd[0x18];
2072
2073         u8         page_offset[0x6];
2074         u8         reserved_3[0x2];
2075         u8         cqn[0x18];
2076
2077         u8         reserved_4[0x20];
2078
2079         u8         reserved_5[0x2];
2080         u8         log_page_size[0x6];
2081         u8         reserved_6[0x18];
2082
2083         u8         reserved_7[0x20];
2084
2085         u8         reserved_8[0x8];
2086         u8         pd[0x18];
2087
2088         u8         lwm[0x10];
2089         u8         wqe_cnt[0x10];
2090
2091         u8         reserved_9[0x40];
2092
2093         u8         dbr_addr[0x40];
2094
2095         u8         reserved_10[0x80];
2096 };
2097
2098 enum {
2099         MLX5_SQC_STATE_RST  = 0x0,
2100         MLX5_SQC_STATE_RDY  = 0x1,
2101         MLX5_SQC_STATE_ERR  = 0x3,
2102 };
2103
2104 struct mlx5_ifc_sqc_bits {
2105         u8         rlky[0x1];
2106         u8         cd_master[0x1];
2107         u8         fre[0x1];
2108         u8         flush_in_error_en[0x1];
2109         u8         reserved_0[0x4];
2110         u8         state[0x4];
2111         u8         reserved_1[0x14];
2112
2113         u8         reserved_2[0x8];
2114         u8         user_index[0x18];
2115
2116         u8         reserved_3[0x8];
2117         u8         cqn[0x18];
2118
2119         u8         reserved_4[0xa0];
2120
2121         u8         tis_lst_sz[0x10];
2122         u8         reserved_5[0x10];
2123
2124         u8         reserved_6[0x40];
2125
2126         u8         reserved_7[0x8];
2127         u8         tis_num_0[0x18];
2128
2129         struct mlx5_ifc_wq_bits wq;
2130 };
2131
2132 struct mlx5_ifc_rqtc_bits {
2133         u8         reserved_0[0xa0];
2134
2135         u8         reserved_1[0x10];
2136         u8         rqt_max_size[0x10];
2137
2138         u8         reserved_2[0x10];
2139         u8         rqt_actual_size[0x10];
2140
2141         u8         reserved_3[0x6a0];
2142
2143         struct mlx5_ifc_rq_num_bits rq_num[0];
2144 };
2145
2146 enum {
2147         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2148         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2149 };
2150
2151 enum {
2152         MLX5_RQC_STATE_RST  = 0x0,
2153         MLX5_RQC_STATE_RDY  = 0x1,
2154         MLX5_RQC_STATE_ERR  = 0x3,
2155 };
2156
2157 struct mlx5_ifc_rqc_bits {
2158         u8         rlky[0x1];
2159         u8         reserved_0[0x2];
2160         u8         vsd[0x1];
2161         u8         mem_rq_type[0x4];
2162         u8         state[0x4];
2163         u8         reserved_1[0x1];
2164         u8         flush_in_error_en[0x1];
2165         u8         reserved_2[0x12];
2166
2167         u8         reserved_3[0x8];
2168         u8         user_index[0x18];
2169
2170         u8         reserved_4[0x8];
2171         u8         cqn[0x18];
2172
2173         u8         counter_set_id[0x8];
2174         u8         reserved_5[0x18];
2175
2176         u8         reserved_6[0x8];
2177         u8         rmpn[0x18];
2178
2179         u8         reserved_7[0xe0];
2180
2181         struct mlx5_ifc_wq_bits wq;
2182 };
2183
2184 enum {
2185         MLX5_RMPC_STATE_RDY  = 0x1,
2186         MLX5_RMPC_STATE_ERR  = 0x3,
2187 };
2188
2189 struct mlx5_ifc_rmpc_bits {
2190         u8         reserved_0[0x8];
2191         u8         state[0x4];
2192         u8         reserved_1[0x14];
2193
2194         u8         basic_cyclic_rcv_wqe[0x1];
2195         u8         reserved_2[0x1f];
2196
2197         u8         reserved_3[0x140];
2198
2199         struct mlx5_ifc_wq_bits wq;
2200 };
2201
2202 struct mlx5_ifc_nic_vport_context_bits {
2203         u8         reserved_0[0x1f];
2204         u8         roce_en[0x1];
2205
2206         u8         arm_change_event[0x1];
2207         u8         reserved_1[0x1a];
2208         u8         event_on_mtu[0x1];
2209         u8         event_on_promisc_change[0x1];
2210         u8         event_on_vlan_change[0x1];
2211         u8         event_on_mc_address_change[0x1];
2212         u8         event_on_uc_address_change[0x1];
2213
2214         u8         reserved_2[0xf0];
2215
2216         u8         mtu[0x10];
2217
2218         u8         reserved_3[0x640];
2219
2220         u8         promisc_uc[0x1];
2221         u8         promisc_mc[0x1];
2222         u8         promisc_all[0x1];
2223         u8         reserved_4[0x2];
2224         u8         allowed_list_type[0x3];
2225         u8         reserved_5[0xc];
2226         u8         allowed_list_size[0xc];
2227
2228         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2229
2230         u8         reserved_6[0x20];
2231
2232         u8         current_uc_mac_address[0][0x40];
2233 };
2234
2235 enum {
2236         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2237         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2238         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2239 };
2240
2241 struct mlx5_ifc_mkc_bits {
2242         u8         reserved_0[0x1];
2243         u8         free[0x1];
2244         u8         reserved_1[0xd];
2245         u8         small_fence_on_rdma_read_response[0x1];
2246         u8         umr_en[0x1];
2247         u8         a[0x1];
2248         u8         rw[0x1];
2249         u8         rr[0x1];
2250         u8         lw[0x1];
2251         u8         lr[0x1];
2252         u8         access_mode[0x2];
2253         u8         reserved_2[0x8];
2254
2255         u8         qpn[0x18];
2256         u8         mkey_7_0[0x8];
2257
2258         u8         reserved_3[0x20];
2259
2260         u8         length64[0x1];
2261         u8         bsf_en[0x1];
2262         u8         sync_umr[0x1];
2263         u8         reserved_4[0x2];
2264         u8         expected_sigerr_count[0x1];
2265         u8         reserved_5[0x1];
2266         u8         en_rinval[0x1];
2267         u8         pd[0x18];
2268
2269         u8         start_addr[0x40];
2270
2271         u8         len[0x40];
2272
2273         u8         bsf_octword_size[0x20];
2274
2275         u8         reserved_6[0x80];
2276
2277         u8         translations_octword_size[0x20];
2278
2279         u8         reserved_7[0x1b];
2280         u8         log_page_size[0x5];
2281
2282         u8         reserved_8[0x20];
2283 };
2284
2285 struct mlx5_ifc_pkey_bits {
2286         u8         reserved_0[0x10];
2287         u8         pkey[0x10];
2288 };
2289
2290 struct mlx5_ifc_array128_auto_bits {
2291         u8         array128_auto[16][0x8];
2292 };
2293
2294 struct mlx5_ifc_hca_vport_context_bits {
2295         u8         field_select[0x20];
2296
2297         u8         reserved_0[0xe0];
2298
2299         u8         sm_virt_aware[0x1];
2300         u8         has_smi[0x1];
2301         u8         has_raw[0x1];
2302         u8         grh_required[0x1];
2303         u8         reserved_1[0xc];
2304         u8         port_physical_state[0x4];
2305         u8         vport_state_policy[0x4];
2306         u8         port_state[0x4];
2307         u8         vport_state[0x4];
2308
2309         u8         reserved_2[0x20];
2310
2311         u8         system_image_guid[0x40];
2312
2313         u8         port_guid[0x40];
2314
2315         u8         node_guid[0x40];
2316
2317         u8         cap_mask1[0x20];
2318
2319         u8         cap_mask1_field_select[0x20];
2320
2321         u8         cap_mask2[0x20];
2322
2323         u8         cap_mask2_field_select[0x20];
2324
2325         u8         reserved_3[0x80];
2326
2327         u8         lid[0x10];
2328         u8         reserved_4[0x4];
2329         u8         init_type_reply[0x4];
2330         u8         lmc[0x3];
2331         u8         subnet_timeout[0x5];
2332
2333         u8         sm_lid[0x10];
2334         u8         sm_sl[0x4];
2335         u8         reserved_5[0xc];
2336
2337         u8         qkey_violation_counter[0x10];
2338         u8         pkey_violation_counter[0x10];
2339
2340         u8         reserved_6[0xca0];
2341 };
2342
2343 struct mlx5_ifc_esw_vport_context_bits {
2344         u8         reserved_0[0x3];
2345         u8         vport_svlan_strip[0x1];
2346         u8         vport_cvlan_strip[0x1];
2347         u8         vport_svlan_insert[0x1];
2348         u8         vport_cvlan_insert[0x2];
2349         u8         reserved_1[0x18];
2350
2351         u8         reserved_2[0x20];
2352
2353         u8         svlan_cfi[0x1];
2354         u8         svlan_pcp[0x3];
2355         u8         svlan_id[0xc];
2356         u8         cvlan_cfi[0x1];
2357         u8         cvlan_pcp[0x3];
2358         u8         cvlan_id[0xc];
2359
2360         u8         reserved_3[0x7a0];
2361 };
2362
2363 enum {
2364         MLX5_EQC_STATUS_OK                = 0x0,
2365         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2366 };
2367
2368 enum {
2369         MLX5_EQC_ST_ARMED  = 0x9,
2370         MLX5_EQC_ST_FIRED  = 0xa,
2371 };
2372
2373 struct mlx5_ifc_eqc_bits {
2374         u8         status[0x4];
2375         u8         reserved_0[0x9];
2376         u8         ec[0x1];
2377         u8         oi[0x1];
2378         u8         reserved_1[0x5];
2379         u8         st[0x4];
2380         u8         reserved_2[0x8];
2381
2382         u8         reserved_3[0x20];
2383
2384         u8         reserved_4[0x14];
2385         u8         page_offset[0x6];
2386         u8         reserved_5[0x6];
2387
2388         u8         reserved_6[0x3];
2389         u8         log_eq_size[0x5];
2390         u8         uar_page[0x18];
2391
2392         u8         reserved_7[0x20];
2393
2394         u8         reserved_8[0x18];
2395         u8         intr[0x8];
2396
2397         u8         reserved_9[0x3];
2398         u8         log_page_size[0x5];
2399         u8         reserved_10[0x18];
2400
2401         u8         reserved_11[0x60];
2402
2403         u8         reserved_12[0x8];
2404         u8         consumer_counter[0x18];
2405
2406         u8         reserved_13[0x8];
2407         u8         producer_counter[0x18];
2408
2409         u8         reserved_14[0x80];
2410 };
2411
2412 enum {
2413         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2414         MLX5_DCTC_STATE_DRAINING  = 0x1,
2415         MLX5_DCTC_STATE_DRAINED   = 0x2,
2416 };
2417
2418 enum {
2419         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2420         MLX5_DCTC_CS_RES_NA         = 0x1,
2421         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2422 };
2423
2424 enum {
2425         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2426         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2427         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2428         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2429         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2430 };
2431
2432 struct mlx5_ifc_dctc_bits {
2433         u8         reserved_0[0x4];
2434         u8         state[0x4];
2435         u8         reserved_1[0x18];
2436
2437         u8         reserved_2[0x8];
2438         u8         user_index[0x18];
2439
2440         u8         reserved_3[0x8];
2441         u8         cqn[0x18];
2442
2443         u8         counter_set_id[0x8];
2444         u8         atomic_mode[0x4];
2445         u8         rre[0x1];
2446         u8         rwe[0x1];
2447         u8         rae[0x1];
2448         u8         atomic_like_write_en[0x1];
2449         u8         latency_sensitive[0x1];
2450         u8         rlky[0x1];
2451         u8         free_ar[0x1];
2452         u8         reserved_4[0xd];
2453
2454         u8         reserved_5[0x8];
2455         u8         cs_res[0x8];
2456         u8         reserved_6[0x3];
2457         u8         min_rnr_nak[0x5];
2458         u8         reserved_7[0x8];
2459
2460         u8         reserved_8[0x8];
2461         u8         srqn[0x18];
2462
2463         u8         reserved_9[0x8];
2464         u8         pd[0x18];
2465
2466         u8         tclass[0x8];
2467         u8         reserved_10[0x4];
2468         u8         flow_label[0x14];
2469
2470         u8         dc_access_key[0x40];
2471
2472         u8         reserved_11[0x5];
2473         u8         mtu[0x3];
2474         u8         port[0x8];
2475         u8         pkey_index[0x10];
2476
2477         u8         reserved_12[0x8];
2478         u8         my_addr_index[0x8];
2479         u8         reserved_13[0x8];
2480         u8         hop_limit[0x8];
2481
2482         u8         dc_access_key_violation_count[0x20];
2483
2484         u8         reserved_14[0x14];
2485         u8         dei_cfi[0x1];
2486         u8         eth_prio[0x3];
2487         u8         ecn[0x2];
2488         u8         dscp[0x6];
2489
2490         u8         reserved_15[0x40];
2491 };
2492
2493 enum {
2494         MLX5_CQC_STATUS_OK             = 0x0,
2495         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2496         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2497 };
2498
2499 enum {
2500         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2501         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2502 };
2503
2504 enum {
2505         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2506         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2507         MLX5_CQC_ST_FIRED                                 = 0xa,
2508 };
2509
2510 struct mlx5_ifc_cqc_bits {
2511         u8         status[0x4];
2512         u8         reserved_0[0x4];
2513         u8         cqe_sz[0x3];
2514         u8         cc[0x1];
2515         u8         reserved_1[0x1];
2516         u8         scqe_break_moderation_en[0x1];
2517         u8         oi[0x1];
2518         u8         reserved_2[0x2];
2519         u8         cqe_zip_en[0x1];
2520         u8         mini_cqe_res_format[0x2];
2521         u8         st[0x4];
2522         u8         reserved_3[0x8];
2523
2524         u8         reserved_4[0x20];
2525
2526         u8         reserved_5[0x14];
2527         u8         page_offset[0x6];
2528         u8         reserved_6[0x6];
2529
2530         u8         reserved_7[0x3];
2531         u8         log_cq_size[0x5];
2532         u8         uar_page[0x18];
2533
2534         u8         reserved_8[0x4];
2535         u8         cq_period[0xc];
2536         u8         cq_max_count[0x10];
2537
2538         u8         reserved_9[0x18];
2539         u8         c_eqn[0x8];
2540
2541         u8         reserved_10[0x3];
2542         u8         log_page_size[0x5];
2543         u8         reserved_11[0x18];
2544
2545         u8         reserved_12[0x20];
2546
2547         u8         reserved_13[0x8];
2548         u8         last_notified_index[0x18];
2549
2550         u8         reserved_14[0x8];
2551         u8         last_solicit_index[0x18];
2552
2553         u8         reserved_15[0x8];
2554         u8         consumer_counter[0x18];
2555
2556         u8         reserved_16[0x8];
2557         u8         producer_counter[0x18];
2558
2559         u8         reserved_17[0x40];
2560
2561         u8         dbr_addr[0x40];
2562 };
2563
2564 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2565         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2566         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2567         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2568         u8         reserved_0[0x800];
2569 };
2570
2571 struct mlx5_ifc_query_adapter_param_block_bits {
2572         u8         reserved_0[0xc0];
2573
2574         u8         reserved_1[0x8];
2575         u8         ieee_vendor_id[0x18];
2576
2577         u8         reserved_2[0x10];
2578         u8         vsd_vendor_id[0x10];
2579
2580         u8         vsd[208][0x8];
2581
2582         u8         vsd_contd_psid[16][0x8];
2583 };
2584
2585 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2586         struct mlx5_ifc_modify_field_select_bits modify_field_select;
2587         struct mlx5_ifc_resize_field_select_bits resize_field_select;
2588         u8         reserved_0[0x20];
2589 };
2590
2591 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2592         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2593         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2594         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2595         u8         reserved_0[0x20];
2596 };
2597
2598 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2599         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2600         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2601         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2602         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2603         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2604         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2605         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2606         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2607         u8         reserved_0[0x7c0];
2608 };
2609
2610 union mlx5_ifc_event_auto_bits {
2611         struct mlx5_ifc_comp_event_bits comp_event;
2612         struct mlx5_ifc_dct_events_bits dct_events;
2613         struct mlx5_ifc_qp_events_bits qp_events;
2614         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2615         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2616         struct mlx5_ifc_cq_error_bits cq_error;
2617         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2618         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2619         struct mlx5_ifc_gpio_event_bits gpio_event;
2620         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2621         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2622         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2623         u8         reserved_0[0xe0];
2624 };
2625
2626 struct mlx5_ifc_health_buffer_bits {
2627         u8         reserved_0[0x100];
2628
2629         u8         assert_existptr[0x20];
2630
2631         u8         assert_callra[0x20];
2632
2633         u8         reserved_1[0x40];
2634
2635         u8         fw_version[0x20];
2636
2637         u8         hw_id[0x20];
2638
2639         u8         reserved_2[0x20];
2640
2641         u8         irisc_index[0x8];
2642         u8         synd[0x8];
2643         u8         ext_synd[0x10];
2644 };
2645
2646 struct mlx5_ifc_register_loopback_control_bits {
2647         u8         no_lb[0x1];
2648         u8         reserved_0[0x7];
2649         u8         port[0x8];
2650         u8         reserved_1[0x10];
2651
2652         u8         reserved_2[0x60];
2653 };
2654
2655 struct mlx5_ifc_teardown_hca_out_bits {
2656         u8         status[0x8];
2657         u8         reserved_0[0x18];
2658
2659         u8         syndrome[0x20];
2660
2661         u8         reserved_1[0x40];
2662 };
2663
2664 enum {
2665         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
2666         MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
2667 };
2668
2669 struct mlx5_ifc_teardown_hca_in_bits {
2670         u8         opcode[0x10];
2671         u8         reserved_0[0x10];
2672
2673         u8         reserved_1[0x10];
2674         u8         op_mod[0x10];
2675
2676         u8         reserved_2[0x10];
2677         u8         profile[0x10];
2678
2679         u8         reserved_3[0x20];
2680 };
2681
2682 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2683         u8         status[0x8];
2684         u8         reserved_0[0x18];
2685
2686         u8         syndrome[0x20];
2687
2688         u8         reserved_1[0x40];
2689 };
2690
2691 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2692         u8         opcode[0x10];
2693         u8         reserved_0[0x10];
2694
2695         u8         reserved_1[0x10];
2696         u8         op_mod[0x10];
2697
2698         u8         reserved_2[0x8];
2699         u8         qpn[0x18];
2700
2701         u8         reserved_3[0x20];
2702
2703         u8         opt_param_mask[0x20];
2704
2705         u8         reserved_4[0x20];
2706
2707         struct mlx5_ifc_qpc_bits qpc;
2708
2709         u8         reserved_5[0x80];
2710 };
2711
2712 struct mlx5_ifc_sqd2rts_qp_out_bits {
2713         u8         status[0x8];
2714         u8         reserved_0[0x18];
2715
2716         u8         syndrome[0x20];
2717
2718         u8         reserved_1[0x40];
2719 };
2720
2721 struct mlx5_ifc_sqd2rts_qp_in_bits {
2722         u8         opcode[0x10];
2723         u8         reserved_0[0x10];
2724
2725         u8         reserved_1[0x10];
2726         u8         op_mod[0x10];
2727
2728         u8         reserved_2[0x8];
2729         u8         qpn[0x18];
2730
2731         u8         reserved_3[0x20];
2732
2733         u8         opt_param_mask[0x20];
2734
2735         u8         reserved_4[0x20];
2736
2737         struct mlx5_ifc_qpc_bits qpc;
2738
2739         u8         reserved_5[0x80];
2740 };
2741
2742 struct mlx5_ifc_set_roce_address_out_bits {
2743         u8         status[0x8];
2744         u8         reserved_0[0x18];
2745
2746         u8         syndrome[0x20];
2747
2748         u8         reserved_1[0x40];
2749 };
2750
2751 struct mlx5_ifc_set_roce_address_in_bits {
2752         u8         opcode[0x10];
2753         u8         reserved_0[0x10];
2754
2755         u8         reserved_1[0x10];
2756         u8         op_mod[0x10];
2757
2758         u8         roce_address_index[0x10];
2759         u8         reserved_2[0x10];
2760
2761         u8         reserved_3[0x20];
2762
2763         struct mlx5_ifc_roce_addr_layout_bits roce_address;
2764 };
2765
2766 struct mlx5_ifc_set_mad_demux_out_bits {
2767         u8         status[0x8];
2768         u8         reserved_0[0x18];
2769
2770         u8         syndrome[0x20];
2771
2772         u8         reserved_1[0x40];
2773 };
2774
2775 enum {
2776         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
2777         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
2778 };
2779
2780 struct mlx5_ifc_set_mad_demux_in_bits {
2781         u8         opcode[0x10];
2782         u8         reserved_0[0x10];
2783
2784         u8         reserved_1[0x10];
2785         u8         op_mod[0x10];
2786
2787         u8         reserved_2[0x20];
2788
2789         u8         reserved_3[0x6];
2790         u8         demux_mode[0x2];
2791         u8         reserved_4[0x18];
2792 };
2793
2794 struct mlx5_ifc_set_l2_table_entry_out_bits {
2795         u8         status[0x8];
2796         u8         reserved_0[0x18];
2797
2798         u8         syndrome[0x20];
2799
2800         u8         reserved_1[0x40];
2801 };
2802
2803 struct mlx5_ifc_set_l2_table_entry_in_bits {
2804         u8         opcode[0x10];
2805         u8         reserved_0[0x10];
2806
2807         u8         reserved_1[0x10];
2808         u8         op_mod[0x10];
2809
2810         u8         reserved_2[0x60];
2811
2812         u8         reserved_3[0x8];
2813         u8         table_index[0x18];
2814
2815         u8         reserved_4[0x20];
2816
2817         u8         reserved_5[0x13];
2818         u8         vlan_valid[0x1];
2819         u8         vlan[0xc];
2820
2821         struct mlx5_ifc_mac_address_layout_bits mac_address;
2822
2823         u8         reserved_6[0xc0];
2824 };
2825
2826 struct mlx5_ifc_set_issi_out_bits {
2827         u8         status[0x8];
2828         u8         reserved_0[0x18];
2829
2830         u8         syndrome[0x20];
2831
2832         u8         reserved_1[0x40];
2833 };
2834
2835 struct mlx5_ifc_set_issi_in_bits {
2836         u8         opcode[0x10];
2837         u8         reserved_0[0x10];
2838
2839         u8         reserved_1[0x10];
2840         u8         op_mod[0x10];
2841
2842         u8         reserved_2[0x10];
2843         u8         current_issi[0x10];
2844
2845         u8         reserved_3[0x20];
2846 };
2847
2848 struct mlx5_ifc_set_hca_cap_out_bits {
2849         u8         status[0x8];
2850         u8         reserved_0[0x18];
2851
2852         u8         syndrome[0x20];
2853
2854         u8         reserved_1[0x40];
2855 };
2856
2857 struct mlx5_ifc_set_hca_cap_in_bits {
2858         u8         opcode[0x10];
2859         u8         reserved_0[0x10];
2860
2861         u8         reserved_1[0x10];
2862         u8         op_mod[0x10];
2863
2864         u8         reserved_2[0x40];
2865
2866         union mlx5_ifc_hca_cap_union_bits capability;
2867 };
2868
2869 enum {
2870         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
2871         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
2872         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
2873         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
2874 };
2875
2876 struct mlx5_ifc_set_fte_out_bits {
2877         u8         status[0x8];
2878         u8         reserved_0[0x18];
2879
2880         u8         syndrome[0x20];
2881
2882         u8         reserved_1[0x40];
2883 };
2884
2885 struct mlx5_ifc_set_fte_in_bits {
2886         u8         opcode[0x10];
2887         u8         reserved_0[0x10];
2888
2889         u8         reserved_1[0x10];
2890         u8         op_mod[0x10];
2891
2892         u8         reserved_2[0x40];
2893
2894         u8         table_type[0x8];
2895         u8         reserved_3[0x18];
2896
2897         u8         reserved_4[0x8];
2898         u8         table_id[0x18];
2899
2900         u8         reserved_5[0x18];
2901         u8         modify_enable_mask[0x8];
2902
2903         u8         reserved_6[0x20];
2904
2905         u8         flow_index[0x20];
2906
2907         u8         reserved_7[0xe0];
2908
2909         struct mlx5_ifc_flow_context_bits flow_context;
2910 };
2911
2912 struct mlx5_ifc_rts2rts_qp_out_bits {
2913         u8         status[0x8];
2914         u8         reserved_0[0x18];
2915
2916         u8         syndrome[0x20];
2917
2918         u8         reserved_1[0x40];
2919 };
2920
2921 struct mlx5_ifc_rts2rts_qp_in_bits {
2922         u8         opcode[0x10];
2923         u8         reserved_0[0x10];
2924
2925         u8         reserved_1[0x10];
2926         u8         op_mod[0x10];
2927
2928         u8         reserved_2[0x8];
2929         u8         qpn[0x18];
2930
2931         u8         reserved_3[0x20];
2932
2933         u8         opt_param_mask[0x20];
2934
2935         u8         reserved_4[0x20];
2936
2937         struct mlx5_ifc_qpc_bits qpc;
2938
2939         u8         reserved_5[0x80];
2940 };
2941
2942 struct mlx5_ifc_rtr2rts_qp_out_bits {
2943         u8         status[0x8];
2944         u8         reserved_0[0x18];
2945
2946         u8         syndrome[0x20];
2947
2948         u8         reserved_1[0x40];
2949 };
2950
2951 struct mlx5_ifc_rtr2rts_qp_in_bits {
2952         u8         opcode[0x10];
2953         u8         reserved_0[0x10];
2954
2955         u8         reserved_1[0x10];
2956         u8         op_mod[0x10];
2957
2958         u8         reserved_2[0x8];
2959         u8         qpn[0x18];
2960
2961         u8         reserved_3[0x20];
2962
2963         u8         opt_param_mask[0x20];
2964
2965         u8         reserved_4[0x20];
2966
2967         struct mlx5_ifc_qpc_bits qpc;
2968
2969         u8         reserved_5[0x80];
2970 };
2971
2972 struct mlx5_ifc_rst2init_qp_out_bits {
2973         u8         status[0x8];
2974         u8         reserved_0[0x18];
2975
2976         u8         syndrome[0x20];
2977
2978         u8         reserved_1[0x40];
2979 };
2980
2981 struct mlx5_ifc_rst2init_qp_in_bits {
2982         u8         opcode[0x10];
2983         u8         reserved_0[0x10];
2984
2985         u8         reserved_1[0x10];
2986         u8         op_mod[0x10];
2987
2988         u8         reserved_2[0x8];
2989         u8         qpn[0x18];
2990
2991         u8         reserved_3[0x20];
2992
2993         u8         opt_param_mask[0x20];
2994
2995         u8         reserved_4[0x20];
2996
2997         struct mlx5_ifc_qpc_bits qpc;
2998
2999         u8         reserved_5[0x80];
3000 };
3001
3002 struct mlx5_ifc_query_xrc_srq_out_bits {
3003         u8         status[0x8];
3004         u8         reserved_0[0x18];
3005
3006         u8         syndrome[0x20];
3007
3008         u8         reserved_1[0x40];
3009
3010         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3011
3012         u8         reserved_2[0x600];
3013
3014         u8         pas[0][0x40];
3015 };
3016
3017 struct mlx5_ifc_query_xrc_srq_in_bits {
3018         u8         opcode[0x10];
3019         u8         reserved_0[0x10];
3020
3021         u8         reserved_1[0x10];
3022         u8         op_mod[0x10];
3023
3024         u8         reserved_2[0x8];
3025         u8         xrc_srqn[0x18];
3026
3027         u8         reserved_3[0x20];
3028 };
3029
3030 enum {
3031         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3032         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3033 };
3034
3035 struct mlx5_ifc_query_vport_state_out_bits {
3036         u8         status[0x8];
3037         u8         reserved_0[0x18];
3038
3039         u8         syndrome[0x20];
3040
3041         u8         reserved_1[0x20];
3042
3043         u8         reserved_2[0x18];
3044         u8         admin_state[0x4];
3045         u8         state[0x4];
3046 };
3047
3048 enum {
3049         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3050         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3051 };
3052
3053 struct mlx5_ifc_query_vport_state_in_bits {
3054         u8         opcode[0x10];
3055         u8         reserved_0[0x10];
3056
3057         u8         reserved_1[0x10];
3058         u8         op_mod[0x10];
3059
3060         u8         other_vport[0x1];
3061         u8         reserved_2[0xf];
3062         u8         vport_number[0x10];
3063
3064         u8         reserved_3[0x20];
3065 };
3066
3067 struct mlx5_ifc_query_vport_counter_out_bits {
3068         u8         status[0x8];
3069         u8         reserved_0[0x18];
3070
3071         u8         syndrome[0x20];
3072
3073         u8         reserved_1[0x40];
3074
3075         struct mlx5_ifc_traffic_counter_bits received_errors;
3076
3077         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3078
3079         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3080
3081         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3082
3083         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3084
3085         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3086
3087         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3088
3089         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3090
3091         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3092
3093         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3094
3095         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3096
3097         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3098
3099         u8         reserved_2[0xa00];
3100 };
3101
3102 enum {
3103         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3104 };
3105
3106 struct mlx5_ifc_query_vport_counter_in_bits {
3107         u8         opcode[0x10];
3108         u8         reserved_0[0x10];
3109
3110         u8         reserved_1[0x10];
3111         u8         op_mod[0x10];
3112
3113         u8         other_vport[0x1];
3114         u8         reserved_2[0xf];
3115         u8         vport_number[0x10];
3116
3117         u8         reserved_3[0x60];
3118
3119         u8         clear[0x1];
3120         u8         reserved_4[0x1f];
3121
3122         u8         reserved_5[0x20];
3123 };
3124
3125 struct mlx5_ifc_query_tis_out_bits {
3126         u8         status[0x8];
3127         u8         reserved_0[0x18];
3128
3129         u8         syndrome[0x20];
3130
3131         u8         reserved_1[0x40];
3132
3133         struct mlx5_ifc_tisc_bits tis_context;
3134 };
3135
3136 struct mlx5_ifc_query_tis_in_bits {
3137         u8         opcode[0x10];
3138         u8         reserved_0[0x10];
3139
3140         u8         reserved_1[0x10];
3141         u8         op_mod[0x10];
3142
3143         u8         reserved_2[0x8];
3144         u8         tisn[0x18];
3145
3146         u8         reserved_3[0x20];
3147 };
3148
3149 struct mlx5_ifc_query_tir_out_bits {
3150         u8         status[0x8];
3151         u8         reserved_0[0x18];
3152
3153         u8         syndrome[0x20];
3154
3155         u8         reserved_1[0xc0];
3156
3157         struct mlx5_ifc_tirc_bits tir_context;
3158 };
3159
3160 struct mlx5_ifc_query_tir_in_bits {
3161         u8         opcode[0x10];
3162         u8         reserved_0[0x10];
3163
3164         u8         reserved_1[0x10];
3165         u8         op_mod[0x10];
3166
3167         u8         reserved_2[0x8];
3168         u8         tirn[0x18];
3169
3170         u8         reserved_3[0x20];
3171 };
3172
3173 struct mlx5_ifc_query_srq_out_bits {
3174         u8         status[0x8];
3175         u8         reserved_0[0x18];
3176
3177         u8         syndrome[0x20];
3178
3179         u8         reserved_1[0x40];
3180
3181         struct mlx5_ifc_srqc_bits srq_context_entry;
3182
3183         u8         reserved_2[0x600];
3184
3185         u8         pas[0][0x40];
3186 };
3187
3188 struct mlx5_ifc_query_srq_in_bits {
3189         u8         opcode[0x10];
3190         u8         reserved_0[0x10];
3191
3192         u8         reserved_1[0x10];
3193         u8         op_mod[0x10];
3194
3195         u8         reserved_2[0x8];
3196         u8         srqn[0x18];
3197
3198         u8         reserved_3[0x20];
3199 };
3200
3201 struct mlx5_ifc_query_sq_out_bits {
3202         u8         status[0x8];
3203         u8         reserved_0[0x18];
3204
3205         u8         syndrome[0x20];
3206
3207         u8         reserved_1[0xc0];
3208
3209         struct mlx5_ifc_sqc_bits sq_context;
3210 };
3211
3212 struct mlx5_ifc_query_sq_in_bits {
3213         u8         opcode[0x10];
3214         u8         reserved_0[0x10];
3215
3216         u8         reserved_1[0x10];
3217         u8         op_mod[0x10];
3218
3219         u8         reserved_2[0x8];
3220         u8         sqn[0x18];
3221
3222         u8         reserved_3[0x20];
3223 };
3224
3225 struct mlx5_ifc_query_special_contexts_out_bits {
3226         u8         status[0x8];
3227         u8         reserved_0[0x18];
3228
3229         u8         syndrome[0x20];
3230
3231         u8         reserved_1[0x20];
3232
3233         u8         resd_lkey[0x20];
3234 };
3235
3236 struct mlx5_ifc_query_special_contexts_in_bits {
3237         u8         opcode[0x10];
3238         u8         reserved_0[0x10];
3239
3240         u8         reserved_1[0x10];
3241         u8         op_mod[0x10];
3242
3243         u8         reserved_2[0x40];
3244 };
3245
3246 struct mlx5_ifc_query_rqt_out_bits {
3247         u8         status[0x8];
3248         u8         reserved_0[0x18];
3249
3250         u8         syndrome[0x20];
3251
3252         u8         reserved_1[0xc0];
3253
3254         struct mlx5_ifc_rqtc_bits rqt_context;
3255 };
3256
3257 struct mlx5_ifc_query_rqt_in_bits {
3258         u8         opcode[0x10];
3259         u8         reserved_0[0x10];
3260
3261         u8         reserved_1[0x10];
3262         u8         op_mod[0x10];
3263
3264         u8         reserved_2[0x8];
3265         u8         rqtn[0x18];
3266
3267         u8         reserved_3[0x20];
3268 };
3269
3270 struct mlx5_ifc_query_rq_out_bits {
3271         u8         status[0x8];
3272         u8         reserved_0[0x18];
3273
3274         u8         syndrome[0x20];
3275
3276         u8         reserved_1[0xc0];
3277
3278         struct mlx5_ifc_rqc_bits rq_context;
3279 };
3280
3281 struct mlx5_ifc_query_rq_in_bits {
3282         u8         opcode[0x10];
3283         u8         reserved_0[0x10];
3284
3285         u8         reserved_1[0x10];
3286         u8         op_mod[0x10];
3287
3288         u8         reserved_2[0x8];
3289         u8         rqn[0x18];
3290
3291         u8         reserved_3[0x20];
3292 };
3293
3294 struct mlx5_ifc_query_roce_address_out_bits {
3295         u8         status[0x8];
3296         u8         reserved_0[0x18];
3297
3298         u8         syndrome[0x20];
3299
3300         u8         reserved_1[0x40];
3301
3302         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3303 };
3304
3305 struct mlx5_ifc_query_roce_address_in_bits {
3306         u8         opcode[0x10];
3307         u8         reserved_0[0x10];
3308
3309         u8         reserved_1[0x10];
3310         u8         op_mod[0x10];
3311
3312         u8         roce_address_index[0x10];
3313         u8         reserved_2[0x10];
3314
3315         u8         reserved_3[0x20];
3316 };
3317
3318 struct mlx5_ifc_query_rmp_out_bits {
3319         u8         status[0x8];
3320         u8         reserved_0[0x18];
3321
3322         u8         syndrome[0x20];
3323
3324         u8         reserved_1[0xc0];
3325
3326         struct mlx5_ifc_rmpc_bits rmp_context;
3327 };
3328
3329 struct mlx5_ifc_query_rmp_in_bits {
3330         u8         opcode[0x10];
3331         u8         reserved_0[0x10];
3332
3333         u8         reserved_1[0x10];
3334         u8         op_mod[0x10];
3335
3336         u8         reserved_2[0x8];
3337         u8         rmpn[0x18];
3338
3339         u8         reserved_3[0x20];
3340 };
3341
3342 struct mlx5_ifc_query_qp_out_bits {
3343         u8         status[0x8];
3344         u8         reserved_0[0x18];
3345
3346         u8         syndrome[0x20];
3347
3348         u8         reserved_1[0x40];
3349
3350         u8         opt_param_mask[0x20];
3351
3352         u8         reserved_2[0x20];
3353
3354         struct mlx5_ifc_qpc_bits qpc;
3355
3356         u8         reserved_3[0x80];
3357
3358         u8         pas[0][0x40];
3359 };
3360
3361 struct mlx5_ifc_query_qp_in_bits {
3362         u8         opcode[0x10];
3363         u8         reserved_0[0x10];
3364
3365         u8         reserved_1[0x10];
3366         u8         op_mod[0x10];
3367
3368         u8         reserved_2[0x8];
3369         u8         qpn[0x18];
3370
3371         u8         reserved_3[0x20];
3372 };
3373
3374 struct mlx5_ifc_query_q_counter_out_bits {
3375         u8         status[0x8];
3376         u8         reserved_0[0x18];
3377
3378         u8         syndrome[0x20];
3379
3380         u8         reserved_1[0x40];
3381
3382         u8         rx_write_requests[0x20];
3383
3384         u8         reserved_2[0x20];
3385
3386         u8         rx_read_requests[0x20];
3387
3388         u8         reserved_3[0x20];
3389
3390         u8         rx_atomic_requests[0x20];
3391
3392         u8         reserved_4[0x20];
3393
3394         u8         rx_dct_connect[0x20];
3395
3396         u8         reserved_5[0x20];
3397
3398         u8         out_of_buffer[0x20];
3399
3400         u8         reserved_6[0x20];
3401
3402         u8         out_of_sequence[0x20];
3403
3404         u8         reserved_7[0x620];
3405 };
3406
3407 struct mlx5_ifc_query_q_counter_in_bits {
3408         u8         opcode[0x10];
3409         u8         reserved_0[0x10];
3410
3411         u8         reserved_1[0x10];
3412         u8         op_mod[0x10];
3413
3414         u8         reserved_2[0x80];
3415
3416         u8         clear[0x1];
3417         u8         reserved_3[0x1f];
3418
3419         u8         reserved_4[0x18];
3420         u8         counter_set_id[0x8];
3421 };
3422
3423 struct mlx5_ifc_query_pages_out_bits {
3424         u8         status[0x8];
3425         u8         reserved_0[0x18];
3426
3427         u8         syndrome[0x20];
3428
3429         u8         reserved_1[0x10];
3430         u8         function_id[0x10];
3431
3432         u8         num_pages[0x20];
3433 };
3434
3435 enum {
3436         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3437         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3438         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3439 };
3440
3441 struct mlx5_ifc_query_pages_in_bits {
3442         u8         opcode[0x10];
3443         u8         reserved_0[0x10];
3444
3445         u8         reserved_1[0x10];
3446         u8         op_mod[0x10];
3447
3448         u8         reserved_2[0x10];
3449         u8         function_id[0x10];
3450
3451         u8         reserved_3[0x20];
3452 };
3453
3454 struct mlx5_ifc_query_nic_vport_context_out_bits {
3455         u8         status[0x8];
3456         u8         reserved_0[0x18];
3457
3458         u8         syndrome[0x20];
3459
3460         u8         reserved_1[0x40];
3461
3462         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3463 };
3464
3465 struct mlx5_ifc_query_nic_vport_context_in_bits {
3466         u8         opcode[0x10];
3467         u8         reserved_0[0x10];
3468
3469         u8         reserved_1[0x10];
3470         u8         op_mod[0x10];
3471
3472         u8         other_vport[0x1];
3473         u8         reserved_2[0xf];
3474         u8         vport_number[0x10];
3475
3476         u8         reserved_3[0x5];
3477         u8         allowed_list_type[0x3];
3478         u8         reserved_4[0x18];
3479 };
3480
3481 struct mlx5_ifc_query_mkey_out_bits {
3482         u8         status[0x8];
3483         u8         reserved_0[0x18];
3484
3485         u8         syndrome[0x20];
3486
3487         u8         reserved_1[0x40];
3488
3489         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3490
3491         u8         reserved_2[0x600];
3492
3493         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
3494
3495         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
3496 };
3497
3498 struct mlx5_ifc_query_mkey_in_bits {
3499         u8         opcode[0x10];
3500         u8         reserved_0[0x10];
3501
3502         u8         reserved_1[0x10];
3503         u8         op_mod[0x10];
3504
3505         u8         reserved_2[0x8];
3506         u8         mkey_index[0x18];
3507
3508         u8         pg_access[0x1];
3509         u8         reserved_3[0x1f];
3510 };
3511
3512 struct mlx5_ifc_query_mad_demux_out_bits {
3513         u8         status[0x8];
3514         u8         reserved_0[0x18];
3515
3516         u8         syndrome[0x20];
3517
3518         u8         reserved_1[0x40];
3519
3520         u8         mad_dumux_parameters_block[0x20];
3521 };
3522
3523 struct mlx5_ifc_query_mad_demux_in_bits {
3524         u8         opcode[0x10];
3525         u8         reserved_0[0x10];
3526
3527         u8         reserved_1[0x10];
3528         u8         op_mod[0x10];
3529
3530         u8         reserved_2[0x40];
3531 };
3532
3533 struct mlx5_ifc_query_l2_table_entry_out_bits {
3534         u8         status[0x8];
3535         u8         reserved_0[0x18];
3536
3537         u8         syndrome[0x20];
3538
3539         u8         reserved_1[0xa0];
3540
3541         u8         reserved_2[0x13];
3542         u8         vlan_valid[0x1];
3543         u8         vlan[0xc];
3544
3545         struct mlx5_ifc_mac_address_layout_bits mac_address;
3546
3547         u8         reserved_3[0xc0];
3548 };
3549
3550 struct mlx5_ifc_query_l2_table_entry_in_bits {
3551         u8         opcode[0x10];
3552         u8         reserved_0[0x10];
3553
3554         u8         reserved_1[0x10];
3555         u8         op_mod[0x10];
3556
3557         u8         reserved_2[0x60];
3558
3559         u8         reserved_3[0x8];
3560         u8         table_index[0x18];
3561
3562         u8         reserved_4[0x140];
3563 };
3564
3565 struct mlx5_ifc_query_issi_out_bits {
3566         u8         status[0x8];
3567         u8         reserved_0[0x18];
3568
3569         u8         syndrome[0x20];
3570
3571         u8         reserved_1[0x10];
3572         u8         current_issi[0x10];
3573
3574         u8         reserved_2[0xa0];
3575
3576         u8         supported_issi_reserved[76][0x8];
3577         u8         supported_issi_dw0[0x20];
3578 };
3579
3580 struct mlx5_ifc_query_issi_in_bits {
3581         u8         opcode[0x10];
3582         u8         reserved_0[0x10];
3583
3584         u8         reserved_1[0x10];
3585         u8         op_mod[0x10];
3586
3587         u8         reserved_2[0x40];
3588 };
3589
3590 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3591         u8         status[0x8];
3592         u8         reserved_0[0x18];
3593
3594         u8         syndrome[0x20];
3595
3596         u8         reserved_1[0x40];
3597
3598         struct mlx5_ifc_pkey_bits pkey[0];
3599 };
3600
3601 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3602         u8         opcode[0x10];
3603         u8         reserved_0[0x10];
3604
3605         u8         reserved_1[0x10];
3606         u8         op_mod[0x10];
3607
3608         u8         other_vport[0x1];
3609         u8         reserved_2[0xb];
3610         u8         port_num[0x4];
3611         u8         vport_number[0x10];
3612
3613         u8         reserved_3[0x10];
3614         u8         pkey_index[0x10];
3615 };
3616
3617 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3618         u8         status[0x8];
3619         u8         reserved_0[0x18];
3620
3621         u8         syndrome[0x20];
3622
3623         u8         reserved_1[0x20];
3624
3625         u8         gids_num[0x10];
3626         u8         reserved_2[0x10];
3627
3628         struct mlx5_ifc_array128_auto_bits gid[0];
3629 };
3630
3631 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3632         u8         opcode[0x10];
3633         u8         reserved_0[0x10];
3634
3635         u8         reserved_1[0x10];
3636         u8         op_mod[0x10];
3637
3638         u8         other_vport[0x1];
3639         u8         reserved_2[0xb];
3640         u8         port_num[0x4];
3641         u8         vport_number[0x10];
3642
3643         u8         reserved_3[0x10];
3644         u8         gid_index[0x10];
3645 };
3646
3647 struct mlx5_ifc_query_hca_vport_context_out_bits {
3648         u8         status[0x8];
3649         u8         reserved_0[0x18];
3650
3651         u8         syndrome[0x20];
3652
3653         u8         reserved_1[0x40];
3654
3655         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3656 };
3657
3658 struct mlx5_ifc_query_hca_vport_context_in_bits {
3659         u8         opcode[0x10];
3660         u8         reserved_0[0x10];
3661
3662         u8         reserved_1[0x10];
3663         u8         op_mod[0x10];
3664
3665         u8         other_vport[0x1];
3666         u8         reserved_2[0xb];
3667         u8         port_num[0x4];
3668         u8         vport_number[0x10];
3669
3670         u8         reserved_3[0x20];
3671 };
3672
3673 struct mlx5_ifc_query_hca_cap_out_bits {
3674         u8         status[0x8];
3675         u8         reserved_0[0x18];
3676
3677         u8         syndrome[0x20];
3678
3679         u8         reserved_1[0x40];
3680
3681         union mlx5_ifc_hca_cap_union_bits capability;
3682 };
3683
3684 struct mlx5_ifc_query_hca_cap_in_bits {
3685         u8         opcode[0x10];
3686         u8         reserved_0[0x10];
3687
3688         u8         reserved_1[0x10];
3689         u8         op_mod[0x10];
3690
3691         u8         reserved_2[0x40];
3692 };
3693
3694 struct mlx5_ifc_query_flow_table_out_bits {
3695         u8         status[0x8];
3696         u8         reserved_0[0x18];
3697
3698         u8         syndrome[0x20];
3699
3700         u8         reserved_1[0x80];
3701
3702         u8         reserved_2[0x8];
3703         u8         level[0x8];
3704         u8         reserved_3[0x8];
3705         u8         log_size[0x8];
3706
3707         u8         reserved_4[0x120];
3708 };
3709
3710 struct mlx5_ifc_query_flow_table_in_bits {
3711         u8         opcode[0x10];
3712         u8         reserved_0[0x10];
3713
3714         u8         reserved_1[0x10];
3715         u8         op_mod[0x10];
3716
3717         u8         reserved_2[0x40];
3718
3719         u8         table_type[0x8];
3720         u8         reserved_3[0x18];
3721
3722         u8         reserved_4[0x8];
3723         u8         table_id[0x18];
3724
3725         u8         reserved_5[0x140];
3726 };
3727
3728 struct mlx5_ifc_query_fte_out_bits {
3729         u8         status[0x8];
3730         u8         reserved_0[0x18];
3731
3732         u8         syndrome[0x20];
3733
3734         u8         reserved_1[0x1c0];
3735
3736         struct mlx5_ifc_flow_context_bits flow_context;
3737 };
3738
3739 struct mlx5_ifc_query_fte_in_bits {
3740         u8         opcode[0x10];
3741         u8         reserved_0[0x10];
3742
3743         u8         reserved_1[0x10];
3744         u8         op_mod[0x10];
3745
3746         u8         reserved_2[0x40];
3747
3748         u8         table_type[0x8];
3749         u8         reserved_3[0x18];
3750
3751         u8         reserved_4[0x8];
3752         u8         table_id[0x18];
3753
3754         u8         reserved_5[0x40];
3755
3756         u8         flow_index[0x20];
3757
3758         u8         reserved_6[0xe0];
3759 };
3760
3761 enum {
3762         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
3763         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
3764         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
3765 };
3766
3767 struct mlx5_ifc_query_flow_group_out_bits {
3768         u8         status[0x8];
3769         u8         reserved_0[0x18];
3770
3771         u8         syndrome[0x20];
3772
3773         u8         reserved_1[0xa0];
3774
3775         u8         start_flow_index[0x20];
3776
3777         u8         reserved_2[0x20];
3778
3779         u8         end_flow_index[0x20];
3780
3781         u8         reserved_3[0xa0];
3782
3783         u8         reserved_4[0x18];
3784         u8         match_criteria_enable[0x8];
3785
3786         struct mlx5_ifc_fte_match_param_bits match_criteria;
3787
3788         u8         reserved_5[0xe00];
3789 };
3790
3791 struct mlx5_ifc_query_flow_group_in_bits {
3792         u8         opcode[0x10];
3793         u8         reserved_0[0x10];
3794
3795         u8         reserved_1[0x10];
3796         u8         op_mod[0x10];
3797
3798         u8         reserved_2[0x40];
3799
3800         u8         table_type[0x8];
3801         u8         reserved_3[0x18];
3802
3803         u8         reserved_4[0x8];
3804         u8         table_id[0x18];
3805
3806         u8         group_id[0x20];
3807
3808         u8         reserved_5[0x120];
3809 };
3810
3811 struct mlx5_ifc_query_esw_vport_context_out_bits {
3812         u8         status[0x8];
3813         u8         reserved_0[0x18];
3814
3815         u8         syndrome[0x20];
3816
3817         u8         reserved_1[0x40];
3818
3819         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3820 };
3821
3822 struct mlx5_ifc_query_esw_vport_context_in_bits {
3823         u8         opcode[0x10];
3824         u8         reserved_0[0x10];
3825
3826         u8         reserved_1[0x10];
3827         u8         op_mod[0x10];
3828
3829         u8         other_vport[0x1];
3830         u8         reserved_2[0xf];
3831         u8         vport_number[0x10];
3832
3833         u8         reserved_3[0x20];
3834 };
3835
3836 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3837         u8         status[0x8];
3838         u8         reserved_0[0x18];
3839
3840         u8         syndrome[0x20];
3841
3842         u8         reserved_1[0x40];
3843 };
3844
3845 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3846         u8         reserved[0x1c];
3847         u8         vport_cvlan_insert[0x1];
3848         u8         vport_svlan_insert[0x1];
3849         u8         vport_cvlan_strip[0x1];
3850         u8         vport_svlan_strip[0x1];
3851 };
3852
3853 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3854         u8         opcode[0x10];
3855         u8         reserved_0[0x10];
3856
3857         u8         reserved_1[0x10];
3858         u8         op_mod[0x10];
3859
3860         u8         other_vport[0x1];
3861         u8         reserved_2[0xf];
3862         u8         vport_number[0x10];
3863
3864         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3865
3866         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3867 };
3868
3869 struct mlx5_ifc_query_eq_out_bits {
3870         u8         status[0x8];
3871         u8         reserved_0[0x18];
3872
3873         u8         syndrome[0x20];
3874
3875         u8         reserved_1[0x40];
3876
3877         struct mlx5_ifc_eqc_bits eq_context_entry;
3878
3879         u8         reserved_2[0x40];
3880
3881         u8         event_bitmask[0x40];
3882
3883         u8         reserved_3[0x580];
3884
3885         u8         pas[0][0x40];
3886 };
3887
3888 struct mlx5_ifc_query_eq_in_bits {
3889         u8         opcode[0x10];
3890         u8         reserved_0[0x10];
3891
3892         u8         reserved_1[0x10];
3893         u8         op_mod[0x10];
3894
3895         u8         reserved_2[0x18];
3896         u8         eq_number[0x8];
3897
3898         u8         reserved_3[0x20];
3899 };
3900
3901 struct mlx5_ifc_query_dct_out_bits {
3902         u8         status[0x8];
3903         u8         reserved_0[0x18];
3904
3905         u8         syndrome[0x20];
3906
3907         u8         reserved_1[0x40];
3908
3909         struct mlx5_ifc_dctc_bits dct_context_entry;
3910
3911         u8         reserved_2[0x180];
3912 };
3913
3914 struct mlx5_ifc_query_dct_in_bits {
3915         u8         opcode[0x10];
3916         u8         reserved_0[0x10];
3917
3918         u8         reserved_1[0x10];
3919         u8         op_mod[0x10];
3920
3921         u8         reserved_2[0x8];
3922         u8         dctn[0x18];
3923
3924         u8         reserved_3[0x20];
3925 };
3926
3927 struct mlx5_ifc_query_cq_out_bits {
3928         u8         status[0x8];
3929         u8         reserved_0[0x18];
3930
3931         u8         syndrome[0x20];
3932
3933         u8         reserved_1[0x40];
3934
3935         struct mlx5_ifc_cqc_bits cq_context;
3936
3937         u8         reserved_2[0x600];
3938
3939         u8         pas[0][0x40];
3940 };
3941
3942 struct mlx5_ifc_query_cq_in_bits {
3943         u8         opcode[0x10];
3944         u8         reserved_0[0x10];
3945
3946         u8         reserved_1[0x10];
3947         u8         op_mod[0x10];
3948
3949         u8         reserved_2[0x8];
3950         u8         cqn[0x18];
3951
3952         u8         reserved_3[0x20];
3953 };
3954
3955 struct mlx5_ifc_query_cong_status_out_bits {
3956         u8         status[0x8];
3957         u8         reserved_0[0x18];
3958
3959         u8         syndrome[0x20];
3960
3961         u8         reserved_1[0x20];
3962
3963         u8         enable[0x1];
3964         u8         tag_enable[0x1];
3965         u8         reserved_2[0x1e];
3966 };
3967
3968 struct mlx5_ifc_query_cong_status_in_bits {
3969         u8         opcode[0x10];
3970         u8         reserved_0[0x10];
3971
3972         u8         reserved_1[0x10];
3973         u8         op_mod[0x10];
3974
3975         u8         reserved_2[0x18];
3976         u8         priority[0x4];
3977         u8         cong_protocol[0x4];
3978
3979         u8         reserved_3[0x20];
3980 };
3981
3982 struct mlx5_ifc_query_cong_statistics_out_bits {
3983         u8         status[0x8];
3984         u8         reserved_0[0x18];
3985
3986         u8         syndrome[0x20];
3987
3988         u8         reserved_1[0x40];
3989
3990         u8         cur_flows[0x20];
3991
3992         u8         sum_flows[0x20];
3993
3994         u8         cnp_ignored_high[0x20];
3995
3996         u8         cnp_ignored_low[0x20];
3997
3998         u8         cnp_handled_high[0x20];
3999
4000         u8         cnp_handled_low[0x20];
4001
4002         u8         reserved_2[0x100];
4003
4004         u8         time_stamp_high[0x20];
4005
4006         u8         time_stamp_low[0x20];
4007
4008         u8         accumulators_period[0x20];
4009
4010         u8         ecn_marked_roce_packets_high[0x20];
4011
4012         u8         ecn_marked_roce_packets_low[0x20];
4013
4014         u8         cnps_sent_high[0x20];
4015
4016         u8         cnps_sent_low[0x20];
4017
4018         u8         reserved_3[0x560];
4019 };
4020
4021 struct mlx5_ifc_query_cong_statistics_in_bits {
4022         u8         opcode[0x10];
4023         u8         reserved_0[0x10];
4024
4025         u8         reserved_1[0x10];
4026         u8         op_mod[0x10];
4027
4028         u8         clear[0x1];
4029         u8         reserved_2[0x1f];
4030
4031         u8         reserved_3[0x20];
4032 };
4033
4034 struct mlx5_ifc_query_cong_params_out_bits {
4035         u8         status[0x8];
4036         u8         reserved_0[0x18];
4037
4038         u8         syndrome[0x20];
4039
4040         u8         reserved_1[0x40];
4041
4042         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4043 };
4044
4045 struct mlx5_ifc_query_cong_params_in_bits {
4046         u8         opcode[0x10];
4047         u8         reserved_0[0x10];
4048
4049         u8         reserved_1[0x10];
4050         u8         op_mod[0x10];
4051
4052         u8         reserved_2[0x1c];
4053         u8         cong_protocol[0x4];
4054
4055         u8         reserved_3[0x20];
4056 };
4057
4058 struct mlx5_ifc_query_adapter_out_bits {
4059         u8         status[0x8];
4060         u8         reserved_0[0x18];
4061
4062         u8         syndrome[0x20];
4063
4064         u8         reserved_1[0x40];
4065
4066         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4067 };
4068
4069 struct mlx5_ifc_query_adapter_in_bits {
4070         u8         opcode[0x10];
4071         u8         reserved_0[0x10];
4072
4073         u8         reserved_1[0x10];
4074         u8         op_mod[0x10];
4075
4076         u8         reserved_2[0x40];
4077 };
4078
4079 struct mlx5_ifc_qp_2rst_out_bits {
4080         u8         status[0x8];
4081         u8         reserved_0[0x18];
4082
4083         u8         syndrome[0x20];
4084
4085         u8         reserved_1[0x40];
4086 };
4087
4088 struct mlx5_ifc_qp_2rst_in_bits {
4089         u8         opcode[0x10];
4090         u8         reserved_0[0x10];
4091
4092         u8         reserved_1[0x10];
4093         u8         op_mod[0x10];
4094
4095         u8         reserved_2[0x8];
4096         u8         qpn[0x18];
4097
4098         u8         reserved_3[0x20];
4099 };
4100
4101 struct mlx5_ifc_qp_2err_out_bits {
4102         u8         status[0x8];
4103         u8         reserved_0[0x18];
4104
4105         u8         syndrome[0x20];
4106
4107         u8         reserved_1[0x40];
4108 };
4109
4110 struct mlx5_ifc_qp_2err_in_bits {
4111         u8         opcode[0x10];
4112         u8         reserved_0[0x10];
4113
4114         u8         reserved_1[0x10];
4115         u8         op_mod[0x10];
4116
4117         u8         reserved_2[0x8];
4118         u8         qpn[0x18];
4119
4120         u8         reserved_3[0x20];
4121 };
4122
4123 struct mlx5_ifc_page_fault_resume_out_bits {
4124         u8         status[0x8];
4125         u8         reserved_0[0x18];
4126
4127         u8         syndrome[0x20];
4128
4129         u8         reserved_1[0x40];
4130 };
4131
4132 struct mlx5_ifc_page_fault_resume_in_bits {
4133         u8         opcode[0x10];
4134         u8         reserved_0[0x10];
4135
4136         u8         reserved_1[0x10];
4137         u8         op_mod[0x10];
4138
4139         u8         error[0x1];
4140         u8         reserved_2[0x4];
4141         u8         rdma[0x1];
4142         u8         read_write[0x1];
4143         u8         req_res[0x1];
4144         u8         qpn[0x18];
4145
4146         u8         reserved_3[0x20];
4147 };
4148
4149 struct mlx5_ifc_nop_out_bits {
4150         u8         status[0x8];
4151         u8         reserved_0[0x18];
4152
4153         u8         syndrome[0x20];
4154
4155         u8         reserved_1[0x40];
4156 };
4157
4158 struct mlx5_ifc_nop_in_bits {
4159         u8         opcode[0x10];
4160         u8         reserved_0[0x10];
4161
4162         u8         reserved_1[0x10];
4163         u8         op_mod[0x10];
4164
4165         u8         reserved_2[0x40];
4166 };
4167
4168 struct mlx5_ifc_modify_vport_state_out_bits {
4169         u8         status[0x8];
4170         u8         reserved_0[0x18];
4171
4172         u8         syndrome[0x20];
4173
4174         u8         reserved_1[0x40];
4175 };
4176
4177 struct mlx5_ifc_modify_vport_state_in_bits {
4178         u8         opcode[0x10];
4179         u8         reserved_0[0x10];
4180
4181         u8         reserved_1[0x10];
4182         u8         op_mod[0x10];
4183
4184         u8         other_vport[0x1];
4185         u8         reserved_2[0xf];
4186         u8         vport_number[0x10];
4187
4188         u8         reserved_3[0x18];
4189         u8         admin_state[0x4];
4190         u8         reserved_4[0x4];
4191 };
4192
4193 struct mlx5_ifc_modify_tis_out_bits {
4194         u8         status[0x8];
4195         u8         reserved_0[0x18];
4196
4197         u8         syndrome[0x20];
4198
4199         u8         reserved_1[0x40];
4200 };
4201
4202 struct mlx5_ifc_modify_tis_in_bits {
4203         u8         opcode[0x10];
4204         u8         reserved_0[0x10];
4205
4206         u8         reserved_1[0x10];
4207         u8         op_mod[0x10];
4208
4209         u8         reserved_2[0x8];
4210         u8         tisn[0x18];
4211
4212         u8         reserved_3[0x20];
4213
4214         u8         modify_bitmask[0x40];
4215
4216         u8         reserved_4[0x40];
4217
4218         struct mlx5_ifc_tisc_bits ctx;
4219 };
4220
4221 struct mlx5_ifc_modify_tir_bitmask_bits {
4222         u8         reserved_0[0x20];
4223
4224         u8         reserved_1[0x1b];
4225         u8         self_lb_en[0x1];
4226         u8         reserved_2[0x3];
4227         u8         lro[0x1];
4228 };
4229
4230 struct mlx5_ifc_modify_tir_out_bits {
4231         u8         status[0x8];
4232         u8         reserved_0[0x18];
4233
4234         u8         syndrome[0x20];
4235
4236         u8         reserved_1[0x40];
4237 };
4238
4239 struct mlx5_ifc_modify_tir_in_bits {
4240         u8         opcode[0x10];
4241         u8         reserved_0[0x10];
4242
4243         u8         reserved_1[0x10];
4244         u8         op_mod[0x10];
4245
4246         u8         reserved_2[0x8];
4247         u8         tirn[0x18];
4248
4249         u8         reserved_3[0x20];
4250
4251         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4252
4253         u8         reserved_4[0x40];
4254
4255         struct mlx5_ifc_tirc_bits ctx;
4256 };
4257
4258 struct mlx5_ifc_modify_sq_out_bits {
4259         u8         status[0x8];
4260         u8         reserved_0[0x18];
4261
4262         u8         syndrome[0x20];
4263
4264         u8         reserved_1[0x40];
4265 };
4266
4267 struct mlx5_ifc_modify_sq_in_bits {
4268         u8         opcode[0x10];
4269         u8         reserved_0[0x10];
4270
4271         u8         reserved_1[0x10];
4272         u8         op_mod[0x10];
4273
4274         u8         sq_state[0x4];
4275         u8         reserved_2[0x4];
4276         u8         sqn[0x18];
4277
4278         u8         reserved_3[0x20];
4279
4280         u8         modify_bitmask[0x40];
4281
4282         u8         reserved_4[0x40];
4283
4284         struct mlx5_ifc_sqc_bits ctx;
4285 };
4286
4287 struct mlx5_ifc_modify_rqt_out_bits {
4288         u8         status[0x8];
4289         u8         reserved_0[0x18];
4290
4291         u8         syndrome[0x20];
4292
4293         u8         reserved_1[0x40];
4294 };
4295
4296 struct mlx5_ifc_rqt_bitmask_bits {
4297         u8         reserved[0x20];
4298
4299         u8         reserved1[0x1f];
4300         u8         rqn_list[0x1];
4301 };
4302
4303 struct mlx5_ifc_modify_rqt_in_bits {
4304         u8         opcode[0x10];
4305         u8         reserved_0[0x10];
4306
4307         u8         reserved_1[0x10];
4308         u8         op_mod[0x10];
4309
4310         u8         reserved_2[0x8];
4311         u8         rqtn[0x18];
4312
4313         u8         reserved_3[0x20];
4314
4315         struct mlx5_ifc_rqt_bitmask_bits bitmask;
4316
4317         u8         reserved_4[0x40];
4318
4319         struct mlx5_ifc_rqtc_bits ctx;
4320 };
4321
4322 struct mlx5_ifc_modify_rq_out_bits {
4323         u8         status[0x8];
4324         u8         reserved_0[0x18];
4325
4326         u8         syndrome[0x20];
4327
4328         u8         reserved_1[0x40];
4329 };
4330
4331 struct mlx5_ifc_modify_rq_in_bits {
4332         u8         opcode[0x10];
4333         u8         reserved_0[0x10];
4334
4335         u8         reserved_1[0x10];
4336         u8         op_mod[0x10];
4337
4338         u8         rq_state[0x4];
4339         u8         reserved_2[0x4];
4340         u8         rqn[0x18];
4341
4342         u8         reserved_3[0x20];
4343
4344         u8         modify_bitmask[0x40];
4345
4346         u8         reserved_4[0x40];
4347
4348         struct mlx5_ifc_rqc_bits ctx;
4349 };
4350
4351 struct mlx5_ifc_modify_rmp_out_bits {
4352         u8         status[0x8];
4353         u8         reserved_0[0x18];
4354
4355         u8         syndrome[0x20];
4356
4357         u8         reserved_1[0x40];
4358 };
4359
4360 struct mlx5_ifc_rmp_bitmask_bits {
4361         u8         reserved[0x20];
4362
4363         u8         reserved1[0x1f];
4364         u8         lwm[0x1];
4365 };
4366
4367 struct mlx5_ifc_modify_rmp_in_bits {
4368         u8         opcode[0x10];
4369         u8         reserved_0[0x10];
4370
4371         u8         reserved_1[0x10];
4372         u8         op_mod[0x10];
4373
4374         u8         rmp_state[0x4];
4375         u8         reserved_2[0x4];
4376         u8         rmpn[0x18];
4377
4378         u8         reserved_3[0x20];
4379
4380         struct mlx5_ifc_rmp_bitmask_bits bitmask;
4381
4382         u8         reserved_4[0x40];
4383
4384         struct mlx5_ifc_rmpc_bits ctx;
4385 };
4386
4387 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4388         u8         status[0x8];
4389         u8         reserved_0[0x18];
4390
4391         u8         syndrome[0x20];
4392
4393         u8         reserved_1[0x40];
4394 };
4395
4396 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4397         u8         reserved_0[0x19];
4398         u8         mtu[0x1];
4399         u8         change_event[0x1];
4400         u8         promisc[0x1];
4401         u8         permanent_address[0x1];
4402         u8         addresses_list[0x1];
4403         u8         roce_en[0x1];
4404         u8         reserved_1[0x1];
4405 };
4406
4407 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4408         u8         opcode[0x10];
4409         u8         reserved_0[0x10];
4410
4411         u8         reserved_1[0x10];
4412         u8         op_mod[0x10];
4413
4414         u8         other_vport[0x1];
4415         u8         reserved_2[0xf];
4416         u8         vport_number[0x10];
4417
4418         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4419
4420         u8         reserved_3[0x780];
4421
4422         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4423 };
4424
4425 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4426         u8         status[0x8];
4427         u8         reserved_0[0x18];
4428
4429         u8         syndrome[0x20];
4430
4431         u8         reserved_1[0x40];
4432 };
4433
4434 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4435         u8         opcode[0x10];
4436         u8         reserved_0[0x10];
4437
4438         u8         reserved_1[0x10];
4439         u8         op_mod[0x10];
4440
4441         u8         other_vport[0x1];
4442         u8         reserved_2[0xb];
4443         u8         port_num[0x4];
4444         u8         vport_number[0x10];
4445
4446         u8         reserved_3[0x20];
4447
4448         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4449 };
4450
4451 struct mlx5_ifc_modify_cq_out_bits {
4452         u8         status[0x8];
4453         u8         reserved_0[0x18];
4454
4455         u8         syndrome[0x20];
4456
4457         u8         reserved_1[0x40];
4458 };
4459
4460 enum {
4461         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
4462         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
4463 };
4464
4465 struct mlx5_ifc_modify_cq_in_bits {
4466         u8         opcode[0x10];
4467         u8         reserved_0[0x10];
4468
4469         u8         reserved_1[0x10];
4470         u8         op_mod[0x10];
4471
4472         u8         reserved_2[0x8];
4473         u8         cqn[0x18];
4474
4475         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4476
4477         struct mlx5_ifc_cqc_bits cq_context;
4478
4479         u8         reserved_3[0x600];
4480
4481         u8         pas[0][0x40];
4482 };
4483
4484 struct mlx5_ifc_modify_cong_status_out_bits {
4485         u8         status[0x8];
4486         u8         reserved_0[0x18];
4487
4488         u8         syndrome[0x20];
4489
4490         u8         reserved_1[0x40];
4491 };
4492
4493 struct mlx5_ifc_modify_cong_status_in_bits {
4494         u8         opcode[0x10];
4495         u8         reserved_0[0x10];
4496
4497         u8         reserved_1[0x10];
4498         u8         op_mod[0x10];
4499
4500         u8         reserved_2[0x18];
4501         u8         priority[0x4];
4502         u8         cong_protocol[0x4];
4503
4504         u8         enable[0x1];
4505         u8         tag_enable[0x1];
4506         u8         reserved_3[0x1e];
4507 };
4508
4509 struct mlx5_ifc_modify_cong_params_out_bits {
4510         u8         status[0x8];
4511         u8         reserved_0[0x18];
4512
4513         u8         syndrome[0x20];
4514
4515         u8         reserved_1[0x40];
4516 };
4517
4518 struct mlx5_ifc_modify_cong_params_in_bits {
4519         u8         opcode[0x10];
4520         u8         reserved_0[0x10];
4521
4522         u8         reserved_1[0x10];
4523         u8         op_mod[0x10];
4524
4525         u8         reserved_2[0x1c];
4526         u8         cong_protocol[0x4];
4527
4528         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4529
4530         u8         reserved_3[0x80];
4531
4532         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4533 };
4534
4535 struct mlx5_ifc_manage_pages_out_bits {
4536         u8         status[0x8];
4537         u8         reserved_0[0x18];
4538
4539         u8         syndrome[0x20];
4540
4541         u8         output_num_entries[0x20];
4542
4543         u8         reserved_1[0x20];
4544
4545         u8         pas[0][0x40];
4546 };
4547
4548 enum {
4549         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
4550         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
4551         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
4552 };
4553
4554 struct mlx5_ifc_manage_pages_in_bits {
4555         u8         opcode[0x10];
4556         u8         reserved_0[0x10];
4557
4558         u8         reserved_1[0x10];
4559         u8         op_mod[0x10];
4560
4561         u8         reserved_2[0x10];
4562         u8         function_id[0x10];
4563
4564         u8         input_num_entries[0x20];
4565
4566         u8         pas[0][0x40];
4567 };
4568
4569 struct mlx5_ifc_mad_ifc_out_bits {
4570         u8         status[0x8];
4571         u8         reserved_0[0x18];
4572
4573         u8         syndrome[0x20];
4574
4575         u8         reserved_1[0x40];
4576
4577         u8         response_mad_packet[256][0x8];
4578 };
4579
4580 struct mlx5_ifc_mad_ifc_in_bits {
4581         u8         opcode[0x10];
4582         u8         reserved_0[0x10];
4583
4584         u8         reserved_1[0x10];
4585         u8         op_mod[0x10];
4586
4587         u8         remote_lid[0x10];
4588         u8         reserved_2[0x8];
4589         u8         port[0x8];
4590
4591         u8         reserved_3[0x20];
4592
4593         u8         mad[256][0x8];
4594 };
4595
4596 struct mlx5_ifc_init_hca_out_bits {
4597         u8         status[0x8];
4598         u8         reserved_0[0x18];
4599
4600         u8         syndrome[0x20];
4601
4602         u8         reserved_1[0x40];
4603 };
4604
4605 struct mlx5_ifc_init_hca_in_bits {
4606         u8         opcode[0x10];
4607         u8         reserved_0[0x10];
4608
4609         u8         reserved_1[0x10];
4610         u8         op_mod[0x10];
4611
4612         u8         reserved_2[0x40];
4613 };
4614
4615 struct mlx5_ifc_init2rtr_qp_out_bits {
4616         u8         status[0x8];
4617         u8         reserved_0[0x18];
4618
4619         u8         syndrome[0x20];
4620
4621         u8         reserved_1[0x40];
4622 };
4623
4624 struct mlx5_ifc_init2rtr_qp_in_bits {
4625         u8         opcode[0x10];
4626         u8         reserved_0[0x10];
4627
4628         u8         reserved_1[0x10];
4629         u8         op_mod[0x10];
4630
4631         u8         reserved_2[0x8];
4632         u8         qpn[0x18];
4633
4634         u8         reserved_3[0x20];
4635
4636         u8         opt_param_mask[0x20];
4637
4638         u8         reserved_4[0x20];
4639
4640         struct mlx5_ifc_qpc_bits qpc;
4641
4642         u8         reserved_5[0x80];
4643 };
4644
4645 struct mlx5_ifc_init2init_qp_out_bits {
4646         u8         status[0x8];
4647         u8         reserved_0[0x18];
4648
4649         u8         syndrome[0x20];
4650
4651         u8         reserved_1[0x40];
4652 };
4653
4654 struct mlx5_ifc_init2init_qp_in_bits {
4655         u8         opcode[0x10];
4656         u8         reserved_0[0x10];
4657
4658         u8         reserved_1[0x10];
4659         u8         op_mod[0x10];
4660
4661         u8         reserved_2[0x8];
4662         u8         qpn[0x18];
4663
4664         u8         reserved_3[0x20];
4665
4666         u8         opt_param_mask[0x20];
4667
4668         u8         reserved_4[0x20];
4669
4670         struct mlx5_ifc_qpc_bits qpc;
4671
4672         u8         reserved_5[0x80];
4673 };
4674
4675 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4676         u8         status[0x8];
4677         u8         reserved_0[0x18];
4678
4679         u8         syndrome[0x20];
4680
4681         u8         reserved_1[0x40];
4682
4683         u8         packet_headers_log[128][0x8];
4684
4685         u8         packet_syndrome[64][0x8];
4686 };
4687
4688 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4689         u8         opcode[0x10];
4690         u8         reserved_0[0x10];
4691
4692         u8         reserved_1[0x10];
4693         u8         op_mod[0x10];
4694
4695         u8         reserved_2[0x40];
4696 };
4697
4698 struct mlx5_ifc_gen_eqe_in_bits {
4699         u8         opcode[0x10];
4700         u8         reserved_0[0x10];
4701
4702         u8         reserved_1[0x10];
4703         u8         op_mod[0x10];
4704
4705         u8         reserved_2[0x18];
4706         u8         eq_number[0x8];
4707
4708         u8         reserved_3[0x20];
4709
4710         u8         eqe[64][0x8];
4711 };
4712
4713 struct mlx5_ifc_gen_eq_out_bits {
4714         u8         status[0x8];
4715         u8         reserved_0[0x18];
4716
4717         u8         syndrome[0x20];
4718
4719         u8         reserved_1[0x40];
4720 };
4721
4722 struct mlx5_ifc_enable_hca_out_bits {
4723         u8         status[0x8];
4724         u8         reserved_0[0x18];
4725
4726         u8         syndrome[0x20];
4727
4728         u8         reserved_1[0x20];
4729 };
4730
4731 struct mlx5_ifc_enable_hca_in_bits {
4732         u8         opcode[0x10];
4733         u8         reserved_0[0x10];
4734
4735         u8         reserved_1[0x10];
4736         u8         op_mod[0x10];
4737
4738         u8         reserved_2[0x10];
4739         u8         function_id[0x10];
4740
4741         u8         reserved_3[0x20];
4742 };
4743
4744 struct mlx5_ifc_drain_dct_out_bits {
4745         u8         status[0x8];
4746         u8         reserved_0[0x18];
4747
4748         u8         syndrome[0x20];
4749
4750         u8         reserved_1[0x40];
4751 };
4752
4753 struct mlx5_ifc_drain_dct_in_bits {
4754         u8         opcode[0x10];
4755         u8         reserved_0[0x10];
4756
4757         u8         reserved_1[0x10];
4758         u8         op_mod[0x10];
4759
4760         u8         reserved_2[0x8];
4761         u8         dctn[0x18];
4762
4763         u8         reserved_3[0x20];
4764 };
4765
4766 struct mlx5_ifc_disable_hca_out_bits {
4767         u8         status[0x8];
4768         u8         reserved_0[0x18];
4769
4770         u8         syndrome[0x20];
4771
4772         u8         reserved_1[0x20];
4773 };
4774
4775 struct mlx5_ifc_disable_hca_in_bits {
4776         u8         opcode[0x10];
4777         u8         reserved_0[0x10];
4778
4779         u8         reserved_1[0x10];
4780         u8         op_mod[0x10];
4781
4782         u8         reserved_2[0x10];
4783         u8         function_id[0x10];
4784
4785         u8         reserved_3[0x20];
4786 };
4787
4788 struct mlx5_ifc_detach_from_mcg_out_bits {
4789         u8         status[0x8];
4790         u8         reserved_0[0x18];
4791
4792         u8         syndrome[0x20];
4793
4794         u8         reserved_1[0x40];
4795 };
4796
4797 struct mlx5_ifc_detach_from_mcg_in_bits {
4798         u8         opcode[0x10];
4799         u8         reserved_0[0x10];
4800
4801         u8         reserved_1[0x10];
4802         u8         op_mod[0x10];
4803
4804         u8         reserved_2[0x8];
4805         u8         qpn[0x18];
4806
4807         u8         reserved_3[0x20];
4808
4809         u8         multicast_gid[16][0x8];
4810 };
4811
4812 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4813         u8         status[0x8];
4814         u8         reserved_0[0x18];
4815
4816         u8         syndrome[0x20];
4817
4818         u8         reserved_1[0x40];
4819 };
4820
4821 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4822         u8         opcode[0x10];
4823         u8         reserved_0[0x10];
4824
4825         u8         reserved_1[0x10];
4826         u8         op_mod[0x10];
4827
4828         u8         reserved_2[0x8];
4829         u8         xrc_srqn[0x18];
4830
4831         u8         reserved_3[0x20];
4832 };
4833
4834 struct mlx5_ifc_destroy_tis_out_bits {
4835         u8         status[0x8];
4836         u8         reserved_0[0x18];
4837
4838         u8         syndrome[0x20];
4839
4840         u8         reserved_1[0x40];
4841 };
4842
4843 struct mlx5_ifc_destroy_tis_in_bits {
4844         u8         opcode[0x10];
4845         u8         reserved_0[0x10];
4846
4847         u8         reserved_1[0x10];
4848         u8         op_mod[0x10];
4849
4850         u8         reserved_2[0x8];
4851         u8         tisn[0x18];
4852
4853         u8         reserved_3[0x20];
4854 };
4855
4856 struct mlx5_ifc_destroy_tir_out_bits {
4857         u8         status[0x8];
4858         u8         reserved_0[0x18];
4859
4860         u8         syndrome[0x20];
4861
4862         u8         reserved_1[0x40];
4863 };
4864
4865 struct mlx5_ifc_destroy_tir_in_bits {
4866         u8         opcode[0x10];
4867         u8         reserved_0[0x10];
4868
4869         u8         reserved_1[0x10];
4870         u8         op_mod[0x10];
4871
4872         u8         reserved_2[0x8];
4873         u8         tirn[0x18];
4874
4875         u8         reserved_3[0x20];
4876 };
4877
4878 struct mlx5_ifc_destroy_srq_out_bits {
4879         u8         status[0x8];
4880         u8         reserved_0[0x18];
4881
4882         u8         syndrome[0x20];
4883
4884         u8         reserved_1[0x40];
4885 };
4886
4887 struct mlx5_ifc_destroy_srq_in_bits {
4888         u8         opcode[0x10];
4889         u8         reserved_0[0x10];
4890
4891         u8         reserved_1[0x10];
4892         u8         op_mod[0x10];
4893
4894         u8         reserved_2[0x8];
4895         u8         srqn[0x18];
4896
4897         u8         reserved_3[0x20];
4898 };
4899
4900 struct mlx5_ifc_destroy_sq_out_bits {
4901         u8         status[0x8];
4902         u8         reserved_0[0x18];
4903
4904         u8         syndrome[0x20];
4905
4906         u8         reserved_1[0x40];
4907 };
4908
4909 struct mlx5_ifc_destroy_sq_in_bits {
4910         u8         opcode[0x10];
4911         u8         reserved_0[0x10];
4912
4913         u8         reserved_1[0x10];
4914         u8         op_mod[0x10];
4915
4916         u8         reserved_2[0x8];
4917         u8         sqn[0x18];
4918
4919         u8         reserved_3[0x20];
4920 };
4921
4922 struct mlx5_ifc_destroy_rqt_out_bits {
4923         u8         status[0x8];
4924         u8         reserved_0[0x18];
4925
4926         u8         syndrome[0x20];
4927
4928         u8         reserved_1[0x40];
4929 };
4930
4931 struct mlx5_ifc_destroy_rqt_in_bits {
4932         u8         opcode[0x10];
4933         u8         reserved_0[0x10];
4934
4935         u8         reserved_1[0x10];
4936         u8         op_mod[0x10];
4937
4938         u8         reserved_2[0x8];
4939         u8         rqtn[0x18];
4940
4941         u8         reserved_3[0x20];
4942 };
4943
4944 struct mlx5_ifc_destroy_rq_out_bits {
4945         u8         status[0x8];
4946         u8         reserved_0[0x18];
4947
4948         u8         syndrome[0x20];
4949
4950         u8         reserved_1[0x40];
4951 };
4952
4953 struct mlx5_ifc_destroy_rq_in_bits {
4954         u8         opcode[0x10];
4955         u8         reserved_0[0x10];
4956
4957         u8         reserved_1[0x10];
4958         u8         op_mod[0x10];
4959
4960         u8         reserved_2[0x8];
4961         u8         rqn[0x18];
4962
4963         u8         reserved_3[0x20];
4964 };
4965
4966 struct mlx5_ifc_destroy_rmp_out_bits {
4967         u8         status[0x8];
4968         u8         reserved_0[0x18];
4969
4970         u8         syndrome[0x20];
4971
4972         u8         reserved_1[0x40];
4973 };
4974
4975 struct mlx5_ifc_destroy_rmp_in_bits {
4976         u8         opcode[0x10];
4977         u8         reserved_0[0x10];
4978
4979         u8         reserved_1[0x10];
4980         u8         op_mod[0x10];
4981
4982         u8         reserved_2[0x8];
4983         u8         rmpn[0x18];
4984
4985         u8         reserved_3[0x20];
4986 };
4987
4988 struct mlx5_ifc_destroy_qp_out_bits {
4989         u8         status[0x8];
4990         u8         reserved_0[0x18];
4991
4992         u8         syndrome[0x20];
4993
4994         u8         reserved_1[0x40];
4995 };
4996
4997 struct mlx5_ifc_destroy_qp_in_bits {
4998         u8         opcode[0x10];
4999         u8         reserved_0[0x10];
5000
5001         u8         reserved_1[0x10];
5002         u8         op_mod[0x10];
5003
5004         u8         reserved_2[0x8];
5005         u8         qpn[0x18];
5006
5007         u8         reserved_3[0x20];
5008 };
5009
5010 struct mlx5_ifc_destroy_psv_out_bits {
5011         u8         status[0x8];
5012         u8         reserved_0[0x18];
5013
5014         u8         syndrome[0x20];
5015
5016         u8         reserved_1[0x40];
5017 };
5018
5019 struct mlx5_ifc_destroy_psv_in_bits {
5020         u8         opcode[0x10];
5021         u8         reserved_0[0x10];
5022
5023         u8         reserved_1[0x10];
5024         u8         op_mod[0x10];
5025
5026         u8         reserved_2[0x8];
5027         u8         psvn[0x18];
5028
5029         u8         reserved_3[0x20];
5030 };
5031
5032 struct mlx5_ifc_destroy_mkey_out_bits {
5033         u8         status[0x8];
5034         u8         reserved_0[0x18];
5035
5036         u8         syndrome[0x20];
5037
5038         u8         reserved_1[0x40];
5039 };
5040
5041 struct mlx5_ifc_destroy_mkey_in_bits {
5042         u8         opcode[0x10];
5043         u8         reserved_0[0x10];
5044
5045         u8         reserved_1[0x10];
5046         u8         op_mod[0x10];
5047
5048         u8         reserved_2[0x8];
5049         u8         mkey_index[0x18];
5050
5051         u8         reserved_3[0x20];
5052 };
5053
5054 struct mlx5_ifc_destroy_flow_table_out_bits {
5055         u8         status[0x8];
5056         u8         reserved_0[0x18];
5057
5058         u8         syndrome[0x20];
5059
5060         u8         reserved_1[0x40];
5061 };
5062
5063 struct mlx5_ifc_destroy_flow_table_in_bits {
5064         u8         opcode[0x10];
5065         u8         reserved_0[0x10];
5066
5067         u8         reserved_1[0x10];
5068         u8         op_mod[0x10];
5069
5070         u8         reserved_2[0x40];
5071
5072         u8         table_type[0x8];
5073         u8         reserved_3[0x18];
5074
5075         u8         reserved_4[0x8];
5076         u8         table_id[0x18];
5077
5078         u8         reserved_5[0x140];
5079 };
5080
5081 struct mlx5_ifc_destroy_flow_group_out_bits {
5082         u8         status[0x8];
5083         u8         reserved_0[0x18];
5084
5085         u8         syndrome[0x20];
5086
5087         u8         reserved_1[0x40];
5088 };
5089
5090 struct mlx5_ifc_destroy_flow_group_in_bits {
5091         u8         opcode[0x10];
5092         u8         reserved_0[0x10];
5093
5094         u8         reserved_1[0x10];
5095         u8         op_mod[0x10];
5096
5097         u8         reserved_2[0x40];
5098
5099         u8         table_type[0x8];
5100         u8         reserved_3[0x18];
5101
5102         u8         reserved_4[0x8];
5103         u8         table_id[0x18];
5104
5105         u8         group_id[0x20];
5106
5107         u8         reserved_5[0x120];
5108 };
5109
5110 struct mlx5_ifc_destroy_eq_out_bits {
5111         u8         status[0x8];
5112         u8         reserved_0[0x18];
5113
5114         u8         syndrome[0x20];
5115
5116         u8         reserved_1[0x40];
5117 };
5118
5119 struct mlx5_ifc_destroy_eq_in_bits {
5120         u8         opcode[0x10];
5121         u8         reserved_0[0x10];
5122
5123         u8         reserved_1[0x10];
5124         u8         op_mod[0x10];
5125
5126         u8         reserved_2[0x18];
5127         u8         eq_number[0x8];
5128
5129         u8         reserved_3[0x20];
5130 };
5131
5132 struct mlx5_ifc_destroy_dct_out_bits {
5133         u8         status[0x8];
5134         u8         reserved_0[0x18];
5135
5136         u8         syndrome[0x20];
5137
5138         u8         reserved_1[0x40];
5139 };
5140
5141 struct mlx5_ifc_destroy_dct_in_bits {
5142         u8         opcode[0x10];
5143         u8         reserved_0[0x10];
5144
5145         u8         reserved_1[0x10];
5146         u8         op_mod[0x10];
5147
5148         u8         reserved_2[0x8];
5149         u8         dctn[0x18];
5150
5151         u8         reserved_3[0x20];
5152 };
5153
5154 struct mlx5_ifc_destroy_cq_out_bits {
5155         u8         status[0x8];
5156         u8         reserved_0[0x18];
5157
5158         u8         syndrome[0x20];
5159
5160         u8         reserved_1[0x40];
5161 };
5162
5163 struct mlx5_ifc_destroy_cq_in_bits {
5164         u8         opcode[0x10];
5165         u8         reserved_0[0x10];
5166
5167         u8         reserved_1[0x10];
5168         u8         op_mod[0x10];
5169
5170         u8         reserved_2[0x8];
5171         u8         cqn[0x18];
5172
5173         u8         reserved_3[0x20];
5174 };
5175
5176 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5177         u8         status[0x8];
5178         u8         reserved_0[0x18];
5179
5180         u8         syndrome[0x20];
5181
5182         u8         reserved_1[0x40];
5183 };
5184
5185 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5186         u8         opcode[0x10];
5187         u8         reserved_0[0x10];
5188
5189         u8         reserved_1[0x10];
5190         u8         op_mod[0x10];
5191
5192         u8         reserved_2[0x20];
5193
5194         u8         reserved_3[0x10];
5195         u8         vxlan_udp_port[0x10];
5196 };
5197
5198 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5199         u8         status[0x8];
5200         u8         reserved_0[0x18];
5201
5202         u8         syndrome[0x20];
5203
5204         u8         reserved_1[0x40];
5205 };
5206
5207 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5208         u8         opcode[0x10];
5209         u8         reserved_0[0x10];
5210
5211         u8         reserved_1[0x10];
5212         u8         op_mod[0x10];
5213
5214         u8         reserved_2[0x60];
5215
5216         u8         reserved_3[0x8];
5217         u8         table_index[0x18];
5218
5219         u8         reserved_4[0x140];
5220 };
5221
5222 struct mlx5_ifc_delete_fte_out_bits {
5223         u8         status[0x8];
5224         u8         reserved_0[0x18];
5225
5226         u8         syndrome[0x20];
5227
5228         u8         reserved_1[0x40];
5229 };
5230
5231 struct mlx5_ifc_delete_fte_in_bits {
5232         u8         opcode[0x10];
5233         u8         reserved_0[0x10];
5234
5235         u8         reserved_1[0x10];
5236         u8         op_mod[0x10];
5237
5238         u8         reserved_2[0x40];
5239
5240         u8         table_type[0x8];
5241         u8         reserved_3[0x18];
5242
5243         u8         reserved_4[0x8];
5244         u8         table_id[0x18];
5245
5246         u8         reserved_5[0x40];
5247
5248         u8         flow_index[0x20];
5249
5250         u8         reserved_6[0xe0];
5251 };
5252
5253 struct mlx5_ifc_dealloc_xrcd_out_bits {
5254         u8         status[0x8];
5255         u8         reserved_0[0x18];
5256
5257         u8         syndrome[0x20];
5258
5259         u8         reserved_1[0x40];
5260 };
5261
5262 struct mlx5_ifc_dealloc_xrcd_in_bits {
5263         u8         opcode[0x10];
5264         u8         reserved_0[0x10];
5265
5266         u8         reserved_1[0x10];
5267         u8         op_mod[0x10];
5268
5269         u8         reserved_2[0x8];
5270         u8         xrcd[0x18];
5271
5272         u8         reserved_3[0x20];
5273 };
5274
5275 struct mlx5_ifc_dealloc_uar_out_bits {
5276         u8         status[0x8];
5277         u8         reserved_0[0x18];
5278
5279         u8         syndrome[0x20];
5280
5281         u8         reserved_1[0x40];
5282 };
5283
5284 struct mlx5_ifc_dealloc_uar_in_bits {
5285         u8         opcode[0x10];
5286         u8         reserved_0[0x10];
5287
5288         u8         reserved_1[0x10];
5289         u8         op_mod[0x10];
5290
5291         u8         reserved_2[0x8];
5292         u8         uar[0x18];
5293
5294         u8         reserved_3[0x20];
5295 };
5296
5297 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5298         u8         status[0x8];
5299         u8         reserved_0[0x18];
5300
5301         u8         syndrome[0x20];
5302
5303         u8         reserved_1[0x40];
5304 };
5305
5306 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5307         u8         opcode[0x10];
5308         u8         reserved_0[0x10];
5309
5310         u8         reserved_1[0x10];
5311         u8         op_mod[0x10];
5312
5313         u8         reserved_2[0x8];
5314         u8         transport_domain[0x18];
5315
5316         u8         reserved_3[0x20];
5317 };
5318
5319 struct mlx5_ifc_dealloc_q_counter_out_bits {
5320         u8         status[0x8];
5321         u8         reserved_0[0x18];
5322
5323         u8         syndrome[0x20];
5324
5325         u8         reserved_1[0x40];
5326 };
5327
5328 struct mlx5_ifc_dealloc_q_counter_in_bits {
5329         u8         opcode[0x10];
5330         u8         reserved_0[0x10];
5331
5332         u8         reserved_1[0x10];
5333         u8         op_mod[0x10];
5334
5335         u8         reserved_2[0x18];
5336         u8         counter_set_id[0x8];
5337
5338         u8         reserved_3[0x20];
5339 };
5340
5341 struct mlx5_ifc_dealloc_pd_out_bits {
5342         u8         status[0x8];
5343         u8         reserved_0[0x18];
5344
5345         u8         syndrome[0x20];
5346
5347         u8         reserved_1[0x40];
5348 };
5349
5350 struct mlx5_ifc_dealloc_pd_in_bits {
5351         u8         opcode[0x10];
5352         u8         reserved_0[0x10];
5353
5354         u8         reserved_1[0x10];
5355         u8         op_mod[0x10];
5356
5357         u8         reserved_2[0x8];
5358         u8         pd[0x18];
5359
5360         u8         reserved_3[0x20];
5361 };
5362
5363 struct mlx5_ifc_create_xrc_srq_out_bits {
5364         u8         status[0x8];
5365         u8         reserved_0[0x18];
5366
5367         u8         syndrome[0x20];
5368
5369         u8         reserved_1[0x8];
5370         u8         xrc_srqn[0x18];
5371
5372         u8         reserved_2[0x20];
5373 };
5374
5375 struct mlx5_ifc_create_xrc_srq_in_bits {
5376         u8         opcode[0x10];
5377         u8         reserved_0[0x10];
5378
5379         u8         reserved_1[0x10];
5380         u8         op_mod[0x10];
5381
5382         u8         reserved_2[0x40];
5383
5384         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5385
5386         u8         reserved_3[0x600];
5387
5388         u8         pas[0][0x40];
5389 };
5390
5391 struct mlx5_ifc_create_tis_out_bits {
5392         u8         status[0x8];
5393         u8         reserved_0[0x18];
5394
5395         u8         syndrome[0x20];
5396
5397         u8         reserved_1[0x8];
5398         u8         tisn[0x18];
5399
5400         u8         reserved_2[0x20];
5401 };
5402
5403 struct mlx5_ifc_create_tis_in_bits {
5404         u8         opcode[0x10];
5405         u8         reserved_0[0x10];
5406
5407         u8         reserved_1[0x10];
5408         u8         op_mod[0x10];
5409
5410         u8         reserved_2[0xc0];
5411
5412         struct mlx5_ifc_tisc_bits ctx;
5413 };
5414
5415 struct mlx5_ifc_create_tir_out_bits {
5416         u8         status[0x8];
5417         u8         reserved_0[0x18];
5418
5419         u8         syndrome[0x20];
5420
5421         u8         reserved_1[0x8];
5422         u8         tirn[0x18];
5423
5424         u8         reserved_2[0x20];
5425 };
5426
5427 struct mlx5_ifc_create_tir_in_bits {
5428         u8         opcode[0x10];
5429         u8         reserved_0[0x10];
5430
5431         u8         reserved_1[0x10];
5432         u8         op_mod[0x10];
5433
5434         u8         reserved_2[0xc0];
5435
5436         struct mlx5_ifc_tirc_bits ctx;
5437 };
5438
5439 struct mlx5_ifc_create_srq_out_bits {
5440         u8         status[0x8];
5441         u8         reserved_0[0x18];
5442
5443         u8         syndrome[0x20];
5444
5445         u8         reserved_1[0x8];
5446         u8         srqn[0x18];
5447
5448         u8         reserved_2[0x20];
5449 };
5450
5451 struct mlx5_ifc_create_srq_in_bits {
5452         u8         opcode[0x10];
5453         u8         reserved_0[0x10];
5454
5455         u8         reserved_1[0x10];
5456         u8         op_mod[0x10];
5457
5458         u8         reserved_2[0x40];
5459
5460         struct mlx5_ifc_srqc_bits srq_context_entry;
5461
5462         u8         reserved_3[0x600];
5463
5464         u8         pas[0][0x40];
5465 };
5466
5467 struct mlx5_ifc_create_sq_out_bits {
5468         u8         status[0x8];
5469         u8         reserved_0[0x18];
5470
5471         u8         syndrome[0x20];
5472
5473         u8         reserved_1[0x8];
5474         u8         sqn[0x18];
5475
5476         u8         reserved_2[0x20];
5477 };
5478
5479 struct mlx5_ifc_create_sq_in_bits {
5480         u8         opcode[0x10];
5481         u8         reserved_0[0x10];
5482
5483         u8         reserved_1[0x10];
5484         u8         op_mod[0x10];
5485
5486         u8         reserved_2[0xc0];
5487
5488         struct mlx5_ifc_sqc_bits ctx;
5489 };
5490
5491 struct mlx5_ifc_create_rqt_out_bits {
5492         u8         status[0x8];
5493         u8         reserved_0[0x18];
5494
5495         u8         syndrome[0x20];
5496
5497         u8         reserved_1[0x8];
5498         u8         rqtn[0x18];
5499
5500         u8         reserved_2[0x20];
5501 };
5502
5503 struct mlx5_ifc_create_rqt_in_bits {
5504         u8         opcode[0x10];
5505         u8         reserved_0[0x10];
5506
5507         u8         reserved_1[0x10];
5508         u8         op_mod[0x10];
5509
5510         u8         reserved_2[0xc0];
5511
5512         struct mlx5_ifc_rqtc_bits rqt_context;
5513 };
5514
5515 struct mlx5_ifc_create_rq_out_bits {
5516         u8         status[0x8];
5517         u8         reserved_0[0x18];
5518
5519         u8         syndrome[0x20];
5520
5521         u8         reserved_1[0x8];
5522         u8         rqn[0x18];
5523
5524         u8         reserved_2[0x20];
5525 };
5526
5527 struct mlx5_ifc_create_rq_in_bits {
5528         u8         opcode[0x10];
5529         u8         reserved_0[0x10];
5530
5531         u8         reserved_1[0x10];
5532         u8         op_mod[0x10];
5533
5534         u8         reserved_2[0xc0];
5535
5536         struct mlx5_ifc_rqc_bits ctx;
5537 };
5538
5539 struct mlx5_ifc_create_rmp_out_bits {
5540         u8         status[0x8];
5541         u8         reserved_0[0x18];
5542
5543         u8         syndrome[0x20];
5544
5545         u8         reserved_1[0x8];
5546         u8         rmpn[0x18];
5547
5548         u8         reserved_2[0x20];
5549 };
5550
5551 struct mlx5_ifc_create_rmp_in_bits {
5552         u8         opcode[0x10];
5553         u8         reserved_0[0x10];
5554
5555         u8         reserved_1[0x10];
5556         u8         op_mod[0x10];
5557
5558         u8         reserved_2[0xc0];
5559
5560         struct mlx5_ifc_rmpc_bits ctx;
5561 };
5562
5563 struct mlx5_ifc_create_qp_out_bits {
5564         u8         status[0x8];
5565         u8         reserved_0[0x18];
5566
5567         u8         syndrome[0x20];
5568
5569         u8         reserved_1[0x8];
5570         u8         qpn[0x18];
5571
5572         u8         reserved_2[0x20];
5573 };
5574
5575 struct mlx5_ifc_create_qp_in_bits {
5576         u8         opcode[0x10];
5577         u8         reserved_0[0x10];
5578
5579         u8         reserved_1[0x10];
5580         u8         op_mod[0x10];
5581
5582         u8         reserved_2[0x40];
5583
5584         u8         opt_param_mask[0x20];
5585
5586         u8         reserved_3[0x20];
5587
5588         struct mlx5_ifc_qpc_bits qpc;
5589
5590         u8         reserved_4[0x80];
5591
5592         u8         pas[0][0x40];
5593 };
5594
5595 struct mlx5_ifc_create_psv_out_bits {
5596         u8         status[0x8];
5597         u8         reserved_0[0x18];
5598
5599         u8         syndrome[0x20];
5600
5601         u8         reserved_1[0x40];
5602
5603         u8         reserved_2[0x8];
5604         u8         psv0_index[0x18];
5605
5606         u8         reserved_3[0x8];
5607         u8         psv1_index[0x18];
5608
5609         u8         reserved_4[0x8];
5610         u8         psv2_index[0x18];
5611
5612         u8         reserved_5[0x8];
5613         u8         psv3_index[0x18];
5614 };
5615
5616 struct mlx5_ifc_create_psv_in_bits {
5617         u8         opcode[0x10];
5618         u8         reserved_0[0x10];
5619
5620         u8         reserved_1[0x10];
5621         u8         op_mod[0x10];
5622
5623         u8         num_psv[0x4];
5624         u8         reserved_2[0x4];
5625         u8         pd[0x18];
5626
5627         u8         reserved_3[0x20];
5628 };
5629
5630 struct mlx5_ifc_create_mkey_out_bits {
5631         u8         status[0x8];
5632         u8         reserved_0[0x18];
5633
5634         u8         syndrome[0x20];
5635
5636         u8         reserved_1[0x8];
5637         u8         mkey_index[0x18];
5638
5639         u8         reserved_2[0x20];
5640 };
5641
5642 struct mlx5_ifc_create_mkey_in_bits {
5643         u8         opcode[0x10];
5644         u8         reserved_0[0x10];
5645
5646         u8         reserved_1[0x10];
5647         u8         op_mod[0x10];
5648
5649         u8         reserved_2[0x20];
5650
5651         u8         pg_access[0x1];
5652         u8         reserved_3[0x1f];
5653
5654         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5655
5656         u8         reserved_4[0x80];
5657
5658         u8         translations_octword_actual_size[0x20];
5659
5660         u8         reserved_5[0x560];
5661
5662         u8         klm_pas_mtt[0][0x20];
5663 };
5664
5665 struct mlx5_ifc_create_flow_table_out_bits {
5666         u8         status[0x8];
5667         u8         reserved_0[0x18];
5668
5669         u8         syndrome[0x20];
5670
5671         u8         reserved_1[0x8];
5672         u8         table_id[0x18];
5673
5674         u8         reserved_2[0x20];
5675 };
5676
5677 struct mlx5_ifc_create_flow_table_in_bits {
5678         u8         opcode[0x10];
5679         u8         reserved_0[0x10];
5680
5681         u8         reserved_1[0x10];
5682         u8         op_mod[0x10];
5683
5684         u8         reserved_2[0x40];
5685
5686         u8         table_type[0x8];
5687         u8         reserved_3[0x18];
5688
5689         u8         reserved_4[0x20];
5690
5691         u8         reserved_5[0x4];
5692         u8         table_miss_mode[0x4];
5693         u8         level[0x8];
5694         u8         reserved_6[0x8];
5695         u8         log_size[0x8];
5696
5697         u8         reserved_7[0x8];
5698         u8         table_miss_id[0x18];
5699
5700         u8         reserved_8[0x100];
5701 };
5702
5703 struct mlx5_ifc_create_flow_group_out_bits {
5704         u8         status[0x8];
5705         u8         reserved_0[0x18];
5706
5707         u8         syndrome[0x20];
5708
5709         u8         reserved_1[0x8];
5710         u8         group_id[0x18];
5711
5712         u8         reserved_2[0x20];
5713 };
5714
5715 enum {
5716         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5717         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5718         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5719 };
5720
5721 struct mlx5_ifc_create_flow_group_in_bits {
5722         u8         opcode[0x10];
5723         u8         reserved_0[0x10];
5724
5725         u8         reserved_1[0x10];
5726         u8         op_mod[0x10];
5727
5728         u8         reserved_2[0x40];
5729
5730         u8         table_type[0x8];
5731         u8         reserved_3[0x18];
5732
5733         u8         reserved_4[0x8];
5734         u8         table_id[0x18];
5735
5736         u8         reserved_5[0x20];
5737
5738         u8         start_flow_index[0x20];
5739
5740         u8         reserved_6[0x20];
5741
5742         u8         end_flow_index[0x20];
5743
5744         u8         reserved_7[0xa0];
5745
5746         u8         reserved_8[0x18];
5747         u8         match_criteria_enable[0x8];
5748
5749         struct mlx5_ifc_fte_match_param_bits match_criteria;
5750
5751         u8         reserved_9[0xe00];
5752 };
5753
5754 struct mlx5_ifc_create_eq_out_bits {
5755         u8         status[0x8];
5756         u8         reserved_0[0x18];
5757
5758         u8         syndrome[0x20];
5759
5760         u8         reserved_1[0x18];
5761         u8         eq_number[0x8];
5762
5763         u8         reserved_2[0x20];
5764 };
5765
5766 struct mlx5_ifc_create_eq_in_bits {
5767         u8         opcode[0x10];
5768         u8         reserved_0[0x10];
5769
5770         u8         reserved_1[0x10];
5771         u8         op_mod[0x10];
5772
5773         u8         reserved_2[0x40];
5774
5775         struct mlx5_ifc_eqc_bits eq_context_entry;
5776
5777         u8         reserved_3[0x40];
5778
5779         u8         event_bitmask[0x40];
5780
5781         u8         reserved_4[0x580];
5782
5783         u8         pas[0][0x40];
5784 };
5785
5786 struct mlx5_ifc_create_dct_out_bits {
5787         u8         status[0x8];
5788         u8         reserved_0[0x18];
5789
5790         u8         syndrome[0x20];
5791
5792         u8         reserved_1[0x8];
5793         u8         dctn[0x18];
5794
5795         u8         reserved_2[0x20];
5796 };
5797
5798 struct mlx5_ifc_create_dct_in_bits {
5799         u8         opcode[0x10];
5800         u8         reserved_0[0x10];
5801
5802         u8         reserved_1[0x10];
5803         u8         op_mod[0x10];
5804
5805         u8         reserved_2[0x40];
5806
5807         struct mlx5_ifc_dctc_bits dct_context_entry;
5808
5809         u8         reserved_3[0x180];
5810 };
5811
5812 struct mlx5_ifc_create_cq_out_bits {
5813         u8         status[0x8];
5814         u8         reserved_0[0x18];
5815
5816         u8         syndrome[0x20];
5817
5818         u8         reserved_1[0x8];
5819         u8         cqn[0x18];
5820
5821         u8         reserved_2[0x20];
5822 };
5823
5824 struct mlx5_ifc_create_cq_in_bits {
5825         u8         opcode[0x10];
5826         u8         reserved_0[0x10];
5827
5828         u8         reserved_1[0x10];
5829         u8         op_mod[0x10];
5830
5831         u8         reserved_2[0x40];
5832
5833         struct mlx5_ifc_cqc_bits cq_context;
5834
5835         u8         reserved_3[0x600];
5836
5837         u8         pas[0][0x40];
5838 };
5839
5840 struct mlx5_ifc_config_int_moderation_out_bits {
5841         u8         status[0x8];
5842         u8         reserved_0[0x18];
5843
5844         u8         syndrome[0x20];
5845
5846         u8         reserved_1[0x4];
5847         u8         min_delay[0xc];
5848         u8         int_vector[0x10];
5849
5850         u8         reserved_2[0x20];
5851 };
5852
5853 enum {
5854         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
5855         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
5856 };
5857
5858 struct mlx5_ifc_config_int_moderation_in_bits {
5859         u8         opcode[0x10];
5860         u8         reserved_0[0x10];
5861
5862         u8         reserved_1[0x10];
5863         u8         op_mod[0x10];
5864
5865         u8         reserved_2[0x4];
5866         u8         min_delay[0xc];
5867         u8         int_vector[0x10];
5868
5869         u8         reserved_3[0x20];
5870 };
5871
5872 struct mlx5_ifc_attach_to_mcg_out_bits {
5873         u8         status[0x8];
5874         u8         reserved_0[0x18];
5875
5876         u8         syndrome[0x20];
5877
5878         u8         reserved_1[0x40];
5879 };
5880
5881 struct mlx5_ifc_attach_to_mcg_in_bits {
5882         u8         opcode[0x10];
5883         u8         reserved_0[0x10];
5884
5885         u8         reserved_1[0x10];
5886         u8         op_mod[0x10];
5887
5888         u8         reserved_2[0x8];
5889         u8         qpn[0x18];
5890
5891         u8         reserved_3[0x20];
5892
5893         u8         multicast_gid[16][0x8];
5894 };
5895
5896 struct mlx5_ifc_arm_xrc_srq_out_bits {
5897         u8         status[0x8];
5898         u8         reserved_0[0x18];
5899
5900         u8         syndrome[0x20];
5901
5902         u8         reserved_1[0x40];
5903 };
5904
5905 enum {
5906         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
5907 };
5908
5909 struct mlx5_ifc_arm_xrc_srq_in_bits {
5910         u8         opcode[0x10];
5911         u8         reserved_0[0x10];
5912
5913         u8         reserved_1[0x10];
5914         u8         op_mod[0x10];
5915
5916         u8         reserved_2[0x8];
5917         u8         xrc_srqn[0x18];
5918
5919         u8         reserved_3[0x10];
5920         u8         lwm[0x10];
5921 };
5922
5923 struct mlx5_ifc_arm_rq_out_bits {
5924         u8         status[0x8];
5925         u8         reserved_0[0x18];
5926
5927         u8         syndrome[0x20];
5928
5929         u8         reserved_1[0x40];
5930 };
5931
5932 enum {
5933         MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
5934 };
5935
5936 struct mlx5_ifc_arm_rq_in_bits {
5937         u8         opcode[0x10];
5938         u8         reserved_0[0x10];
5939
5940         u8         reserved_1[0x10];
5941         u8         op_mod[0x10];
5942
5943         u8         reserved_2[0x8];
5944         u8         srq_number[0x18];
5945
5946         u8         reserved_3[0x10];
5947         u8         lwm[0x10];
5948 };
5949
5950 struct mlx5_ifc_arm_dct_out_bits {
5951         u8         status[0x8];
5952         u8         reserved_0[0x18];
5953
5954         u8         syndrome[0x20];
5955
5956         u8         reserved_1[0x40];
5957 };
5958
5959 struct mlx5_ifc_arm_dct_in_bits {
5960         u8         opcode[0x10];
5961         u8         reserved_0[0x10];
5962
5963         u8         reserved_1[0x10];
5964         u8         op_mod[0x10];
5965
5966         u8         reserved_2[0x8];
5967         u8         dct_number[0x18];
5968
5969         u8         reserved_3[0x20];
5970 };
5971
5972 struct mlx5_ifc_alloc_xrcd_out_bits {
5973         u8         status[0x8];
5974         u8         reserved_0[0x18];
5975
5976         u8         syndrome[0x20];
5977
5978         u8         reserved_1[0x8];
5979         u8         xrcd[0x18];
5980
5981         u8         reserved_2[0x20];
5982 };
5983
5984 struct mlx5_ifc_alloc_xrcd_in_bits {
5985         u8         opcode[0x10];
5986         u8         reserved_0[0x10];
5987
5988         u8         reserved_1[0x10];
5989         u8         op_mod[0x10];
5990
5991         u8         reserved_2[0x40];
5992 };
5993
5994 struct mlx5_ifc_alloc_uar_out_bits {
5995         u8         status[0x8];
5996         u8         reserved_0[0x18];
5997
5998         u8         syndrome[0x20];
5999
6000         u8         reserved_1[0x8];
6001         u8         uar[0x18];
6002
6003         u8         reserved_2[0x20];
6004 };
6005
6006 struct mlx5_ifc_alloc_uar_in_bits {
6007         u8         opcode[0x10];
6008         u8         reserved_0[0x10];
6009
6010         u8         reserved_1[0x10];
6011         u8         op_mod[0x10];
6012
6013         u8         reserved_2[0x40];
6014 };
6015
6016 struct mlx5_ifc_alloc_transport_domain_out_bits {
6017         u8         status[0x8];
6018         u8         reserved_0[0x18];
6019
6020         u8         syndrome[0x20];
6021
6022         u8         reserved_1[0x8];
6023         u8         transport_domain[0x18];
6024
6025         u8         reserved_2[0x20];
6026 };
6027
6028 struct mlx5_ifc_alloc_transport_domain_in_bits {
6029         u8         opcode[0x10];
6030         u8         reserved_0[0x10];
6031
6032         u8         reserved_1[0x10];
6033         u8         op_mod[0x10];
6034
6035         u8         reserved_2[0x40];
6036 };
6037
6038 struct mlx5_ifc_alloc_q_counter_out_bits {
6039         u8         status[0x8];
6040         u8         reserved_0[0x18];
6041
6042         u8         syndrome[0x20];
6043
6044         u8         reserved_1[0x18];
6045         u8         counter_set_id[0x8];
6046
6047         u8         reserved_2[0x20];
6048 };
6049
6050 struct mlx5_ifc_alloc_q_counter_in_bits {
6051         u8         opcode[0x10];
6052         u8         reserved_0[0x10];
6053
6054         u8         reserved_1[0x10];
6055         u8         op_mod[0x10];
6056
6057         u8         reserved_2[0x40];
6058 };
6059
6060 struct mlx5_ifc_alloc_pd_out_bits {
6061         u8         status[0x8];
6062         u8         reserved_0[0x18];
6063
6064         u8         syndrome[0x20];
6065
6066         u8         reserved_1[0x8];
6067         u8         pd[0x18];
6068
6069         u8         reserved_2[0x20];
6070 };
6071
6072 struct mlx5_ifc_alloc_pd_in_bits {
6073         u8         opcode[0x10];
6074         u8         reserved_0[0x10];
6075
6076         u8         reserved_1[0x10];
6077         u8         op_mod[0x10];
6078
6079         u8         reserved_2[0x40];
6080 };
6081
6082 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6083         u8         status[0x8];
6084         u8         reserved_0[0x18];
6085
6086         u8         syndrome[0x20];
6087
6088         u8         reserved_1[0x40];
6089 };
6090
6091 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6092         u8         opcode[0x10];
6093         u8         reserved_0[0x10];
6094
6095         u8         reserved_1[0x10];
6096         u8         op_mod[0x10];
6097
6098         u8         reserved_2[0x20];
6099
6100         u8         reserved_3[0x10];
6101         u8         vxlan_udp_port[0x10];
6102 };
6103
6104 struct mlx5_ifc_access_register_out_bits {
6105         u8         status[0x8];
6106         u8         reserved_0[0x18];
6107
6108         u8         syndrome[0x20];
6109
6110         u8         reserved_1[0x40];
6111
6112         u8         register_data[0][0x20];
6113 };
6114
6115 enum {
6116         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
6117         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
6118 };
6119
6120 struct mlx5_ifc_access_register_in_bits {
6121         u8         opcode[0x10];
6122         u8         reserved_0[0x10];
6123
6124         u8         reserved_1[0x10];
6125         u8         op_mod[0x10];
6126
6127         u8         reserved_2[0x10];
6128         u8         register_id[0x10];
6129
6130         u8         argument[0x20];
6131
6132         u8         register_data[0][0x20];
6133 };
6134
6135 struct mlx5_ifc_sltp_reg_bits {
6136         u8         status[0x4];
6137         u8         version[0x4];
6138         u8         local_port[0x8];
6139         u8         pnat[0x2];
6140         u8         reserved_0[0x2];
6141         u8         lane[0x4];
6142         u8         reserved_1[0x8];
6143
6144         u8         reserved_2[0x20];
6145
6146         u8         reserved_3[0x7];
6147         u8         polarity[0x1];
6148         u8         ob_tap0[0x8];
6149         u8         ob_tap1[0x8];
6150         u8         ob_tap2[0x8];
6151
6152         u8         reserved_4[0xc];
6153         u8         ob_preemp_mode[0x4];
6154         u8         ob_reg[0x8];
6155         u8         ob_bias[0x8];
6156
6157         u8         reserved_5[0x20];
6158 };
6159
6160 struct mlx5_ifc_slrg_reg_bits {
6161         u8         status[0x4];
6162         u8         version[0x4];
6163         u8         local_port[0x8];
6164         u8         pnat[0x2];
6165         u8         reserved_0[0x2];
6166         u8         lane[0x4];
6167         u8         reserved_1[0x8];
6168
6169         u8         time_to_link_up[0x10];
6170         u8         reserved_2[0xc];
6171         u8         grade_lane_speed[0x4];
6172
6173         u8         grade_version[0x8];
6174         u8         grade[0x18];
6175
6176         u8         reserved_3[0x4];
6177         u8         height_grade_type[0x4];
6178         u8         height_grade[0x18];
6179
6180         u8         height_dz[0x10];
6181         u8         height_dv[0x10];
6182
6183         u8         reserved_4[0x10];
6184         u8         height_sigma[0x10];
6185
6186         u8         reserved_5[0x20];
6187
6188         u8         reserved_6[0x4];
6189         u8         phase_grade_type[0x4];
6190         u8         phase_grade[0x18];
6191
6192         u8         reserved_7[0x8];
6193         u8         phase_eo_pos[0x8];
6194         u8         reserved_8[0x8];
6195         u8         phase_eo_neg[0x8];
6196
6197         u8         ffe_set_tested[0x10];
6198         u8         test_errors_per_lane[0x10];
6199 };
6200
6201 struct mlx5_ifc_pvlc_reg_bits {
6202         u8         reserved_0[0x8];
6203         u8         local_port[0x8];
6204         u8         reserved_1[0x10];
6205
6206         u8         reserved_2[0x1c];
6207         u8         vl_hw_cap[0x4];
6208
6209         u8         reserved_3[0x1c];
6210         u8         vl_admin[0x4];
6211
6212         u8         reserved_4[0x1c];
6213         u8         vl_operational[0x4];
6214 };
6215
6216 struct mlx5_ifc_pude_reg_bits {
6217         u8         swid[0x8];
6218         u8         local_port[0x8];
6219         u8         reserved_0[0x4];
6220         u8         admin_status[0x4];
6221         u8         reserved_1[0x4];
6222         u8         oper_status[0x4];
6223
6224         u8         reserved_2[0x60];
6225 };
6226
6227 struct mlx5_ifc_ptys_reg_bits {
6228         u8         reserved_0[0x8];
6229         u8         local_port[0x8];
6230         u8         reserved_1[0xd];
6231         u8         proto_mask[0x3];
6232
6233         u8         reserved_2[0x40];
6234
6235         u8         eth_proto_capability[0x20];
6236
6237         u8         ib_link_width_capability[0x10];
6238         u8         ib_proto_capability[0x10];
6239
6240         u8         reserved_3[0x20];
6241
6242         u8         eth_proto_admin[0x20];
6243
6244         u8         ib_link_width_admin[0x10];
6245         u8         ib_proto_admin[0x10];
6246
6247         u8         reserved_4[0x20];
6248
6249         u8         eth_proto_oper[0x20];
6250
6251         u8         ib_link_width_oper[0x10];
6252         u8         ib_proto_oper[0x10];
6253
6254         u8         reserved_5[0x20];
6255
6256         u8         eth_proto_lp_advertise[0x20];
6257
6258         u8         reserved_6[0x60];
6259 };
6260
6261 struct mlx5_ifc_ptas_reg_bits {
6262         u8         reserved_0[0x20];
6263
6264         u8         algorithm_options[0x10];
6265         u8         reserved_1[0x4];
6266         u8         repetitions_mode[0x4];
6267         u8         num_of_repetitions[0x8];
6268
6269         u8         grade_version[0x8];
6270         u8         height_grade_type[0x4];
6271         u8         phase_grade_type[0x4];
6272         u8         height_grade_weight[0x8];
6273         u8         phase_grade_weight[0x8];
6274
6275         u8         gisim_measure_bits[0x10];
6276         u8         adaptive_tap_measure_bits[0x10];
6277
6278         u8         ber_bath_high_error_threshold[0x10];
6279         u8         ber_bath_mid_error_threshold[0x10];
6280
6281         u8         ber_bath_low_error_threshold[0x10];
6282         u8         one_ratio_high_threshold[0x10];
6283
6284         u8         one_ratio_high_mid_threshold[0x10];
6285         u8         one_ratio_low_mid_threshold[0x10];
6286
6287         u8         one_ratio_low_threshold[0x10];
6288         u8         ndeo_error_threshold[0x10];
6289
6290         u8         mixer_offset_step_size[0x10];
6291         u8         reserved_2[0x8];
6292         u8         mix90_phase_for_voltage_bath[0x8];
6293
6294         u8         mixer_offset_start[0x10];
6295         u8         mixer_offset_end[0x10];
6296
6297         u8         reserved_3[0x15];
6298         u8         ber_test_time[0xb];
6299 };
6300
6301 struct mlx5_ifc_pspa_reg_bits {
6302         u8         swid[0x8];
6303         u8         local_port[0x8];
6304         u8         sub_port[0x8];
6305         u8         reserved_0[0x8];
6306
6307         u8         reserved_1[0x20];
6308 };
6309
6310 struct mlx5_ifc_pqdr_reg_bits {
6311         u8         reserved_0[0x8];
6312         u8         local_port[0x8];
6313         u8         reserved_1[0x5];
6314         u8         prio[0x3];
6315         u8         reserved_2[0x6];
6316         u8         mode[0x2];
6317
6318         u8         reserved_3[0x20];
6319
6320         u8         reserved_4[0x10];
6321         u8         min_threshold[0x10];
6322
6323         u8         reserved_5[0x10];
6324         u8         max_threshold[0x10];
6325
6326         u8         reserved_6[0x10];
6327         u8         mark_probability_denominator[0x10];
6328
6329         u8         reserved_7[0x60];
6330 };
6331
6332 struct mlx5_ifc_ppsc_reg_bits {
6333         u8         reserved_0[0x8];
6334         u8         local_port[0x8];
6335         u8         reserved_1[0x10];
6336
6337         u8         reserved_2[0x60];
6338
6339         u8         reserved_3[0x1c];
6340         u8         wrps_admin[0x4];
6341
6342         u8         reserved_4[0x1c];
6343         u8         wrps_status[0x4];
6344
6345         u8         reserved_5[0x8];
6346         u8         up_threshold[0x8];
6347         u8         reserved_6[0x8];
6348         u8         down_threshold[0x8];
6349
6350         u8         reserved_7[0x20];
6351
6352         u8         reserved_8[0x1c];
6353         u8         srps_admin[0x4];
6354
6355         u8         reserved_9[0x1c];
6356         u8         srps_status[0x4];
6357
6358         u8         reserved_10[0x40];
6359 };
6360
6361 struct mlx5_ifc_pplr_reg_bits {
6362         u8         reserved_0[0x8];
6363         u8         local_port[0x8];
6364         u8         reserved_1[0x10];
6365
6366         u8         reserved_2[0x8];
6367         u8         lb_cap[0x8];
6368         u8         reserved_3[0x8];
6369         u8         lb_en[0x8];
6370 };
6371
6372 struct mlx5_ifc_pplm_reg_bits {
6373         u8         reserved_0[0x8];
6374         u8         local_port[0x8];
6375         u8         reserved_1[0x10];
6376
6377         u8         reserved_2[0x20];
6378
6379         u8         port_profile_mode[0x8];
6380         u8         static_port_profile[0x8];
6381         u8         active_port_profile[0x8];
6382         u8         reserved_3[0x8];
6383
6384         u8         retransmission_active[0x8];
6385         u8         fec_mode_active[0x18];
6386
6387         u8         reserved_4[0x20];
6388 };
6389
6390 struct mlx5_ifc_ppcnt_reg_bits {
6391         u8         swid[0x8];
6392         u8         local_port[0x8];
6393         u8         pnat[0x2];
6394         u8         reserved_0[0x8];
6395         u8         grp[0x6];
6396
6397         u8         clr[0x1];
6398         u8         reserved_1[0x1c];
6399         u8         prio_tc[0x3];
6400
6401         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6402 };
6403
6404 struct mlx5_ifc_ppad_reg_bits {
6405         u8         reserved_0[0x3];
6406         u8         single_mac[0x1];
6407         u8         reserved_1[0x4];
6408         u8         local_port[0x8];
6409         u8         mac_47_32[0x10];
6410
6411         u8         mac_31_0[0x20];
6412
6413         u8         reserved_2[0x40];
6414 };
6415
6416 struct mlx5_ifc_pmtu_reg_bits {
6417         u8         reserved_0[0x8];
6418         u8         local_port[0x8];
6419         u8         reserved_1[0x10];
6420
6421         u8         max_mtu[0x10];
6422         u8         reserved_2[0x10];
6423
6424         u8         admin_mtu[0x10];
6425         u8         reserved_3[0x10];
6426
6427         u8         oper_mtu[0x10];
6428         u8         reserved_4[0x10];
6429 };
6430
6431 struct mlx5_ifc_pmpr_reg_bits {
6432         u8         reserved_0[0x8];
6433         u8         module[0x8];
6434         u8         reserved_1[0x10];
6435
6436         u8         reserved_2[0x18];
6437         u8         attenuation_5g[0x8];
6438
6439         u8         reserved_3[0x18];
6440         u8         attenuation_7g[0x8];
6441
6442         u8         reserved_4[0x18];
6443         u8         attenuation_12g[0x8];
6444 };
6445
6446 struct mlx5_ifc_pmpe_reg_bits {
6447         u8         reserved_0[0x8];
6448         u8         module[0x8];
6449         u8         reserved_1[0xc];
6450         u8         module_status[0x4];
6451
6452         u8         reserved_2[0x60];
6453 };
6454
6455 struct mlx5_ifc_pmpc_reg_bits {
6456         u8         module_state_updated[32][0x8];
6457 };
6458
6459 struct mlx5_ifc_pmlpn_reg_bits {
6460         u8         reserved_0[0x4];
6461         u8         mlpn_status[0x4];
6462         u8         local_port[0x8];
6463         u8         reserved_1[0x10];
6464
6465         u8         e[0x1];
6466         u8         reserved_2[0x1f];
6467 };
6468
6469 struct mlx5_ifc_pmlp_reg_bits {
6470         u8         rxtx[0x1];
6471         u8         reserved_0[0x7];
6472         u8         local_port[0x8];
6473         u8         reserved_1[0x8];
6474         u8         width[0x8];
6475
6476         u8         lane0_module_mapping[0x20];
6477
6478         u8         lane1_module_mapping[0x20];
6479
6480         u8         lane2_module_mapping[0x20];
6481
6482         u8         lane3_module_mapping[0x20];
6483
6484         u8         reserved_2[0x160];
6485 };
6486
6487 struct mlx5_ifc_pmaos_reg_bits {
6488         u8         reserved_0[0x8];
6489         u8         module[0x8];
6490         u8         reserved_1[0x4];
6491         u8         admin_status[0x4];
6492         u8         reserved_2[0x4];
6493         u8         oper_status[0x4];
6494
6495         u8         ase[0x1];
6496         u8         ee[0x1];
6497         u8         reserved_3[0x1c];
6498         u8         e[0x2];
6499
6500         u8         reserved_4[0x40];
6501 };
6502
6503 struct mlx5_ifc_plpc_reg_bits {
6504         u8         reserved_0[0x4];
6505         u8         profile_id[0xc];
6506         u8         reserved_1[0x4];
6507         u8         proto_mask[0x4];
6508         u8         reserved_2[0x8];
6509
6510         u8         reserved_3[0x10];
6511         u8         lane_speed[0x10];
6512
6513         u8         reserved_4[0x17];
6514         u8         lpbf[0x1];
6515         u8         fec_mode_policy[0x8];
6516
6517         u8         retransmission_capability[0x8];
6518         u8         fec_mode_capability[0x18];
6519
6520         u8         retransmission_support_admin[0x8];
6521         u8         fec_mode_support_admin[0x18];
6522
6523         u8         retransmission_request_admin[0x8];
6524         u8         fec_mode_request_admin[0x18];
6525
6526         u8         reserved_5[0x80];
6527 };
6528
6529 struct mlx5_ifc_plib_reg_bits {
6530         u8         reserved_0[0x8];
6531         u8         local_port[0x8];
6532         u8         reserved_1[0x8];
6533         u8         ib_port[0x8];
6534
6535         u8         reserved_2[0x60];
6536 };
6537
6538 struct mlx5_ifc_plbf_reg_bits {
6539         u8         reserved_0[0x8];
6540         u8         local_port[0x8];
6541         u8         reserved_1[0xd];
6542         u8         lbf_mode[0x3];
6543
6544         u8         reserved_2[0x20];
6545 };
6546
6547 struct mlx5_ifc_pipg_reg_bits {
6548         u8         reserved_0[0x8];
6549         u8         local_port[0x8];
6550         u8         reserved_1[0x10];
6551
6552         u8         dic[0x1];
6553         u8         reserved_2[0x19];
6554         u8         ipg[0x4];
6555         u8         reserved_3[0x2];
6556 };
6557
6558 struct mlx5_ifc_pifr_reg_bits {
6559         u8         reserved_0[0x8];
6560         u8         local_port[0x8];
6561         u8         reserved_1[0x10];
6562
6563         u8         reserved_2[0xe0];
6564
6565         u8         port_filter[8][0x20];
6566
6567         u8         port_filter_update_en[8][0x20];
6568 };
6569
6570 struct mlx5_ifc_pfcc_reg_bits {
6571         u8         reserved_0[0x8];
6572         u8         local_port[0x8];
6573         u8         reserved_1[0x10];
6574
6575         u8         ppan[0x4];
6576         u8         reserved_2[0x4];
6577         u8         prio_mask_tx[0x8];
6578         u8         reserved_3[0x8];
6579         u8         prio_mask_rx[0x8];
6580
6581         u8         pptx[0x1];
6582         u8         aptx[0x1];
6583         u8         reserved_4[0x6];
6584         u8         pfctx[0x8];
6585         u8         reserved_5[0x10];
6586
6587         u8         pprx[0x1];
6588         u8         aprx[0x1];
6589         u8         reserved_6[0x6];
6590         u8         pfcrx[0x8];
6591         u8         reserved_7[0x10];
6592
6593         u8         reserved_8[0x80];
6594 };
6595
6596 struct mlx5_ifc_pelc_reg_bits {
6597         u8         op[0x4];
6598         u8         reserved_0[0x4];
6599         u8         local_port[0x8];
6600         u8         reserved_1[0x10];
6601
6602         u8         op_admin[0x8];
6603         u8         op_capability[0x8];
6604         u8         op_request[0x8];
6605         u8         op_active[0x8];
6606
6607         u8         admin[0x40];
6608
6609         u8         capability[0x40];
6610
6611         u8         request[0x40];
6612
6613         u8         active[0x40];
6614
6615         u8         reserved_2[0x80];
6616 };
6617
6618 struct mlx5_ifc_peir_reg_bits {
6619         u8         reserved_0[0x8];
6620         u8         local_port[0x8];
6621         u8         reserved_1[0x10];
6622
6623         u8         reserved_2[0xc];
6624         u8         error_count[0x4];
6625         u8         reserved_3[0x10];
6626
6627         u8         reserved_4[0xc];
6628         u8         lane[0x4];
6629         u8         reserved_5[0x8];
6630         u8         error_type[0x8];
6631 };
6632
6633 struct mlx5_ifc_pcap_reg_bits {
6634         u8         reserved_0[0x8];
6635         u8         local_port[0x8];
6636         u8         reserved_1[0x10];
6637
6638         u8         port_capability_mask[4][0x20];
6639 };
6640
6641 struct mlx5_ifc_paos_reg_bits {
6642         u8         swid[0x8];
6643         u8         local_port[0x8];
6644         u8         reserved_0[0x4];
6645         u8         admin_status[0x4];
6646         u8         reserved_1[0x4];
6647         u8         oper_status[0x4];
6648
6649         u8         ase[0x1];
6650         u8         ee[0x1];
6651         u8         reserved_2[0x1c];
6652         u8         e[0x2];
6653
6654         u8         reserved_3[0x40];
6655 };
6656
6657 struct mlx5_ifc_pamp_reg_bits {
6658         u8         reserved_0[0x8];
6659         u8         opamp_group[0x8];
6660         u8         reserved_1[0xc];
6661         u8         opamp_group_type[0x4];
6662
6663         u8         start_index[0x10];
6664         u8         reserved_2[0x4];
6665         u8         num_of_indices[0xc];
6666
6667         u8         index_data[18][0x10];
6668 };
6669
6670 struct mlx5_ifc_lane_2_module_mapping_bits {
6671         u8         reserved_0[0x6];
6672         u8         rx_lane[0x2];
6673         u8         reserved_1[0x6];
6674         u8         tx_lane[0x2];
6675         u8         reserved_2[0x8];
6676         u8         module[0x8];
6677 };
6678
6679 struct mlx5_ifc_bufferx_reg_bits {
6680         u8         reserved_0[0x6];
6681         u8         lossy[0x1];
6682         u8         epsb[0x1];
6683         u8         reserved_1[0xc];
6684         u8         size[0xc];
6685
6686         u8         xoff_threshold[0x10];
6687         u8         xon_threshold[0x10];
6688 };
6689
6690 struct mlx5_ifc_set_node_in_bits {
6691         u8         node_description[64][0x8];
6692 };
6693
6694 struct mlx5_ifc_register_power_settings_bits {
6695         u8         reserved_0[0x18];
6696         u8         power_settings_level[0x8];
6697
6698         u8         reserved_1[0x60];
6699 };
6700
6701 struct mlx5_ifc_register_host_endianness_bits {
6702         u8         he[0x1];
6703         u8         reserved_0[0x1f];
6704
6705         u8         reserved_1[0x60];
6706 };
6707
6708 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6709         u8         reserved_0[0x20];
6710
6711         u8         mkey[0x20];
6712
6713         u8         addressh_63_32[0x20];
6714
6715         u8         addressl_31_0[0x20];
6716 };
6717
6718 struct mlx5_ifc_ud_adrs_vector_bits {
6719         u8         dc_key[0x40];
6720
6721         u8         ext[0x1];
6722         u8         reserved_0[0x7];
6723         u8         destination_qp_dct[0x18];
6724
6725         u8         static_rate[0x4];
6726         u8         sl_eth_prio[0x4];
6727         u8         fl[0x1];
6728         u8         mlid[0x7];
6729         u8         rlid_udp_sport[0x10];
6730
6731         u8         reserved_1[0x20];
6732
6733         u8         rmac_47_16[0x20];
6734
6735         u8         rmac_15_0[0x10];
6736         u8         tclass[0x8];
6737         u8         hop_limit[0x8];
6738
6739         u8         reserved_2[0x1];
6740         u8         grh[0x1];
6741         u8         reserved_3[0x2];
6742         u8         src_addr_index[0x8];
6743         u8         flow_label[0x14];
6744
6745         u8         rgid_rip[16][0x8];
6746 };
6747
6748 struct mlx5_ifc_pages_req_event_bits {
6749         u8         reserved_0[0x10];
6750         u8         function_id[0x10];
6751
6752         u8         num_pages[0x20];
6753
6754         u8         reserved_1[0xa0];
6755 };
6756
6757 struct mlx5_ifc_eqe_bits {
6758         u8         reserved_0[0x8];
6759         u8         event_type[0x8];
6760         u8         reserved_1[0x8];
6761         u8         event_sub_type[0x8];
6762
6763         u8         reserved_2[0xe0];
6764
6765         union mlx5_ifc_event_auto_bits event_data;
6766
6767         u8         reserved_3[0x10];
6768         u8         signature[0x8];
6769         u8         reserved_4[0x7];
6770         u8         owner[0x1];
6771 };
6772
6773 enum {
6774         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
6775 };
6776
6777 struct mlx5_ifc_cmd_queue_entry_bits {
6778         u8         type[0x8];
6779         u8         reserved_0[0x18];
6780
6781         u8         input_length[0x20];
6782
6783         u8         input_mailbox_pointer_63_32[0x20];
6784
6785         u8         input_mailbox_pointer_31_9[0x17];
6786         u8         reserved_1[0x9];
6787
6788         u8         command_input_inline_data[16][0x8];
6789
6790         u8         command_output_inline_data[16][0x8];
6791
6792         u8         output_mailbox_pointer_63_32[0x20];
6793
6794         u8         output_mailbox_pointer_31_9[0x17];
6795         u8         reserved_2[0x9];
6796
6797         u8         output_length[0x20];
6798
6799         u8         token[0x8];
6800         u8         signature[0x8];
6801         u8         reserved_3[0x8];
6802         u8         status[0x7];
6803         u8         ownership[0x1];
6804 };
6805
6806 struct mlx5_ifc_cmd_out_bits {
6807         u8         status[0x8];
6808         u8         reserved_0[0x18];
6809
6810         u8         syndrome[0x20];
6811
6812         u8         command_output[0x20];
6813 };
6814
6815 struct mlx5_ifc_cmd_in_bits {
6816         u8         opcode[0x10];
6817         u8         reserved_0[0x10];
6818
6819         u8         reserved_1[0x10];
6820         u8         op_mod[0x10];
6821
6822         u8         command[0][0x20];
6823 };
6824
6825 struct mlx5_ifc_cmd_if_box_bits {
6826         u8         mailbox_data[512][0x8];
6827
6828         u8         reserved_0[0x180];
6829
6830         u8         next_pointer_63_32[0x20];
6831
6832         u8         next_pointer_31_10[0x16];
6833         u8         reserved_1[0xa];
6834
6835         u8         block_number[0x20];
6836
6837         u8         reserved_2[0x8];
6838         u8         token[0x8];
6839         u8         ctrl_signature[0x8];
6840         u8         signature[0x8];
6841 };
6842
6843 struct mlx5_ifc_mtt_bits {
6844         u8         ptag_63_32[0x20];
6845
6846         u8         ptag_31_8[0x18];
6847         u8         reserved_0[0x6];
6848         u8         wr_en[0x1];
6849         u8         rd_en[0x1];
6850 };
6851
6852 enum {
6853         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
6854         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
6855         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
6856 };
6857
6858 enum {
6859         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
6860         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
6861         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
6862 };
6863
6864 enum {
6865         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
6866         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
6867         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
6868         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
6869         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
6870         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
6871         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
6872         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
6873         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
6874         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
6875         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
6876 };
6877
6878 struct mlx5_ifc_initial_seg_bits {
6879         u8         fw_rev_minor[0x10];
6880         u8         fw_rev_major[0x10];
6881
6882         u8         cmd_interface_rev[0x10];
6883         u8         fw_rev_subminor[0x10];
6884
6885         u8         reserved_0[0x40];
6886
6887         u8         cmdq_phy_addr_63_32[0x20];
6888
6889         u8         cmdq_phy_addr_31_12[0x14];
6890         u8         reserved_1[0x2];
6891         u8         nic_interface[0x2];
6892         u8         log_cmdq_size[0x4];
6893         u8         log_cmdq_stride[0x4];
6894
6895         u8         command_doorbell_vector[0x20];
6896
6897         u8         reserved_2[0xf00];
6898
6899         u8         initializing[0x1];
6900         u8         reserved_3[0x4];
6901         u8         nic_interface_supported[0x3];
6902         u8         reserved_4[0x18];
6903
6904         struct mlx5_ifc_health_buffer_bits health_buffer;
6905
6906         u8         no_dram_nic_offset[0x20];
6907
6908         u8         reserved_5[0x6e40];
6909
6910         u8         reserved_6[0x1f];
6911         u8         clear_int[0x1];
6912
6913         u8         health_syndrome[0x8];
6914         u8         health_counter[0x18];
6915
6916         u8         reserved_7[0x17fc0];
6917 };
6918
6919 union mlx5_ifc_ports_control_registers_document_bits {
6920         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6921         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6922         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6923         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6924         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6925         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6926         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6927         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6928         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6929         struct mlx5_ifc_pamp_reg_bits pamp_reg;
6930         struct mlx5_ifc_paos_reg_bits paos_reg;
6931         struct mlx5_ifc_pcap_reg_bits pcap_reg;
6932         struct mlx5_ifc_peir_reg_bits peir_reg;
6933         struct mlx5_ifc_pelc_reg_bits pelc_reg;
6934         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6935         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6936         struct mlx5_ifc_pifr_reg_bits pifr_reg;
6937         struct mlx5_ifc_pipg_reg_bits pipg_reg;
6938         struct mlx5_ifc_plbf_reg_bits plbf_reg;
6939         struct mlx5_ifc_plib_reg_bits plib_reg;
6940         struct mlx5_ifc_plpc_reg_bits plpc_reg;
6941         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6942         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6943         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6944         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6945         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6946         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6947         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6948         struct mlx5_ifc_ppad_reg_bits ppad_reg;
6949         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6950         struct mlx5_ifc_pplm_reg_bits pplm_reg;
6951         struct mlx5_ifc_pplr_reg_bits pplr_reg;
6952         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6953         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6954         struct mlx5_ifc_pspa_reg_bits pspa_reg;
6955         struct mlx5_ifc_ptas_reg_bits ptas_reg;
6956         struct mlx5_ifc_ptys_reg_bits ptys_reg;
6957         struct mlx5_ifc_pude_reg_bits pude_reg;
6958         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6959         struct mlx5_ifc_slrg_reg_bits slrg_reg;
6960         struct mlx5_ifc_sltp_reg_bits sltp_reg;
6961         u8         reserved_0[0x60e0];
6962 };
6963
6964 union mlx5_ifc_debug_enhancements_document_bits {
6965         struct mlx5_ifc_health_buffer_bits health_buffer;
6966         u8         reserved_0[0x200];
6967 };
6968
6969 union mlx5_ifc_uplink_pci_interface_document_bits {
6970         struct mlx5_ifc_initial_seg_bits initial_seg;
6971         u8         reserved_0[0x20060];
6972 };
6973
6974 struct mlx5_ifc_set_flow_table_root_out_bits {
6975         u8         status[0x8];
6976         u8         reserved_0[0x18];
6977
6978         u8         syndrome[0x20];
6979
6980         u8         reserved_1[0x40];
6981 };
6982
6983 struct mlx5_ifc_set_flow_table_root_in_bits {
6984         u8         opcode[0x10];
6985         u8         reserved_0[0x10];
6986
6987         u8         reserved_1[0x10];
6988         u8         op_mod[0x10];
6989
6990         u8         reserved_2[0x40];
6991
6992         u8         table_type[0x8];
6993         u8         reserved_3[0x18];
6994
6995         u8         reserved_4[0x8];
6996         u8         table_id[0x18];
6997
6998         u8         reserved_5[0x140];
6999 };
7000
7001 enum {
7002         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7003 };
7004
7005 struct mlx5_ifc_modify_flow_table_out_bits {
7006         u8         status[0x8];
7007         u8         reserved_0[0x18];
7008
7009         u8         syndrome[0x20];
7010
7011         u8         reserved_1[0x40];
7012 };
7013
7014 struct mlx5_ifc_modify_flow_table_in_bits {
7015         u8         opcode[0x10];
7016         u8         reserved_0[0x10];
7017
7018         u8         reserved_1[0x10];
7019         u8         op_mod[0x10];
7020
7021         u8         reserved_2[0x20];
7022
7023         u8         reserved_3[0x10];
7024         u8         modify_field_select[0x10];
7025
7026         u8         table_type[0x8];
7027         u8         reserved_4[0x18];
7028
7029         u8         reserved_5[0x8];
7030         u8         table_id[0x18];
7031
7032         u8         reserved_6[0x4];
7033         u8         table_miss_mode[0x4];
7034         u8         reserved_7[0x18];
7035
7036         u8         reserved_8[0x8];
7037         u8         table_miss_id[0x18];
7038
7039         u8         reserved_9[0x100];
7040 };
7041
7042 #endif /* MLX5_IFC_H */