2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #ifndef LINUX_MMC_DW_MMC_H
15 #define LINUX_MMC_DW_MMC_H
17 #include <linux/scatterlist.h>
18 #include <linux/mmc/core.h>
20 #define MAX_MCI_SLOTS 2
30 STATE_WAITING_CMD11_DONE,
34 EVENT_CMD_COMPLETE = 0,
44 * struct dw_mci - MMC controller state shared between all slots
45 * @lock: Spinlock protecting the queue and associated data.
46 * @regs: Pointer to MMIO registers.
47 * @sg: Scatterlist entry currently being processed by PIO code, if any.
48 * @sg_miter: PIO mapping scatterlist iterator.
49 * @cur_slot: The slot which is currently using the controller.
50 * @mrq: The request currently being processed on @cur_slot,
51 * or NULL if the controller is idle.
52 * @cmd: The command currently being sent to the card, or NULL.
53 * @data: The data currently being transferred, or NULL if no data
54 * transfer is in progress.
55 * @use_dma: Whether DMA channel is initialized or not.
56 * @using_dma: Whether DMA is in use for the current transfer.
57 * @sg_dma: Bus address of DMA buffer.
58 * @sg_cpu: Virtual address of DMA buffer.
59 * @dma_ops: Pointer to platform-specific DMA callbacks.
60 * @cmd_status: Snapshot of SR taken upon completion of the current
61 * command. Only valid when EVENT_CMD_COMPLETE is pending.
62 * @data_status: Snapshot of SR taken upon completion of the current
63 * data transfer. Only valid when EVENT_DATA_COMPLETE or
64 * EVENT_DATA_ERROR is pending.
65 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
67 * @dir_status: Direction of current transfer.
68 * @tasklet: Tasklet running the request state machine.
69 * @card_tasklet: Tasklet handling card detect.
70 * @pending_events: Bitmask of events flagged by the interrupt handler
71 * to be processed by the tasklet.
72 * @completed_events: Bitmask of events which the state machine has
74 * @state: Tasklet state.
75 * @queue: List of slots waiting for access to the controller.
76 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
77 * rate and timeout calculations.
78 * @current_speed: Configured rate of the controller.
79 * @num_slots: Number of slots available.
80 * @verid: Denote Version ID.
81 * @data_offset: Set the offset of DATA register according to VERID.
82 * @dev: Device associated with the MMC controller.
83 * @pdata: Platform data associated with the MMC controller.
84 * @drv_data: Driver specific data for identified variant of the controller
85 * @priv: Implementation defined private data.
86 * @biu_clk: Pointer to bus interface unit clock instance.
87 * @ciu_clk: Pointer to card interface unit clock instance.
88 * @slot: Slots sharing this MMC controller.
89 * @fifo_depth: depth of FIFO.
90 * @data_shift: log2 of FIFO item size.
91 * @part_buf_start: Start index in part_buf.
92 * @part_buf_count: Bytes of partial data in part_buf.
93 * @part_buf: Simple buffer for partial fifo reads/writes.
94 * @push_data: Pointer to FIFO push function.
95 * @pull_data: Pointer to FIFO pull function.
96 * @quirks: Set of quirks that apply to specific versions of the IP.
97 * @irq_flags: The flags to be passed to request_irq.
98 * @irq: The irq value to be passed to request_irq.
103 * @lock is a softirq-safe spinlock protecting @queue as well as
104 * @cur_slot, @mrq and @state. These must always be updated
105 * at the same time while holding @lock.
107 * The @mrq field of struct dw_mci_slot is also protected by @lock,
108 * and must always be written at the same time as the slot is added to
111 * @pending_events and @completed_events are accessed using atomic bit
112 * operations, so they don't need any locking.
114 * None of the fields touched by the interrupt handler need any
115 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
116 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
117 * interrupts must be disabled and @data_status updated with a
118 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
119 * CMDRDY interrupt must be disabled and @cmd_status updated with a
120 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
121 * bytes_xfered field of @data must be written. This is ensured by
128 struct scatterlist *sg;
129 struct sg_mapping_iter sg_miter;
131 struct dw_mci_slot *cur_slot;
132 struct mmc_request *mrq;
133 struct mmc_command *cmd;
134 struct mmc_data *data;
135 struct mmc_command stop_abort;
136 unsigned int prev_blksz;
137 unsigned char timing;
138 struct workqueue_struct *card_workqueue;
140 /* DMA interface members*/
146 const struct dw_mci_dma_ops *dma_ops;
147 #ifdef CONFIG_MMC_DW_IDMAC
148 unsigned int ring_size;
150 struct dw_mci_dma_data *dma_data;
156 struct tasklet_struct tasklet;
157 struct work_struct card_work;
158 unsigned long pending_events;
159 unsigned long completed_events;
160 enum dw_mci_state state;
161 struct list_head queue;
170 struct dw_mci_board *pdata;
171 const struct dw_mci_drv_data *drv_data;
175 struct dw_mci_slot *slot[MAX_MCI_SLOTS];
177 /* FIFO push and pull */
187 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
188 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
190 /* Workaround flags */
194 unsigned long irq_flags; /* IRQ flags */
198 /* DMA ops for Internal/External DMAC interface */
199 struct dw_mci_dma_ops {
201 int (*init)(struct dw_mci *host);
202 void (*start)(struct dw_mci *host, unsigned int sg_len);
203 void (*complete)(struct dw_mci *host);
204 void (*stop)(struct dw_mci *host);
205 void (*cleanup)(struct dw_mci *host);
206 void (*exit)(struct dw_mci *host);
209 /* IP Quirks/flags. */
210 /* DTO fix for command transmission with IDMAC configured */
211 #define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
212 /* delay needed between retries on some 2.11a implementations */
213 #define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
214 /* High Speed Capable - Supports HS cards (up to 50MHz) */
215 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
216 /* Unreliable card detection */
217 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
218 /* No write protect */
219 #define DW_MCI_QUIRK_NO_WRITE_PROTECT BIT(4)
221 /* Slot level quirks */
222 /* This slot has no write protect */
223 #define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT BIT(0)
227 struct block_settings {
228 unsigned short max_segs; /* see blk_queue_max_segments */
229 unsigned int max_blk_size; /* maximum size of one mmc block */
230 unsigned int max_blk_count; /* maximum number of blocks in one req*/
231 unsigned int max_req_size; /* maximum number of bytes in one req*/
232 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
235 /* Board platform data */
236 struct dw_mci_board {
239 u32 quirks; /* Workaround / Quirk flags */
240 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
242 u32 caps; /* Capabilities */
243 u32 caps2; /* More capabilities */
244 u32 pm_caps; /* PM capabilities */
246 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
247 * but note that this may not be reliable after a bootloader has used
250 unsigned int fifo_depth;
252 /* delay in mS before detecting cards after interrupt */
255 struct dw_mci_dma_ops *dma_ops;
256 struct dma_pdata *data;
257 struct block_settings *blk_settings;
260 #endif /* LINUX_MMC_DW_MMC_H */