1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #ifndef _QED_ROCE_IF_H
33 #define _QED_ROCE_IF_H
34 #include <linux/types.h>
35 #include <linux/delay.h>
36 #include <linux/list.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/slab.h>
40 #include <linux/qed/qed_if.h>
41 #include <linux/qed/qed_ll2_if.h>
43 #define QED_RDMA_MAX_CNQ_SIZE (0xFFFF)
47 enum qed_roce_qp_state {
48 QED_ROCE_QP_STATE_RESET,
49 QED_ROCE_QP_STATE_INIT,
50 QED_ROCE_QP_STATE_RTR,
51 QED_ROCE_QP_STATE_RTS,
52 QED_ROCE_QP_STATE_SQD,
53 QED_ROCE_QP_STATE_ERR,
57 enum qed_rdma_tid_type {
58 QED_RDMA_TID_REGISTERED_MR,
60 QED_RDMA_TID_MW_TYPE1,
61 QED_RDMA_TID_MW_TYPE2A
64 struct qed_rdma_events {
66 void (*affiliated_event)(void *context, u8 fw_event_code,
68 void (*unaffiliated_event)(void *context, u8 event_code);
71 struct qed_rdma_device {
86 u8 max_qp_resp_rd_atomic_resc;
87 u8 max_qp_req_rd_atomic_resc;
88 u64 max_dev_resp_rd_atomic_resc;
97 u32 max_mr_mw_fmr_pbl;
98 u64 max_mr_mw_fmr_size;
106 /* Abilty to support RNR-NAK generation */
108 #define QED_RDMA_DEV_CAP_RNR_NAK_MASK 0x1
109 #define QED_RDMA_DEV_CAP_RNR_NAK_SHIFT 0
110 /* Abilty to support shutdown port */
111 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1
112 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT 1
113 /* Abilty to support port active event */
114 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1
115 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2
116 /* Abilty to support port change event */
117 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1
118 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3
119 /* Abilty to support system image GUID */
120 #define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1
121 #define QED_RDMA_DEV_CAP_SYS_IMAGE_SHIFT 4
122 /* Abilty to support bad P_Key counter support */
123 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1
124 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT 5
125 /* Abilty to support atomic operations */
126 #define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1
127 #define QED_RDMA_DEV_CAP_ATOMIC_OP_SHIFT 6
128 #define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1
129 #define QED_RDMA_DEV_CAP_RESIZE_CQ_SHIFT 7
130 /* Abilty to support modifying the maximum number of
131 * outstanding work requests per QP
133 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1
134 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT 8
135 /* Abilty to support automatic path migration */
136 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1
137 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT 9
138 /* Abilty to support the base memory management extensions */
139 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1
140 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10
141 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1
142 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11
143 /* Abilty to support multipile page sizes per memory region */
144 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1
145 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12
146 /* Abilty to support block list physical buffer list */
147 #define QED_RDMA_DEV_CAP_BLOCK_MODE_MASK 0x1
148 #define QED_RDMA_DEV_CAP_BLOCK_MODE_SHIFT 13
149 /* Abilty to support zero based virtual addresses */
150 #define QED_RDMA_DEV_CAP_ZBVA_MASK 0x1
151 #define QED_RDMA_DEV_CAP_ZBVA_SHIFT 14
152 /* Abilty to support local invalidate fencing */
153 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1
154 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15
155 /* Abilty to support Loopback on QP */
156 #define QED_RDMA_DEV_CAP_LB_INDICATOR_MASK 0x1
157 #define QED_RDMA_DEV_CAP_LB_INDICATOR_SHIFT 16
161 u32 bad_pkey_counter;
162 struct qed_rdma_events events;
165 enum qed_port_state {
170 enum qed_roce_capability {
171 QED_ROCE_V1 = 1 << 0,
172 QED_ROCE_V2 = 1 << 1,
175 struct qed_rdma_port {
176 enum qed_port_state port_state;
179 u8 source_gid_table_len;
180 void *source_gid_table_ptr;
182 void *pkey_table_ptr;
183 u32 pkey_bad_counter;
184 enum qed_roce_capability capability;
187 struct qed_rdma_cnq_params {
192 /* The CQ Mode affects the CQ doorbell transaction size.
193 * 64/32 bit machines should configure to 32/16 bits respectively.
195 enum qed_rdma_cq_mode {
196 QED_RDMA_CQ_MODE_16_BITS,
197 QED_RDMA_CQ_MODE_32_BITS,
200 struct qed_roce_dcqcn_params {
201 u8 notification_point;
204 /* fields for notification point */
205 u32 cnp_send_timeout;
207 /* fields for reaction point */
214 u32 dcqcn_timeout_us;
217 struct qed_rdma_start_in_params {
218 struct qed_rdma_events *events;
219 struct qed_rdma_cnq_params cnq_pbl_list[128];
221 enum qed_rdma_cq_mode cq_mode;
222 struct qed_roce_dcqcn_params dcqcn_params;
224 u8 mac_addr[ETH_ALEN];
228 struct qed_rdma_add_user_out_params {
250 struct qed_rdma_register_tid_in_params {
252 enum qed_rdma_tid_type tid_type;
263 u8 pbl_page_size_log;
277 struct qed_rdma_create_cq_in_params {
285 u8 pbl_page_size_log;
290 struct qed_rdma_create_srq_in_params {
298 struct qed_rdma_destroy_cq_in_params {
302 struct qed_rdma_destroy_cq_out_params {
306 struct qed_rdma_create_qp_in_params {
309 u32 qp_handle_async_lo;
310 u32 qp_handle_async_hi;
313 bool fmr_and_reserved_lkey;
327 struct qed_rdma_create_qp_out_params {
331 dma_addr_t rq_pbl_phys;
333 dma_addr_t sq_pbl_phys;
336 struct qed_rdma_modify_qp_in_params {
338 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK 0x1
339 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT 0
340 #define QED_ROCE_MODIFY_QP_VALID_PKEY_MASK 0x1
341 #define QED_ROCE_MODIFY_QP_VALID_PKEY_SHIFT 1
342 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK 0x1
343 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT 2
344 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_MASK 0x1
345 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT 3
346 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK 0x1
347 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT 4
348 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK 0x1
349 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT 5
350 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK 0x1
351 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT 6
352 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK 0x1
353 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT 7
354 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK 0x1
355 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT 8
356 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK 0x1
357 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT 9
358 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK 0x1
359 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT 10
360 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK 0x1
361 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT 11
362 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK 0x1
363 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT 12
364 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK 0x1
365 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT 13
366 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK 0x1
367 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT 14
369 enum qed_roce_qp_state new_state;
371 bool incoming_rdma_read_en;
372 bool incoming_rdma_write_en;
373 bool incoming_atomic_en;
374 bool e2e_flow_control_en;
378 u8 traffic_class_tos;
389 u8 max_rd_atomic_resp;
390 u8 max_rd_atomic_req;
394 u8 min_rnr_nak_timer;
396 u8 remote_mac_addr[6];
397 u8 local_mac_addr[6];
399 enum roce_mode roce_mode;
402 struct qed_rdma_query_qp_out_params {
403 enum qed_roce_qp_state state;
409 bool incoming_rdma_read_en;
410 bool incoming_rdma_write_en;
411 bool incoming_atomic_en;
412 bool e2e_flow_control_en;
417 u8 traffic_class_tos;
421 u8 min_rnr_nak_timer;
424 u8 max_dest_rd_atomic;
428 struct qed_rdma_create_srq_out_params {
432 struct qed_rdma_destroy_srq_in_params {
436 struct qed_rdma_modify_srq_in_params {
441 struct qed_rdma_stats_out_params {
448 struct qed_rdma_counters_out_params {
461 #define QED_ROCE_TX_HEAD_FAILURE (1)
462 #define QED_ROCE_TX_FRAG_FAILURE (2)
468 struct qed_dev_rdma_info {
469 struct qed_dev_info common;
470 enum qed_rdma_type rdma_type;
473 struct qed_rdma_ops {
474 const struct qed_common_ops *common;
476 int (*fill_dev_info)(struct qed_dev *cdev,
477 struct qed_dev_rdma_info *info);
478 void *(*rdma_get_rdma_ctx)(struct qed_dev *cdev);
480 int (*rdma_init)(struct qed_dev *dev,
481 struct qed_rdma_start_in_params *iparams);
483 int (*rdma_add_user)(void *rdma_cxt,
484 struct qed_rdma_add_user_out_params *oparams);
486 void (*rdma_remove_user)(void *rdma_cxt, u16 dpi);
487 int (*rdma_stop)(void *rdma_cxt);
488 struct qed_rdma_device* (*rdma_query_device)(void *rdma_cxt);
489 struct qed_rdma_port* (*rdma_query_port)(void *rdma_cxt);
490 int (*rdma_get_start_sb)(struct qed_dev *cdev);
491 int (*rdma_get_min_cnq_msix)(struct qed_dev *cdev);
492 void (*rdma_cnq_prod_update)(void *rdma_cxt, u8 cnq_index, u16 prod);
493 int (*rdma_get_rdma_int)(struct qed_dev *cdev,
494 struct qed_int_info *info);
495 int (*rdma_set_rdma_int)(struct qed_dev *cdev, u16 cnt);
496 int (*rdma_alloc_pd)(void *rdma_cxt, u16 *pd);
497 void (*rdma_dealloc_pd)(void *rdma_cxt, u16 pd);
498 int (*rdma_create_cq)(void *rdma_cxt,
499 struct qed_rdma_create_cq_in_params *params,
501 int (*rdma_destroy_cq)(void *rdma_cxt,
502 struct qed_rdma_destroy_cq_in_params *iparams,
503 struct qed_rdma_destroy_cq_out_params *oparams);
505 (*rdma_create_qp)(void *rdma_cxt,
506 struct qed_rdma_create_qp_in_params *iparams,
507 struct qed_rdma_create_qp_out_params *oparams);
509 int (*rdma_modify_qp)(void *roce_cxt, struct qed_rdma_qp *qp,
510 struct qed_rdma_modify_qp_in_params *iparams);
512 int (*rdma_query_qp)(void *rdma_cxt, struct qed_rdma_qp *qp,
513 struct qed_rdma_query_qp_out_params *oparams);
514 int (*rdma_destroy_qp)(void *rdma_cxt, struct qed_rdma_qp *qp);
517 const struct qed_rdma_ops *qed_get_rdma_ops(void);