1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #ifndef _QED_ROCE_IF_H
33 #define _QED_ROCE_IF_H
34 #include <linux/types.h>
35 #include <linux/delay.h>
36 #include <linux/list.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/slab.h>
40 #include <linux/qed/qed_if.h>
41 #include <linux/qed/qed_ll2_if.h>
43 #define QED_RDMA_MAX_CNQ_SIZE (0xFFFF)
46 enum qed_rdma_tid_type {
47 QED_RDMA_TID_REGISTERED_MR,
49 QED_RDMA_TID_MW_TYPE1,
50 QED_RDMA_TID_MW_TYPE2A
53 struct qed_rdma_events {
55 void (*affiliated_event)(void *context, u8 fw_event_code,
57 void (*unaffiliated_event)(void *context, u8 event_code);
60 struct qed_rdma_device {
75 u8 max_qp_resp_rd_atomic_resc;
76 u8 max_qp_req_rd_atomic_resc;
77 u64 max_dev_resp_rd_atomic_resc;
86 u32 max_mr_mw_fmr_pbl;
87 u64 max_mr_mw_fmr_size;
95 /* Abilty to support RNR-NAK generation */
97 #define QED_RDMA_DEV_CAP_RNR_NAK_MASK 0x1
98 #define QED_RDMA_DEV_CAP_RNR_NAK_SHIFT 0
99 /* Abilty to support shutdown port */
100 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1
101 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT 1
102 /* Abilty to support port active event */
103 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1
104 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2
105 /* Abilty to support port change event */
106 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1
107 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3
108 /* Abilty to support system image GUID */
109 #define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1
110 #define QED_RDMA_DEV_CAP_SYS_IMAGE_SHIFT 4
111 /* Abilty to support bad P_Key counter support */
112 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1
113 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT 5
114 /* Abilty to support atomic operations */
115 #define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1
116 #define QED_RDMA_DEV_CAP_ATOMIC_OP_SHIFT 6
117 #define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1
118 #define QED_RDMA_DEV_CAP_RESIZE_CQ_SHIFT 7
119 /* Abilty to support modifying the maximum number of
120 * outstanding work requests per QP
122 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1
123 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT 8
124 /* Abilty to support automatic path migration */
125 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1
126 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT 9
127 /* Abilty to support the base memory management extensions */
128 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1
129 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10
130 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1
131 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11
132 /* Abilty to support multipile page sizes per memory region */
133 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1
134 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12
135 /* Abilty to support block list physical buffer list */
136 #define QED_RDMA_DEV_CAP_BLOCK_MODE_MASK 0x1
137 #define QED_RDMA_DEV_CAP_BLOCK_MODE_SHIFT 13
138 /* Abilty to support zero based virtual addresses */
139 #define QED_RDMA_DEV_CAP_ZBVA_MASK 0x1
140 #define QED_RDMA_DEV_CAP_ZBVA_SHIFT 14
141 /* Abilty to support local invalidate fencing */
142 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1
143 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15
144 /* Abilty to support Loopback on QP */
145 #define QED_RDMA_DEV_CAP_LB_INDICATOR_MASK 0x1
146 #define QED_RDMA_DEV_CAP_LB_INDICATOR_SHIFT 16
150 u32 bad_pkey_counter;
151 struct qed_rdma_events events;
154 enum qed_port_state {
159 enum qed_roce_capability {
160 QED_ROCE_V1 = 1 << 0,
161 QED_ROCE_V2 = 1 << 1,
164 struct qed_rdma_port {
165 enum qed_port_state port_state;
168 u8 source_gid_table_len;
169 void *source_gid_table_ptr;
171 void *pkey_table_ptr;
172 u32 pkey_bad_counter;
173 enum qed_roce_capability capability;
176 struct qed_rdma_cnq_params {
181 /* The CQ Mode affects the CQ doorbell transaction size.
182 * 64/32 bit machines should configure to 32/16 bits respectively.
184 enum qed_rdma_cq_mode {
185 QED_RDMA_CQ_MODE_16_BITS,
186 QED_RDMA_CQ_MODE_32_BITS,
189 struct qed_roce_dcqcn_params {
190 u8 notification_point;
193 /* fields for notification point */
194 u32 cnp_send_timeout;
196 /* fields for reaction point */
203 u32 dcqcn_timeout_us;
206 struct qed_rdma_start_in_params {
207 struct qed_rdma_events *events;
208 struct qed_rdma_cnq_params cnq_pbl_list[128];
210 enum qed_rdma_cq_mode cq_mode;
211 struct qed_roce_dcqcn_params dcqcn_params;
213 u8 mac_addr[ETH_ALEN];
217 struct qed_rdma_add_user_out_params {
239 struct qed_rdma_register_tid_in_params {
241 enum qed_rdma_tid_type tid_type;
252 u8 pbl_page_size_log;
266 struct qed_rdma_create_cq_in_params {
274 u8 pbl_page_size_log;
279 struct qed_rdma_create_srq_in_params {
287 struct qed_rdma_destroy_cq_in_params {
291 struct qed_rdma_destroy_cq_out_params {
295 struct qed_rdma_create_srq_out_params {
299 struct qed_rdma_destroy_srq_in_params {
303 struct qed_rdma_modify_srq_in_params {
308 struct qed_rdma_stats_out_params {
315 struct qed_rdma_counters_out_params {
328 #define QED_ROCE_TX_HEAD_FAILURE (1)
329 #define QED_ROCE_TX_FRAG_FAILURE (2)
335 struct qed_dev_rdma_info {
336 struct qed_dev_info common;
337 enum qed_rdma_type rdma_type;
340 struct qed_rdma_ops {
341 const struct qed_common_ops *common;
343 int (*fill_dev_info)(struct qed_dev *cdev,
344 struct qed_dev_rdma_info *info);
345 void *(*rdma_get_rdma_ctx)(struct qed_dev *cdev);
347 int (*rdma_init)(struct qed_dev *dev,
348 struct qed_rdma_start_in_params *iparams);
350 int (*rdma_add_user)(void *rdma_cxt,
351 struct qed_rdma_add_user_out_params *oparams);
353 void (*rdma_remove_user)(void *rdma_cxt, u16 dpi);
354 int (*rdma_stop)(void *rdma_cxt);
355 struct qed_rdma_device* (*rdma_query_device)(void *rdma_cxt);
356 struct qed_rdma_port* (*rdma_query_port)(void *rdma_cxt);
357 int (*rdma_get_start_sb)(struct qed_dev *cdev);
358 int (*rdma_get_min_cnq_msix)(struct qed_dev *cdev);
359 void (*rdma_cnq_prod_update)(void *rdma_cxt, u8 cnq_index, u16 prod);
360 int (*rdma_get_rdma_int)(struct qed_dev *cdev,
361 struct qed_int_info *info);
362 int (*rdma_set_rdma_int)(struct qed_dev *cdev, u16 cnt);
363 int (*rdma_alloc_pd)(void *rdma_cxt, u16 *pd);
364 void (*rdma_dealloc_pd)(void *rdma_cxt, u16 pd);
365 int (*rdma_create_cq)(void *rdma_cxt,
366 struct qed_rdma_create_cq_in_params *params,
368 int (*rdma_destroy_cq)(void *rdma_cxt,
369 struct qed_rdma_destroy_cq_in_params *iparams,
370 struct qed_rdma_destroy_cq_out_params *oparams);
373 const struct qed_rdma_ops *qed_get_rdma_ops(void);