include/uapi/linux/v4l2-dv-timings.h

   1 /*
   2  * V4L2 DV timings header.
   3  *
   4  * Copyright (C) 2012  Hans Verkuil <hans.verkuil@cisco.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  */
  20
  21 #ifndef _V4L2_DV_TIMINGS_H
  22 #define _V4L2_DV_TIMINGS_H
  23
  24 #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
  25 /* Sadly gcc versions older than 4.6 have a bug in how they initialize
  26    anonymous unions where they require additional curly brackets.
  27    This violates the C1x standard. This workaround adds the curly brackets
  28    if needed. */
  29 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
  30         { .bt = { _width , ## args } }
  31 #else
  32 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
  33         .bt = { _width , ## args }
  34 #endif
  35
  36 /* CEA-861-E timings (i.e. standard HDTV timings) */
  37
  38 #define V4L2_DV_BT_CEA_640X480P59_94 { \
  39         .type = V4L2_DV_BT_656_1120, \
  40         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  41                 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
  42                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
  43 }
  44
  45 /* Note: these are the nominal timings, for HDMI links this format is typically
  46  * double-clocked to meet the minimum pixelclock requirements.  */
  47 #define V4L2_DV_BT_CEA_720X480I59_94 { \
  48         .type = V4L2_DV_BT_656_1120, \
  49         V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
  50                 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
  51                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
  52 }
  53
  54 #define V4L2_DV_BT_CEA_720X480P59_94 { \
  55         .type = V4L2_DV_BT_656_1120, \
  56         V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
  57                 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
  58                 V4L2_DV_BT_STD_CEA861, 0) \
  59 }
  60
  61 /* Note: these are the nominal timings, for HDMI links this format is typically
  62  * double-clocked to meet the minimum pixelclock requirements.  */
  63 #define V4L2_DV_BT_CEA_720X576I50 { \
  64         .type = V4L2_DV_BT_656_1120, \
  65         V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
  66                 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
  67                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
  68 }
  69
  70 #define V4L2_DV_BT_CEA_720X576P50 { \
  71         .type = V4L2_DV_BT_656_1120, \
  72         V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
  73                 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
  74                 V4L2_DV_BT_STD_CEA861, 0) \
  75 }
  76
  77 #define V4L2_DV_BT_CEA_1280X720P24 { \
  78         .type = V4L2_DV_BT_656_1120, \
  79         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  80                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  81                 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  82                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
  83                 V4L2_DV_FL_CAN_REDUCE_FPS) \
  84 }
  85
  86 #define V4L2_DV_BT_CEA_1280X720P25 { \
  87         .type = V4L2_DV_BT_656_1120, \
  88         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  89                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  90                 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
  91                 V4L2_DV_BT_STD_CEA861, 0) \
  92 }
  93
  94 #define V4L2_DV_BT_CEA_1280X720P30 { \
  95         .type = V4L2_DV_BT_656_1120, \
  96         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  97                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  98                 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  99                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 100 }
 101
 102 #define V4L2_DV_BT_CEA_1280X720P50 { \
 103         .type = V4L2_DV_BT_656_1120, \
 104         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
 105                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 106                 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
 107                 V4L2_DV_BT_STD_CEA861, 0) \
 108 }
 109
 110 #define V4L2_DV_BT_CEA_1280X720P60 { \
 111         .type = V4L2_DV_BT_656_1120, \
 112         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
 113                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 114                 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
 115                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 116 }
 117
 118 #define V4L2_DV_BT_CEA_1920X1080P24 { \
 119         .type = V4L2_DV_BT_656_1120, \
 120         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 121                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 122                 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
 123                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 124 }
 125
 126 #define V4L2_DV_BT_CEA_1920X1080P25 { \
 127         .type = V4L2_DV_BT_656_1120, \
 128         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 129                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 130                 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
 131                 V4L2_DV_BT_STD_CEA861, 0) \
 132 }
 133
 134 #define V4L2_DV_BT_CEA_1920X1080P30 { \
 135         .type = V4L2_DV_BT_656_1120, \
 136         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 137                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 138                 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
 139                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 140 }
 141
 142 #define V4L2_DV_BT_CEA_1920X1080I50 { \
 143         .type = V4L2_DV_BT_656_1120, \
 144         V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
 145                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 146                 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
 147                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
 148 }
 149
 150 #define V4L2_DV_BT_CEA_1920X1080P50 { \
 151         .type = V4L2_DV_BT_656_1120, \
 152         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 153                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 154                 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
 155                 V4L2_DV_BT_STD_CEA861, 0) \
 156 }
 157
 158 #define V4L2_DV_BT_CEA_1920X1080I60 { \
 159         .type = V4L2_DV_BT_656_1120, \
 160         V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
 161                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 162                 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
 163                 V4L2_DV_BT_STD_CEA861, \
 164                 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \
 165 }
 166
 167 #define V4L2_DV_BT_CEA_1920X1080P60 { \
 168         .type = V4L2_DV_BT_656_1120, \
 169         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 170                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 171                 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
 172                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
 173                 V4L2_DV_FL_CAN_REDUCE_FPS) \
 174 }
 175
 176 #define V4L2_DV_BT_CEA_3840X2160P24 { \
 177         .type = V4L2_DV_BT_656_1120, \
 178         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 179                 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
 180                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 181 }
 182
 183 #define V4L2_DV_BT_CEA_3840X2160P25 { \
 184         .type = V4L2_DV_BT_656_1120, \
 185         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 186                 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
 187                 V4L2_DV_BT_STD_CEA861, 0) \
 188 }
 189
 190 #define V4L2_DV_BT_CEA_3840X2160P30 { \
 191         .type = V4L2_DV_BT_656_1120, \
 192         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 193                 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
 194                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 195 }
 196
 197 #define V4L2_DV_BT_CEA_3840X2160P50 { \
 198         .type = V4L2_DV_BT_656_1120, \
 199         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 200                 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
 201                 V4L2_DV_BT_STD_CEA861, 0) \
 202 }
 203
 204 #define V4L2_DV_BT_CEA_3840X2160P60 { \
 205         .type = V4L2_DV_BT_656_1120, \
 206         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 207                 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
 208                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 209 }
 210
 211 #define V4L2_DV_BT_CEA_4096X2160P24 { \
 212         .type = V4L2_DV_BT_656_1120, \
 213         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 214                 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
 215                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 216 }
 217
 218 #define V4L2_DV_BT_CEA_4096X2160P25 { \
 219         .type = V4L2_DV_BT_656_1120, \
 220         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 221                 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
 222                 V4L2_DV_BT_STD_CEA861, 0) \
 223 }
 224
 225 #define V4L2_DV_BT_CEA_4096X2160P30 { \
 226         .type = V4L2_DV_BT_656_1120, \
 227         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 228                 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
 229                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 230 }
 231
 232 #define V4L2_DV_BT_CEA_4096X2160P50 { \
 233         .type = V4L2_DV_BT_656_1120, \
 234         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 235                 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
 236                 V4L2_DV_BT_STD_CEA861, 0) \
 237 }
 238
 239 #define V4L2_DV_BT_CEA_4096X2160P60 { \
 240         .type = V4L2_DV_BT_656_1120, \
 241         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 242                 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
 243                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 244 }
 245
 246
 247 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
 248
 249 #define V4L2_DV_BT_DMT_640X350P85 { \
 250         .type = V4L2_DV_BT_656_1120, \
 251         V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
 252                 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
 253                 V4L2_DV_BT_STD_DMT, 0) \
 254 }
 255
 256 #define V4L2_DV_BT_DMT_640X400P85 { \
 257         .type = V4L2_DV_BT_656_1120, \
 258         V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
 259                 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
 260                 V4L2_DV_BT_STD_DMT, 0) \
 261 }
 262
 263 #define V4L2_DV_BT_DMT_720X400P85 { \
 264         .type = V4L2_DV_BT_656_1120, \
 265         V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
 266                 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
 267                 V4L2_DV_BT_STD_DMT, 0) \
 268 }
 269
 270 /* VGA resolutions */
 271 #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
 272
 273 #define V4L2_DV_BT_DMT_640X480P72 { \
 274         .type = V4L2_DV_BT_656_1120, \
 275         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
 276                 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
 277                 V4L2_DV_BT_STD_DMT, 0) \
 278 }
 279
 280 #define V4L2_DV_BT_DMT_640X480P75 { \
 281         .type = V4L2_DV_BT_656_1120, \
 282         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
 283                 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
 284                 V4L2_DV_BT_STD_DMT, 0) \
 285 }
 286
 287 #define V4L2_DV_BT_DMT_640X480P85 { \
 288         .type = V4L2_DV_BT_656_1120, \
 289         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
 290                 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
 291                 V4L2_DV_BT_STD_DMT, 0) \
 292 }
 293
 294 /* SVGA resolutions */
 295 #define V4L2_DV_BT_DMT_800X600P56 { \
 296         .type = V4L2_DV_BT_656_1120, \
 297         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 298                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 299                 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
 300                 V4L2_DV_BT_STD_DMT, 0) \
 301 }
 302
 303 #define V4L2_DV_BT_DMT_800X600P60 { \
 304         .type = V4L2_DV_BT_656_1120, \
 305         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 306                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 307                 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
 308                 V4L2_DV_BT_STD_DMT, 0) \
 309 }
 310
 311 #define V4L2_DV_BT_DMT_800X600P72 { \
 312         .type = V4L2_DV_BT_656_1120, \
 313         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 314                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 315                 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
 316                 V4L2_DV_BT_STD_DMT, 0) \
 317 }
 318
 319 #define V4L2_DV_BT_DMT_800X600P75 { \
 320         .type = V4L2_DV_BT_656_1120, \
 321         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 322                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 323                 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
 324                 V4L2_DV_BT_STD_DMT, 0) \
 325 }
 326
 327 #define V4L2_DV_BT_DMT_800X600P85 { \
 328         .type = V4L2_DV_BT_656_1120, \
 329         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 330                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 331                 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
 332                 V4L2_DV_BT_STD_DMT, 0) \
 333 }
 334
 335 #define V4L2_DV_BT_DMT_800X600P120_RB { \
 336         .type = V4L2_DV_BT_656_1120, \
 337         V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
 338                 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
 339                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 340                 V4L2_DV_FL_REDUCED_BLANKING) \
 341 }
 342
 343 #define V4L2_DV_BT_DMT_848X480P60 { \
 344         .type = V4L2_DV_BT_656_1120, \
 345         V4L2_INIT_BT_TIMINGS(848, 480, 0, \
 346                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 347                 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
 348                 V4L2_DV_BT_STD_DMT, 0) \
 349 }
 350
 351 #define V4L2_DV_BT_DMT_1024X768I43 { \
 352         .type = V4L2_DV_BT_656_1120, \
 353         V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
 354                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 355                 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
 356                 V4L2_DV_BT_STD_DMT, 0) \
 357 }
 358
 359 /* XGA resolutions */
 360 #define V4L2_DV_BT_DMT_1024X768P60 { \
 361         .type = V4L2_DV_BT_656_1120, \
 362         V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
 363                 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
 364                 V4L2_DV_BT_STD_DMT, 0) \
 365 }
 366
 367 #define V4L2_DV_BT_DMT_1024X768P70 { \
 368         .type = V4L2_DV_BT_656_1120, \
 369         V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
 370                 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
 371                 V4L2_DV_BT_STD_DMT, 0) \
 372 }
 373
 374 #define V4L2_DV_BT_DMT_1024X768P75 { \
 375         .type = V4L2_DV_BT_656_1120, \
 376         V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
 377                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 378                 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
 379                 V4L2_DV_BT_STD_DMT, 0) \
 380 }
 381
 382 #define V4L2_DV_BT_DMT_1024X768P85 { \
 383         .type = V4L2_DV_BT_656_1120, \
 384         V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
 385                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 386                 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
 387                 V4L2_DV_BT_STD_DMT, 0) \
 388 }
 389
 390 #define V4L2_DV_BT_DMT_1024X768P120_RB { \
 391         .type = V4L2_DV_BT_656_1120, \
 392         V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 393                 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
 394                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 395                 V4L2_DV_FL_REDUCED_BLANKING) \
 396 }
 397
 398 /* XGA+ resolution */
 399 #define V4L2_DV_BT_DMT_1152X864P75 { \
 400         .type = V4L2_DV_BT_656_1120, \
 401         V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
 402                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 403                 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
 404                 V4L2_DV_BT_STD_DMT, 0) \
 405 }
 406
 407 #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
 408
 409 /* WXGA resolutions */
 410 #define V4L2_DV_BT_DMT_1280X768P60_RB { \
 411         .type = V4L2_DV_BT_656_1120, \
 412         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 413                 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
 414                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 415                 V4L2_DV_FL_REDUCED_BLANKING) \
 416 }
 417
 418 #define V4L2_DV_BT_DMT_1280X768P60 { \
 419         .type = V4L2_DV_BT_656_1120, \
 420         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
 421                 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
 422                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 423 }
 424
 425 #define V4L2_DV_BT_DMT_1280X768P75 { \
 426         .type = V4L2_DV_BT_656_1120, \
 427         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
 428                 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
 429                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 430 }
 431
 432 #define V4L2_DV_BT_DMT_1280X768P85 { \
 433         .type = V4L2_DV_BT_656_1120, \
 434         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
 435                 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
 436                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 437 }
 438
 439 #define V4L2_DV_BT_DMT_1280X768P120_RB { \
 440         .type = V4L2_DV_BT_656_1120, \
 441         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 442                 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
 443                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 444                 V4L2_DV_FL_REDUCED_BLANKING) \
 445 }
 446
 447 #define V4L2_DV_BT_DMT_1280X800P60_RB { \
 448         .type = V4L2_DV_BT_656_1120, \
 449         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
 450                 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
 451                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 452                 V4L2_DV_FL_REDUCED_BLANKING) \
 453 }
 454
 455 #define V4L2_DV_BT_DMT_1280X800P60 { \
 456         .type = V4L2_DV_BT_656_1120, \
 457         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
 458                 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
 459                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 460 }
 461
 462 #define V4L2_DV_BT_DMT_1280X800P75 { \
 463         .type = V4L2_DV_BT_656_1120, \
 464         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
 465                 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
 466                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 467 }
 468
 469 #define V4L2_DV_BT_DMT_1280X800P85 { \
 470         .type = V4L2_DV_BT_656_1120, \
 471         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
 472                 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
 473                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 474 }
 475
 476 #define V4L2_DV_BT_DMT_1280X800P120_RB { \
 477         .type = V4L2_DV_BT_656_1120, \
 478         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
 479                 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
 480                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 481                 V4L2_DV_FL_REDUCED_BLANKING) \
 482 }
 483
 484 #define V4L2_DV_BT_DMT_1280X960P60 { \
 485         .type = V4L2_DV_BT_656_1120, \
 486         V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
 487                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 488                 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
 489                 V4L2_DV_BT_STD_DMT, 0) \
 490 }
 491
 492 #define V4L2_DV_BT_DMT_1280X960P85 { \
 493         .type = V4L2_DV_BT_656_1120, \
 494         V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
 495                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 496                 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
 497                 V4L2_DV_BT_STD_DMT, 0) \
 498 }
 499
 500 #define V4L2_DV_BT_DMT_1280X960P120_RB { \
 501         .type = V4L2_DV_BT_656_1120, \
 502         V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
 503                 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
 504                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 505                 V4L2_DV_FL_REDUCED_BLANKING) \
 506 }
 507
 508 /* SXGA resolutions */
 509 #define V4L2_DV_BT_DMT_1280X1024P60 { \
 510         .type = V4L2_DV_BT_656_1120, \
 511         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
 512                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 513                 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
 514                 V4L2_DV_BT_STD_DMT, 0) \
 515 }
 516
 517 #define V4L2_DV_BT_DMT_1280X1024P75 { \
 518         .type = V4L2_DV_BT_656_1120, \
 519         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
 520                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 521                 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
 522                 V4L2_DV_BT_STD_DMT, 0) \
 523 }
 524
 525 #define V4L2_DV_BT_DMT_1280X1024P85 { \
 526         .type = V4L2_DV_BT_656_1120, \
 527         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
 528                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 529                 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
 530                 V4L2_DV_BT_STD_DMT, 0) \
 531 }
 532
 533 #define V4L2_DV_BT_DMT_1280X1024P120_RB { \
 534         .type = V4L2_DV_BT_656_1120, \
 535         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
 536                 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
 537                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 538                 V4L2_DV_FL_REDUCED_BLANKING) \
 539 }
 540
 541 #define V4L2_DV_BT_DMT_1360X768P60 { \
 542         .type = V4L2_DV_BT_656_1120, \
 543         V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
 544                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 545                 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
 546                 V4L2_DV_BT_STD_DMT, 0) \
 547 }
 548
 549 #define V4L2_DV_BT_DMT_1360X768P120_RB { \
 550         .type = V4L2_DV_BT_656_1120, \
 551         V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 552                 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
 553                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 554                 V4L2_DV_FL_REDUCED_BLANKING) \
 555 }
 556
 557 #define V4L2_DV_BT_DMT_1366X768P60 { \
 558         .type = V4L2_DV_BT_656_1120, \
 559         V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
 560                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 561                 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
 562                 V4L2_DV_BT_STD_DMT, 0) \
 563 }
 564
 565 #define V4L2_DV_BT_DMT_1366X768P60_RB { \
 566         .type = V4L2_DV_BT_656_1120, \
 567         V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
 568                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 569                 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
 570                 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
 571 }
 572
 573 /* SXGA+ resolutions */
 574 #define V4L2_DV_BT_DMT_1400X1050P60_RB { \
 575         .type = V4L2_DV_BT_656_1120, \
 576         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 577                 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
 578                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 579                 V4L2_DV_FL_REDUCED_BLANKING) \
 580 }
 581
 582 #define V4L2_DV_BT_DMT_1400X1050P60 { \
 583         .type = V4L2_DV_BT_656_1120, \
 584         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 585                 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
 586                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 587 }
 588
 589 #define V4L2_DV_BT_DMT_1400X1050P75 { \
 590         .type = V4L2_DV_BT_656_1120, \
 591         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 592                 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
 593                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 594 }
 595
 596 #define V4L2_DV_BT_DMT_1400X1050P85 { \
 597         .type = V4L2_DV_BT_656_1120, \
 598         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 599                 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
 600                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 601 }
 602
 603 #define V4L2_DV_BT_DMT_1400X1050P120_RB { \
 604         .type = V4L2_DV_BT_656_1120, \
 605         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 606                 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
 607                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 608                 V4L2_DV_FL_REDUCED_BLANKING) \
 609 }
 610
 611 /* WXGA+ resolutions */
 612 #define V4L2_DV_BT_DMT_1440X900P60_RB { \
 613         .type = V4L2_DV_BT_656_1120, \
 614         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
 615                 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
 616                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 617                 V4L2_DV_FL_REDUCED_BLANKING) \
 618 }
 619
 620 #define V4L2_DV_BT_DMT_1440X900P60 { \
 621         .type = V4L2_DV_BT_656_1120, \
 622         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
 623                 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
 624                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 625 }
 626
 627 #define V4L2_DV_BT_DMT_1440X900P75 { \
 628         .type = V4L2_DV_BT_656_1120, \
 629         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
 630                 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
 631                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 632 }
 633
 634 #define V4L2_DV_BT_DMT_1440X900P85 { \
 635         .type = V4L2_DV_BT_656_1120, \
 636         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
 637                 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
 638                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 639 }
 640
 641 #define V4L2_DV_BT_DMT_1440X900P120_RB { \
 642         .type = V4L2_DV_BT_656_1120, \
 643         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
 644                 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
 645                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 646                 V4L2_DV_FL_REDUCED_BLANKING) \
 647 }
 648
 649 #define V4L2_DV_BT_DMT_1600X900P60_RB { \
 650         .type = V4L2_DV_BT_656_1120, \
 651         V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
 652                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 653                 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
 654                 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
 655 }
 656
 657 /* UXGA resolutions */
 658 #define V4L2_DV_BT_DMT_1600X1200P60 { \
 659         .type = V4L2_DV_BT_656_1120, \
 660         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 661                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 662                 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 663                 V4L2_DV_BT_STD_DMT, 0) \
 664 }
 665
 666 #define V4L2_DV_BT_DMT_1600X1200P65 { \
 667         .type = V4L2_DV_BT_656_1120, \
 668         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 669                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 670                 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 671                 V4L2_DV_BT_STD_DMT, 0) \
 672 }
 673
 674 #define V4L2_DV_BT_DMT_1600X1200P70 { \
 675         .type = V4L2_DV_BT_656_1120, \
 676         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 677                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 678                 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 679                 V4L2_DV_BT_STD_DMT, 0) \
 680 }
 681
 682 #define V4L2_DV_BT_DMT_1600X1200P75 { \
 683         .type = V4L2_DV_BT_656_1120, \
 684         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 685                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 686                 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 687                 V4L2_DV_BT_STD_DMT, 0) \
 688 }
 689
 690 #define V4L2_DV_BT_DMT_1600X1200P85 { \
 691         .type = V4L2_DV_BT_656_1120, \
 692         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 693                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 694                 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 695                 V4L2_DV_BT_STD_DMT, 0) \
 696 }
 697
 698 #define V4L2_DV_BT_DMT_1600X1200P120_RB { \
 699         .type = V4L2_DV_BT_656_1120, \
 700         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
 701                 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
 702                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 703                 V4L2_DV_FL_REDUCED_BLANKING) \
 704 }
 705
 706 /* WSXGA+ resolutions */
 707 #define V4L2_DV_BT_DMT_1680X1050P60_RB { \
 708         .type = V4L2_DV_BT_656_1120, \
 709         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 710                 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
 711                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 712                 V4L2_DV_FL_REDUCED_BLANKING) \
 713 }
 714
 715 #define V4L2_DV_BT_DMT_1680X1050P60 { \
 716         .type = V4L2_DV_BT_656_1120, \
 717         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 718                 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
 719                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 720 }
 721
 722 #define V4L2_DV_BT_DMT_1680X1050P75 { \
 723         .type = V4L2_DV_BT_656_1120, \
 724         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 725                 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
 726                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 727 }
 728
 729 #define V4L2_DV_BT_DMT_1680X1050P85 { \
 730         .type = V4L2_DV_BT_656_1120, \
 731         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 732                 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
 733                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 734 }
 735
 736 #define V4L2_DV_BT_DMT_1680X1050P120_RB { \
 737         .type = V4L2_DV_BT_656_1120, \
 738         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 739                 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
 740                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 741                 V4L2_DV_FL_REDUCED_BLANKING) \
 742 }
 743
 744 #define V4L2_DV_BT_DMT_1792X1344P60 { \
 745         .type = V4L2_DV_BT_656_1120, \
 746         V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
 747                 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
 748                 V4L2_DV_BT_STD_DMT, 0) \
 749 }
 750
 751 #define V4L2_DV_BT_DMT_1792X1344P75 { \
 752         .type = V4L2_DV_BT_656_1120, \
 753         V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
 754                 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
 755                 V4L2_DV_BT_STD_DMT, 0) \
 756 }
 757
 758 #define V4L2_DV_BT_DMT_1792X1344P120_RB { \
 759         .type = V4L2_DV_BT_656_1120, \
 760         V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
 761                 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
 762                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 763                 V4L2_DV_FL_REDUCED_BLANKING) \
 764 }
 765
 766 #define V4L2_DV_BT_DMT_1856X1392P60 { \
 767         .type = V4L2_DV_BT_656_1120, \
 768         V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
 769                 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
 770                 V4L2_DV_BT_STD_DMT, 0) \
 771 }
 772
 773 #define V4L2_DV_BT_DMT_1856X1392P75 { \
 774         .type = V4L2_DV_BT_656_1120, \
 775         V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
 776                 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
 777                 V4L2_DV_BT_STD_DMT, 0) \
 778 }
 779
 780 #define V4L2_DV_BT_DMT_1856X1392P120_RB { \
 781         .type = V4L2_DV_BT_656_1120, \
 782         V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
 783                 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
 784                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 785                 V4L2_DV_FL_REDUCED_BLANKING) \
 786 }
 787
 788 #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
 789
 790 /* WUXGA resolutions */
 791 #define V4L2_DV_BT_DMT_1920X1200P60_RB { \
 792         .type = V4L2_DV_BT_656_1120, \
 793         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
 794                 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
 795                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 796                 V4L2_DV_FL_REDUCED_BLANKING) \
 797 }
 798
 799 #define V4L2_DV_BT_DMT_1920X1200P60 { \
 800         .type = V4L2_DV_BT_656_1120, \
 801         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
 802                 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
 803                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 804 }
 805
 806 #define V4L2_DV_BT_DMT_1920X1200P75 { \
 807         .type = V4L2_DV_BT_656_1120, \
 808         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
 809                 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
 810                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 811 }
 812
 813 #define V4L2_DV_BT_DMT_1920X1200P85 { \
 814         .type = V4L2_DV_BT_656_1120, \
 815         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
 816                 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
 817                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 818 }
 819
 820 #define V4L2_DV_BT_DMT_1920X1200P120_RB { \
 821         .type = V4L2_DV_BT_656_1120, \
 822         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
 823                 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
 824                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 825                 V4L2_DV_FL_REDUCED_BLANKING) \
 826 }
 827
 828 #define V4L2_DV_BT_DMT_1920X1440P60 { \
 829         .type = V4L2_DV_BT_656_1120, \
 830         V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
 831                 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
 832                 V4L2_DV_BT_STD_DMT, 0) \
 833 }
 834
 835 #define V4L2_DV_BT_DMT_1920X1440P75 { \
 836         .type = V4L2_DV_BT_656_1120, \
 837         V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
 838                 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
 839                 V4L2_DV_BT_STD_DMT, 0) \
 840 }
 841
 842 #define V4L2_DV_BT_DMT_1920X1440P120_RB { \
 843         .type = V4L2_DV_BT_656_1120, \
 844         V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
 845                 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
 846                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 847                 V4L2_DV_FL_REDUCED_BLANKING) \
 848 }
 849
 850 #define V4L2_DV_BT_DMT_2048X1152P60_RB { \
 851         .type = V4L2_DV_BT_656_1120, \
 852         V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
 853                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 854                 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
 855                 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
 856 }
 857
 858 /* WQXGA resolutions */
 859 #define V4L2_DV_BT_DMT_2560X1600P60_RB { \
 860         .type = V4L2_DV_BT_656_1120, \
 861         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
 862                 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
 863                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 864                 V4L2_DV_FL_REDUCED_BLANKING) \
 865 }
 866
 867 #define V4L2_DV_BT_DMT_2560X1600P60 { \
 868         .type = V4L2_DV_BT_656_1120, \
 869         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
 870                 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
 871                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 872 }
 873
 874 #define V4L2_DV_BT_DMT_2560X1600P75 { \
 875         .type = V4L2_DV_BT_656_1120, \
 876         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
 877                 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
 878                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 879 }
 880
 881 #define V4L2_DV_BT_DMT_2560X1600P85 { \
 882         .type = V4L2_DV_BT_656_1120, \
 883         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
 884                 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
 885                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 886 }
 887
 888 #define V4L2_DV_BT_DMT_2560X1600P120_RB { \
 889         .type = V4L2_DV_BT_656_1120, \
 890         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
 891                 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
 892                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 893                 V4L2_DV_FL_REDUCED_BLANKING) \
 894 }
 895
 896 /* 4K resolutions */
 897 #define V4L2_DV_BT_DMT_4096X2160P60_RB { \
 898         .type = V4L2_DV_BT_656_1120, \
 899         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 900                 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
 901                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 902                 V4L2_DV_FL_REDUCED_BLANKING) \
 903 }
 904
 905 #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \
 906         .type = V4L2_DV_BT_656_1120, \
 907         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 908                 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
 909                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 910                 V4L2_DV_FL_REDUCED_BLANKING) \
 911 }
 912
 913 #endif