sound/hda/hdac_controller.c

   1 /*
   2  * HD-audio controller helpers
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/export.h>
   8 #include <sound/core.h>
   9 #include <sound/hdaudio.h>
  10 #include <sound/hda_register.h>
  11
  12 /* clear CORB read pointer properly */
  13 static void azx_clear_corbrp(struct hdac_bus *bus)
  14 {
  15         int timeout;
  16
  17         for (timeout = 1000; timeout > 0; timeout--) {
  18                 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
  19                         break;
  20                 udelay(1);
  21         }
  22         if (timeout <= 0)
  23                 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
  24                         snd_hdac_chip_readw(bus, CORBRP));
  25
  26         snd_hdac_chip_writew(bus, CORBRP, 0);
  27         for (timeout = 1000; timeout > 0; timeout--) {
  28                 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
  29                         break;
  30                 udelay(1);
  31         }
  32         if (timeout <= 0)
  33                 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
  34                         snd_hdac_chip_readw(bus, CORBRP));
  35 }
  36
  37 /**
  38  * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
  39  * @bus: HD-audio core bus
  40  */
  41 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
  42 {
  43         spin_lock_irq(&bus->reg_lock);
  44         /* CORB set up */
  45         bus->corb.addr = bus->rb.addr;
  46         bus->corb.buf = (__le32 *)bus->rb.area;
  47         snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
  48         snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
  49
  50         /* set the corb size to 256 entries (ULI requires explicitly) */
  51         snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
  52         /* set the corb write pointer to 0 */
  53         snd_hdac_chip_writew(bus, CORBWP, 0);
  54
  55         /* reset the corb hw read pointer */
  56         snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
  57         if (!bus->corbrp_self_clear)
  58                 azx_clear_corbrp(bus);
  59
  60         /* enable corb dma */
  61         snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
  62
  63         /* RIRB set up */
  64         bus->rirb.addr = bus->rb.addr + 2048;
  65         bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
  66         bus->rirb.wp = bus->rirb.rp = 0;
  67         memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
  68         snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
  69         snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
  70
  71         /* set the rirb size to 256 entries (ULI requires explicitly) */
  72         snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
  73         /* reset the rirb hw write pointer */
  74         snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
  75         /* set N=1, get RIRB response interrupt for new entry */
  76         snd_hdac_chip_writew(bus, RINTCNT, 1);
  77         /* enable rirb dma and response irq */
  78         snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
  79         spin_unlock_irq(&bus->reg_lock);
  80 }
  81 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
  82
  83 /* wait for cmd dmas till they are stopped */
  84 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
  85 {
  86         unsigned long timeout;
  87
  88         timeout = jiffies + msecs_to_jiffies(100);
  89         while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
  90                 && time_before(jiffies, timeout))
  91                 udelay(10);
  92
  93         timeout = jiffies + msecs_to_jiffies(100);
  94         while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
  95                 && time_before(jiffies, timeout))
  96                 udelay(10);
  97 }
  98
  99 /**
 100  * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
 101  * @bus: HD-audio core bus
 102  */
 103 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
 104 {
 105         spin_lock_irq(&bus->reg_lock);
 106         /* disable ringbuffer DMAs */
 107         snd_hdac_chip_writeb(bus, RIRBCTL, 0);
 108         snd_hdac_chip_writeb(bus, CORBCTL, 0);
 109         hdac_wait_for_cmd_dmas(bus);
 110         /* disable unsolicited responses */
 111         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
 112         spin_unlock_irq(&bus->reg_lock);
 113 }
 114 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
 115
 116 static unsigned int azx_command_addr(u32 cmd)
 117 {
 118         unsigned int addr = cmd >> 28;
 119
 120         if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
 121                 addr = 0;
 122         return addr;
 123 }
 124
 125 /**
 126  * snd_hdac_bus_send_cmd - send a command verb via CORB
 127  * @bus: HD-audio core bus
 128  * @val: encoded verb value to send
 129  *
 130  * Returns zero for success or a negative error code.
 131  */
 132 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
 133 {
 134         unsigned int addr = azx_command_addr(val);
 135         unsigned int wp, rp;
 136
 137         spin_lock_irq(&bus->reg_lock);
 138
 139         bus->last_cmd[azx_command_addr(val)] = val;
 140
 141         /* add command to corb */
 142         wp = snd_hdac_chip_readw(bus, CORBWP);
 143         if (wp == 0xffff) {
 144                 /* something wrong, controller likely turned to D3 */
 145                 spin_unlock_irq(&bus->reg_lock);
 146                 return -EIO;
 147         }
 148         wp++;
 149         wp %= AZX_MAX_CORB_ENTRIES;
 150
 151         rp = snd_hdac_chip_readw(bus, CORBRP);
 152         if (wp == rp) {
 153                 /* oops, it's full */
 154                 spin_unlock_irq(&bus->reg_lock);
 155                 return -EAGAIN;
 156         }
 157
 158         bus->rirb.cmds[addr]++;
 159         bus->corb.buf[wp] = cpu_to_le32(val);
 160         snd_hdac_chip_writew(bus, CORBWP, wp);
 161
 162         spin_unlock_irq(&bus->reg_lock);
 163
 164         return 0;
 165 }
 166 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
 167
 168 #define AZX_RIRB_EX_UNSOL_EV    (1<<4)
 169
 170 /**
 171  * snd_hdac_bus_update_rirb - retrieve RIRB entries
 172  * @bus: HD-audio core bus
 173  *
 174  * Usually called from interrupt handler.
 175  */
 176 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
 177 {
 178         unsigned int rp, wp;
 179         unsigned int addr;
 180         u32 res, res_ex;
 181
 182         wp = snd_hdac_chip_readw(bus, RIRBWP);
 183         if (wp == 0xffff) {
 184                 /* something wrong, controller likely turned to D3 */
 185                 return;
 186         }
 187
 188         if (wp == bus->rirb.wp)
 189                 return;
 190         bus->rirb.wp = wp;
 191
 192         while (bus->rirb.rp != wp) {
 193                 bus->rirb.rp++;
 194                 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
 195
 196                 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 197                 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
 198                 res = le32_to_cpu(bus->rirb.buf[rp]);
 199                 addr = res_ex & 0xf;
 200                 if (addr >= HDA_MAX_CODECS) {
 201                         dev_err(bus->dev,
 202                                 "spurious response %#x:%#x, rp = %d, wp = %d",
 203                                 res, res_ex, bus->rirb.rp, wp);
 204                         snd_BUG();
 205                 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
 206                         snd_hdac_bus_queue_event(bus, res, res_ex);
 207                 else if (bus->rirb.cmds[addr]) {
 208                         bus->rirb.res[addr] = res;
 209                         bus->rirb.cmds[addr]--;
 210                 } else {
 211                         dev_err_ratelimited(bus->dev,
 212                                 "spurious response %#x:%#x, last cmd=%#08x\n",
 213                                 res, res_ex, bus->last_cmd[addr]);
 214                 }
 215         }
 216 }
 217 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
 218
 219 /**
 220  * snd_hdac_bus_get_response - receive a response via RIRB
 221  * @bus: HD-audio core bus
 222  * @addr: codec address
 223  * @res: pointer to store the value, NULL when not needed
 224  *
 225  * Returns zero if a value is read, or a negative error code.
 226  */
 227 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
 228                               unsigned int *res)
 229 {
 230         unsigned long timeout;
 231         unsigned long loopcounter;
 232
 233         timeout = jiffies + msecs_to_jiffies(1000);
 234
 235         for (loopcounter = 0;; loopcounter++) {
 236                 spin_lock_irq(&bus->reg_lock);
 237                 if (!bus->rirb.cmds[addr]) {
 238                         if (res)
 239                                 *res = bus->rirb.res[addr]; /* the last value */
 240                         spin_unlock_irq(&bus->reg_lock);
 241                         return 0;
 242                 }
 243                 spin_unlock_irq(&bus->reg_lock);
 244                 if (time_after(jiffies, timeout))
 245                         break;
 246                 if (loopcounter > 3000)
 247                         msleep(2); /* temporary workaround */
 248                 else {
 249                         udelay(10);
 250                         cond_resched();
 251                 }
 252         }
 253
 254         return -EIO;
 255 }
 256 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
 257
 258 #define HDAC_MAX_CAPS 10
 259 /**
 260  * snd_hdac_bus_parse_capabilities - parse capability structure
 261  * @bus: the pointer to bus object
 262  *
 263  * Returns 0 if successful, or a negative error code.
 264  */
 265 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
 266 {
 267         unsigned int cur_cap;
 268         unsigned int offset;
 269         unsigned int counter = 0;
 270
 271         offset = snd_hdac_chip_readl(bus, LLCH);
 272
 273         /* Lets walk the linked capabilities list */
 274         do {
 275                 cur_cap = _snd_hdac_chip_read(l, bus, offset);
 276
 277                 dev_dbg(bus->dev, "Capability version: 0x%x\n",
 278                         (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
 279
 280                 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
 281                         (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
 282
 283                 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
 284                 case AZX_ML_CAP_ID:
 285                         dev_dbg(bus->dev, "Found ML capability\n");
 286                         bus->mlcap = bus->remap_addr + offset;
 287                         break;
 288
 289                 case AZX_GTS_CAP_ID:
 290                         dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
 291                         bus->gtscap = bus->remap_addr + offset;
 292                         break;
 293
 294                 case AZX_PP_CAP_ID:
 295                         /* PP capability found, the Audio DSP is present */
 296                         dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
 297                         bus->ppcap = bus->remap_addr + offset;
 298                         break;
 299
 300                 case AZX_SPB_CAP_ID:
 301                         /* SPIB capability found, handler function */
 302                         dev_dbg(bus->dev, "Found SPB capability\n");
 303                         bus->spbcap = bus->remap_addr + offset;
 304                         break;
 305
 306                 case AZX_DRSM_CAP_ID:
 307                         /* DMA resume  capability found, handler function */
 308                         dev_dbg(bus->dev, "Found DRSM capability\n");
 309                         bus->drsmcap = bus->remap_addr + offset;
 310                         break;
 311
 312                 default:
 313                         dev_dbg(bus->dev, "Unknown capability %d\n", cur_cap);
 314                         break;
 315                 }
 316
 317                 counter++;
 318
 319                 if (counter > HDAC_MAX_CAPS) {
 320                         dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
 321                         break;
 322                 }
 323
 324                 /* read the offset of next capability */
 325                 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
 326
 327         } while (offset);
 328
 329         return 0;
 330 }
 331 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
 332
 333 /*
 334  * Lowlevel interface
 335  */
 336
 337 /**
 338  * snd_hdac_bus_enter_link_reset - enter link reset
 339  * @bus: HD-audio core bus
 340  *
 341  * Enter to the link reset state.
 342  */
 343 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
 344 {
 345         unsigned long timeout;
 346
 347         /* reset controller */
 348         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
 349
 350         timeout = jiffies + msecs_to_jiffies(100);
 351         while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
 352                time_before(jiffies, timeout))
 353                 usleep_range(500, 1000);
 354 }
 355 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
 356
 357 /**
 358  * snd_hdac_bus_exit_link_reset - exit link reset
 359  * @bus: HD-audio core bus
 360  *
 361  * Exit from the link reset state.
 362  */
 363 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
 364 {
 365         unsigned long timeout;
 366
 367         snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET);
 368
 369         timeout = jiffies + msecs_to_jiffies(100);
 370         while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
 371                 usleep_range(500, 1000);
 372 }
 373 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
 374
 375 /* reset codec link */
 376 static int azx_reset(struct hdac_bus *bus, bool full_reset)
 377 {
 378         if (!full_reset)
 379                 goto skip_reset;
 380
 381         /* clear STATESTS */
 382         snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
 383
 384         /* reset controller */
 385         snd_hdac_bus_enter_link_reset(bus);
 386
 387         /* delay for >= 100us for codec PLL to settle per spec
 388          * Rev 0.9 section 5.5.1
 389          */
 390         usleep_range(500, 1000);
 391
 392         /* Bring controller out of reset */
 393         snd_hdac_bus_exit_link_reset(bus);
 394
 395         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 396         usleep_range(1000, 1200);
 397
 398  skip_reset:
 399         /* check to see if controller is ready */
 400         if (!snd_hdac_chip_readb(bus, GCTL)) {
 401                 dev_dbg(bus->dev, "azx_reset: controller not ready!\n");
 402                 return -EBUSY;
 403         }
 404
 405         /* Accept unsolicited responses */
 406         snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL);
 407
 408         /* detect codecs */
 409         if (!bus->codec_mask) {
 410                 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
 411                 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
 412         }
 413
 414         return 0;
 415 }
 416
 417 /* enable interrupts */
 418 static void azx_int_enable(struct hdac_bus *bus)
 419 {
 420         /* enable controller CIE and GIE */
 421         snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
 422 }
 423
 424 /* disable interrupts */
 425 static void azx_int_disable(struct hdac_bus *bus)
 426 {
 427         struct hdac_stream *azx_dev;
 428
 429         /* disable interrupts in stream descriptor */
 430         list_for_each_entry(azx_dev, &bus->stream_list, list)
 431                 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
 432
 433         /* disable SIE for all streams */
 434         snd_hdac_chip_writeb(bus, INTCTL, 0);
 435
 436         /* disable controller CIE and GIE */
 437         snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
 438 }
 439
 440 /* clear interrupts */
 441 static void azx_int_clear(struct hdac_bus *bus)
 442 {
 443         struct hdac_stream *azx_dev;
 444
 445         /* clear stream status */
 446         list_for_each_entry(azx_dev, &bus->stream_list, list)
 447                 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
 448
 449         /* clear STATESTS */
 450         snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
 451
 452         /* clear rirb status */
 453         snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
 454
 455         /* clear int status */
 456         snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
 457 }
 458
 459 /**
 460  * snd_hdac_bus_init_chip - reset and start the controller registers
 461  * @bus: HD-audio core bus
 462  * @full_reset: Do full reset
 463  */
 464 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
 465 {
 466         if (bus->chip_init)
 467                 return false;
 468
 469         /* reset controller */
 470         azx_reset(bus, full_reset);
 471
 472         /* initialize interrupts */
 473         azx_int_clear(bus);
 474         azx_int_enable(bus);
 475
 476         /* initialize the codec command I/O */
 477         snd_hdac_bus_init_cmd_io(bus);
 478
 479         /* program the position buffer */
 480         if (bus->use_posbuf && bus->posbuf.addr) {
 481                 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
 482                 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
 483         }
 484
 485         bus->chip_init = true;
 486         return true;
 487 }
 488 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
 489
 490 /**
 491  * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
 492  * @bus: HD-audio core bus
 493  */
 494 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
 495 {
 496         if (!bus->chip_init)
 497                 return;
 498
 499         /* disable interrupts */
 500         azx_int_disable(bus);
 501         azx_int_clear(bus);
 502
 503         /* disable CORB/RIRB */
 504         snd_hdac_bus_stop_cmd_io(bus);
 505
 506         /* disable position buffer */
 507         if (bus->posbuf.addr) {
 508                 snd_hdac_chip_writel(bus, DPLBASE, 0);
 509                 snd_hdac_chip_writel(bus, DPUBASE, 0);
 510         }
 511
 512         bus->chip_init = false;
 513 }
 514 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
 515
 516 /**
 517  * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
 518  * @bus: HD-audio core bus
 519  * @status: INTSTS register value
 520  * @ask: callback to be called for woken streams
 521  *
 522  * Returns the bits of handled streams, or zero if no stream is handled.
 523  */
 524 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
 525                                     void (*ack)(struct hdac_bus *,
 526                                                 struct hdac_stream *))
 527 {
 528         struct hdac_stream *azx_dev;
 529         u8 sd_status;
 530         int handled = 0;
 531
 532         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 533                 if (status & azx_dev->sd_int_sta_mask) {
 534                         sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
 535                         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
 536                         handled |= 1 << azx_dev->index;
 537                         if (!azx_dev->substream || !azx_dev->running ||
 538                             !(sd_status & SD_INT_COMPLETE))
 539                                 continue;
 540                         if (ack)
 541                                 ack(bus, azx_dev);
 542                 }
 543         }
 544         return handled;
 545 }
 546 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
 547
 548 /**
 549  * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
 550  * @bus: HD-audio core bus
 551  *
 552  * Call this after assigning the all streams.
 553  * Returns zero for success, or a negative error code.
 554  */
 555 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
 556 {
 557         struct hdac_stream *s;
 558         int num_streams = 0;
 559         int err;
 560
 561         list_for_each_entry(s, &bus->stream_list, list) {
 562                 /* allocate memory for the BDL for each stream */
 563                 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
 564                                                    BDL_SIZE, &s->bdl);
 565                 num_streams++;
 566                 if (err < 0)
 567                         return -ENOMEM;
 568         }
 569
 570         if (WARN_ON(!num_streams))
 571                 return -EINVAL;
 572         /* allocate memory for the position buffer */
 573         err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
 574                                            num_streams * 8, &bus->posbuf);
 575         if (err < 0)
 576                 return -ENOMEM;
 577         list_for_each_entry(s, &bus->stream_list, list)
 578                 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
 579
 580         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 581         return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
 582                                             PAGE_SIZE, &bus->rb);
 583 }
 584 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
 585
 586 /**
 587  * snd_hdac_bus_free_stream_pages - release BDL and other buffers
 588  * @bus: HD-audio core bus
 589  */
 590 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
 591 {
 592         struct hdac_stream *s;
 593
 594         list_for_each_entry(s, &bus->stream_list, list) {
 595                 if (s->bdl.area)
 596                         bus->io_ops->dma_free_pages(bus, &s->bdl);
 597         }
 598
 599         if (bus->rb.area)
 600                 bus->io_ops->dma_free_pages(bus, &bus->rb);
 601         if (bus->posbuf.area)
 602                 bus->io_ops->dma_free_pages(bus, &bus->posbuf);
 603 }
 604 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);