sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #endif
  58 #include <sound/core.h>
  59 #include <sound/initval.h>
  60 #include <sound/hdaudio.h>
  61 #include <sound/hda_i915.h>
  62 #include <linux/vgaarb.h>
  63 #include <linux/vga_switcheroo.h>
  64 #include <linux/firmware.h>
  65 #include "hda_codec.h"
  66 #include "hda_controller.h"
  67 #include "hda_intel.h"
  68
  69 #define CREATE_TRACE_POINTS
  70 #include "hda_intel_trace.h"
  71
  72 /* position fix mode */
  73 enum {
  74         POS_FIX_AUTO,
  75         POS_FIX_LPIB,
  76         POS_FIX_POSBUF,
  77         POS_FIX_VIACOMBO,
  78         POS_FIX_COMBO,
  79 };
  80
  81 /* Defines for ATI HD Audio support in SB450 south bridge */
  82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  84
  85 /* Defines for Nvidia HDA support */
  86 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  87 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  88 #define NVIDIA_HDA_ISTRM_COH          0x4d
  89 #define NVIDIA_HDA_OSTRM_COH          0x4c
  90 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  91
  92 /* Defines for Intel SCH HDA snoop control */
  93 #define INTEL_HDA_CGCTL  0x48
  94 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  95 #define INTEL_SCH_HDA_DEVC      0x78
  96 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  97
  98 /* Define IN stream 0 FIFO size offset in VIA controller */
  99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 100 /* Define VIA HD Audio Device ID*/
 101 #define VIA_HDAC_DEVICE_ID              0x3288
 102
 103 /* max number of SDs */
 104 /* ICH, ATI and VIA have 4 playback and 4 capture */
 105 #define ICH6_NUM_CAPTURE        4
 106 #define ICH6_NUM_PLAYBACK       4
 107
 108 /* ULI has 6 playback and 5 capture */
 109 #define ULI_NUM_CAPTURE         5
 110 #define ULI_NUM_PLAYBACK        6
 111
 112 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 113 #define ATIHDMI_NUM_CAPTURE     0
 114 #define ATIHDMI_NUM_PLAYBACK    8
 115
 116 /* TERA has 4 playback and 3 capture */
 117 #define TERA_NUM_CAPTURE        3
 118 #define TERA_NUM_PLAYBACK       4
 119
 120
 121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 124 static char *model[SNDRV_CARDS];
 125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int probe_only[SNDRV_CARDS];
 129 static int jackpoll_ms[SNDRV_CARDS];
 130 static bool single_cmd;
 131 static int enable_msi = -1;
 132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 133 static char *patch[SNDRV_CARDS];
 134 #endif
 135 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 137                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 138 #endif
 139
 140 module_param_array(index, int, NULL, 0444);
 141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 142 module_param_array(id, charp, NULL, 0444);
 143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 144 module_param_array(enable, bool, NULL, 0444);
 145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 146 module_param_array(model, charp, NULL, 0444);
 147 MODULE_PARM_DESC(model, "Use the given board model.");
 148 module_param_array(position_fix, int, NULL, 0444);
 149 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 150                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 151 module_param_array(bdl_pos_adj, int, NULL, 0644);
 152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 153 module_param_array(probe_mask, int, NULL, 0444);
 154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 155 module_param_array(probe_only, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 157 module_param_array(jackpoll_ms, int, NULL, 0444);
 158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 159 module_param(single_cmd, bool, 0444);
 160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 161                  "(for debugging only).");
 162 module_param(enable_msi, bint, 0444);
 163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 165 module_param_array(patch, charp, NULL, 0444);
 166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 167 #endif
 168 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 169 module_param_array(beep_mode, bool, NULL, 0444);
 170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 171                             "(0=off, 1=on) (default=1).");
 172 #endif
 173
 174 #ifdef CONFIG_PM
 175 static int param_set_xint(const char *val, const struct kernel_param *kp);
 176 static const struct kernel_param_ops param_ops_xint = {
 177         .set = param_set_xint,
 178         .get = param_get_int,
 179 };
 180 #define param_check_xint param_check_int
 181
 182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 183 module_param(power_save, xint, 0644);
 184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 185                  "(in second, 0 = disable).");
 186
 187 /* reset the HD-audio controller in power save mode.
 188  * this may give more power-saving, but will take longer time to
 189  * wake up.
 190  */
 191 static bool power_save_controller = 1;
 192 module_param(power_save_controller, bool, 0644);
 193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 194 #else
 195 #define power_save      0
 196 #endif /* CONFIG_PM */
 197
 198 static int align_buffer_size = -1;
 199 module_param(align_buffer_size, bint, 0644);
 200 MODULE_PARM_DESC(align_buffer_size,
 201                 "Force buffer and period sizes to be multiple of 128 bytes.");
 202
 203 #ifdef CONFIG_X86
 204 static int hda_snoop = -1;
 205 module_param_named(snoop, hda_snoop, bint, 0444);
 206 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 207 #else
 208 #define hda_snoop               true
 209 #endif
 210
 211
 212 MODULE_LICENSE("GPL");
 213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 214                          "{Intel, ICH6M},"
 215                          "{Intel, ICH7},"
 216                          "{Intel, ESB2},"
 217                          "{Intel, ICH8},"
 218                          "{Intel, ICH9},"
 219                          "{Intel, ICH10},"
 220                          "{Intel, PCH},"
 221                          "{Intel, CPT},"
 222                          "{Intel, PPT},"
 223                          "{Intel, LPT},"
 224                          "{Intel, LPT_LP},"
 225                          "{Intel, WPT_LP},"
 226                          "{Intel, SPT},"
 227                          "{Intel, SPT_LP},"
 228                          "{Intel, HPT},"
 229                          "{Intel, PBG},"
 230                          "{Intel, SCH},"
 231                          "{ATI, SB450},"
 232                          "{ATI, SB600},"
 233                          "{ATI, RS600},"
 234                          "{ATI, RS690},"
 235                          "{ATI, RS780},"
 236                          "{ATI, R600},"
 237                          "{ATI, RV630},"
 238                          "{ATI, RV610},"
 239                          "{ATI, RV670},"
 240                          "{ATI, RV635},"
 241                          "{ATI, RV620},"
 242                          "{ATI, RV770},"
 243                          "{VIA, VT8251},"
 244                          "{VIA, VT8237A},"
 245                          "{SiS, SIS966},"
 246                          "{ULI, M5461}}");
 247 MODULE_DESCRIPTION("Intel HDA driver");
 248
 249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 251 #define SUPPORT_VGA_SWITCHEROO
 252 #endif
 253 #endif
 254
 255
 256 /*
 257  */
 258
 259 /* driver types */
 260 enum {
 261         AZX_DRIVER_ICH,
 262         AZX_DRIVER_PCH,
 263         AZX_DRIVER_SCH,
 264         AZX_DRIVER_HDMI,
 265         AZX_DRIVER_ATI,
 266         AZX_DRIVER_ATIHDMI,
 267         AZX_DRIVER_ATIHDMI_NS,
 268         AZX_DRIVER_VIA,
 269         AZX_DRIVER_SIS,
 270         AZX_DRIVER_ULI,
 271         AZX_DRIVER_NVIDIA,
 272         AZX_DRIVER_TERA,
 273         AZX_DRIVER_CTX,
 274         AZX_DRIVER_CTHDA,
 275         AZX_DRIVER_CMEDIA,
 276         AZX_DRIVER_GENERIC,
 277         AZX_NUM_DRIVERS, /* keep this as last entry */
 278 };
 279
 280 #define azx_get_snoop_type(chip) \
 281         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 283
 284 /* quirks for old Intel chipsets */
 285 #define AZX_DCAPS_INTEL_ICH \
 286         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 287
 288 /* quirks for Intel PCH */
 289 #define AZX_DCAPS_INTEL_PCH_BASE \
 290         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 291          AZX_DCAPS_SNOOP_TYPE(SCH))
 292
 293 /* PCH up to IVB; no runtime PM */
 294 #define AZX_DCAPS_INTEL_PCH_NOPM \
 295         (AZX_DCAPS_INTEL_PCH_BASE)
 296
 297 /* PCH for HSW/BDW; with runtime PM */
 298 #define AZX_DCAPS_INTEL_PCH \
 299         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 300
 301 /* HSW HDMI */
 302 #define AZX_DCAPS_INTEL_HASWELL \
 303         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 304          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 305          AZX_DCAPS_SNOOP_TYPE(SCH))
 306
 307 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 308 #define AZX_DCAPS_INTEL_BROADWELL \
 309         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 310          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 311          AZX_DCAPS_SNOOP_TYPE(SCH))
 312
 313 #define AZX_DCAPS_INTEL_BAYTRAIL \
 314         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 315
 316 #define AZX_DCAPS_INTEL_BRASWELL \
 317         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 318
 319 #define AZX_DCAPS_INTEL_SKYLAKE \
 320         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 321          AZX_DCAPS_I915_POWERWELL)
 322
 323 #define AZX_DCAPS_INTEL_BROXTON \
 324         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 325          AZX_DCAPS_I915_POWERWELL)
 326
 327 /* quirks for ATI SB / AMD Hudson */
 328 #define AZX_DCAPS_PRESET_ATI_SB \
 329         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 330          AZX_DCAPS_SNOOP_TYPE(ATI))
 331
 332 /* quirks for ATI/AMD HDMI */
 333 #define AZX_DCAPS_PRESET_ATI_HDMI \
 334         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 335          AZX_DCAPS_NO_MSI64)
 336
 337 /* quirks for ATI HDMI with snoop off */
 338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 339         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 340
 341 /* quirks for Nvidia */
 342 #define AZX_DCAPS_PRESET_NVIDIA \
 343         (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
 344          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 345          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 346
 347 #define AZX_DCAPS_PRESET_CTHDA \
 348         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 349          AZX_DCAPS_NO_64BIT |\
 350          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 351
 352 /*
 353  * vga_switcheroo support
 354  */
 355 #ifdef SUPPORT_VGA_SWITCHEROO
 356 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 357 #else
 358 #define use_vga_switcheroo(chip)        0
 359 #endif
 360
 361 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 362                                         ((pci)->device == 0x0c0c) || \
 363                                         ((pci)->device == 0x0d0c) || \
 364                                         ((pci)->device == 0x160c))
 365
 366 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
 367 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
 368 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
 369 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
 370 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 371 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
 372                         IS_KBL(pci) || IS_KBL_LP(pci)
 373
 374 static char *driver_short_names[] = {
 375         [AZX_DRIVER_ICH] = "HDA Intel",
 376         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 377         [AZX_DRIVER_SCH] = "HDA Intel MID",
 378         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 379         [AZX_DRIVER_ATI] = "HDA ATI SB",
 380         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 381         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 382         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 383         [AZX_DRIVER_SIS] = "HDA SIS966",
 384         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 385         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 386         [AZX_DRIVER_TERA] = "HDA Teradici",
 387         [AZX_DRIVER_CTX] = "HDA Creative",
 388         [AZX_DRIVER_CTHDA] = "HDA Creative",
 389         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 390         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 391 };
 392
 393 #ifdef CONFIG_X86
 394 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 395 {
 396         int pages;
 397
 398         if (azx_snoop(chip))
 399                 return;
 400         if (!dmab || !dmab->area || !dmab->bytes)
 401                 return;
 402
 403 #ifdef CONFIG_SND_DMA_SGBUF
 404         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 405                 struct snd_sg_buf *sgbuf = dmab->private_data;
 406                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 407                         return; /* deal with only CORB/RIRB buffers */
 408                 if (on)
 409                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 410                 else
 411                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 412                 return;
 413         }
 414 #endif
 415
 416         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 417         if (on)
 418                 set_memory_wc((unsigned long)dmab->area, pages);
 419         else
 420                 set_memory_wb((unsigned long)dmab->area, pages);
 421 }
 422
 423 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 424                                  bool on)
 425 {
 426         __mark_pages_wc(chip, buf, on);
 427 }
 428 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 429                                    struct snd_pcm_substream *substream, bool on)
 430 {
 431         if (azx_dev->wc_marked != on) {
 432                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 433                 azx_dev->wc_marked = on;
 434         }
 435 }
 436 #else
 437 /* NOP for other archs */
 438 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 439                                  bool on)
 440 {
 441 }
 442 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 443                                    struct snd_pcm_substream *substream, bool on)
 444 {
 445 }
 446 #endif
 447
 448 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 449
 450 /*
 451  * initialize the PCI registers
 452  */
 453 /* update bits in a PCI register byte */
 454 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 455                             unsigned char mask, unsigned char val)
 456 {
 457         unsigned char data;
 458
 459         pci_read_config_byte(pci, reg, &data);
 460         data &= ~mask;
 461         data |= (val & mask);
 462         pci_write_config_byte(pci, reg, data);
 463 }
 464
 465 static void azx_init_pci(struct azx *chip)
 466 {
 467         int snoop_type = azx_get_snoop_type(chip);
 468
 469         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 470          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 471          * Ensuring these bits are 0 clears playback static on some HD Audio
 472          * codecs.
 473          * The PCI register TCSEL is defined in the Intel manuals.
 474          */
 475         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 476                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 477                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 478         }
 479
 480         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 481          * we need to enable snoop.
 482          */
 483         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 484                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 485                         azx_snoop(chip));
 486                 update_pci_byte(chip->pci,
 487                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 488                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 489         }
 490
 491         /* For NVIDIA HDA, enable snoop */
 492         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 493                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 494                         azx_snoop(chip));
 495                 update_pci_byte(chip->pci,
 496                                 NVIDIA_HDA_TRANSREG_ADDR,
 497                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 498                 update_pci_byte(chip->pci,
 499                                 NVIDIA_HDA_ISTRM_COH,
 500                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 501                 update_pci_byte(chip->pci,
 502                                 NVIDIA_HDA_OSTRM_COH,
 503                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 504         }
 505
 506         /* Enable SCH/PCH snoop if needed */
 507         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 508                 unsigned short snoop;
 509                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 510                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 511                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 512                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 513                         if (!azx_snoop(chip))
 514                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 515                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 516                         pci_read_config_word(chip->pci,
 517                                 INTEL_SCH_HDA_DEVC, &snoop);
 518                 }
 519                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 520                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 521                         "Disabled" : "Enabled");
 522         }
 523 }
 524
 525 /*
 526  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 527  * and makes an audio stream sensitive to system latencies when
 528  * 24/32 bits are playing.
 529  * Adjusting threshold of DMA fifo to force the DMA request
 530  * sooner to improve latency tolerance at the expense of power.
 531  */
 532 static void bxt_reduce_dma_latency(struct azx *chip)
 533 {
 534         u32 val;
 535
 536         val = azx_readl(chip, SKL_EM4L);
 537         val &= (0x3 << 20);
 538         azx_writel(chip, SKL_EM4L, val);
 539 }
 540
 541 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 542 {
 543         struct hdac_bus *bus = azx_bus(chip);
 544         struct pci_dev *pci = chip->pci;
 545         u32 val;
 546
 547         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 548                 snd_hdac_set_codec_wakeup(bus, true);
 549         if (IS_SKL_PLUS(pci)) {
 550                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 551                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 552                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 553         }
 554         azx_init_chip(chip, full_reset);
 555         if (IS_SKL_PLUS(pci)) {
 556                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 557                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 558                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 559         }
 560         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 561                 snd_hdac_set_codec_wakeup(bus, false);
 562
 563         /* reduce dma latency to avoid noise */
 564         if (IS_BXT(pci))
 565                 bxt_reduce_dma_latency(chip);
 566 }
 567
 568 /* calculate runtime delay from LPIB */
 569 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 570                                    unsigned int pos)
 571 {
 572         struct snd_pcm_substream *substream = azx_dev->core.substream;
 573         int stream = substream->stream;
 574         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 575         int delay;
 576
 577         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 578                 delay = pos - lpib_pos;
 579         else
 580                 delay = lpib_pos - pos;
 581         if (delay < 0) {
 582                 if (delay >= azx_dev->core.delay_negative_threshold)
 583                         delay = 0;
 584                 else
 585                         delay += azx_dev->core.bufsize;
 586         }
 587
 588         if (delay >= azx_dev->core.period_bytes) {
 589                 dev_info(chip->card->dev,
 590                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 591                          delay, azx_dev->core.period_bytes);
 592                 delay = 0;
 593                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 594                 chip->get_delay[stream] = NULL;
 595         }
 596
 597         return bytes_to_frames(substream->runtime, delay);
 598 }
 599
 600 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 601
 602 /* called from IRQ */
 603 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 604 {
 605         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 606         int ok;
 607
 608         ok = azx_position_ok(chip, azx_dev);
 609         if (ok == 1) {
 610                 azx_dev->irq_pending = 0;
 611                 return ok;
 612         } else if (ok == 0) {
 613                 /* bogus IRQ, process it later */
 614                 azx_dev->irq_pending = 1;
 615                 schedule_work(&hda->irq_pending_work);
 616         }
 617         return 0;
 618 }
 619
 620 /* Enable/disable i915 display power for the link */
 621 static int azx_intel_link_power(struct azx *chip, bool enable)
 622 {
 623         struct hdac_bus *bus = azx_bus(chip);
 624
 625         return snd_hdac_display_power(bus, enable);
 626 }
 627
 628 /*
 629  * Check whether the current DMA position is acceptable for updating
 630  * periods.  Returns non-zero if it's OK.
 631  *
 632  * Many HD-audio controllers appear pretty inaccurate about
 633  * the update-IRQ timing.  The IRQ is issued before actually the
 634  * data is processed.  So, we need to process it afterwords in a
 635  * workqueue.
 636  */
 637 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 638 {
 639         struct snd_pcm_substream *substream = azx_dev->core.substream;
 640         int stream = substream->stream;
 641         u32 wallclk;
 642         unsigned int pos;
 643
 644         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 645         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 646                 return -1;      /* bogus (too early) interrupt */
 647
 648         if (chip->get_position[stream])
 649                 pos = chip->get_position[stream](chip, azx_dev);
 650         else { /* use the position buffer as default */
 651                 pos = azx_get_pos_posbuf(chip, azx_dev);
 652                 if (!pos || pos == (u32)-1) {
 653                         dev_info(chip->card->dev,
 654                                  "Invalid position buffer, using LPIB read method instead.\n");
 655                         chip->get_position[stream] = azx_get_pos_lpib;
 656                         if (chip->get_position[0] == azx_get_pos_lpib &&
 657                             chip->get_position[1] == azx_get_pos_lpib)
 658                                 azx_bus(chip)->use_posbuf = false;
 659                         pos = azx_get_pos_lpib(chip, azx_dev);
 660                         chip->get_delay[stream] = NULL;
 661                 } else {
 662                         chip->get_position[stream] = azx_get_pos_posbuf;
 663                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 664                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 665                 }
 666         }
 667
 668         if (pos >= azx_dev->core.bufsize)
 669                 pos = 0;
 670
 671         if (WARN_ONCE(!azx_dev->core.period_bytes,
 672                       "hda-intel: zero azx_dev->period_bytes"))
 673                 return -1; /* this shouldn't happen! */
 674         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 675             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 676                 /* NG - it's below the first next period boundary */
 677                 return chip->bdl_pos_adj ? 0 : -1;
 678         azx_dev->core.start_wallclk += wallclk;
 679         return 1; /* OK, it's fine */
 680 }
 681
 682 /*
 683  * The work for pending PCM period updates.
 684  */
 685 static void azx_irq_pending_work(struct work_struct *work)
 686 {
 687         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 688         struct azx *chip = &hda->chip;
 689         struct hdac_bus *bus = azx_bus(chip);
 690         struct hdac_stream *s;
 691         int pending, ok;
 692
 693         if (!hda->irq_pending_warned) {
 694                 dev_info(chip->card->dev,
 695                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 696                          chip->card->number);
 697                 hda->irq_pending_warned = 1;
 698         }
 699
 700         for (;;) {
 701                 pending = 0;
 702                 spin_lock_irq(&bus->reg_lock);
 703                 list_for_each_entry(s, &bus->stream_list, list) {
 704                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 705                         if (!azx_dev->irq_pending ||
 706                             !s->substream ||
 707                             !s->running)
 708                                 continue;
 709                         ok = azx_position_ok(chip, azx_dev);
 710                         if (ok > 0) {
 711                                 azx_dev->irq_pending = 0;
 712                                 spin_unlock(&bus->reg_lock);
 713                                 snd_pcm_period_elapsed(s->substream);
 714                                 spin_lock(&bus->reg_lock);
 715                         } else if (ok < 0) {
 716                                 pending = 0;    /* too early */
 717                         } else
 718                                 pending++;
 719                 }
 720                 spin_unlock_irq(&bus->reg_lock);
 721                 if (!pending)
 722                         return;
 723                 msleep(1);
 724         }
 725 }
 726
 727 /* clear irq_pending flags and assure no on-going workq */
 728 static void azx_clear_irq_pending(struct azx *chip)
 729 {
 730         struct hdac_bus *bus = azx_bus(chip);
 731         struct hdac_stream *s;
 732
 733         spin_lock_irq(&bus->reg_lock);
 734         list_for_each_entry(s, &bus->stream_list, list) {
 735                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 736                 azx_dev->irq_pending = 0;
 737         }
 738         spin_unlock_irq(&bus->reg_lock);
 739 }
 740
 741 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 742 {
 743         struct hdac_bus *bus = azx_bus(chip);
 744
 745         if (request_irq(chip->pci->irq, azx_interrupt,
 746                         chip->msi ? 0 : IRQF_SHARED,
 747                         chip->card->irq_descr, chip)) {
 748                 dev_err(chip->card->dev,
 749                         "unable to grab IRQ %d, disabling device\n",
 750                         chip->pci->irq);
 751                 if (do_disconnect)
 752                         snd_card_disconnect(chip->card);
 753                 return -1;
 754         }
 755         bus->irq = chip->pci->irq;
 756         pci_intx(chip->pci, !chip->msi);
 757         return 0;
 758 }
 759
 760 /* get the current DMA position with correction on VIA chips */
 761 static unsigned int azx_via_get_position(struct azx *chip,
 762                                          struct azx_dev *azx_dev)
 763 {
 764         unsigned int link_pos, mini_pos, bound_pos;
 765         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 766         unsigned int fifo_size;
 767
 768         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 769         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 770                 /* Playback, no problem using link position */
 771                 return link_pos;
 772         }
 773
 774         /* Capture */
 775         /* For new chipset,
 776          * use mod to get the DMA position just like old chipset
 777          */
 778         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 779         mod_dma_pos %= azx_dev->core.period_bytes;
 780
 781         /* azx_dev->fifo_size can't get FIFO size of in stream.
 782          * Get from base address + offset.
 783          */
 784         fifo_size = readw(azx_bus(chip)->remap_addr +
 785                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 786
 787         if (azx_dev->insufficient) {
 788                 /* Link position never gather than FIFO size */
 789                 if (link_pos <= fifo_size)
 790                         return 0;
 791
 792                 azx_dev->insufficient = 0;
 793         }
 794
 795         if (link_pos <= fifo_size)
 796                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 797         else
 798                 mini_pos = link_pos - fifo_size;
 799
 800         /* Find nearest previous boudary */
 801         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 802         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 803         if (mod_link_pos >= fifo_size)
 804                 bound_pos = link_pos - mod_link_pos;
 805         else if (mod_dma_pos >= mod_mini_pos)
 806                 bound_pos = mini_pos - mod_mini_pos;
 807         else {
 808                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 809                 if (bound_pos >= azx_dev->core.bufsize)
 810                         bound_pos = 0;
 811         }
 812
 813         /* Calculate real DMA position we want */
 814         return bound_pos + mod_dma_pos;
 815 }
 816
 817 #ifdef CONFIG_PM
 818 static DEFINE_MUTEX(card_list_lock);
 819 static LIST_HEAD(card_list);
 820
 821 static void azx_add_card_list(struct azx *chip)
 822 {
 823         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 824         mutex_lock(&card_list_lock);
 825         list_add(&hda->list, &card_list);
 826         mutex_unlock(&card_list_lock);
 827 }
 828
 829 static void azx_del_card_list(struct azx *chip)
 830 {
 831         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 832         mutex_lock(&card_list_lock);
 833         list_del_init(&hda->list);
 834         mutex_unlock(&card_list_lock);
 835 }
 836
 837 /* trigger power-save check at writing parameter */
 838 static int param_set_xint(const char *val, const struct kernel_param *kp)
 839 {
 840         struct hda_intel *hda;
 841         struct azx *chip;
 842         int prev = power_save;
 843         int ret = param_set_int(val, kp);
 844
 845         if (ret || prev == power_save)
 846                 return ret;
 847
 848         mutex_lock(&card_list_lock);
 849         list_for_each_entry(hda, &card_list, list) {
 850                 chip = &hda->chip;
 851                 if (!hda->probe_continued || chip->disabled)
 852                         continue;
 853                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 854         }
 855         mutex_unlock(&card_list_lock);
 856         return 0;
 857 }
 858 #else
 859 #define azx_add_card_list(chip) /* NOP */
 860 #define azx_del_card_list(chip) /* NOP */
 861 #endif /* CONFIG_PM */
 862
 863 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 864 /*
 865  * power management
 866  */
 867 static int azx_suspend(struct device *dev)
 868 {
 869         struct snd_card *card = dev_get_drvdata(dev);
 870         struct azx *chip;
 871         struct hda_intel *hda;
 872         struct hdac_bus *bus;
 873
 874         if (!card)
 875                 return 0;
 876
 877         chip = card->private_data;
 878         hda = container_of(chip, struct hda_intel, chip);
 879         if (chip->disabled || hda->init_failed || !chip->running)
 880                 return 0;
 881
 882         bus = azx_bus(chip);
 883         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 884         azx_clear_irq_pending(chip);
 885         azx_stop_chip(chip);
 886         azx_enter_link_reset(chip);
 887         if (bus->irq >= 0) {
 888                 free_irq(bus->irq, chip);
 889                 bus->irq = -1;
 890         }
 891
 892         if (chip->msi)
 893                 pci_disable_msi(chip->pci);
 894         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 895                 && hda->need_i915_power)
 896                 snd_hdac_display_power(bus, false);
 897
 898         trace_azx_suspend(chip);
 899         return 0;
 900 }
 901
 902 static int azx_resume(struct device *dev)
 903 {
 904         struct pci_dev *pci = to_pci_dev(dev);
 905         struct snd_card *card = dev_get_drvdata(dev);
 906         struct azx *chip;
 907         struct hda_intel *hda;
 908
 909         if (!card)
 910                 return 0;
 911
 912         chip = card->private_data;
 913         hda = container_of(chip, struct hda_intel, chip);
 914         if (chip->disabled || hda->init_failed || !chip->running)
 915                 return 0;
 916
 917         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 918                 && hda->need_i915_power) {
 919                 snd_hdac_display_power(azx_bus(chip), true);
 920                 snd_hdac_i915_set_bclk(azx_bus(chip));
 921         }
 922         if (chip->msi)
 923                 if (pci_enable_msi(pci) < 0)
 924                         chip->msi = 0;
 925         if (azx_acquire_irq(chip, 1) < 0)
 926                 return -EIO;
 927         azx_init_pci(chip);
 928
 929         hda_intel_init_chip(chip, true);
 930
 931         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 932
 933         trace_azx_resume(chip);
 934         return 0;
 935 }
 936 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 937
 938 #ifdef CONFIG_PM_SLEEP
 939 /* put codec down to D3 at hibernation for Intel SKL+;
 940  * otherwise BIOS may still access the codec and screw up the driver
 941  */
 942 static int azx_freeze_noirq(struct device *dev)
 943 {
 944         struct pci_dev *pci = to_pci_dev(dev);
 945
 946         if (IS_SKL_PLUS(pci))
 947                 pci_set_power_state(pci, PCI_D3hot);
 948
 949         return 0;
 950 }
 951
 952 static int azx_thaw_noirq(struct device *dev)
 953 {
 954         struct pci_dev *pci = to_pci_dev(dev);
 955
 956         if (IS_SKL_PLUS(pci))
 957                 pci_set_power_state(pci, PCI_D0);
 958
 959         return 0;
 960 }
 961 #endif /* CONFIG_PM_SLEEP */
 962
 963 #ifdef CONFIG_PM
 964 static int azx_runtime_suspend(struct device *dev)
 965 {
 966         struct snd_card *card = dev_get_drvdata(dev);
 967         struct azx *chip;
 968         struct hda_intel *hda;
 969
 970         if (!card)
 971                 return 0;
 972
 973         chip = card->private_data;
 974         hda = container_of(chip, struct hda_intel, chip);
 975         if (chip->disabled || hda->init_failed)
 976                 return 0;
 977
 978         if (!azx_has_pm_runtime(chip))
 979                 return 0;
 980
 981         /* enable controller wake up event */
 982         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
 983                   STATESTS_INT_MASK);
 984
 985         azx_stop_chip(chip);
 986         azx_enter_link_reset(chip);
 987         azx_clear_irq_pending(chip);
 988         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 989                 && hda->need_i915_power)
 990                 snd_hdac_display_power(azx_bus(chip), false);
 991
 992         trace_azx_runtime_suspend(chip);
 993         return 0;
 994 }
 995
 996 static int azx_runtime_resume(struct device *dev)
 997 {
 998         struct snd_card *card = dev_get_drvdata(dev);
 999         struct azx *chip;
1000         struct hda_intel *hda;
1001         struct hdac_bus *bus;
1002         struct hda_codec *codec;
1003         int status;
1004
1005         if (!card)
1006                 return 0;
1007
1008         chip = card->private_data;
1009         hda = container_of(chip, struct hda_intel, chip);
1010         if (chip->disabled || hda->init_failed)
1011                 return 0;
1012
1013         if (!azx_has_pm_runtime(chip))
1014                 return 0;
1015
1016         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1017                 bus = azx_bus(chip);
1018                 if (hda->need_i915_power) {
1019                         snd_hdac_display_power(bus, true);
1020                         snd_hdac_i915_set_bclk(bus);
1021                 } else {
1022                         /* toggle codec wakeup bit for STATESTS read */
1023                         snd_hdac_set_codec_wakeup(bus, true);
1024                         snd_hdac_set_codec_wakeup(bus, false);
1025                 }
1026         }
1027
1028         /* Read STATESTS before controller reset */
1029         status = azx_readw(chip, STATESTS);
1030
1031         azx_init_pci(chip);
1032         hda_intel_init_chip(chip, true);
1033
1034         if (status) {
1035                 list_for_each_codec(codec, &chip->bus)
1036                         if (status & (1 << codec->addr))
1037                                 schedule_delayed_work(&codec->jackpoll_work,
1038                                                       codec->jackpoll_interval);
1039         }
1040
1041         /* disable controller Wake Up event*/
1042         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1043                         ~STATESTS_INT_MASK);
1044
1045         trace_azx_runtime_resume(chip);
1046         return 0;
1047 }
1048
1049 static int azx_runtime_idle(struct device *dev)
1050 {
1051         struct snd_card *card = dev_get_drvdata(dev);
1052         struct azx *chip;
1053         struct hda_intel *hda;
1054
1055         if (!card)
1056                 return 0;
1057
1058         chip = card->private_data;
1059         hda = container_of(chip, struct hda_intel, chip);
1060         if (chip->disabled || hda->init_failed)
1061                 return 0;
1062
1063         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1064             azx_bus(chip)->codec_powered || !chip->running)
1065                 return -EBUSY;
1066
1067         return 0;
1068 }
1069
1070 static const struct dev_pm_ops azx_pm = {
1071         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1072 #ifdef CONFIG_PM_SLEEP
1073         .freeze_noirq = azx_freeze_noirq,
1074         .thaw_noirq = azx_thaw_noirq,
1075 #endif
1076         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1077 };
1078
1079 #define AZX_PM_OPS      &azx_pm
1080 #else
1081 #define AZX_PM_OPS      NULL
1082 #endif /* CONFIG_PM */
1083
1084
1085 static int azx_probe_continue(struct azx *chip);
1086
1087 #ifdef SUPPORT_VGA_SWITCHEROO
1088 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1089
1090 static void azx_vs_set_state(struct pci_dev *pci,
1091                              enum vga_switcheroo_state state)
1092 {
1093         struct snd_card *card = pci_get_drvdata(pci);
1094         struct azx *chip = card->private_data;
1095         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1096         bool disabled;
1097
1098         wait_for_completion(&hda->probe_wait);
1099         if (hda->init_failed)
1100                 return;
1101
1102         disabled = (state == VGA_SWITCHEROO_OFF);
1103         if (chip->disabled == disabled)
1104                 return;
1105
1106         if (!hda->probe_continued) {
1107                 chip->disabled = disabled;
1108                 if (!disabled) {
1109                         dev_info(chip->card->dev,
1110                                  "Start delayed initialization\n");
1111                         if (azx_probe_continue(chip) < 0) {
1112                                 dev_err(chip->card->dev, "initialization error\n");
1113                                 hda->init_failed = true;
1114                         }
1115                 }
1116         } else {
1117                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1118                          disabled ? "Disabling" : "Enabling");
1119                 if (disabled) {
1120                         pm_runtime_put_sync_suspend(card->dev);
1121                         azx_suspend(card->dev);
1122                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1123                          * however we have no ACPI handle, so pci/acpi can't put us there,
1124                          * put ourselves there */
1125                         pci->current_state = PCI_D3cold;
1126                         chip->disabled = true;
1127                         if (snd_hda_lock_devices(&chip->bus))
1128                                 dev_warn(chip->card->dev,
1129                                          "Cannot lock devices!\n");
1130                 } else {
1131                         snd_hda_unlock_devices(&chip->bus);
1132                         pm_runtime_get_noresume(card->dev);
1133                         chip->disabled = false;
1134                         azx_resume(card->dev);
1135                 }
1136         }
1137 }
1138
1139 static bool azx_vs_can_switch(struct pci_dev *pci)
1140 {
1141         struct snd_card *card = pci_get_drvdata(pci);
1142         struct azx *chip = card->private_data;
1143         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1144
1145         wait_for_completion(&hda->probe_wait);
1146         if (hda->init_failed)
1147                 return false;
1148         if (chip->disabled || !hda->probe_continued)
1149                 return true;
1150         if (snd_hda_lock_devices(&chip->bus))
1151                 return false;
1152         snd_hda_unlock_devices(&chip->bus);
1153         return true;
1154 }
1155
1156 static void init_vga_switcheroo(struct azx *chip)
1157 {
1158         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1159         struct pci_dev *p = get_bound_vga(chip->pci);
1160         if (p) {
1161                 dev_info(chip->card->dev,
1162                          "Handle vga_switcheroo audio client\n");
1163                 hda->use_vga_switcheroo = 1;
1164                 pci_dev_put(p);
1165         }
1166 }
1167
1168 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1169         .set_gpu_state = azx_vs_set_state,
1170         .can_switch = azx_vs_can_switch,
1171 };
1172
1173 static int register_vga_switcheroo(struct azx *chip)
1174 {
1175         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1176         int err;
1177
1178         if (!hda->use_vga_switcheroo)
1179                 return 0;
1180         /* FIXME: currently only handling DIS controller
1181          * is there any machine with two switchable HDMI audio controllers?
1182          */
1183         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1184                                                    VGA_SWITCHEROO_DIS);
1185         if (err < 0)
1186                 return err;
1187         hda->vga_switcheroo_registered = 1;
1188
1189         /* register as an optimus hdmi audio power domain */
1190         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1191                                                          &hda->hdmi_pm_domain);
1192         return 0;
1193 }
1194 #else
1195 #define init_vga_switcheroo(chip)               /* NOP */
1196 #define register_vga_switcheroo(chip)           0
1197 #define check_hdmi_disabled(pci)        false
1198 #endif /* SUPPORT_VGA_SWITCHER */
1199
1200 /*
1201  * destructor
1202  */
1203 static int azx_free(struct azx *chip)
1204 {
1205         struct pci_dev *pci = chip->pci;
1206         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1207         struct hdac_bus *bus = azx_bus(chip);
1208
1209         if (azx_has_pm_runtime(chip) && chip->running)
1210                 pm_runtime_get_noresume(&pci->dev);
1211
1212         azx_del_card_list(chip);
1213
1214         hda->init_failed = 1; /* to be sure */
1215         complete_all(&hda->probe_wait);
1216
1217         if (use_vga_switcheroo(hda)) {
1218                 if (chip->disabled && hda->probe_continued)
1219                         snd_hda_unlock_devices(&chip->bus);
1220                 if (hda->vga_switcheroo_registered)
1221                         vga_switcheroo_unregister_client(chip->pci);
1222         }
1223
1224         if (bus->chip_init) {
1225                 azx_clear_irq_pending(chip);
1226                 azx_stop_all_streams(chip);
1227                 azx_stop_chip(chip);
1228         }
1229
1230         if (bus->irq >= 0)
1231                 free_irq(bus->irq, (void*)chip);
1232         if (chip->msi)
1233                 pci_disable_msi(chip->pci);
1234         iounmap(bus->remap_addr);
1235
1236         azx_free_stream_pages(chip);
1237         azx_free_streams(chip);
1238         snd_hdac_bus_exit(bus);
1239
1240         if (chip->region_requested)
1241                 pci_release_regions(chip->pci);
1242
1243         pci_disable_device(chip->pci);
1244 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1245         release_firmware(chip->fw);
1246 #endif
1247
1248         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1249                 if (hda->need_i915_power)
1250                         snd_hdac_display_power(bus, false);
1251                 snd_hdac_i915_exit(bus);
1252         }
1253         kfree(hda);
1254
1255         return 0;
1256 }
1257
1258 static int azx_dev_disconnect(struct snd_device *device)
1259 {
1260         struct azx *chip = device->device_data;
1261
1262         chip->bus.shutdown = 1;
1263         return 0;
1264 }
1265
1266 static int azx_dev_free(struct snd_device *device)
1267 {
1268         return azx_free(device->device_data);
1269 }
1270
1271 #ifdef SUPPORT_VGA_SWITCHEROO
1272 /*
1273  * Check of disabled HDMI controller by vga_switcheroo
1274  */
1275 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1276 {
1277         struct pci_dev *p;
1278
1279         /* check only discrete GPU */
1280         switch (pci->vendor) {
1281         case PCI_VENDOR_ID_ATI:
1282         case PCI_VENDOR_ID_AMD:
1283         case PCI_VENDOR_ID_NVIDIA:
1284                 if (pci->devfn == 1) {
1285                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1286                                                         pci->bus->number, 0);
1287                         if (p) {
1288                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1289                                         return p;
1290                                 pci_dev_put(p);
1291                         }
1292                 }
1293                 break;
1294         }
1295         return NULL;
1296 }
1297
1298 static bool check_hdmi_disabled(struct pci_dev *pci)
1299 {
1300         bool vga_inactive = false;
1301         struct pci_dev *p = get_bound_vga(pci);
1302
1303         if (p) {
1304                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1305                         vga_inactive = true;
1306                 pci_dev_put(p);
1307         }
1308         return vga_inactive;
1309 }
1310 #endif /* SUPPORT_VGA_SWITCHEROO */
1311
1312 /*
1313  * white/black-listing for position_fix
1314  */
1315 static struct snd_pci_quirk position_fix_list[] = {
1316         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1317         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1318         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1319         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1320         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1321         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1322         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1323         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1324         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1325         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1326         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1327         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1328         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1329         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1330         {}
1331 };
1332
1333 static int check_position_fix(struct azx *chip, int fix)
1334 {
1335         const struct snd_pci_quirk *q;
1336
1337         switch (fix) {
1338         case POS_FIX_AUTO:
1339         case POS_FIX_LPIB:
1340         case POS_FIX_POSBUF:
1341         case POS_FIX_VIACOMBO:
1342         case POS_FIX_COMBO:
1343                 return fix;
1344         }
1345
1346         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1347         if (q) {
1348                 dev_info(chip->card->dev,
1349                          "position_fix set to %d for device %04x:%04x\n",
1350                          q->value, q->subvendor, q->subdevice);
1351                 return q->value;
1352         }
1353
1354         /* Check VIA/ATI HD Audio Controller exist */
1355         if (chip->driver_type == AZX_DRIVER_VIA) {
1356                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1357                 return POS_FIX_VIACOMBO;
1358         }
1359         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1360                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1361                 return POS_FIX_LPIB;
1362         }
1363         return POS_FIX_AUTO;
1364 }
1365
1366 static void assign_position_fix(struct azx *chip, int fix)
1367 {
1368         static azx_get_pos_callback_t callbacks[] = {
1369                 [POS_FIX_AUTO] = NULL,
1370                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1371                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1372                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1373                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1374         };
1375
1376         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1377
1378         /* combo mode uses LPIB only for playback */
1379         if (fix == POS_FIX_COMBO)
1380                 chip->get_position[1] = NULL;
1381
1382         if (fix == POS_FIX_POSBUF &&
1383             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1384                 chip->get_delay[0] = chip->get_delay[1] =
1385                         azx_get_delay_from_lpib;
1386         }
1387
1388 }
1389
1390 /*
1391  * black-lists for probe_mask
1392  */
1393 static struct snd_pci_quirk probe_mask_list[] = {
1394         /* Thinkpad often breaks the controller communication when accessing
1395          * to the non-working (or non-existing) modem codec slot.
1396          */
1397         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1398         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1399         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1400         /* broken BIOS */
1401         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1402         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1403         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1404         /* forced codec slots */
1405         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1406         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1407         /* WinFast VP200 H (Teradici) user reported broken communication */
1408         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1409         {}
1410 };
1411
1412 #define AZX_FORCE_CODEC_MASK    0x100
1413
1414 static void check_probe_mask(struct azx *chip, int dev)
1415 {
1416         const struct snd_pci_quirk *q;
1417
1418         chip->codec_probe_mask = probe_mask[dev];
1419         if (chip->codec_probe_mask == -1) {
1420                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1421                 if (q) {
1422                         dev_info(chip->card->dev,
1423                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1424                                  q->value, q->subvendor, q->subdevice);
1425                         chip->codec_probe_mask = q->value;
1426                 }
1427         }
1428
1429         /* check forced option */
1430         if (chip->codec_probe_mask != -1 &&
1431             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1432                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1433                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1434                          (int)azx_bus(chip)->codec_mask);
1435         }
1436 }
1437
1438 /*
1439  * white/black-list for enable_msi
1440  */
1441 static struct snd_pci_quirk msi_black_list[] = {
1442         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1443         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1444         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1445         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1446         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1447         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1448         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1449         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1450         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1451         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1452         {}
1453 };
1454
1455 static void check_msi(struct azx *chip)
1456 {
1457         const struct snd_pci_quirk *q;
1458
1459         if (enable_msi >= 0) {
1460                 chip->msi = !!enable_msi;
1461                 return;
1462         }
1463         chip->msi = 1;  /* enable MSI as default */
1464         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1465         if (q) {
1466                 dev_info(chip->card->dev,
1467                          "msi for device %04x:%04x set to %d\n",
1468                          q->subvendor, q->subdevice, q->value);
1469                 chip->msi = q->value;
1470                 return;
1471         }
1472
1473         /* NVidia chipsets seem to cause troubles with MSI */
1474         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1475                 dev_info(chip->card->dev, "Disabling MSI\n");
1476                 chip->msi = 0;
1477         }
1478 }
1479
1480 /* check the snoop mode availability */
1481 static void azx_check_snoop_available(struct azx *chip)
1482 {
1483         int snoop = hda_snoop;
1484
1485         if (snoop >= 0) {
1486                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1487                          snoop ? "snoop" : "non-snoop");
1488                 chip->snoop = snoop;
1489                 return;
1490         }
1491
1492         snoop = true;
1493         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1494             chip->driver_type == AZX_DRIVER_VIA) {
1495                 /* force to non-snoop mode for a new VIA controller
1496                  * when BIOS is set
1497                  */
1498                 u8 val;
1499                 pci_read_config_byte(chip->pci, 0x42, &val);
1500                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1501                         snoop = false;
1502         }
1503
1504         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1505                 snoop = false;
1506
1507         chip->snoop = snoop;
1508         if (!snoop)
1509                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1510 }
1511
1512 static void azx_probe_work(struct work_struct *work)
1513 {
1514         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1515         azx_probe_continue(&hda->chip);
1516 }
1517
1518 static int default_bdl_pos_adj(struct azx *chip)
1519 {
1520         /* some exceptions: Atoms seem problematic with value 1 */
1521         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1522                 switch (chip->pci->device) {
1523                 case 0x0f04: /* Baytrail */
1524                 case 0x2284: /* Braswell */
1525                         return 32;
1526                 }
1527         }
1528
1529         switch (chip->driver_type) {
1530         case AZX_DRIVER_ICH:
1531         case AZX_DRIVER_PCH:
1532                 return 1;
1533         default:
1534                 return 32;
1535         }
1536 }
1537
1538 /*
1539  * constructor
1540  */
1541 static const struct hdac_io_ops pci_hda_io_ops;
1542 static const struct hda_controller_ops pci_hda_ops;
1543
1544 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1545                       int dev, unsigned int driver_caps,
1546                       struct azx **rchip)
1547 {
1548         static struct snd_device_ops ops = {
1549                 .dev_disconnect = azx_dev_disconnect,
1550                 .dev_free = azx_dev_free,
1551         };
1552         struct hda_intel *hda;
1553         struct azx *chip;
1554         int err;
1555
1556         *rchip = NULL;
1557
1558         err = pci_enable_device(pci);
1559         if (err < 0)
1560                 return err;
1561
1562         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1563         if (!hda) {
1564                 pci_disable_device(pci);
1565                 return -ENOMEM;
1566         }
1567
1568         chip = &hda->chip;
1569         mutex_init(&chip->open_mutex);
1570         chip->card = card;
1571         chip->pci = pci;
1572         chip->ops = &pci_hda_ops;
1573         chip->driver_caps = driver_caps;
1574         chip->driver_type = driver_caps & 0xff;
1575         check_msi(chip);
1576         chip->dev_index = dev;
1577         chip->jackpoll_ms = jackpoll_ms;
1578         INIT_LIST_HEAD(&chip->pcm_list);
1579         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1580         INIT_LIST_HEAD(&hda->list);
1581         init_vga_switcheroo(chip);
1582         init_completion(&hda->probe_wait);
1583
1584         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1585
1586         check_probe_mask(chip, dev);
1587
1588         chip->single_cmd = single_cmd;
1589         azx_check_snoop_available(chip);
1590
1591         if (bdl_pos_adj[dev] < 0)
1592                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1593         else
1594                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1595
1596         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1597         if (err < 0) {
1598                 kfree(hda);
1599                 pci_disable_device(pci);
1600                 return err;
1601         }
1602
1603         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1604                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1605                 chip->bus.needs_damn_long_delay = 1;
1606         }
1607
1608         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1609         if (err < 0) {
1610                 dev_err(card->dev, "Error creating device [card]!\n");
1611                 azx_free(chip);
1612                 return err;
1613         }
1614
1615         /* continue probing in work context as may trigger request module */
1616         INIT_WORK(&hda->probe_work, azx_probe_work);
1617
1618         *rchip = chip;
1619
1620         return 0;
1621 }
1622
1623 static int azx_first_init(struct azx *chip)
1624 {
1625         int dev = chip->dev_index;
1626         struct pci_dev *pci = chip->pci;
1627         struct snd_card *card = chip->card;
1628         struct hdac_bus *bus = azx_bus(chip);
1629         int err;
1630         unsigned short gcap;
1631         unsigned int dma_bits = 64;
1632
1633 #if BITS_PER_LONG != 64
1634         /* Fix up base address on ULI M5461 */
1635         if (chip->driver_type == AZX_DRIVER_ULI) {
1636                 u16 tmp3;
1637                 pci_read_config_word(pci, 0x40, &tmp3);
1638                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1639                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1640         }
1641 #endif
1642
1643         err = pci_request_regions(pci, "ICH HD audio");
1644         if (err < 0)
1645                 return err;
1646         chip->region_requested = 1;
1647
1648         bus->addr = pci_resource_start(pci, 0);
1649         bus->remap_addr = pci_ioremap_bar(pci, 0);
1650         if (bus->remap_addr == NULL) {
1651                 dev_err(card->dev, "ioremap error\n");
1652                 return -ENXIO;
1653         }
1654
1655         if (chip->msi) {
1656                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1657                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1658                         pci->no_64bit_msi = true;
1659                 }
1660                 if (pci_enable_msi(pci) < 0)
1661                         chip->msi = 0;
1662         }
1663
1664         if (azx_acquire_irq(chip, 0) < 0)
1665                 return -EBUSY;
1666
1667         pci_set_master(pci);
1668         synchronize_irq(bus->irq);
1669
1670         gcap = azx_readw(chip, GCAP);
1671         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1672
1673         /* AMD devices support 40 or 48bit DMA, take the safe one */
1674         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1675                 dma_bits = 40;
1676
1677         /* disable SB600 64bit support for safety */
1678         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1679                 struct pci_dev *p_smbus;
1680                 dma_bits = 40;
1681                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1682                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1683                                          NULL);
1684                 if (p_smbus) {
1685                         if (p_smbus->revision < 0x30)
1686                                 gcap &= ~AZX_GCAP_64OK;
1687                         pci_dev_put(p_smbus);
1688                 }
1689         }
1690
1691         /* disable 64bit DMA address on some devices */
1692         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1693                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1694                 gcap &= ~AZX_GCAP_64OK;
1695         }
1696
1697         /* disable buffer size rounding to 128-byte multiples if supported */
1698         if (align_buffer_size >= 0)
1699                 chip->align_buffer_size = !!align_buffer_size;
1700         else {
1701                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1702                         chip->align_buffer_size = 0;
1703                 else
1704                         chip->align_buffer_size = 1;
1705         }
1706
1707         /* allow 64bit DMA address if supported by H/W */
1708         if (!(gcap & AZX_GCAP_64OK))
1709                 dma_bits = 32;
1710         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1711                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1712         } else {
1713                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1714                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1715         }
1716
1717         /* read number of streams from GCAP register instead of using
1718          * hardcoded value
1719          */
1720         chip->capture_streams = (gcap >> 8) & 0x0f;
1721         chip->playback_streams = (gcap >> 12) & 0x0f;
1722         if (!chip->playback_streams && !chip->capture_streams) {
1723                 /* gcap didn't give any info, switching to old method */
1724
1725                 switch (chip->driver_type) {
1726                 case AZX_DRIVER_ULI:
1727                         chip->playback_streams = ULI_NUM_PLAYBACK;
1728                         chip->capture_streams = ULI_NUM_CAPTURE;
1729                         break;
1730                 case AZX_DRIVER_ATIHDMI:
1731                 case AZX_DRIVER_ATIHDMI_NS:
1732                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1733                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1734                         break;
1735                 case AZX_DRIVER_GENERIC:
1736                 default:
1737                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1738                         chip->capture_streams = ICH6_NUM_CAPTURE;
1739                         break;
1740                 }
1741         }
1742         chip->capture_index_offset = 0;
1743         chip->playback_index_offset = chip->capture_streams;
1744         chip->num_streams = chip->playback_streams + chip->capture_streams;
1745
1746         /* initialize streams */
1747         err = azx_init_streams(chip);
1748         if (err < 0)
1749                 return err;
1750
1751         err = azx_alloc_stream_pages(chip);
1752         if (err < 0)
1753                 return err;
1754
1755         /* initialize chip */
1756         azx_init_pci(chip);
1757
1758         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1759                 snd_hdac_i915_set_bclk(bus);
1760
1761         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1762
1763         /* codec detection */
1764         if (!azx_bus(chip)->codec_mask) {
1765                 dev_err(card->dev, "no codecs found!\n");
1766                 return -ENODEV;
1767         }
1768
1769         strcpy(card->driver, "HDA-Intel");
1770         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1771                 sizeof(card->shortname));
1772         snprintf(card->longname, sizeof(card->longname),
1773                  "%s at 0x%lx irq %i",
1774                  card->shortname, bus->addr, bus->irq);
1775
1776         return 0;
1777 }
1778
1779 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1780 /* callback from request_firmware_nowait() */
1781 static void azx_firmware_cb(const struct firmware *fw, void *context)
1782 {
1783         struct snd_card *card = context;
1784         struct azx *chip = card->private_data;
1785         struct pci_dev *pci = chip->pci;
1786
1787         if (!fw) {
1788                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1789                 goto error;
1790         }
1791
1792         chip->fw = fw;
1793         if (!chip->disabled) {
1794                 /* continue probing */
1795                 if (azx_probe_continue(chip))
1796                         goto error;
1797         }
1798         return; /* OK */
1799
1800  error:
1801         snd_card_free(card);
1802         pci_set_drvdata(pci, NULL);
1803 }
1804 #endif
1805
1806 /*
1807  * HDA controller ops.
1808  */
1809
1810 /* PCI register access. */
1811 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1812 {
1813         writel(value, addr);
1814 }
1815
1816 static u32 pci_azx_readl(u32 __iomem *addr)
1817 {
1818         return readl(addr);
1819 }
1820
1821 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1822 {
1823         writew(value, addr);
1824 }
1825
1826 static u16 pci_azx_readw(u16 __iomem *addr)
1827 {
1828         return readw(addr);
1829 }
1830
1831 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1832 {
1833         writeb(value, addr);
1834 }
1835
1836 static u8 pci_azx_readb(u8 __iomem *addr)
1837 {
1838         return readb(addr);
1839 }
1840
1841 static int disable_msi_reset_irq(struct azx *chip)
1842 {
1843         struct hdac_bus *bus = azx_bus(chip);
1844         int err;
1845
1846         free_irq(bus->irq, chip);
1847         bus->irq = -1;
1848         pci_disable_msi(chip->pci);
1849         chip->msi = 0;
1850         err = azx_acquire_irq(chip, 1);
1851         if (err < 0)
1852                 return err;
1853
1854         return 0;
1855 }
1856
1857 /* DMA page allocation helpers.  */
1858 static int dma_alloc_pages(struct hdac_bus *bus,
1859                            int type,
1860                            size_t size,
1861                            struct snd_dma_buffer *buf)
1862 {
1863         struct azx *chip = bus_to_azx(bus);
1864         int err;
1865
1866         err = snd_dma_alloc_pages(type,
1867                                   bus->dev,
1868                                   size, buf);
1869         if (err < 0)
1870                 return err;
1871         mark_pages_wc(chip, buf, true);
1872         return 0;
1873 }
1874
1875 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1876 {
1877         struct azx *chip = bus_to_azx(bus);
1878
1879         mark_pages_wc(chip, buf, false);
1880         snd_dma_free_pages(buf);
1881 }
1882
1883 static int substream_alloc_pages(struct azx *chip,
1884                                  struct snd_pcm_substream *substream,
1885                                  size_t size)
1886 {
1887         struct azx_dev *azx_dev = get_azx_dev(substream);
1888         int ret;
1889
1890         mark_runtime_wc(chip, azx_dev, substream, false);
1891         ret = snd_pcm_lib_malloc_pages(substream, size);
1892         if (ret < 0)
1893                 return ret;
1894         mark_runtime_wc(chip, azx_dev, substream, true);
1895         return 0;
1896 }
1897
1898 static int substream_free_pages(struct azx *chip,
1899                                 struct snd_pcm_substream *substream)
1900 {
1901         struct azx_dev *azx_dev = get_azx_dev(substream);
1902         mark_runtime_wc(chip, azx_dev, substream, false);
1903         return snd_pcm_lib_free_pages(substream);
1904 }
1905
1906 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1907                              struct vm_area_struct *area)
1908 {
1909 #ifdef CONFIG_X86
1910         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1911         struct azx *chip = apcm->chip;
1912         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1913                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1914 #endif
1915 }
1916
1917 static const struct hdac_io_ops pci_hda_io_ops = {
1918         .reg_writel = pci_azx_writel,
1919         .reg_readl = pci_azx_readl,
1920         .reg_writew = pci_azx_writew,
1921         .reg_readw = pci_azx_readw,
1922         .reg_writeb = pci_azx_writeb,
1923         .reg_readb = pci_azx_readb,
1924         .dma_alloc_pages = dma_alloc_pages,
1925         .dma_free_pages = dma_free_pages,
1926 };
1927
1928 static const struct hda_controller_ops pci_hda_ops = {
1929         .disable_msi_reset_irq = disable_msi_reset_irq,
1930         .substream_alloc_pages = substream_alloc_pages,
1931         .substream_free_pages = substream_free_pages,
1932         .pcm_mmap_prepare = pcm_mmap_prepare,
1933         .position_check = azx_position_check,
1934         .link_power = azx_intel_link_power,
1935 };
1936
1937 static int azx_probe(struct pci_dev *pci,
1938                      const struct pci_device_id *pci_id)
1939 {
1940         static int dev;
1941         struct snd_card *card;
1942         struct hda_intel *hda;
1943         struct azx *chip;
1944         bool schedule_probe;
1945         int err;
1946
1947         if (dev >= SNDRV_CARDS)
1948                 return -ENODEV;
1949         if (!enable[dev]) {
1950                 dev++;
1951                 return -ENOENT;
1952         }
1953
1954         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1955                            0, &card);
1956         if (err < 0) {
1957                 dev_err(&pci->dev, "Error creating card!\n");
1958                 return err;
1959         }
1960
1961         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1962         if (err < 0)
1963                 goto out_free;
1964         card->private_data = chip;
1965         hda = container_of(chip, struct hda_intel, chip);
1966
1967         pci_set_drvdata(pci, card);
1968
1969         err = register_vga_switcheroo(chip);
1970         if (err < 0) {
1971                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
1972                 goto out_free;
1973         }
1974
1975         if (check_hdmi_disabled(pci)) {
1976                 dev_info(card->dev, "VGA controller is disabled\n");
1977                 dev_info(card->dev, "Delaying initialization\n");
1978                 chip->disabled = true;
1979         }
1980
1981         schedule_probe = !chip->disabled;
1982
1983 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1984         if (patch[dev] && *patch[dev]) {
1985                 dev_info(card->dev, "Applying patch firmware '%s'\n",
1986                          patch[dev]);
1987                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1988                                               &pci->dev, GFP_KERNEL, card,
1989                                               azx_firmware_cb);
1990                 if (err < 0)
1991                         goto out_free;
1992                 schedule_probe = false; /* continued in azx_firmware_cb() */
1993         }
1994 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1995
1996 #ifndef CONFIG_SND_HDA_I915
1997         if (CONTROLLER_IN_GPU(pci))
1998                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
1999 #endif
2000
2001         if (schedule_probe)
2002                 schedule_work(&hda->probe_work);
2003
2004         dev++;
2005         if (chip->disabled)
2006                 complete_all(&hda->probe_wait);
2007         return 0;
2008
2009 out_free:
2010         snd_card_free(card);
2011         return err;
2012 }
2013
2014 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2015 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2016         [AZX_DRIVER_NVIDIA] = 8,
2017         [AZX_DRIVER_TERA] = 1,
2018 };
2019
2020 static int azx_probe_continue(struct azx *chip)
2021 {
2022         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2023         struct hdac_bus *bus = azx_bus(chip);
2024         struct pci_dev *pci = chip->pci;
2025         int dev = chip->dev_index;
2026         int err;
2027
2028         hda->probe_continued = 1;
2029
2030         /* Request display power well for the HDA controller or codec. For
2031          * Haswell/Broadwell, both the display HDA controller and codec need
2032          * this power. For other platforms, like Baytrail/Braswell, only the
2033          * display codec needs the power and it can be released after probe.
2034          */
2035         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2036                 /* HSW/BDW controllers need this power */
2037                 if (CONTROLLER_IN_GPU(pci))
2038                         hda->need_i915_power = 1;
2039
2040                 err = snd_hdac_i915_init(bus);
2041                 if (err < 0) {
2042                         /* if the controller is bound only with HDMI/DP
2043                          * (for HSW and BDW), we need to abort the probe;
2044                          * for other chips, still continue probing as other
2045                          * codecs can be on the same link.
2046                          */
2047                         if (CONTROLLER_IN_GPU(pci)) {
2048                                 dev_err(chip->card->dev,
2049                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2050                                 goto out_free;
2051                         } else
2052                                 goto skip_i915;
2053                 }
2054
2055                 err = snd_hdac_display_power(bus, true);
2056                 if (err < 0) {
2057                         dev_err(chip->card->dev,
2058                                 "Cannot turn on display power on i915\n");
2059                         goto i915_power_fail;
2060                 }
2061         }
2062
2063  skip_i915:
2064         err = azx_first_init(chip);
2065         if (err < 0)
2066                 goto out_free;
2067
2068 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2069         chip->beep_mode = beep_mode[dev];
2070 #endif
2071
2072         /* create codec instances */
2073         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2074         if (err < 0)
2075                 goto out_free;
2076
2077 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2078         if (chip->fw) {
2079                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2080                                          chip->fw->data);
2081                 if (err < 0)
2082                         goto out_free;
2083 #ifndef CONFIG_PM
2084                 release_firmware(chip->fw); /* no longer needed */
2085                 chip->fw = NULL;
2086 #endif
2087         }
2088 #endif
2089         if ((probe_only[dev] & 1) == 0) {
2090                 err = azx_codec_configure(chip);
2091                 if (err < 0)
2092                         goto out_free;
2093         }
2094
2095         err = snd_card_register(chip->card);
2096         if (err < 0)
2097                 goto out_free;
2098
2099         chip->running = 1;
2100         azx_add_card_list(chip);
2101         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2102         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2103                 pm_runtime_put_autosuspend(&pci->dev);
2104
2105 out_free:
2106         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2107                 && !hda->need_i915_power)
2108                 snd_hdac_display_power(bus, false);
2109
2110 i915_power_fail:
2111         if (err < 0)
2112                 hda->init_failed = 1;
2113         complete_all(&hda->probe_wait);
2114         return err;
2115 }
2116
2117 static void azx_remove(struct pci_dev *pci)
2118 {
2119         struct snd_card *card = pci_get_drvdata(pci);
2120         struct azx *chip;
2121         struct hda_intel *hda;
2122
2123         if (card) {
2124                 /* cancel the pending probing work */
2125                 chip = card->private_data;
2126                 hda = container_of(chip, struct hda_intel, chip);
2127                 cancel_work_sync(&hda->probe_work);
2128
2129                 snd_card_free(card);
2130         }
2131 }
2132
2133 static void azx_shutdown(struct pci_dev *pci)
2134 {
2135         struct snd_card *card = pci_get_drvdata(pci);
2136         struct azx *chip;
2137
2138         if (!card)
2139                 return;
2140         chip = card->private_data;
2141         if (chip && chip->running)
2142                 azx_stop_chip(chip);
2143 }
2144
2145 /* PCI IDs */
2146 static const struct pci_device_id azx_ids[] = {
2147         /* CPT */
2148         { PCI_DEVICE(0x8086, 0x1c20),
2149           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2150         /* PBG */
2151         { PCI_DEVICE(0x8086, 0x1d20),
2152           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2153         /* Panther Point */
2154         { PCI_DEVICE(0x8086, 0x1e20),
2155           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2156         /* Lynx Point */
2157         { PCI_DEVICE(0x8086, 0x8c20),
2158           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2159         /* 9 Series */
2160         { PCI_DEVICE(0x8086, 0x8ca0),
2161           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2162         /* Wellsburg */
2163         { PCI_DEVICE(0x8086, 0x8d20),
2164           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2165         { PCI_DEVICE(0x8086, 0x8d21),
2166           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2167         /* Lewisburg */
2168         { PCI_DEVICE(0x8086, 0xa1f0),
2169           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2170         { PCI_DEVICE(0x8086, 0xa270),
2171           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2172         /* Lynx Point-LP */
2173         { PCI_DEVICE(0x8086, 0x9c20),
2174           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2175         /* Lynx Point-LP */
2176         { PCI_DEVICE(0x8086, 0x9c21),
2177           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2178         /* Wildcat Point-LP */
2179         { PCI_DEVICE(0x8086, 0x9ca0),
2180           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2181         /* Sunrise Point */
2182         { PCI_DEVICE(0x8086, 0xa170),
2183           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2184         /* Sunrise Point-LP */
2185         { PCI_DEVICE(0x8086, 0x9d70),
2186           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2187         /* Kabylake */
2188         { PCI_DEVICE(0x8086, 0xa171),
2189           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2190         /* Kabylake-LP */
2191         { PCI_DEVICE(0x8086, 0x9d71),
2192           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2193         /* Broxton-P(Apollolake) */
2194         { PCI_DEVICE(0x8086, 0x5a98),
2195           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2196         /* Broxton-T */
2197         { PCI_DEVICE(0x8086, 0x1a98),
2198           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2199         /* Haswell */
2200         { PCI_DEVICE(0x8086, 0x0a0c),
2201           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2202         { PCI_DEVICE(0x8086, 0x0c0c),
2203           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2204         { PCI_DEVICE(0x8086, 0x0d0c),
2205           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2206         /* Broadwell */
2207         { PCI_DEVICE(0x8086, 0x160c),
2208           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2209         /* 5 Series/3400 */
2210         { PCI_DEVICE(0x8086, 0x3b56),
2211           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2212         /* Poulsbo */
2213         { PCI_DEVICE(0x8086, 0x811b),
2214           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2215         /* Oaktrail */
2216         { PCI_DEVICE(0x8086, 0x080a),
2217           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2218         /* BayTrail */
2219         { PCI_DEVICE(0x8086, 0x0f04),
2220           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2221         /* Braswell */
2222         { PCI_DEVICE(0x8086, 0x2284),
2223           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2224         /* ICH6 */
2225         { PCI_DEVICE(0x8086, 0x2668),
2226           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2227         /* ICH7 */
2228         { PCI_DEVICE(0x8086, 0x27d8),
2229           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2230         /* ESB2 */
2231         { PCI_DEVICE(0x8086, 0x269a),
2232           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2233         /* ICH8 */
2234         { PCI_DEVICE(0x8086, 0x284b),
2235           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2236         /* ICH9 */
2237         { PCI_DEVICE(0x8086, 0x293e),
2238           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2239         /* ICH9 */
2240         { PCI_DEVICE(0x8086, 0x293f),
2241           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2242         /* ICH10 */
2243         { PCI_DEVICE(0x8086, 0x3a3e),
2244           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2245         /* ICH10 */
2246         { PCI_DEVICE(0x8086, 0x3a6e),
2247           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2248         /* Generic Intel */
2249         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2250           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2251           .class_mask = 0xffffff,
2252           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2253         /* ATI SB 450/600/700/800/900 */
2254         { PCI_DEVICE(0x1002, 0x437b),
2255           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2256         { PCI_DEVICE(0x1002, 0x4383),
2257           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2258         /* AMD Hudson */
2259         { PCI_DEVICE(0x1022, 0x780d),
2260           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2261         /* ATI HDMI */
2262         { PCI_DEVICE(0x1002, 0x1308),
2263           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2264         { PCI_DEVICE(0x1002, 0x157a),
2265           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2266         { PCI_DEVICE(0x1002, 0x793b),
2267           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2268         { PCI_DEVICE(0x1002, 0x7919),
2269           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2270         { PCI_DEVICE(0x1002, 0x960f),
2271           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2272         { PCI_DEVICE(0x1002, 0x970f),
2273           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2274         { PCI_DEVICE(0x1002, 0x9840),
2275           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2276         { PCI_DEVICE(0x1002, 0xaa00),
2277           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2278         { PCI_DEVICE(0x1002, 0xaa08),
2279           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2280         { PCI_DEVICE(0x1002, 0xaa10),
2281           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2282         { PCI_DEVICE(0x1002, 0xaa18),
2283           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2284         { PCI_DEVICE(0x1002, 0xaa20),
2285           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2286         { PCI_DEVICE(0x1002, 0xaa28),
2287           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2288         { PCI_DEVICE(0x1002, 0xaa30),
2289           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2290         { PCI_DEVICE(0x1002, 0xaa38),
2291           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2292         { PCI_DEVICE(0x1002, 0xaa40),
2293           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2294         { PCI_DEVICE(0x1002, 0xaa48),
2295           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2296         { PCI_DEVICE(0x1002, 0xaa50),
2297           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2298         { PCI_DEVICE(0x1002, 0xaa58),
2299           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2300         { PCI_DEVICE(0x1002, 0xaa60),
2301           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2302         { PCI_DEVICE(0x1002, 0xaa68),
2303           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2304         { PCI_DEVICE(0x1002, 0xaa80),
2305           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2306         { PCI_DEVICE(0x1002, 0xaa88),
2307           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2308         { PCI_DEVICE(0x1002, 0xaa90),
2309           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2310         { PCI_DEVICE(0x1002, 0xaa98),
2311           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2312         { PCI_DEVICE(0x1002, 0x9902),
2313           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2314         { PCI_DEVICE(0x1002, 0xaaa0),
2315           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2316         { PCI_DEVICE(0x1002, 0xaaa8),
2317           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2318         { PCI_DEVICE(0x1002, 0xaab0),
2319           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2320         { PCI_DEVICE(0x1002, 0xaac0),
2321           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2322         { PCI_DEVICE(0x1002, 0xaac8),
2323           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2324         { PCI_DEVICE(0x1002, 0xaad8),
2325           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2326         { PCI_DEVICE(0x1002, 0xaae8),
2327           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2328         { PCI_DEVICE(0x1002, 0xaae0),
2329           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2330         { PCI_DEVICE(0x1002, 0xaaf0),
2331           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2332         /* VIA VT8251/VT8237A */
2333         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2334         /* VIA GFX VT7122/VX900 */
2335         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2336         /* VIA GFX VT6122/VX11 */
2337         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2338         /* SIS966 */
2339         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2340         /* ULI M5461 */
2341         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2342         /* NVIDIA MCP */
2343         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2344           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2345           .class_mask = 0xffffff,
2346           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2347         /* Teradici */
2348         { PCI_DEVICE(0x6549, 0x1200),
2349           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2350         { PCI_DEVICE(0x6549, 0x2200),
2351           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2352         /* Creative X-Fi (CA0110-IBG) */
2353         /* CTHDA chips */
2354         { PCI_DEVICE(0x1102, 0x0010),
2355           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2356         { PCI_DEVICE(0x1102, 0x0012),
2357           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2358 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2359         /* the following entry conflicts with snd-ctxfi driver,
2360          * as ctxfi driver mutates from HD-audio to native mode with
2361          * a special command sequence.
2362          */
2363         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2364           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2365           .class_mask = 0xffffff,
2366           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2367           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2368 #else
2369         /* this entry seems still valid -- i.e. without emu20kx chip */
2370         { PCI_DEVICE(0x1102, 0x0009),
2371           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2372           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2373 #endif
2374         /* CM8888 */
2375         { PCI_DEVICE(0x13f6, 0x5011),
2376           .driver_data = AZX_DRIVER_CMEDIA |
2377           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2378         /* Vortex86MX */
2379         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2380         /* VMware HDAudio */
2381         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2382         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2383         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2384           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2385           .class_mask = 0xffffff,
2386           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2387         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2388           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2389           .class_mask = 0xffffff,
2390           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2391         { 0, }
2392 };
2393 MODULE_DEVICE_TABLE(pci, azx_ids);
2394
2395 /* pci_driver definition */
2396 static struct pci_driver azx_driver = {
2397         .name = KBUILD_MODNAME,
2398         .id_table = azx_ids,
2399         .probe = azx_probe,
2400         .remove = azx_remove,
2401         .shutdown = azx_shutdown,
2402         .driver = {
2403                 .pm = AZX_PM_OPS,
2404         },
2405 };
2406
2407 module_pci_driver(azx_driver);