sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #endif
  58 #include <sound/core.h>
  59 #include <sound/initval.h>
  60 #include <linux/vgaarb.h>
  61 #include <linux/vga_switcheroo.h>
  62 #include <linux/firmware.h>
  63 #include "hda_codec.h"
  64 #include "hda_controller.h"
  65 #include "hda_intel.h"
  66
  67 /* position fix mode */
  68 enum {
  69         POS_FIX_AUTO,
  70         POS_FIX_LPIB,
  71         POS_FIX_POSBUF,
  72         POS_FIX_VIACOMBO,
  73         POS_FIX_COMBO,
  74 };
  75
  76 /* Defines for ATI HD Audio support in SB450 south bridge */
  77 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  78 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  79
  80 /* Defines for Nvidia HDA support */
  81 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  82 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  83 #define NVIDIA_HDA_ISTRM_COH          0x4d
  84 #define NVIDIA_HDA_OSTRM_COH          0x4c
  85 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  86
  87 /* Defines for Intel SCH HDA snoop control */
  88 #define INTEL_SCH_HDA_DEVC      0x78
  89 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  90
  91 /* Define IN stream 0 FIFO size offset in VIA controller */
  92 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  93 /* Define VIA HD Audio Device ID*/
  94 #define VIA_HDAC_DEVICE_ID              0x3288
  95
  96 /* max number of SDs */
  97 /* ICH, ATI and VIA have 4 playback and 4 capture */
  98 #define ICH6_NUM_CAPTURE        4
  99 #define ICH6_NUM_PLAYBACK       4
 100
 101 /* ULI has 6 playback and 5 capture */
 102 #define ULI_NUM_CAPTURE         5
 103 #define ULI_NUM_PLAYBACK        6
 104
 105 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 106 #define ATIHDMI_NUM_CAPTURE     0
 107 #define ATIHDMI_NUM_PLAYBACK    8
 108
 109 /* TERA has 4 playback and 3 capture */
 110 #define TERA_NUM_CAPTURE        3
 111 #define TERA_NUM_PLAYBACK       4
 112
 113
 114 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 115 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 116 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 117 static char *model[SNDRV_CARDS];
 118 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 119 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 120 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 121 static int probe_only[SNDRV_CARDS];
 122 static int jackpoll_ms[SNDRV_CARDS];
 123 static bool single_cmd;
 124 static int enable_msi = -1;
 125 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 126 static char *patch[SNDRV_CARDS];
 127 #endif
 128 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 129 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 130                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 131 #endif
 132
 133 module_param_array(index, int, NULL, 0444);
 134 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 135 module_param_array(id, charp, NULL, 0444);
 136 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 137 module_param_array(enable, bool, NULL, 0444);
 138 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 139 module_param_array(model, charp, NULL, 0444);
 140 MODULE_PARM_DESC(model, "Use the given board model.");
 141 module_param_array(position_fix, int, NULL, 0444);
 142 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 143                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 144 module_param_array(bdl_pos_adj, int, NULL, 0644);
 145 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 146 module_param_array(probe_mask, int, NULL, 0444);
 147 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 148 module_param_array(probe_only, int, NULL, 0444);
 149 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 150 module_param_array(jackpoll_ms, int, NULL, 0444);
 151 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 152 module_param(single_cmd, bool, 0444);
 153 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 154                  "(for debugging only).");
 155 module_param(enable_msi, bint, 0444);
 156 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 157 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 158 module_param_array(patch, charp, NULL, 0444);
 159 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 160 #endif
 161 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 162 module_param_array(beep_mode, bool, NULL, 0444);
 163 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 164                             "(0=off, 1=on) (default=1).");
 165 #endif
 166
 167 #ifdef CONFIG_PM
 168 static int param_set_xint(const char *val, const struct kernel_param *kp);
 169 static struct kernel_param_ops param_ops_xint = {
 170         .set = param_set_xint,
 171         .get = param_get_int,
 172 };
 173 #define param_check_xint param_check_int
 174
 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 176 module_param(power_save, xint, 0644);
 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 178                  "(in second, 0 = disable).");
 179
 180 /* reset the HD-audio controller in power save mode.
 181  * this may give more power-saving, but will take longer time to
 182  * wake up.
 183  */
 184 static bool power_save_controller = 1;
 185 module_param(power_save_controller, bool, 0644);
 186 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 187 #else
 188 #define power_save      0
 189 #endif /* CONFIG_PM */
 190
 191 static int align_buffer_size = -1;
 192 module_param(align_buffer_size, bint, 0644);
 193 MODULE_PARM_DESC(align_buffer_size,
 194                 "Force buffer and period sizes to be multiple of 128 bytes.");
 195
 196 #ifdef CONFIG_X86
 197 static int hda_snoop = -1;
 198 module_param_named(snoop, hda_snoop, bint, 0444);
 199 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 200 #else
 201 #define hda_snoop               true
 202 #endif
 203
 204
 205 MODULE_LICENSE("GPL");
 206 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 207                          "{Intel, ICH6M},"
 208                          "{Intel, ICH7},"
 209                          "{Intel, ESB2},"
 210                          "{Intel, ICH8},"
 211                          "{Intel, ICH9},"
 212                          "{Intel, ICH10},"
 213                          "{Intel, PCH},"
 214                          "{Intel, CPT},"
 215                          "{Intel, PPT},"
 216                          "{Intel, LPT},"
 217                          "{Intel, LPT_LP},"
 218                          "{Intel, WPT_LP},"
 219                          "{Intel, SPT},"
 220                          "{Intel, SPT_LP},"
 221                          "{Intel, HPT},"
 222                          "{Intel, PBG},"
 223                          "{Intel, SCH},"
 224                          "{ATI, SB450},"
 225                          "{ATI, SB600},"
 226                          "{ATI, RS600},"
 227                          "{ATI, RS690},"
 228                          "{ATI, RS780},"
 229                          "{ATI, R600},"
 230                          "{ATI, RV630},"
 231                          "{ATI, RV610},"
 232                          "{ATI, RV670},"
 233                          "{ATI, RV635},"
 234                          "{ATI, RV620},"
 235                          "{ATI, RV770},"
 236                          "{VIA, VT8251},"
 237                          "{VIA, VT8237A},"
 238                          "{SiS, SIS966},"
 239                          "{ULI, M5461}}");
 240 MODULE_DESCRIPTION("Intel HDA driver");
 241
 242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 244 #define SUPPORT_VGA_SWITCHEROO
 245 #endif
 246 #endif
 247
 248
 249 /*
 250  */
 251
 252 /* driver types */
 253 enum {
 254         AZX_DRIVER_ICH,
 255         AZX_DRIVER_PCH,
 256         AZX_DRIVER_SCH,
 257         AZX_DRIVER_HDMI,
 258         AZX_DRIVER_ATI,
 259         AZX_DRIVER_ATIHDMI,
 260         AZX_DRIVER_ATIHDMI_NS,
 261         AZX_DRIVER_VIA,
 262         AZX_DRIVER_SIS,
 263         AZX_DRIVER_ULI,
 264         AZX_DRIVER_NVIDIA,
 265         AZX_DRIVER_TERA,
 266         AZX_DRIVER_CTX,
 267         AZX_DRIVER_CTHDA,
 268         AZX_DRIVER_CMEDIA,
 269         AZX_DRIVER_GENERIC,
 270         AZX_NUM_DRIVERS, /* keep this as last entry */
 271 };
 272
 273 #define azx_get_snoop_type(chip) \
 274         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 276
 277 /* quirks for old Intel chipsets */
 278 #define AZX_DCAPS_INTEL_ICH \
 279         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 280
 281 /* quirks for Intel PCH */
 282 #define AZX_DCAPS_INTEL_PCH_NOPM \
 283         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 284          AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
 285
 286 #define AZX_DCAPS_INTEL_PCH \
 287         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 288
 289 #define AZX_DCAPS_INTEL_HASWELL \
 290         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 291          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 292          AZX_DCAPS_SNOOP_TYPE(SCH))
 293
 294 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 295 #define AZX_DCAPS_INTEL_BROADWELL \
 296         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 297          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 298          AZX_DCAPS_SNOOP_TYPE(SCH))
 299
 300 #define AZX_DCAPS_INTEL_BAYTRAIL \
 301         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 302
 303 #define AZX_DCAPS_INTEL_BRASWELL \
 304         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 305
 306 #define AZX_DCAPS_INTEL_SKYLAKE \
 307         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 308          AZX_DCAPS_I915_POWERWELL)
 309
 310 /* quirks for ATI SB / AMD Hudson */
 311 #define AZX_DCAPS_PRESET_ATI_SB \
 312         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 313          AZX_DCAPS_SNOOP_TYPE(ATI))
 314
 315 /* quirks for ATI/AMD HDMI */
 316 #define AZX_DCAPS_PRESET_ATI_HDMI \
 317         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 318          AZX_DCAPS_NO_MSI64)
 319
 320 /* quirks for ATI HDMI with snoop off */
 321 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 322         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 323
 324 /* quirks for Nvidia */
 325 #define AZX_DCAPS_PRESET_NVIDIA \
 326         (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
 327          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 328          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 329
 330 #define AZX_DCAPS_PRESET_CTHDA \
 331         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 332          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 333
 334 /*
 335  * VGA-switcher support
 336  */
 337 #ifdef SUPPORT_VGA_SWITCHEROO
 338 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 339 #else
 340 #define use_vga_switcheroo(chip)        0
 341 #endif
 342
 343 static char *driver_short_names[] = {
 344         [AZX_DRIVER_ICH] = "HDA Intel",
 345         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 346         [AZX_DRIVER_SCH] = "HDA Intel MID",
 347         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 348         [AZX_DRIVER_ATI] = "HDA ATI SB",
 349         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 350         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 351         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 352         [AZX_DRIVER_SIS] = "HDA SIS966",
 353         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 354         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 355         [AZX_DRIVER_TERA] = "HDA Teradici",
 356         [AZX_DRIVER_CTX] = "HDA Creative",
 357         [AZX_DRIVER_CTHDA] = "HDA Creative",
 358         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 359         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 360 };
 361
 362 #ifdef CONFIG_X86
 363 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 364 {
 365         int pages;
 366
 367         if (azx_snoop(chip))
 368                 return;
 369         if (!dmab || !dmab->area || !dmab->bytes)
 370                 return;
 371
 372 #ifdef CONFIG_SND_DMA_SGBUF
 373         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 374                 struct snd_sg_buf *sgbuf = dmab->private_data;
 375                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 376                         return; /* deal with only CORB/RIRB buffers */
 377                 if (on)
 378                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 379                 else
 380                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 381                 return;
 382         }
 383 #endif
 384
 385         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 386         if (on)
 387                 set_memory_wc((unsigned long)dmab->area, pages);
 388         else
 389                 set_memory_wb((unsigned long)dmab->area, pages);
 390 }
 391
 392 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 393                                  bool on)
 394 {
 395         __mark_pages_wc(chip, buf, on);
 396 }
 397 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 398                                    struct snd_pcm_substream *substream, bool on)
 399 {
 400         if (azx_dev->wc_marked != on) {
 401                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 402                 azx_dev->wc_marked = on;
 403         }
 404 }
 405 #else
 406 /* NOP for other archs */
 407 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 408                                  bool on)
 409 {
 410 }
 411 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 412                                    struct snd_pcm_substream *substream, bool on)
 413 {
 414 }
 415 #endif
 416
 417 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 418
 419 /*
 420  * initialize the PCI registers
 421  */
 422 /* update bits in a PCI register byte */
 423 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 424                             unsigned char mask, unsigned char val)
 425 {
 426         unsigned char data;
 427
 428         pci_read_config_byte(pci, reg, &data);
 429         data &= ~mask;
 430         data |= (val & mask);
 431         pci_write_config_byte(pci, reg, data);
 432 }
 433
 434 static void azx_init_pci(struct azx *chip)
 435 {
 436         int snoop_type = azx_get_snoop_type(chip);
 437
 438         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 439          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 440          * Ensuring these bits are 0 clears playback static on some HD Audio
 441          * codecs.
 442          * The PCI register TCSEL is defined in the Intel manuals.
 443          */
 444         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 445                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 446                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 447         }
 448
 449         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 450          * we need to enable snoop.
 451          */
 452         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 453                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 454                         azx_snoop(chip));
 455                 update_pci_byte(chip->pci,
 456                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 457                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 458         }
 459
 460         /* For NVIDIA HDA, enable snoop */
 461         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 462                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 463                         azx_snoop(chip));
 464                 update_pci_byte(chip->pci,
 465                                 NVIDIA_HDA_TRANSREG_ADDR,
 466                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 467                 update_pci_byte(chip->pci,
 468                                 NVIDIA_HDA_ISTRM_COH,
 469                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 470                 update_pci_byte(chip->pci,
 471                                 NVIDIA_HDA_OSTRM_COH,
 472                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 473         }
 474
 475         /* Enable SCH/PCH snoop if needed */
 476         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 477                 unsigned short snoop;
 478                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 479                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 480                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 481                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 482                         if (!azx_snoop(chip))
 483                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 484                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 485                         pci_read_config_word(chip->pci,
 486                                 INTEL_SCH_HDA_DEVC, &snoop);
 487                 }
 488                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 489                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 490                         "Disabled" : "Enabled");
 491         }
 492 }
 493
 494 /* calculate runtime delay from LPIB */
 495 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 496                                    unsigned int pos)
 497 {
 498         struct snd_pcm_substream *substream = azx_dev->core.substream;
 499         int stream = substream->stream;
 500         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 501         int delay;
 502
 503         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 504                 delay = pos - lpib_pos;
 505         else
 506                 delay = lpib_pos - pos;
 507         if (delay < 0) {
 508                 if (delay >= azx_dev->core.delay_negative_threshold)
 509                         delay = 0;
 510                 else
 511                         delay += azx_dev->core.bufsize;
 512         }
 513
 514         if (delay >= azx_dev->core.period_bytes) {
 515                 dev_info(chip->card->dev,
 516                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 517                          delay, azx_dev->core.period_bytes);
 518                 delay = 0;
 519                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 520                 chip->get_delay[stream] = NULL;
 521         }
 522
 523         return bytes_to_frames(substream->runtime, delay);
 524 }
 525
 526 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 527
 528 /* called from IRQ */
 529 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 530 {
 531         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 532         int ok;
 533
 534         ok = azx_position_ok(chip, azx_dev);
 535         if (ok == 1) {
 536                 azx_dev->irq_pending = 0;
 537                 return ok;
 538         } else if (ok == 0) {
 539                 /* bogus IRQ, process it later */
 540                 azx_dev->irq_pending = 1;
 541                 schedule_work(&hda->irq_pending_work);
 542         }
 543         return 0;
 544 }
 545
 546 /*
 547  * Check whether the current DMA position is acceptable for updating
 548  * periods.  Returns non-zero if it's OK.
 549  *
 550  * Many HD-audio controllers appear pretty inaccurate about
 551  * the update-IRQ timing.  The IRQ is issued before actually the
 552  * data is processed.  So, we need to process it afterwords in a
 553  * workqueue.
 554  */
 555 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 556 {
 557         struct snd_pcm_substream *substream = azx_dev->core.substream;
 558         int stream = substream->stream;
 559         u32 wallclk;
 560         unsigned int pos;
 561
 562         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 563         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 564                 return -1;      /* bogus (too early) interrupt */
 565
 566         if (chip->get_position[stream])
 567                 pos = chip->get_position[stream](chip, azx_dev);
 568         else { /* use the position buffer as default */
 569                 pos = azx_get_pos_posbuf(chip, azx_dev);
 570                 if (!pos || pos == (u32)-1) {
 571                         dev_info(chip->card->dev,
 572                                  "Invalid position buffer, using LPIB read method instead.\n");
 573                         chip->get_position[stream] = azx_get_pos_lpib;
 574                         if (chip->get_position[0] == azx_get_pos_lpib &&
 575                             chip->get_position[1] == azx_get_pos_lpib)
 576                                 azx_bus(chip)->use_posbuf = false;
 577                         pos = azx_get_pos_lpib(chip, azx_dev);
 578                         chip->get_delay[stream] = NULL;
 579                 } else {
 580                         chip->get_position[stream] = azx_get_pos_posbuf;
 581                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 582                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 583                 }
 584         }
 585
 586         if (pos >= azx_dev->core.bufsize)
 587                 pos = 0;
 588
 589         if (WARN_ONCE(!azx_dev->core.period_bytes,
 590                       "hda-intel: zero azx_dev->period_bytes"))
 591                 return -1; /* this shouldn't happen! */
 592         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 593             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 594                 /* NG - it's below the first next period boundary */
 595                 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
 596         azx_dev->core.start_wallclk += wallclk;
 597         return 1; /* OK, it's fine */
 598 }
 599
 600 /*
 601  * The work for pending PCM period updates.
 602  */
 603 static void azx_irq_pending_work(struct work_struct *work)
 604 {
 605         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 606         struct azx *chip = &hda->chip;
 607         struct hdac_bus *bus = azx_bus(chip);
 608         struct hdac_stream *s;
 609         int pending, ok;
 610
 611         if (!hda->irq_pending_warned) {
 612                 dev_info(chip->card->dev,
 613                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 614                          chip->card->number);
 615                 hda->irq_pending_warned = 1;
 616         }
 617
 618         for (;;) {
 619                 pending = 0;
 620                 spin_lock_irq(&bus->reg_lock);
 621                 list_for_each_entry(s, &bus->stream_list, list) {
 622                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 623                         if (!azx_dev->irq_pending ||
 624                             !s->substream ||
 625                             !s->running)
 626                                 continue;
 627                         ok = azx_position_ok(chip, azx_dev);
 628                         if (ok > 0) {
 629                                 azx_dev->irq_pending = 0;
 630                                 spin_unlock(&bus->reg_lock);
 631                                 snd_pcm_period_elapsed(s->substream);
 632                                 spin_lock(&bus->reg_lock);
 633                         } else if (ok < 0) {
 634                                 pending = 0;    /* too early */
 635                         } else
 636                                 pending++;
 637                 }
 638                 spin_unlock_irq(&bus->reg_lock);
 639                 if (!pending)
 640                         return;
 641                 msleep(1);
 642         }
 643 }
 644
 645 /* clear irq_pending flags and assure no on-going workq */
 646 static void azx_clear_irq_pending(struct azx *chip)
 647 {
 648         struct hdac_bus *bus = azx_bus(chip);
 649         struct hdac_stream *s;
 650
 651         spin_lock_irq(&bus->reg_lock);
 652         list_for_each_entry(s, &bus->stream_list, list) {
 653                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 654                 azx_dev->irq_pending = 0;
 655         }
 656         spin_unlock_irq(&bus->reg_lock);
 657 }
 658
 659 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 660 {
 661         struct hdac_bus *bus = azx_bus(chip);
 662
 663         if (request_irq(chip->pci->irq, azx_interrupt,
 664                         chip->msi ? 0 : IRQF_SHARED,
 665                         KBUILD_MODNAME, chip)) {
 666                 dev_err(chip->card->dev,
 667                         "unable to grab IRQ %d, disabling device\n",
 668                         chip->pci->irq);
 669                 if (do_disconnect)
 670                         snd_card_disconnect(chip->card);
 671                 return -1;
 672         }
 673         bus->irq = chip->pci->irq;
 674         pci_intx(chip->pci, !chip->msi);
 675         return 0;
 676 }
 677
 678 /* get the current DMA position with correction on VIA chips */
 679 static unsigned int azx_via_get_position(struct azx *chip,
 680                                          struct azx_dev *azx_dev)
 681 {
 682         unsigned int link_pos, mini_pos, bound_pos;
 683         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 684         unsigned int fifo_size;
 685
 686         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 687         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 688                 /* Playback, no problem using link position */
 689                 return link_pos;
 690         }
 691
 692         /* Capture */
 693         /* For new chipset,
 694          * use mod to get the DMA position just like old chipset
 695          */
 696         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 697         mod_dma_pos %= azx_dev->core.period_bytes;
 698
 699         /* azx_dev->fifo_size can't get FIFO size of in stream.
 700          * Get from base address + offset.
 701          */
 702         fifo_size = readw(azx_bus(chip)->remap_addr +
 703                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 704
 705         if (azx_dev->insufficient) {
 706                 /* Link position never gather than FIFO size */
 707                 if (link_pos <= fifo_size)
 708                         return 0;
 709
 710                 azx_dev->insufficient = 0;
 711         }
 712
 713         if (link_pos <= fifo_size)
 714                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 715         else
 716                 mini_pos = link_pos - fifo_size;
 717
 718         /* Find nearest previous boudary */
 719         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 720         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 721         if (mod_link_pos >= fifo_size)
 722                 bound_pos = link_pos - mod_link_pos;
 723         else if (mod_dma_pos >= mod_mini_pos)
 724                 bound_pos = mini_pos - mod_mini_pos;
 725         else {
 726                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 727                 if (bound_pos >= azx_dev->core.bufsize)
 728                         bound_pos = 0;
 729         }
 730
 731         /* Calculate real DMA position we want */
 732         return bound_pos + mod_dma_pos;
 733 }
 734
 735 #ifdef CONFIG_PM
 736 static DEFINE_MUTEX(card_list_lock);
 737 static LIST_HEAD(card_list);
 738
 739 static void azx_add_card_list(struct azx *chip)
 740 {
 741         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 742         mutex_lock(&card_list_lock);
 743         list_add(&hda->list, &card_list);
 744         mutex_unlock(&card_list_lock);
 745 }
 746
 747 static void azx_del_card_list(struct azx *chip)
 748 {
 749         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 750         mutex_lock(&card_list_lock);
 751         list_del_init(&hda->list);
 752         mutex_unlock(&card_list_lock);
 753 }
 754
 755 /* trigger power-save check at writing parameter */
 756 static int param_set_xint(const char *val, const struct kernel_param *kp)
 757 {
 758         struct hda_intel *hda;
 759         struct azx *chip;
 760         int prev = power_save;
 761         int ret = param_set_int(val, kp);
 762
 763         if (ret || prev == power_save)
 764                 return ret;
 765
 766         mutex_lock(&card_list_lock);
 767         list_for_each_entry(hda, &card_list, list) {
 768                 chip = &hda->chip;
 769                 if (!hda->probe_continued || chip->disabled)
 770                         continue;
 771                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 772         }
 773         mutex_unlock(&card_list_lock);
 774         return 0;
 775 }
 776 #else
 777 #define azx_add_card_list(chip) /* NOP */
 778 #define azx_del_card_list(chip) /* NOP */
 779 #endif /* CONFIG_PM */
 780
 781 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 782 /*
 783  * power management
 784  */
 785 static int azx_suspend(struct device *dev)
 786 {
 787         struct snd_card *card = dev_get_drvdata(dev);
 788         struct azx *chip;
 789         struct hda_intel *hda;
 790         struct hdac_bus *bus;
 791
 792         if (!card)
 793                 return 0;
 794
 795         chip = card->private_data;
 796         hda = container_of(chip, struct hda_intel, chip);
 797         if (chip->disabled || hda->init_failed)
 798                 return 0;
 799
 800         bus = azx_bus(chip);
 801         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 802         azx_clear_irq_pending(chip);
 803         azx_stop_chip(chip);
 804         azx_enter_link_reset(chip);
 805         if (bus->irq >= 0) {
 806                 free_irq(bus->irq, chip);
 807                 bus->irq = -1;
 808         }
 809
 810         if (chip->msi)
 811                 pci_disable_msi(chip->pci);
 812         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 813                 hda_display_power(hda, false);
 814         return 0;
 815 }
 816
 817 static int azx_resume(struct device *dev)
 818 {
 819         struct pci_dev *pci = to_pci_dev(dev);
 820         struct snd_card *card = dev_get_drvdata(dev);
 821         struct azx *chip;
 822         struct hda_intel *hda;
 823
 824         if (!card)
 825                 return 0;
 826
 827         chip = card->private_data;
 828         hda = container_of(chip, struct hda_intel, chip);
 829         if (chip->disabled || hda->init_failed)
 830                 return 0;
 831
 832         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 833                 hda_display_power(hda, true);
 834                 haswell_set_bclk(hda);
 835         }
 836         if (chip->msi)
 837                 if (pci_enable_msi(pci) < 0)
 838                         chip->msi = 0;
 839         if (azx_acquire_irq(chip, 1) < 0)
 840                 return -EIO;
 841         azx_init_pci(chip);
 842
 843         azx_init_chip(chip, true);
 844
 845         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 846         return 0;
 847 }
 848 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 849
 850 #ifdef CONFIG_PM
 851 static int azx_runtime_suspend(struct device *dev)
 852 {
 853         struct snd_card *card = dev_get_drvdata(dev);
 854         struct azx *chip;
 855         struct hda_intel *hda;
 856
 857         if (!card)
 858                 return 0;
 859
 860         chip = card->private_data;
 861         hda = container_of(chip, struct hda_intel, chip);
 862         if (chip->disabled || hda->init_failed)
 863                 return 0;
 864
 865         if (!azx_has_pm_runtime(chip))
 866                 return 0;
 867
 868         /* enable controller wake up event */
 869         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
 870                   STATESTS_INT_MASK);
 871
 872         azx_stop_chip(chip);
 873         azx_enter_link_reset(chip);
 874         azx_clear_irq_pending(chip);
 875         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 876                 hda_display_power(hda, false);
 877
 878         return 0;
 879 }
 880
 881 static int azx_runtime_resume(struct device *dev)
 882 {
 883         struct snd_card *card = dev_get_drvdata(dev);
 884         struct azx *chip;
 885         struct hda_intel *hda;
 886         struct hda_codec *codec;
 887         int status;
 888
 889         if (!card)
 890                 return 0;
 891
 892         chip = card->private_data;
 893         hda = container_of(chip, struct hda_intel, chip);
 894         if (chip->disabled || hda->init_failed)
 895                 return 0;
 896
 897         if (!azx_has_pm_runtime(chip))
 898                 return 0;
 899
 900         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 901                 hda_display_power(hda, true);
 902                 haswell_set_bclk(hda);
 903         }
 904
 905         /* Read STATESTS before controller reset */
 906         status = azx_readw(chip, STATESTS);
 907
 908         azx_init_pci(chip);
 909         azx_init_chip(chip, true);
 910
 911         if (status) {
 912                 list_for_each_codec(codec, &chip->bus)
 913                         if (status & (1 << codec->addr))
 914                                 schedule_delayed_work(&codec->jackpoll_work,
 915                                                       codec->jackpoll_interval);
 916         }
 917
 918         /* disable controller Wake Up event*/
 919         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
 920                         ~STATESTS_INT_MASK);
 921
 922         return 0;
 923 }
 924
 925 static int azx_runtime_idle(struct device *dev)
 926 {
 927         struct snd_card *card = dev_get_drvdata(dev);
 928         struct azx *chip;
 929         struct hda_intel *hda;
 930
 931         if (!card)
 932                 return 0;
 933
 934         chip = card->private_data;
 935         hda = container_of(chip, struct hda_intel, chip);
 936         if (chip->disabled || hda->init_failed)
 937                 return 0;
 938
 939         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
 940             azx_bus(chip)->codec_powered)
 941                 return -EBUSY;
 942
 943         return 0;
 944 }
 945
 946 static const struct dev_pm_ops azx_pm = {
 947         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
 948         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
 949 };
 950
 951 #define AZX_PM_OPS      &azx_pm
 952 #else
 953 #define AZX_PM_OPS      NULL
 954 #endif /* CONFIG_PM */
 955
 956
 957 static int azx_probe_continue(struct azx *chip);
 958
 959 #ifdef SUPPORT_VGA_SWITCHEROO
 960 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
 961
 962 static void azx_vs_set_state(struct pci_dev *pci,
 963                              enum vga_switcheroo_state state)
 964 {
 965         struct snd_card *card = pci_get_drvdata(pci);
 966         struct azx *chip = card->private_data;
 967         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 968         bool disabled;
 969
 970         wait_for_completion(&hda->probe_wait);
 971         if (hda->init_failed)
 972                 return;
 973
 974         disabled = (state == VGA_SWITCHEROO_OFF);
 975         if (chip->disabled == disabled)
 976                 return;
 977
 978         if (!hda->probe_continued) {
 979                 chip->disabled = disabled;
 980                 if (!disabled) {
 981                         dev_info(chip->card->dev,
 982                                  "Start delayed initialization\n");
 983                         if (azx_probe_continue(chip) < 0) {
 984                                 dev_err(chip->card->dev, "initialization error\n");
 985                                 hda->init_failed = true;
 986                         }
 987                 }
 988         } else {
 989                 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
 990                          disabled ? "Disabling" : "Enabling");
 991                 if (disabled) {
 992                         pm_runtime_put_sync_suspend(card->dev);
 993                         azx_suspend(card->dev);
 994                         /* when we get suspended by vga switcheroo we end up in D3cold,
 995                          * however we have no ACPI handle, so pci/acpi can't put us there,
 996                          * put ourselves there */
 997                         pci->current_state = PCI_D3cold;
 998                         chip->disabled = true;
 999                         if (snd_hda_lock_devices(&chip->bus))
1000                                 dev_warn(chip->card->dev,
1001                                          "Cannot lock devices!\n");
1002                 } else {
1003                         snd_hda_unlock_devices(&chip->bus);
1004                         pm_runtime_get_noresume(card->dev);
1005                         chip->disabled = false;
1006                         azx_resume(card->dev);
1007                 }
1008         }
1009 }
1010
1011 static bool azx_vs_can_switch(struct pci_dev *pci)
1012 {
1013         struct snd_card *card = pci_get_drvdata(pci);
1014         struct azx *chip = card->private_data;
1015         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1016
1017         wait_for_completion(&hda->probe_wait);
1018         if (hda->init_failed)
1019                 return false;
1020         if (chip->disabled || !hda->probe_continued)
1021                 return true;
1022         if (snd_hda_lock_devices(&chip->bus))
1023                 return false;
1024         snd_hda_unlock_devices(&chip->bus);
1025         return true;
1026 }
1027
1028 static void init_vga_switcheroo(struct azx *chip)
1029 {
1030         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1031         struct pci_dev *p = get_bound_vga(chip->pci);
1032         if (p) {
1033                 dev_info(chip->card->dev,
1034                          "Handle VGA-switcheroo audio client\n");
1035                 hda->use_vga_switcheroo = 1;
1036                 pci_dev_put(p);
1037         }
1038 }
1039
1040 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1041         .set_gpu_state = azx_vs_set_state,
1042         .can_switch = azx_vs_can_switch,
1043 };
1044
1045 static int register_vga_switcheroo(struct azx *chip)
1046 {
1047         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1048         int err;
1049
1050         if (!hda->use_vga_switcheroo)
1051                 return 0;
1052         /* FIXME: currently only handling DIS controller
1053          * is there any machine with two switchable HDMI audio controllers?
1054          */
1055         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1056                                                     VGA_SWITCHEROO_DIS,
1057                                                     hda->probe_continued);
1058         if (err < 0)
1059                 return err;
1060         hda->vga_switcheroo_registered = 1;
1061
1062         /* register as an optimus hdmi audio power domain */
1063         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1064                                                          &hda->hdmi_pm_domain);
1065         return 0;
1066 }
1067 #else
1068 #define init_vga_switcheroo(chip)               /* NOP */
1069 #define register_vga_switcheroo(chip)           0
1070 #define check_hdmi_disabled(pci)        false
1071 #endif /* SUPPORT_VGA_SWITCHER */
1072
1073 /*
1074  * destructor
1075  */
1076 static int azx_free(struct azx *chip)
1077 {
1078         struct pci_dev *pci = chip->pci;
1079         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1080         struct hdac_bus *bus = azx_bus(chip);
1081
1082         if (azx_has_pm_runtime(chip) && chip->running)
1083                 pm_runtime_get_noresume(&pci->dev);
1084
1085         azx_del_card_list(chip);
1086
1087         hda->init_failed = 1; /* to be sure */
1088         complete_all(&hda->probe_wait);
1089
1090         if (use_vga_switcheroo(hda)) {
1091                 if (chip->disabled && hda->probe_continued)
1092                         snd_hda_unlock_devices(&chip->bus);
1093                 if (hda->vga_switcheroo_registered)
1094                         vga_switcheroo_unregister_client(chip->pci);
1095         }
1096
1097         if (bus->chip_init) {
1098                 azx_clear_irq_pending(chip);
1099                 azx_stop_all_streams(chip);
1100                 azx_stop_chip(chip);
1101         }
1102
1103         if (bus->irq >= 0)
1104                 free_irq(bus->irq, (void*)chip);
1105         if (chip->msi)
1106                 pci_disable_msi(chip->pci);
1107         iounmap(bus->remap_addr);
1108
1109         azx_free_stream_pages(chip);
1110         azx_free_streams(chip);
1111         snd_hdac_bus_exit(bus);
1112
1113         if (chip->region_requested)
1114                 pci_release_regions(chip->pci);
1115
1116         pci_disable_device(chip->pci);
1117 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1118         release_firmware(chip->fw);
1119 #endif
1120         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1121                 hda_display_power(hda, false);
1122                 hda_i915_exit(hda);
1123         }
1124         kfree(hda);
1125
1126         return 0;
1127 }
1128
1129 static int azx_dev_disconnect(struct snd_device *device)
1130 {
1131         struct azx *chip = device->device_data;
1132
1133         chip->bus.shutdown = 1;
1134         return 0;
1135 }
1136
1137 static int azx_dev_free(struct snd_device *device)
1138 {
1139         return azx_free(device->device_data);
1140 }
1141
1142 #ifdef SUPPORT_VGA_SWITCHEROO
1143 /*
1144  * Check of disabled HDMI controller by vga-switcheroo
1145  */
1146 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1147 {
1148         struct pci_dev *p;
1149
1150         /* check only discrete GPU */
1151         switch (pci->vendor) {
1152         case PCI_VENDOR_ID_ATI:
1153         case PCI_VENDOR_ID_AMD:
1154         case PCI_VENDOR_ID_NVIDIA:
1155                 if (pci->devfn == 1) {
1156                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1157                                                         pci->bus->number, 0);
1158                         if (p) {
1159                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1160                                         return p;
1161                                 pci_dev_put(p);
1162                         }
1163                 }
1164                 break;
1165         }
1166         return NULL;
1167 }
1168
1169 static bool check_hdmi_disabled(struct pci_dev *pci)
1170 {
1171         bool vga_inactive = false;
1172         struct pci_dev *p = get_bound_vga(pci);
1173
1174         if (p) {
1175                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1176                         vga_inactive = true;
1177                 pci_dev_put(p);
1178         }
1179         return vga_inactive;
1180 }
1181 #endif /* SUPPORT_VGA_SWITCHEROO */
1182
1183 /*
1184  * white/black-listing for position_fix
1185  */
1186 static struct snd_pci_quirk position_fix_list[] = {
1187         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1188         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1189         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1190         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1191         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1192         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1193         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1194         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1195         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1196         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1197         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1198         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1199         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1200         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1201         {}
1202 };
1203
1204 static int check_position_fix(struct azx *chip, int fix)
1205 {
1206         const struct snd_pci_quirk *q;
1207
1208         switch (fix) {
1209         case POS_FIX_AUTO:
1210         case POS_FIX_LPIB:
1211         case POS_FIX_POSBUF:
1212         case POS_FIX_VIACOMBO:
1213         case POS_FIX_COMBO:
1214                 return fix;
1215         }
1216
1217         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1218         if (q) {
1219                 dev_info(chip->card->dev,
1220                          "position_fix set to %d for device %04x:%04x\n",
1221                          q->value, q->subvendor, q->subdevice);
1222                 return q->value;
1223         }
1224
1225         /* Check VIA/ATI HD Audio Controller exist */
1226         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1227                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1228                 return POS_FIX_VIACOMBO;
1229         }
1230         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1231                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1232                 return POS_FIX_LPIB;
1233         }
1234         return POS_FIX_AUTO;
1235 }
1236
1237 static void assign_position_fix(struct azx *chip, int fix)
1238 {
1239         static azx_get_pos_callback_t callbacks[] = {
1240                 [POS_FIX_AUTO] = NULL,
1241                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1242                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1243                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1244                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1245         };
1246
1247         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1248
1249         /* combo mode uses LPIB only for playback */
1250         if (fix == POS_FIX_COMBO)
1251                 chip->get_position[1] = NULL;
1252
1253         if (fix == POS_FIX_POSBUF &&
1254             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1255                 chip->get_delay[0] = chip->get_delay[1] =
1256                         azx_get_delay_from_lpib;
1257         }
1258
1259 }
1260
1261 /*
1262  * black-lists for probe_mask
1263  */
1264 static struct snd_pci_quirk probe_mask_list[] = {
1265         /* Thinkpad often breaks the controller communication when accessing
1266          * to the non-working (or non-existing) modem codec slot.
1267          */
1268         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1269         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1270         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1271         /* broken BIOS */
1272         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1273         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1274         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1275         /* forced codec slots */
1276         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1277         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1278         /* WinFast VP200 H (Teradici) user reported broken communication */
1279         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1280         {}
1281 };
1282
1283 #define AZX_FORCE_CODEC_MASK    0x100
1284
1285 static void check_probe_mask(struct azx *chip, int dev)
1286 {
1287         const struct snd_pci_quirk *q;
1288
1289         chip->codec_probe_mask = probe_mask[dev];
1290         if (chip->codec_probe_mask == -1) {
1291                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1292                 if (q) {
1293                         dev_info(chip->card->dev,
1294                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1295                                  q->value, q->subvendor, q->subdevice);
1296                         chip->codec_probe_mask = q->value;
1297                 }
1298         }
1299
1300         /* check forced option */
1301         if (chip->codec_probe_mask != -1 &&
1302             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1303                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1304                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1305                          (int)azx_bus(chip)->codec_mask);
1306         }
1307 }
1308
1309 /*
1310  * white/black-list for enable_msi
1311  */
1312 static struct snd_pci_quirk msi_black_list[] = {
1313         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1314         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1315         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1316         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1317         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1318         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1319         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1320         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1321         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1322         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1323         {}
1324 };
1325
1326 static void check_msi(struct azx *chip)
1327 {
1328         const struct snd_pci_quirk *q;
1329
1330         if (enable_msi >= 0) {
1331                 chip->msi = !!enable_msi;
1332                 return;
1333         }
1334         chip->msi = 1;  /* enable MSI as default */
1335         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1336         if (q) {
1337                 dev_info(chip->card->dev,
1338                          "msi for device %04x:%04x set to %d\n",
1339                          q->subvendor, q->subdevice, q->value);
1340                 chip->msi = q->value;
1341                 return;
1342         }
1343
1344         /* NVidia chipsets seem to cause troubles with MSI */
1345         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1346                 dev_info(chip->card->dev, "Disabling MSI\n");
1347                 chip->msi = 0;
1348         }
1349 }
1350
1351 /* check the snoop mode availability */
1352 static void azx_check_snoop_available(struct azx *chip)
1353 {
1354         int snoop = hda_snoop;
1355
1356         if (snoop >= 0) {
1357                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1358                          snoop ? "snoop" : "non-snoop");
1359                 chip->snoop = snoop;
1360                 return;
1361         }
1362
1363         snoop = true;
1364         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1365             chip->driver_type == AZX_DRIVER_VIA) {
1366                 /* force to non-snoop mode for a new VIA controller
1367                  * when BIOS is set
1368                  */
1369                 u8 val;
1370                 pci_read_config_byte(chip->pci, 0x42, &val);
1371                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1372                         snoop = false;
1373         }
1374
1375         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1376                 snoop = false;
1377
1378         chip->snoop = snoop;
1379         if (!snoop)
1380                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1381 }
1382
1383 static void azx_probe_work(struct work_struct *work)
1384 {
1385         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1386         azx_probe_continue(&hda->chip);
1387 }
1388
1389 /*
1390  * constructor
1391  */
1392 static const struct hdac_io_ops pci_hda_io_ops;
1393 static const struct hda_controller_ops pci_hda_ops;
1394
1395 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1396                       int dev, unsigned int driver_caps,
1397                       struct azx **rchip)
1398 {
1399         static struct snd_device_ops ops = {
1400                 .dev_disconnect = azx_dev_disconnect,
1401                 .dev_free = azx_dev_free,
1402         };
1403         struct hda_intel *hda;
1404         struct azx *chip;
1405         int err;
1406
1407         *rchip = NULL;
1408
1409         err = pci_enable_device(pci);
1410         if (err < 0)
1411                 return err;
1412
1413         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1414         if (!hda) {
1415                 pci_disable_device(pci);
1416                 return -ENOMEM;
1417         }
1418
1419         chip = &hda->chip;
1420         mutex_init(&chip->open_mutex);
1421         chip->card = card;
1422         chip->pci = pci;
1423         chip->ops = &pci_hda_ops;
1424         chip->driver_caps = driver_caps;
1425         chip->driver_type = driver_caps & 0xff;
1426         check_msi(chip);
1427         chip->dev_index = dev;
1428         chip->jackpoll_ms = jackpoll_ms;
1429         INIT_LIST_HEAD(&chip->pcm_list);
1430         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1431         INIT_LIST_HEAD(&hda->list);
1432         init_vga_switcheroo(chip);
1433         init_completion(&hda->probe_wait);
1434
1435         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1436
1437         check_probe_mask(chip, dev);
1438
1439         chip->single_cmd = single_cmd;
1440         azx_check_snoop_available(chip);
1441
1442         if (bdl_pos_adj[dev] < 0) {
1443                 switch (chip->driver_type) {
1444                 case AZX_DRIVER_ICH:
1445                 case AZX_DRIVER_PCH:
1446                         bdl_pos_adj[dev] = 1;
1447                         break;
1448                 default:
1449                         bdl_pos_adj[dev] = 32;
1450                         break;
1451                 }
1452         }
1453         chip->bdl_pos_adj = bdl_pos_adj;
1454
1455         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1456         if (err < 0) {
1457                 kfree(hda);
1458                 pci_disable_device(pci);
1459                 return err;
1460         }
1461
1462         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1463         if (err < 0) {
1464                 dev_err(card->dev, "Error creating device [card]!\n");
1465                 azx_free(chip);
1466                 return err;
1467         }
1468
1469         /* continue probing in work context as may trigger request module */
1470         INIT_WORK(&hda->probe_work, azx_probe_work);
1471
1472         *rchip = chip;
1473
1474         return 0;
1475 }
1476
1477 static int azx_first_init(struct azx *chip)
1478 {
1479         int dev = chip->dev_index;
1480         struct pci_dev *pci = chip->pci;
1481         struct snd_card *card = chip->card;
1482         struct hdac_bus *bus = azx_bus(chip);
1483         int err;
1484         unsigned short gcap;
1485         unsigned int dma_bits = 64;
1486
1487 #if BITS_PER_LONG != 64
1488         /* Fix up base address on ULI M5461 */
1489         if (chip->driver_type == AZX_DRIVER_ULI) {
1490                 u16 tmp3;
1491                 pci_read_config_word(pci, 0x40, &tmp3);
1492                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1493                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1494         }
1495 #endif
1496
1497         err = pci_request_regions(pci, "ICH HD audio");
1498         if (err < 0)
1499                 return err;
1500         chip->region_requested = 1;
1501
1502         bus->addr = pci_resource_start(pci, 0);
1503         bus->remap_addr = pci_ioremap_bar(pci, 0);
1504         if (bus->remap_addr == NULL) {
1505                 dev_err(card->dev, "ioremap error\n");
1506                 return -ENXIO;
1507         }
1508
1509         if (chip->msi) {
1510                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1511                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1512                         pci->no_64bit_msi = true;
1513                 }
1514                 if (pci_enable_msi(pci) < 0)
1515                         chip->msi = 0;
1516         }
1517
1518         if (azx_acquire_irq(chip, 0) < 0)
1519                 return -EBUSY;
1520
1521         pci_set_master(pci);
1522         synchronize_irq(bus->irq);
1523
1524         gcap = azx_readw(chip, GCAP);
1525         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1526
1527         /* AMD devices support 40 or 48bit DMA, take the safe one */
1528         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1529                 dma_bits = 40;
1530
1531         /* disable SB600 64bit support for safety */
1532         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1533                 struct pci_dev *p_smbus;
1534                 dma_bits = 40;
1535                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1536                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1537                                          NULL);
1538                 if (p_smbus) {
1539                         if (p_smbus->revision < 0x30)
1540                                 gcap &= ~AZX_GCAP_64OK;
1541                         pci_dev_put(p_smbus);
1542                 }
1543         }
1544
1545         /* disable 64bit DMA address on some devices */
1546         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1547                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1548                 gcap &= ~AZX_GCAP_64OK;
1549         }
1550
1551         /* disable buffer size rounding to 128-byte multiples if supported */
1552         if (align_buffer_size >= 0)
1553                 chip->align_buffer_size = !!align_buffer_size;
1554         else {
1555                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1556                         chip->align_buffer_size = 0;
1557                 else
1558                         chip->align_buffer_size = 1;
1559         }
1560
1561         /* allow 64bit DMA address if supported by H/W */
1562         if (!(gcap & AZX_GCAP_64OK))
1563                 dma_bits = 32;
1564         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1565                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1566         } else {
1567                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1568                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1569         }
1570
1571         /* read number of streams from GCAP register instead of using
1572          * hardcoded value
1573          */
1574         chip->capture_streams = (gcap >> 8) & 0x0f;
1575         chip->playback_streams = (gcap >> 12) & 0x0f;
1576         if (!chip->playback_streams && !chip->capture_streams) {
1577                 /* gcap didn't give any info, switching to old method */
1578
1579                 switch (chip->driver_type) {
1580                 case AZX_DRIVER_ULI:
1581                         chip->playback_streams = ULI_NUM_PLAYBACK;
1582                         chip->capture_streams = ULI_NUM_CAPTURE;
1583                         break;
1584                 case AZX_DRIVER_ATIHDMI:
1585                 case AZX_DRIVER_ATIHDMI_NS:
1586                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1587                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1588                         break;
1589                 case AZX_DRIVER_GENERIC:
1590                 default:
1591                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1592                         chip->capture_streams = ICH6_NUM_CAPTURE;
1593                         break;
1594                 }
1595         }
1596         chip->capture_index_offset = 0;
1597         chip->playback_index_offset = chip->capture_streams;
1598         chip->num_streams = chip->playback_streams + chip->capture_streams;
1599
1600         /* initialize streams */
1601         err = azx_init_streams(chip);
1602         if (err < 0)
1603                 return err;
1604
1605         err = azx_alloc_stream_pages(chip);
1606         if (err < 0)
1607                 return err;
1608
1609         /* initialize chip */
1610         azx_init_pci(chip);
1611
1612         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1613                 struct hda_intel *hda;
1614
1615                 hda = container_of(chip, struct hda_intel, chip);
1616                 haswell_set_bclk(hda);
1617         }
1618
1619         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1620
1621         /* codec detection */
1622         if (!azx_bus(chip)->codec_mask) {
1623                 dev_err(card->dev, "no codecs found!\n");
1624                 return -ENODEV;
1625         }
1626
1627         strcpy(card->driver, "HDA-Intel");
1628         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1629                 sizeof(card->shortname));
1630         snprintf(card->longname, sizeof(card->longname),
1631                  "%s at 0x%lx irq %i",
1632                  card->shortname, bus->addr, bus->irq);
1633
1634         return 0;
1635 }
1636
1637 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1638 /* callback from request_firmware_nowait() */
1639 static void azx_firmware_cb(const struct firmware *fw, void *context)
1640 {
1641         struct snd_card *card = context;
1642         struct azx *chip = card->private_data;
1643         struct pci_dev *pci = chip->pci;
1644
1645         if (!fw) {
1646                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1647                 goto error;
1648         }
1649
1650         chip->fw = fw;
1651         if (!chip->disabled) {
1652                 /* continue probing */
1653                 if (azx_probe_continue(chip))
1654                         goto error;
1655         }
1656         return; /* OK */
1657
1658  error:
1659         snd_card_free(card);
1660         pci_set_drvdata(pci, NULL);
1661 }
1662 #endif
1663
1664 /*
1665  * HDA controller ops.
1666  */
1667
1668 /* PCI register access. */
1669 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1670 {
1671         writel(value, addr);
1672 }
1673
1674 static u32 pci_azx_readl(u32 __iomem *addr)
1675 {
1676         return readl(addr);
1677 }
1678
1679 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1680 {
1681         writew(value, addr);
1682 }
1683
1684 static u16 pci_azx_readw(u16 __iomem *addr)
1685 {
1686         return readw(addr);
1687 }
1688
1689 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1690 {
1691         writeb(value, addr);
1692 }
1693
1694 static u8 pci_azx_readb(u8 __iomem *addr)
1695 {
1696         return readb(addr);
1697 }
1698
1699 static int disable_msi_reset_irq(struct azx *chip)
1700 {
1701         struct hdac_bus *bus = azx_bus(chip);
1702         int err;
1703
1704         free_irq(bus->irq, chip);
1705         bus->irq = -1;
1706         pci_disable_msi(chip->pci);
1707         chip->msi = 0;
1708         err = azx_acquire_irq(chip, 1);
1709         if (err < 0)
1710                 return err;
1711
1712         return 0;
1713 }
1714
1715 /* DMA page allocation helpers.  */
1716 static int dma_alloc_pages(struct hdac_bus *bus,
1717                            int type,
1718                            size_t size,
1719                            struct snd_dma_buffer *buf)
1720 {
1721         struct azx *chip = bus_to_azx(bus);
1722         int err;
1723
1724         err = snd_dma_alloc_pages(type,
1725                                   bus->dev,
1726                                   size, buf);
1727         if (err < 0)
1728                 return err;
1729         mark_pages_wc(chip, buf, true);
1730         return 0;
1731 }
1732
1733 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1734 {
1735         struct azx *chip = bus_to_azx(bus);
1736
1737         mark_pages_wc(chip, buf, false);
1738         snd_dma_free_pages(buf);
1739 }
1740
1741 static int substream_alloc_pages(struct azx *chip,
1742                                  struct snd_pcm_substream *substream,
1743                                  size_t size)
1744 {
1745         struct azx_dev *azx_dev = get_azx_dev(substream);
1746         int ret;
1747
1748         mark_runtime_wc(chip, azx_dev, substream, false);
1749         ret = snd_pcm_lib_malloc_pages(substream, size);
1750         if (ret < 0)
1751                 return ret;
1752         mark_runtime_wc(chip, azx_dev, substream, true);
1753         return 0;
1754 }
1755
1756 static int substream_free_pages(struct azx *chip,
1757                                 struct snd_pcm_substream *substream)
1758 {
1759         struct azx_dev *azx_dev = get_azx_dev(substream);
1760         mark_runtime_wc(chip, azx_dev, substream, false);
1761         return snd_pcm_lib_free_pages(substream);
1762 }
1763
1764 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1765                              struct vm_area_struct *area)
1766 {
1767 #ifdef CONFIG_X86
1768         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1769         struct azx *chip = apcm->chip;
1770         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1771                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1772 #endif
1773 }
1774
1775 static const struct hdac_io_ops pci_hda_io_ops = {
1776         .reg_writel = pci_azx_writel,
1777         .reg_readl = pci_azx_readl,
1778         .reg_writew = pci_azx_writew,
1779         .reg_readw = pci_azx_readw,
1780         .reg_writeb = pci_azx_writeb,
1781         .reg_readb = pci_azx_readb,
1782         .dma_alloc_pages = dma_alloc_pages,
1783         .dma_free_pages = dma_free_pages,
1784 };
1785
1786 static const struct hda_controller_ops pci_hda_ops = {
1787         .disable_msi_reset_irq = disable_msi_reset_irq,
1788         .substream_alloc_pages = substream_alloc_pages,
1789         .substream_free_pages = substream_free_pages,
1790         .pcm_mmap_prepare = pcm_mmap_prepare,
1791         .position_check = azx_position_check,
1792 };
1793
1794 static int azx_probe(struct pci_dev *pci,
1795                      const struct pci_device_id *pci_id)
1796 {
1797         static int dev;
1798         struct snd_card *card;
1799         struct hda_intel *hda;
1800         struct azx *chip;
1801         bool schedule_probe;
1802         int err;
1803
1804         if (dev >= SNDRV_CARDS)
1805                 return -ENODEV;
1806         if (!enable[dev]) {
1807                 dev++;
1808                 return -ENOENT;
1809         }
1810
1811         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1812                            0, &card);
1813         if (err < 0) {
1814                 dev_err(&pci->dev, "Error creating card!\n");
1815                 return err;
1816         }
1817
1818         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1819         if (err < 0)
1820                 goto out_free;
1821         card->private_data = chip;
1822         hda = container_of(chip, struct hda_intel, chip);
1823
1824         pci_set_drvdata(pci, card);
1825
1826         err = register_vga_switcheroo(chip);
1827         if (err < 0) {
1828                 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1829                 goto out_free;
1830         }
1831
1832         if (check_hdmi_disabled(pci)) {
1833                 dev_info(card->dev, "VGA controller is disabled\n");
1834                 dev_info(card->dev, "Delaying initialization\n");
1835                 chip->disabled = true;
1836         }
1837
1838         schedule_probe = !chip->disabled;
1839
1840 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1841         if (patch[dev] && *patch[dev]) {
1842                 dev_info(card->dev, "Applying patch firmware '%s'\n",
1843                          patch[dev]);
1844                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1845                                               &pci->dev, GFP_KERNEL, card,
1846                                               azx_firmware_cb);
1847                 if (err < 0)
1848                         goto out_free;
1849                 schedule_probe = false; /* continued in azx_firmware_cb() */
1850         }
1851 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1852
1853 #ifndef CONFIG_SND_HDA_I915
1854         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1855                 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1856 #endif
1857
1858         if (schedule_probe)
1859                 schedule_work(&hda->probe_work);
1860
1861         dev++;
1862         if (chip->disabled)
1863                 complete_all(&hda->probe_wait);
1864         return 0;
1865
1866 out_free:
1867         snd_card_free(card);
1868         return err;
1869 }
1870
1871 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1872 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1873         [AZX_DRIVER_NVIDIA] = 8,
1874         [AZX_DRIVER_TERA] = 1,
1875 };
1876
1877 static int azx_probe_continue(struct azx *chip)
1878 {
1879         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1880         struct pci_dev *pci = chip->pci;
1881         int dev = chip->dev_index;
1882         int err;
1883
1884         hda->probe_continued = 1;
1885         /* Request power well for Haswell HDA controller and codec */
1886         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1887 #ifdef CONFIG_SND_HDA_I915
1888                 err = hda_i915_init(hda);
1889                 if (err < 0)
1890                         goto out_free;
1891                 err = hda_display_power(hda, true);
1892                 if (err < 0) {
1893                         dev_err(chip->card->dev,
1894                                 "Cannot turn on display power on i915\n");
1895                         goto out_free;
1896                 }
1897 #endif
1898         }
1899
1900         err = azx_first_init(chip);
1901         if (err < 0)
1902                 goto out_free;
1903
1904 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1905         chip->beep_mode = beep_mode[dev];
1906 #endif
1907
1908         /* create codec instances */
1909         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
1910         if (err < 0)
1911                 goto out_free;
1912
1913 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1914         if (chip->fw) {
1915                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
1916                                          chip->fw->data);
1917                 if (err < 0)
1918                         goto out_free;
1919 #ifndef CONFIG_PM
1920                 release_firmware(chip->fw); /* no longer needed */
1921                 chip->fw = NULL;
1922 #endif
1923         }
1924 #endif
1925         if ((probe_only[dev] & 1) == 0) {
1926                 err = azx_codec_configure(chip);
1927                 if (err < 0)
1928                         goto out_free;
1929         }
1930
1931         err = snd_card_register(chip->card);
1932         if (err < 0)
1933                 goto out_free;
1934
1935         chip->running = 1;
1936         azx_add_card_list(chip);
1937         snd_hda_set_power_save(&chip->bus, power_save * 1000);
1938         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
1939                 pm_runtime_put_noidle(&pci->dev);
1940
1941 out_free:
1942         if (err < 0)
1943                 hda->init_failed = 1;
1944         complete_all(&hda->probe_wait);
1945         return err;
1946 }
1947
1948 static void azx_remove(struct pci_dev *pci)
1949 {
1950         struct snd_card *card = pci_get_drvdata(pci);
1951
1952         if (card)
1953                 snd_card_free(card);
1954 }
1955
1956 static void azx_shutdown(struct pci_dev *pci)
1957 {
1958         struct snd_card *card = pci_get_drvdata(pci);
1959         struct azx *chip;
1960
1961         if (!card)
1962                 return;
1963         chip = card->private_data;
1964         if (chip && chip->running)
1965                 azx_stop_chip(chip);
1966 }
1967
1968 /* PCI IDs */
1969 static const struct pci_device_id azx_ids[] = {
1970         /* CPT */
1971         { PCI_DEVICE(0x8086, 0x1c20),
1972           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1973         /* PBG */
1974         { PCI_DEVICE(0x8086, 0x1d20),
1975           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1976         /* Panther Point */
1977         { PCI_DEVICE(0x8086, 0x1e20),
1978           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1979         /* Lynx Point */
1980         { PCI_DEVICE(0x8086, 0x8c20),
1981           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1982         /* 9 Series */
1983         { PCI_DEVICE(0x8086, 0x8ca0),
1984           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1985         /* Wellsburg */
1986         { PCI_DEVICE(0x8086, 0x8d20),
1987           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1988         { PCI_DEVICE(0x8086, 0x8d21),
1989           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1990         /* Lynx Point-LP */
1991         { PCI_DEVICE(0x8086, 0x9c20),
1992           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1993         /* Lynx Point-LP */
1994         { PCI_DEVICE(0x8086, 0x9c21),
1995           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1996         /* Wildcat Point-LP */
1997         { PCI_DEVICE(0x8086, 0x9ca0),
1998           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1999         /* Sunrise Point */
2000         { PCI_DEVICE(0x8086, 0xa170),
2001           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2002         /* Sunrise Point-LP */
2003         { PCI_DEVICE(0x8086, 0x9d70),
2004           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2005         /* Haswell */
2006         { PCI_DEVICE(0x8086, 0x0a0c),
2007           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2008         { PCI_DEVICE(0x8086, 0x0c0c),
2009           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2010         { PCI_DEVICE(0x8086, 0x0d0c),
2011           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2012         /* Broadwell */
2013         { PCI_DEVICE(0x8086, 0x160c),
2014           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2015         /* 5 Series/3400 */
2016         { PCI_DEVICE(0x8086, 0x3b56),
2017           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2018         /* Poulsbo */
2019         { PCI_DEVICE(0x8086, 0x811b),
2020           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2021         /* Oaktrail */
2022         { PCI_DEVICE(0x8086, 0x080a),
2023           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2024         /* BayTrail */
2025         { PCI_DEVICE(0x8086, 0x0f04),
2026           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2027         /* Braswell */
2028         { PCI_DEVICE(0x8086, 0x2284),
2029           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2030         /* ICH6 */
2031         { PCI_DEVICE(0x8086, 0x2668),
2032           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2033         /* ICH7 */
2034         { PCI_DEVICE(0x8086, 0x27d8),
2035           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2036         /* ESB2 */
2037         { PCI_DEVICE(0x8086, 0x269a),
2038           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2039         /* ICH8 */
2040         { PCI_DEVICE(0x8086, 0x284b),
2041           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2042         /* ICH9 */
2043         { PCI_DEVICE(0x8086, 0x293e),
2044           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2045         /* ICH9 */
2046         { PCI_DEVICE(0x8086, 0x293f),
2047           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2048         /* ICH10 */
2049         { PCI_DEVICE(0x8086, 0x3a3e),
2050           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2051         /* ICH10 */
2052         { PCI_DEVICE(0x8086, 0x3a6e),
2053           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2054         /* Generic Intel */
2055         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2056           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2057           .class_mask = 0xffffff,
2058           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2059         /* ATI SB 450/600/700/800/900 */
2060         { PCI_DEVICE(0x1002, 0x437b),
2061           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2062         { PCI_DEVICE(0x1002, 0x4383),
2063           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2064         /* AMD Hudson */
2065         { PCI_DEVICE(0x1022, 0x780d),
2066           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2067         /* ATI HDMI */
2068         { PCI_DEVICE(0x1002, 0x793b),
2069           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2070         { PCI_DEVICE(0x1002, 0x7919),
2071           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2072         { PCI_DEVICE(0x1002, 0x960f),
2073           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2074         { PCI_DEVICE(0x1002, 0x970f),
2075           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2076         { PCI_DEVICE(0x1002, 0xaa00),
2077           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2078         { PCI_DEVICE(0x1002, 0xaa08),
2079           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2080         { PCI_DEVICE(0x1002, 0xaa10),
2081           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2082         { PCI_DEVICE(0x1002, 0xaa18),
2083           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2084         { PCI_DEVICE(0x1002, 0xaa20),
2085           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2086         { PCI_DEVICE(0x1002, 0xaa28),
2087           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2088         { PCI_DEVICE(0x1002, 0xaa30),
2089           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2090         { PCI_DEVICE(0x1002, 0xaa38),
2091           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2092         { PCI_DEVICE(0x1002, 0xaa40),
2093           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2094         { PCI_DEVICE(0x1002, 0xaa48),
2095           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2096         { PCI_DEVICE(0x1002, 0xaa50),
2097           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2098         { PCI_DEVICE(0x1002, 0xaa58),
2099           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2100         { PCI_DEVICE(0x1002, 0xaa60),
2101           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2102         { PCI_DEVICE(0x1002, 0xaa68),
2103           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2104         { PCI_DEVICE(0x1002, 0xaa80),
2105           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2106         { PCI_DEVICE(0x1002, 0xaa88),
2107           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2108         { PCI_DEVICE(0x1002, 0xaa90),
2109           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2110         { PCI_DEVICE(0x1002, 0xaa98),
2111           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2112         { PCI_DEVICE(0x1002, 0x9902),
2113           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2114         { PCI_DEVICE(0x1002, 0xaaa0),
2115           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2116         { PCI_DEVICE(0x1002, 0xaaa8),
2117           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2118         { PCI_DEVICE(0x1002, 0xaab0),
2119           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2120         /* VIA VT8251/VT8237A */
2121         { PCI_DEVICE(0x1106, 0x3288),
2122           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2123         /* VIA GFX VT7122/VX900 */
2124         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2125         /* VIA GFX VT6122/VX11 */
2126         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2127         /* SIS966 */
2128         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2129         /* ULI M5461 */
2130         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2131         /* NVIDIA MCP */
2132         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2133           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2134           .class_mask = 0xffffff,
2135           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2136         /* Teradici */
2137         { PCI_DEVICE(0x6549, 0x1200),
2138           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2139         { PCI_DEVICE(0x6549, 0x2200),
2140           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2141         /* Creative X-Fi (CA0110-IBG) */
2142         /* CTHDA chips */
2143         { PCI_DEVICE(0x1102, 0x0010),
2144           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2145         { PCI_DEVICE(0x1102, 0x0012),
2146           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2147 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2148         /* the following entry conflicts with snd-ctxfi driver,
2149          * as ctxfi driver mutates from HD-audio to native mode with
2150          * a special command sequence.
2151          */
2152         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2153           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2154           .class_mask = 0xffffff,
2155           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2156           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2157 #else
2158         /* this entry seems still valid -- i.e. without emu20kx chip */
2159         { PCI_DEVICE(0x1102, 0x0009),
2160           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2161           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2162 #endif
2163         /* CM8888 */
2164         { PCI_DEVICE(0x13f6, 0x5011),
2165           .driver_data = AZX_DRIVER_CMEDIA |
2166           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2167         /* Vortex86MX */
2168         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2169         /* VMware HDAudio */
2170         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2171         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2172         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2173           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2174           .class_mask = 0xffffff,
2175           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2176         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2177           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2178           .class_mask = 0xffffff,
2179           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2180         { 0, }
2181 };
2182 MODULE_DEVICE_TABLE(pci, azx_ids);
2183
2184 /* pci_driver definition */
2185 static struct pci_driver azx_driver = {
2186         .name = KBUILD_MODNAME,
2187         .id_table = azx_ids,
2188         .probe = azx_probe,
2189         .remove = azx_remove,
2190         .shutdown = azx_shutdown,
2191         .driver = {
2192                 .pm = AZX_PM_OPS,
2193         },
2194 };
2195
2196 module_pci_driver(azx_driver);