sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include "hda_codec.h"
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80 };
  81
  82 /* Defines for ATI HD Audio support in SB450 south bridge */
  83 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  84 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  85
  86 /* Defines for Nvidia HDA support */
  87 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  88 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  89 #define NVIDIA_HDA_ISTRM_COH          0x4d
  90 #define NVIDIA_HDA_OSTRM_COH          0x4c
  91 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  92
  93 /* Defines for Intel SCH HDA snoop control */
  94 #define INTEL_HDA_CGCTL  0x48
  95 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  96 #define INTEL_SCH_HDA_DEVC      0x78
  97 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  98
  99 /* Define IN stream 0 FIFO size offset in VIA controller */
 100 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 101 /* Define VIA HD Audio Device ID*/
 102 #define VIA_HDAC_DEVICE_ID              0x3288
 103
 104 /* max number of SDs */
 105 /* ICH, ATI and VIA have 4 playback and 4 capture */
 106 #define ICH6_NUM_CAPTURE        4
 107 #define ICH6_NUM_PLAYBACK       4
 108
 109 /* ULI has 6 playback and 5 capture */
 110 #define ULI_NUM_CAPTURE         5
 111 #define ULI_NUM_PLAYBACK        6
 112
 113 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 114 #define ATIHDMI_NUM_CAPTURE     0
 115 #define ATIHDMI_NUM_PLAYBACK    8
 116
 117 /* TERA has 4 playback and 3 capture */
 118 #define TERA_NUM_CAPTURE        3
 119 #define TERA_NUM_PLAYBACK       4
 120
 121
 122 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 123 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 124 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 125 static char *model[SNDRV_CARDS];
 126 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 127 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int probe_only[SNDRV_CARDS];
 130 static int jackpoll_ms[SNDRV_CARDS];
 131 static bool single_cmd;
 132 static int enable_msi = -1;
 133 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 134 static char *patch[SNDRV_CARDS];
 135 #endif
 136 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 137 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 138                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 139 #endif
 140
 141 module_param_array(index, int, NULL, 0444);
 142 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 143 module_param_array(id, charp, NULL, 0444);
 144 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 145 module_param_array(enable, bool, NULL, 0444);
 146 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 147 module_param_array(model, charp, NULL, 0444);
 148 MODULE_PARM_DESC(model, "Use the given board model.");
 149 module_param_array(position_fix, int, NULL, 0444);
 150 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 151                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 152 module_param_array(bdl_pos_adj, int, NULL, 0644);
 153 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 154 module_param_array(probe_mask, int, NULL, 0444);
 155 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 156 module_param_array(probe_only, int, NULL, 0444);
 157 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 158 module_param_array(jackpoll_ms, int, NULL, 0444);
 159 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 160 module_param(single_cmd, bool, 0444);
 161 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 162                  "(for debugging only).");
 163 module_param(enable_msi, bint, 0444);
 164 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 165 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 166 module_param_array(patch, charp, NULL, 0444);
 167 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 168 #endif
 169 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 170 module_param_array(beep_mode, bool, NULL, 0444);
 171 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 172                             "(0=off, 1=on) (default=1).");
 173 #endif
 174
 175 #ifdef CONFIG_PM
 176 static int param_set_xint(const char *val, const struct kernel_param *kp);
 177 static const struct kernel_param_ops param_ops_xint = {
 178         .set = param_set_xint,
 179         .get = param_get_int,
 180 };
 181 #define param_check_xint param_check_int
 182
 183 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 184 module_param(power_save, xint, 0644);
 185 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 186                  "(in second, 0 = disable).");
 187
 188 /* reset the HD-audio controller in power save mode.
 189  * this may give more power-saving, but will take longer time to
 190  * wake up.
 191  */
 192 static bool power_save_controller = 1;
 193 module_param(power_save_controller, bool, 0644);
 194 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 195 #else
 196 #define power_save      0
 197 #endif /* CONFIG_PM */
 198
 199 static int align_buffer_size = -1;
 200 module_param(align_buffer_size, bint, 0644);
 201 MODULE_PARM_DESC(align_buffer_size,
 202                 "Force buffer and period sizes to be multiple of 128 bytes.");
 203
 204 #ifdef CONFIG_X86
 205 static int hda_snoop = -1;
 206 module_param_named(snoop, hda_snoop, bint, 0444);
 207 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 208 #else
 209 #define hda_snoop               true
 210 #endif
 211
 212
 213 MODULE_LICENSE("GPL");
 214 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 215                          "{Intel, ICH6M},"
 216                          "{Intel, ICH7},"
 217                          "{Intel, ESB2},"
 218                          "{Intel, ICH8},"
 219                          "{Intel, ICH9},"
 220                          "{Intel, ICH10},"
 221                          "{Intel, PCH},"
 222                          "{Intel, CPT},"
 223                          "{Intel, PPT},"
 224                          "{Intel, LPT},"
 225                          "{Intel, LPT_LP},"
 226                          "{Intel, WPT_LP},"
 227                          "{Intel, SPT},"
 228                          "{Intel, SPT_LP},"
 229                          "{Intel, HPT},"
 230                          "{Intel, PBG},"
 231                          "{Intel, SCH},"
 232                          "{ATI, SB450},"
 233                          "{ATI, SB600},"
 234                          "{ATI, RS600},"
 235                          "{ATI, RS690},"
 236                          "{ATI, RS780},"
 237                          "{ATI, R600},"
 238                          "{ATI, RV630},"
 239                          "{ATI, RV610},"
 240                          "{ATI, RV670},"
 241                          "{ATI, RV635},"
 242                          "{ATI, RV620},"
 243                          "{ATI, RV770},"
 244                          "{VIA, VT8251},"
 245                          "{VIA, VT8237A},"
 246                          "{SiS, SIS966},"
 247                          "{ULI, M5461}}");
 248 MODULE_DESCRIPTION("Intel HDA driver");
 249
 250 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 251 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 252 #define SUPPORT_VGA_SWITCHEROO
 253 #endif
 254 #endif
 255
 256
 257 /*
 258  */
 259
 260 /* driver types */
 261 enum {
 262         AZX_DRIVER_ICH,
 263         AZX_DRIVER_PCH,
 264         AZX_DRIVER_SCH,
 265         AZX_DRIVER_HDMI,
 266         AZX_DRIVER_ATI,
 267         AZX_DRIVER_ATIHDMI,
 268         AZX_DRIVER_ATIHDMI_NS,
 269         AZX_DRIVER_VIA,
 270         AZX_DRIVER_SIS,
 271         AZX_DRIVER_ULI,
 272         AZX_DRIVER_NVIDIA,
 273         AZX_DRIVER_TERA,
 274         AZX_DRIVER_CTX,
 275         AZX_DRIVER_CTHDA,
 276         AZX_DRIVER_CMEDIA,
 277         AZX_DRIVER_GENERIC,
 278         AZX_NUM_DRIVERS, /* keep this as last entry */
 279 };
 280
 281 #define azx_get_snoop_type(chip) \
 282         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 283 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 284
 285 /* quirks for old Intel chipsets */
 286 #define AZX_DCAPS_INTEL_ICH \
 287         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 288
 289 /* quirks for Intel PCH */
 290 #define AZX_DCAPS_INTEL_PCH_BASE \
 291         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 292          AZX_DCAPS_SNOOP_TYPE(SCH))
 293
 294 /* PCH up to IVB; no runtime PM */
 295 #define AZX_DCAPS_INTEL_PCH_NOPM \
 296         (AZX_DCAPS_INTEL_PCH_BASE)
 297
 298 /* PCH for HSW/BDW; with runtime PM */
 299 #define AZX_DCAPS_INTEL_PCH \
 300         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 301
 302 /* HSW HDMI */
 303 #define AZX_DCAPS_INTEL_HASWELL \
 304         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 305          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 306          AZX_DCAPS_SNOOP_TYPE(SCH))
 307
 308 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 309 #define AZX_DCAPS_INTEL_BROADWELL \
 310         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 311          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 312          AZX_DCAPS_SNOOP_TYPE(SCH))
 313
 314 #define AZX_DCAPS_INTEL_BAYTRAIL \
 315         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 316
 317 #define AZX_DCAPS_INTEL_BRASWELL \
 318         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 319
 320 #define AZX_DCAPS_INTEL_SKYLAKE \
 321         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 322          AZX_DCAPS_I915_POWERWELL)
 323
 324 #define AZX_DCAPS_INTEL_BROXTON \
 325         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 326          AZX_DCAPS_I915_POWERWELL)
 327
 328 /* quirks for ATI SB / AMD Hudson */
 329 #define AZX_DCAPS_PRESET_ATI_SB \
 330         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 331          AZX_DCAPS_SNOOP_TYPE(ATI))
 332
 333 /* quirks for ATI/AMD HDMI */
 334 #define AZX_DCAPS_PRESET_ATI_HDMI \
 335         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 336          AZX_DCAPS_NO_MSI64)
 337
 338 /* quirks for ATI HDMI with snoop off */
 339 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 340         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 341
 342 /* quirks for Nvidia */
 343 #define AZX_DCAPS_PRESET_NVIDIA \
 344         (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
 345          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 346          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 347
 348 #define AZX_DCAPS_PRESET_CTHDA \
 349         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 350          AZX_DCAPS_NO_64BIT |\
 351          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 352
 353 /*
 354  * vga_switcheroo support
 355  */
 356 #ifdef SUPPORT_VGA_SWITCHEROO
 357 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 358 #else
 359 #define use_vga_switcheroo(chip)        0
 360 #endif
 361
 362 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 363                                         ((pci)->device == 0x0c0c) || \
 364                                         ((pci)->device == 0x0d0c) || \
 365                                         ((pci)->device == 0x160c))
 366
 367 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
 368 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
 369 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
 370 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
 371 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
 372 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 373 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
 374                         IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci)
 375
 376 static char *driver_short_names[] = {
 377         [AZX_DRIVER_ICH] = "HDA Intel",
 378         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 379         [AZX_DRIVER_SCH] = "HDA Intel MID",
 380         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 381         [AZX_DRIVER_ATI] = "HDA ATI SB",
 382         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 383         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 384         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 385         [AZX_DRIVER_SIS] = "HDA SIS966",
 386         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 387         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 388         [AZX_DRIVER_TERA] = "HDA Teradici",
 389         [AZX_DRIVER_CTX] = "HDA Creative",
 390         [AZX_DRIVER_CTHDA] = "HDA Creative",
 391         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 392         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 393 };
 394
 395 #ifdef CONFIG_X86
 396 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 397 {
 398         int pages;
 399
 400         if (azx_snoop(chip))
 401                 return;
 402         if (!dmab || !dmab->area || !dmab->bytes)
 403                 return;
 404
 405 #ifdef CONFIG_SND_DMA_SGBUF
 406         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 407                 struct snd_sg_buf *sgbuf = dmab->private_data;
 408                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 409                         return; /* deal with only CORB/RIRB buffers */
 410                 if (on)
 411                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 412                 else
 413                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 414                 return;
 415         }
 416 #endif
 417
 418         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 419         if (on)
 420                 set_memory_wc((unsigned long)dmab->area, pages);
 421         else
 422                 set_memory_wb((unsigned long)dmab->area, pages);
 423 }
 424
 425 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 426                                  bool on)
 427 {
 428         __mark_pages_wc(chip, buf, on);
 429 }
 430 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 431                                    struct snd_pcm_substream *substream, bool on)
 432 {
 433         if (azx_dev->wc_marked != on) {
 434                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 435                 azx_dev->wc_marked = on;
 436         }
 437 }
 438 #else
 439 /* NOP for other archs */
 440 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 441                                  bool on)
 442 {
 443 }
 444 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 445                                    struct snd_pcm_substream *substream, bool on)
 446 {
 447 }
 448 #endif
 449
 450 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 451
 452 /*
 453  * initialize the PCI registers
 454  */
 455 /* update bits in a PCI register byte */
 456 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 457                             unsigned char mask, unsigned char val)
 458 {
 459         unsigned char data;
 460
 461         pci_read_config_byte(pci, reg, &data);
 462         data &= ~mask;
 463         data |= (val & mask);
 464         pci_write_config_byte(pci, reg, data);
 465 }
 466
 467 static void azx_init_pci(struct azx *chip)
 468 {
 469         int snoop_type = azx_get_snoop_type(chip);
 470
 471         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 472          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 473          * Ensuring these bits are 0 clears playback static on some HD Audio
 474          * codecs.
 475          * The PCI register TCSEL is defined in the Intel manuals.
 476          */
 477         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 478                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 479                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 480         }
 481
 482         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 483          * we need to enable snoop.
 484          */
 485         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 486                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 487                         azx_snoop(chip));
 488                 update_pci_byte(chip->pci,
 489                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 490                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 491         }
 492
 493         /* For NVIDIA HDA, enable snoop */
 494         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 495                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 496                         azx_snoop(chip));
 497                 update_pci_byte(chip->pci,
 498                                 NVIDIA_HDA_TRANSREG_ADDR,
 499                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 500                 update_pci_byte(chip->pci,
 501                                 NVIDIA_HDA_ISTRM_COH,
 502                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 503                 update_pci_byte(chip->pci,
 504                                 NVIDIA_HDA_OSTRM_COH,
 505                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 506         }
 507
 508         /* Enable SCH/PCH snoop if needed */
 509         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 510                 unsigned short snoop;
 511                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 512                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 513                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 514                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 515                         if (!azx_snoop(chip))
 516                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 517                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 518                         pci_read_config_word(chip->pci,
 519                                 INTEL_SCH_HDA_DEVC, &snoop);
 520                 }
 521                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 522                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 523                         "Disabled" : "Enabled");
 524         }
 525 }
 526
 527 /*
 528  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 529  * and makes an audio stream sensitive to system latencies when
 530  * 24/32 bits are playing.
 531  * Adjusting threshold of DMA fifo to force the DMA request
 532  * sooner to improve latency tolerance at the expense of power.
 533  */
 534 static void bxt_reduce_dma_latency(struct azx *chip)
 535 {
 536         u32 val;
 537
 538         val = azx_readl(chip, SKL_EM4L);
 539         val &= (0x3 << 20);
 540         azx_writel(chip, SKL_EM4L, val);
 541 }
 542
 543 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 544 {
 545         struct hdac_bus *bus = azx_bus(chip);
 546         struct pci_dev *pci = chip->pci;
 547         u32 val;
 548
 549         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 550                 snd_hdac_set_codec_wakeup(bus, true);
 551         if (IS_SKL_PLUS(pci)) {
 552                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 553                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 554                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 555         }
 556         azx_init_chip(chip, full_reset);
 557         if (IS_SKL_PLUS(pci)) {
 558                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 559                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 560                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 561         }
 562         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 563                 snd_hdac_set_codec_wakeup(bus, false);
 564
 565         /* reduce dma latency to avoid noise */
 566         if (IS_BXT(pci))
 567                 bxt_reduce_dma_latency(chip);
 568 }
 569
 570 /* calculate runtime delay from LPIB */
 571 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 572                                    unsigned int pos)
 573 {
 574         struct snd_pcm_substream *substream = azx_dev->core.substream;
 575         int stream = substream->stream;
 576         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 577         int delay;
 578
 579         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 580                 delay = pos - lpib_pos;
 581         else
 582                 delay = lpib_pos - pos;
 583         if (delay < 0) {
 584                 if (delay >= azx_dev->core.delay_negative_threshold)
 585                         delay = 0;
 586                 else
 587                         delay += azx_dev->core.bufsize;
 588         }
 589
 590         if (delay >= azx_dev->core.period_bytes) {
 591                 dev_info(chip->card->dev,
 592                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 593                          delay, azx_dev->core.period_bytes);
 594                 delay = 0;
 595                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 596                 chip->get_delay[stream] = NULL;
 597         }
 598
 599         return bytes_to_frames(substream->runtime, delay);
 600 }
 601
 602 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 603
 604 /* called from IRQ */
 605 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 606 {
 607         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 608         int ok;
 609
 610         ok = azx_position_ok(chip, azx_dev);
 611         if (ok == 1) {
 612                 azx_dev->irq_pending = 0;
 613                 return ok;
 614         } else if (ok == 0) {
 615                 /* bogus IRQ, process it later */
 616                 azx_dev->irq_pending = 1;
 617                 schedule_work(&hda->irq_pending_work);
 618         }
 619         return 0;
 620 }
 621
 622 /* Enable/disable i915 display power for the link */
 623 static int azx_intel_link_power(struct azx *chip, bool enable)
 624 {
 625         struct hdac_bus *bus = azx_bus(chip);
 626
 627         return snd_hdac_display_power(bus, enable);
 628 }
 629
 630 /*
 631  * Check whether the current DMA position is acceptable for updating
 632  * periods.  Returns non-zero if it's OK.
 633  *
 634  * Many HD-audio controllers appear pretty inaccurate about
 635  * the update-IRQ timing.  The IRQ is issued before actually the
 636  * data is processed.  So, we need to process it afterwords in a
 637  * workqueue.
 638  */
 639 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 640 {
 641         struct snd_pcm_substream *substream = azx_dev->core.substream;
 642         int stream = substream->stream;
 643         u32 wallclk;
 644         unsigned int pos;
 645
 646         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 647         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 648                 return -1;      /* bogus (too early) interrupt */
 649
 650         if (chip->get_position[stream])
 651                 pos = chip->get_position[stream](chip, azx_dev);
 652         else { /* use the position buffer as default */
 653                 pos = azx_get_pos_posbuf(chip, azx_dev);
 654                 if (!pos || pos == (u32)-1) {
 655                         dev_info(chip->card->dev,
 656                                  "Invalid position buffer, using LPIB read method instead.\n");
 657                         chip->get_position[stream] = azx_get_pos_lpib;
 658                         if (chip->get_position[0] == azx_get_pos_lpib &&
 659                             chip->get_position[1] == azx_get_pos_lpib)
 660                                 azx_bus(chip)->use_posbuf = false;
 661                         pos = azx_get_pos_lpib(chip, azx_dev);
 662                         chip->get_delay[stream] = NULL;
 663                 } else {
 664                         chip->get_position[stream] = azx_get_pos_posbuf;
 665                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 666                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 667                 }
 668         }
 669
 670         if (pos >= azx_dev->core.bufsize)
 671                 pos = 0;
 672
 673         if (WARN_ONCE(!azx_dev->core.period_bytes,
 674                       "hda-intel: zero azx_dev->period_bytes"))
 675                 return -1; /* this shouldn't happen! */
 676         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 677             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 678                 /* NG - it's below the first next period boundary */
 679                 return chip->bdl_pos_adj ? 0 : -1;
 680         azx_dev->core.start_wallclk += wallclk;
 681         return 1; /* OK, it's fine */
 682 }
 683
 684 /*
 685  * The work for pending PCM period updates.
 686  */
 687 static void azx_irq_pending_work(struct work_struct *work)
 688 {
 689         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 690         struct azx *chip = &hda->chip;
 691         struct hdac_bus *bus = azx_bus(chip);
 692         struct hdac_stream *s;
 693         int pending, ok;
 694
 695         if (!hda->irq_pending_warned) {
 696                 dev_info(chip->card->dev,
 697                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 698                          chip->card->number);
 699                 hda->irq_pending_warned = 1;
 700         }
 701
 702         for (;;) {
 703                 pending = 0;
 704                 spin_lock_irq(&bus->reg_lock);
 705                 list_for_each_entry(s, &bus->stream_list, list) {
 706                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 707                         if (!azx_dev->irq_pending ||
 708                             !s->substream ||
 709                             !s->running)
 710                                 continue;
 711                         ok = azx_position_ok(chip, azx_dev);
 712                         if (ok > 0) {
 713                                 azx_dev->irq_pending = 0;
 714                                 spin_unlock(&bus->reg_lock);
 715                                 snd_pcm_period_elapsed(s->substream);
 716                                 spin_lock(&bus->reg_lock);
 717                         } else if (ok < 0) {
 718                                 pending = 0;    /* too early */
 719                         } else
 720                                 pending++;
 721                 }
 722                 spin_unlock_irq(&bus->reg_lock);
 723                 if (!pending)
 724                         return;
 725                 msleep(1);
 726         }
 727 }
 728
 729 /* clear irq_pending flags and assure no on-going workq */
 730 static void azx_clear_irq_pending(struct azx *chip)
 731 {
 732         struct hdac_bus *bus = azx_bus(chip);
 733         struct hdac_stream *s;
 734
 735         spin_lock_irq(&bus->reg_lock);
 736         list_for_each_entry(s, &bus->stream_list, list) {
 737                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 738                 azx_dev->irq_pending = 0;
 739         }
 740         spin_unlock_irq(&bus->reg_lock);
 741 }
 742
 743 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 744 {
 745         struct hdac_bus *bus = azx_bus(chip);
 746
 747         if (request_irq(chip->pci->irq, azx_interrupt,
 748                         chip->msi ? 0 : IRQF_SHARED,
 749                         chip->card->irq_descr, chip)) {
 750                 dev_err(chip->card->dev,
 751                         "unable to grab IRQ %d, disabling device\n",
 752                         chip->pci->irq);
 753                 if (do_disconnect)
 754                         snd_card_disconnect(chip->card);
 755                 return -1;
 756         }
 757         bus->irq = chip->pci->irq;
 758         pci_intx(chip->pci, !chip->msi);
 759         return 0;
 760 }
 761
 762 /* get the current DMA position with correction on VIA chips */
 763 static unsigned int azx_via_get_position(struct azx *chip,
 764                                          struct azx_dev *azx_dev)
 765 {
 766         unsigned int link_pos, mini_pos, bound_pos;
 767         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 768         unsigned int fifo_size;
 769
 770         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 771         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 772                 /* Playback, no problem using link position */
 773                 return link_pos;
 774         }
 775
 776         /* Capture */
 777         /* For new chipset,
 778          * use mod to get the DMA position just like old chipset
 779          */
 780         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 781         mod_dma_pos %= azx_dev->core.period_bytes;
 782
 783         /* azx_dev->fifo_size can't get FIFO size of in stream.
 784          * Get from base address + offset.
 785          */
 786         fifo_size = readw(azx_bus(chip)->remap_addr +
 787                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 788
 789         if (azx_dev->insufficient) {
 790                 /* Link position never gather than FIFO size */
 791                 if (link_pos <= fifo_size)
 792                         return 0;
 793
 794                 azx_dev->insufficient = 0;
 795         }
 796
 797         if (link_pos <= fifo_size)
 798                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 799         else
 800                 mini_pos = link_pos - fifo_size;
 801
 802         /* Find nearest previous boudary */
 803         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 804         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 805         if (mod_link_pos >= fifo_size)
 806                 bound_pos = link_pos - mod_link_pos;
 807         else if (mod_dma_pos >= mod_mini_pos)
 808                 bound_pos = mini_pos - mod_mini_pos;
 809         else {
 810                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 811                 if (bound_pos >= azx_dev->core.bufsize)
 812                         bound_pos = 0;
 813         }
 814
 815         /* Calculate real DMA position we want */
 816         return bound_pos + mod_dma_pos;
 817 }
 818
 819 #ifdef CONFIG_PM
 820 static DEFINE_MUTEX(card_list_lock);
 821 static LIST_HEAD(card_list);
 822
 823 static void azx_add_card_list(struct azx *chip)
 824 {
 825         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 826         mutex_lock(&card_list_lock);
 827         list_add(&hda->list, &card_list);
 828         mutex_unlock(&card_list_lock);
 829 }
 830
 831 static void azx_del_card_list(struct azx *chip)
 832 {
 833         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 834         mutex_lock(&card_list_lock);
 835         list_del_init(&hda->list);
 836         mutex_unlock(&card_list_lock);
 837 }
 838
 839 /* trigger power-save check at writing parameter */
 840 static int param_set_xint(const char *val, const struct kernel_param *kp)
 841 {
 842         struct hda_intel *hda;
 843         struct azx *chip;
 844         int prev = power_save;
 845         int ret = param_set_int(val, kp);
 846
 847         if (ret || prev == power_save)
 848                 return ret;
 849
 850         mutex_lock(&card_list_lock);
 851         list_for_each_entry(hda, &card_list, list) {
 852                 chip = &hda->chip;
 853                 if (!hda->probe_continued || chip->disabled)
 854                         continue;
 855                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 856         }
 857         mutex_unlock(&card_list_lock);
 858         return 0;
 859 }
 860 #else
 861 #define azx_add_card_list(chip) /* NOP */
 862 #define azx_del_card_list(chip) /* NOP */
 863 #endif /* CONFIG_PM */
 864
 865 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 866 /*
 867  * power management
 868  */
 869 static int azx_suspend(struct device *dev)
 870 {
 871         struct snd_card *card = dev_get_drvdata(dev);
 872         struct azx *chip;
 873         struct hda_intel *hda;
 874         struct hdac_bus *bus;
 875
 876         if (!card)
 877                 return 0;
 878
 879         chip = card->private_data;
 880         hda = container_of(chip, struct hda_intel, chip);
 881         if (chip->disabled || hda->init_failed || !chip->running)
 882                 return 0;
 883
 884         bus = azx_bus(chip);
 885         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 886         azx_clear_irq_pending(chip);
 887         azx_stop_chip(chip);
 888         azx_enter_link_reset(chip);
 889         if (bus->irq >= 0) {
 890                 free_irq(bus->irq, chip);
 891                 bus->irq = -1;
 892         }
 893
 894         if (chip->msi)
 895                 pci_disable_msi(chip->pci);
 896         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 897                 && hda->need_i915_power)
 898                 snd_hdac_display_power(bus, false);
 899
 900         trace_azx_suspend(chip);
 901         return 0;
 902 }
 903
 904 static int azx_resume(struct device *dev)
 905 {
 906         struct pci_dev *pci = to_pci_dev(dev);
 907         struct snd_card *card = dev_get_drvdata(dev);
 908         struct azx *chip;
 909         struct hda_intel *hda;
 910         struct hdac_bus *bus;
 911
 912         if (!card)
 913                 return 0;
 914
 915         chip = card->private_data;
 916         hda = container_of(chip, struct hda_intel, chip);
 917         bus = azx_bus(chip);
 918         if (chip->disabled || hda->init_failed || !chip->running)
 919                 return 0;
 920
 921         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 922                 snd_hdac_display_power(bus, true);
 923                 if (hda->need_i915_power)
 924                         snd_hdac_i915_set_bclk(bus);
 925         }
 926
 927         if (chip->msi)
 928                 if (pci_enable_msi(pci) < 0)
 929                         chip->msi = 0;
 930         if (azx_acquire_irq(chip, 1) < 0)
 931                 return -EIO;
 932         azx_init_pci(chip);
 933
 934         hda_intel_init_chip(chip, true);
 935
 936         /* power down again for link-controlled chips */
 937         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
 938             !hda->need_i915_power)
 939                 snd_hdac_display_power(bus, false);
 940
 941         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 942
 943         trace_azx_resume(chip);
 944         return 0;
 945 }
 946 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 947
 948 #ifdef CONFIG_PM_SLEEP
 949 /* put codec down to D3 at hibernation for Intel SKL+;
 950  * otherwise BIOS may still access the codec and screw up the driver
 951  */
 952 static int azx_freeze_noirq(struct device *dev)
 953 {
 954         struct pci_dev *pci = to_pci_dev(dev);
 955
 956         if (IS_SKL_PLUS(pci))
 957                 pci_set_power_state(pci, PCI_D3hot);
 958
 959         return 0;
 960 }
 961
 962 static int azx_thaw_noirq(struct device *dev)
 963 {
 964         struct pci_dev *pci = to_pci_dev(dev);
 965
 966         if (IS_SKL_PLUS(pci))
 967                 pci_set_power_state(pci, PCI_D0);
 968
 969         return 0;
 970 }
 971 #endif /* CONFIG_PM_SLEEP */
 972
 973 #ifdef CONFIG_PM
 974 static int azx_runtime_suspend(struct device *dev)
 975 {
 976         struct snd_card *card = dev_get_drvdata(dev);
 977         struct azx *chip;
 978         struct hda_intel *hda;
 979
 980         if (!card)
 981                 return 0;
 982
 983         chip = card->private_data;
 984         hda = container_of(chip, struct hda_intel, chip);
 985         if (chip->disabled || hda->init_failed)
 986                 return 0;
 987
 988         if (!azx_has_pm_runtime(chip))
 989                 return 0;
 990
 991         /* enable controller wake up event */
 992         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
 993                   STATESTS_INT_MASK);
 994
 995         azx_stop_chip(chip);
 996         azx_enter_link_reset(chip);
 997         azx_clear_irq_pending(chip);
 998         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 999                 && hda->need_i915_power)
1000                 snd_hdac_display_power(azx_bus(chip), false);
1001
1002         trace_azx_runtime_suspend(chip);
1003         return 0;
1004 }
1005
1006 static int azx_runtime_resume(struct device *dev)
1007 {
1008         struct snd_card *card = dev_get_drvdata(dev);
1009         struct azx *chip;
1010         struct hda_intel *hda;
1011         struct hdac_bus *bus;
1012         struct hda_codec *codec;
1013         int status;
1014
1015         if (!card)
1016                 return 0;
1017
1018         chip = card->private_data;
1019         hda = container_of(chip, struct hda_intel, chip);
1020         bus = azx_bus(chip);
1021         if (chip->disabled || hda->init_failed)
1022                 return 0;
1023
1024         if (!azx_has_pm_runtime(chip))
1025                 return 0;
1026
1027         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1028                 snd_hdac_display_power(bus, true);
1029                 if (hda->need_i915_power)
1030                         snd_hdac_i915_set_bclk(bus);
1031         }
1032
1033         /* Read STATESTS before controller reset */
1034         status = azx_readw(chip, STATESTS);
1035
1036         azx_init_pci(chip);
1037         hda_intel_init_chip(chip, true);
1038
1039         if (status) {
1040                 list_for_each_codec(codec, &chip->bus)
1041                         if (status & (1 << codec->addr))
1042                                 schedule_delayed_work(&codec->jackpoll_work,
1043                                                       codec->jackpoll_interval);
1044         }
1045
1046         /* disable controller Wake Up event*/
1047         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1048                         ~STATESTS_INT_MASK);
1049
1050         /* power down again for link-controlled chips */
1051         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1052             !hda->need_i915_power)
1053                 snd_hdac_display_power(bus, false);
1054
1055         trace_azx_runtime_resume(chip);
1056         return 0;
1057 }
1058
1059 static int azx_runtime_idle(struct device *dev)
1060 {
1061         struct snd_card *card = dev_get_drvdata(dev);
1062         struct azx *chip;
1063         struct hda_intel *hda;
1064
1065         if (!card)
1066                 return 0;
1067
1068         chip = card->private_data;
1069         hda = container_of(chip, struct hda_intel, chip);
1070         if (chip->disabled || hda->init_failed)
1071                 return 0;
1072
1073         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1074             azx_bus(chip)->codec_powered || !chip->running)
1075                 return -EBUSY;
1076
1077         return 0;
1078 }
1079
1080 static const struct dev_pm_ops azx_pm = {
1081         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1082 #ifdef CONFIG_PM_SLEEP
1083         .freeze_noirq = azx_freeze_noirq,
1084         .thaw_noirq = azx_thaw_noirq,
1085 #endif
1086         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1087 };
1088
1089 #define AZX_PM_OPS      &azx_pm
1090 #else
1091 #define AZX_PM_OPS      NULL
1092 #endif /* CONFIG_PM */
1093
1094
1095 static int azx_probe_continue(struct azx *chip);
1096
1097 #ifdef SUPPORT_VGA_SWITCHEROO
1098 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1099
1100 static void azx_vs_set_state(struct pci_dev *pci,
1101                              enum vga_switcheroo_state state)
1102 {
1103         struct snd_card *card = pci_get_drvdata(pci);
1104         struct azx *chip = card->private_data;
1105         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1106         bool disabled;
1107
1108         wait_for_completion(&hda->probe_wait);
1109         if (hda->init_failed)
1110                 return;
1111
1112         disabled = (state == VGA_SWITCHEROO_OFF);
1113         if (chip->disabled == disabled)
1114                 return;
1115
1116         if (!hda->probe_continued) {
1117                 chip->disabled = disabled;
1118                 if (!disabled) {
1119                         dev_info(chip->card->dev,
1120                                  "Start delayed initialization\n");
1121                         if (azx_probe_continue(chip) < 0) {
1122                                 dev_err(chip->card->dev, "initialization error\n");
1123                                 hda->init_failed = true;
1124                         }
1125                 }
1126         } else {
1127                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1128                          disabled ? "Disabling" : "Enabling");
1129                 if (disabled) {
1130                         pm_runtime_put_sync_suspend(card->dev);
1131                         azx_suspend(card->dev);
1132                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1133                          * however we have no ACPI handle, so pci/acpi can't put us there,
1134                          * put ourselves there */
1135                         pci->current_state = PCI_D3cold;
1136                         chip->disabled = true;
1137                         if (snd_hda_lock_devices(&chip->bus))
1138                                 dev_warn(chip->card->dev,
1139                                          "Cannot lock devices!\n");
1140                 } else {
1141                         snd_hda_unlock_devices(&chip->bus);
1142                         pm_runtime_get_noresume(card->dev);
1143                         chip->disabled = false;
1144                         azx_resume(card->dev);
1145                 }
1146         }
1147 }
1148
1149 static bool azx_vs_can_switch(struct pci_dev *pci)
1150 {
1151         struct snd_card *card = pci_get_drvdata(pci);
1152         struct azx *chip = card->private_data;
1153         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1154
1155         wait_for_completion(&hda->probe_wait);
1156         if (hda->init_failed)
1157                 return false;
1158         if (chip->disabled || !hda->probe_continued)
1159                 return true;
1160         if (snd_hda_lock_devices(&chip->bus))
1161                 return false;
1162         snd_hda_unlock_devices(&chip->bus);
1163         return true;
1164 }
1165
1166 static void init_vga_switcheroo(struct azx *chip)
1167 {
1168         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1169         struct pci_dev *p = get_bound_vga(chip->pci);
1170         if (p) {
1171                 dev_info(chip->card->dev,
1172                          "Handle vga_switcheroo audio client\n");
1173                 hda->use_vga_switcheroo = 1;
1174                 pci_dev_put(p);
1175         }
1176 }
1177
1178 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1179         .set_gpu_state = azx_vs_set_state,
1180         .can_switch = azx_vs_can_switch,
1181 };
1182
1183 static int register_vga_switcheroo(struct azx *chip)
1184 {
1185         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1186         int err;
1187
1188         if (!hda->use_vga_switcheroo)
1189                 return 0;
1190         /* FIXME: currently only handling DIS controller
1191          * is there any machine with two switchable HDMI audio controllers?
1192          */
1193         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1194                                                    VGA_SWITCHEROO_DIS);
1195         if (err < 0)
1196                 return err;
1197         hda->vga_switcheroo_registered = 1;
1198
1199         /* register as an optimus hdmi audio power domain */
1200         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1201                                                          &hda->hdmi_pm_domain);
1202         return 0;
1203 }
1204 #else
1205 #define init_vga_switcheroo(chip)               /* NOP */
1206 #define register_vga_switcheroo(chip)           0
1207 #define check_hdmi_disabled(pci)        false
1208 #endif /* SUPPORT_VGA_SWITCHER */
1209
1210 /*
1211  * destructor
1212  */
1213 static int azx_free(struct azx *chip)
1214 {
1215         struct pci_dev *pci = chip->pci;
1216         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1217         struct hdac_bus *bus = azx_bus(chip);
1218
1219         if (azx_has_pm_runtime(chip) && chip->running)
1220                 pm_runtime_get_noresume(&pci->dev);
1221
1222         azx_del_card_list(chip);
1223
1224         hda->init_failed = 1; /* to be sure */
1225         complete_all(&hda->probe_wait);
1226
1227         if (use_vga_switcheroo(hda)) {
1228                 if (chip->disabled && hda->probe_continued)
1229                         snd_hda_unlock_devices(&chip->bus);
1230                 if (hda->vga_switcheroo_registered) {
1231                         vga_switcheroo_unregister_client(chip->pci);
1232                         vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1233                 }
1234         }
1235
1236         if (bus->chip_init) {
1237                 azx_clear_irq_pending(chip);
1238                 azx_stop_all_streams(chip);
1239                 azx_stop_chip(chip);
1240         }
1241
1242         if (bus->irq >= 0)
1243                 free_irq(bus->irq, (void*)chip);
1244         if (chip->msi)
1245                 pci_disable_msi(chip->pci);
1246         iounmap(bus->remap_addr);
1247
1248         azx_free_stream_pages(chip);
1249         azx_free_streams(chip);
1250         snd_hdac_bus_exit(bus);
1251
1252         if (chip->region_requested)
1253                 pci_release_regions(chip->pci);
1254
1255         pci_disable_device(chip->pci);
1256 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1257         release_firmware(chip->fw);
1258 #endif
1259
1260         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1261                 if (hda->need_i915_power)
1262                         snd_hdac_display_power(bus, false);
1263                 snd_hdac_i915_exit(bus);
1264         }
1265         kfree(hda);
1266
1267         return 0;
1268 }
1269
1270 static int azx_dev_disconnect(struct snd_device *device)
1271 {
1272         struct azx *chip = device->device_data;
1273
1274         chip->bus.shutdown = 1;
1275         return 0;
1276 }
1277
1278 static int azx_dev_free(struct snd_device *device)
1279 {
1280         return azx_free(device->device_data);
1281 }
1282
1283 #ifdef SUPPORT_VGA_SWITCHEROO
1284 /*
1285  * Check of disabled HDMI controller by vga_switcheroo
1286  */
1287 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1288 {
1289         struct pci_dev *p;
1290
1291         /* check only discrete GPU */
1292         switch (pci->vendor) {
1293         case PCI_VENDOR_ID_ATI:
1294         case PCI_VENDOR_ID_AMD:
1295         case PCI_VENDOR_ID_NVIDIA:
1296                 if (pci->devfn == 1) {
1297                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1298                                                         pci->bus->number, 0);
1299                         if (p) {
1300                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1301                                         return p;
1302                                 pci_dev_put(p);
1303                         }
1304                 }
1305                 break;
1306         }
1307         return NULL;
1308 }
1309
1310 static bool check_hdmi_disabled(struct pci_dev *pci)
1311 {
1312         bool vga_inactive = false;
1313         struct pci_dev *p = get_bound_vga(pci);
1314
1315         if (p) {
1316                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1317                         vga_inactive = true;
1318                 pci_dev_put(p);
1319         }
1320         return vga_inactive;
1321 }
1322 #endif /* SUPPORT_VGA_SWITCHEROO */
1323
1324 /*
1325  * white/black-listing for position_fix
1326  */
1327 static struct snd_pci_quirk position_fix_list[] = {
1328         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1329         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1330         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1331         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1332         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1333         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1334         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1335         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1336         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1337         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1338         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1339         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1340         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1341         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1342         {}
1343 };
1344
1345 static int check_position_fix(struct azx *chip, int fix)
1346 {
1347         const struct snd_pci_quirk *q;
1348
1349         switch (fix) {
1350         case POS_FIX_AUTO:
1351         case POS_FIX_LPIB:
1352         case POS_FIX_POSBUF:
1353         case POS_FIX_VIACOMBO:
1354         case POS_FIX_COMBO:
1355                 return fix;
1356         }
1357
1358         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1359         if (q) {
1360                 dev_info(chip->card->dev,
1361                          "position_fix set to %d for device %04x:%04x\n",
1362                          q->value, q->subvendor, q->subdevice);
1363                 return q->value;
1364         }
1365
1366         /* Check VIA/ATI HD Audio Controller exist */
1367         if (chip->driver_type == AZX_DRIVER_VIA) {
1368                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1369                 return POS_FIX_VIACOMBO;
1370         }
1371         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1372                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1373                 return POS_FIX_LPIB;
1374         }
1375         return POS_FIX_AUTO;
1376 }
1377
1378 static void assign_position_fix(struct azx *chip, int fix)
1379 {
1380         static azx_get_pos_callback_t callbacks[] = {
1381                 [POS_FIX_AUTO] = NULL,
1382                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1383                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1384                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1385                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1386         };
1387
1388         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1389
1390         /* combo mode uses LPIB only for playback */
1391         if (fix == POS_FIX_COMBO)
1392                 chip->get_position[1] = NULL;
1393
1394         if (fix == POS_FIX_POSBUF &&
1395             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1396                 chip->get_delay[0] = chip->get_delay[1] =
1397                         azx_get_delay_from_lpib;
1398         }
1399
1400 }
1401
1402 /*
1403  * black-lists for probe_mask
1404  */
1405 static struct snd_pci_quirk probe_mask_list[] = {
1406         /* Thinkpad often breaks the controller communication when accessing
1407          * to the non-working (or non-existing) modem codec slot.
1408          */
1409         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1410         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1411         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1412         /* broken BIOS */
1413         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1414         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1415         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1416         /* forced codec slots */
1417         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1418         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1419         /* WinFast VP200 H (Teradici) user reported broken communication */
1420         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1421         {}
1422 };
1423
1424 #define AZX_FORCE_CODEC_MASK    0x100
1425
1426 static void check_probe_mask(struct azx *chip, int dev)
1427 {
1428         const struct snd_pci_quirk *q;
1429
1430         chip->codec_probe_mask = probe_mask[dev];
1431         if (chip->codec_probe_mask == -1) {
1432                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1433                 if (q) {
1434                         dev_info(chip->card->dev,
1435                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1436                                  q->value, q->subvendor, q->subdevice);
1437                         chip->codec_probe_mask = q->value;
1438                 }
1439         }
1440
1441         /* check forced option */
1442         if (chip->codec_probe_mask != -1 &&
1443             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1444                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1445                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1446                          (int)azx_bus(chip)->codec_mask);
1447         }
1448 }
1449
1450 /*
1451  * white/black-list for enable_msi
1452  */
1453 static struct snd_pci_quirk msi_black_list[] = {
1454         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1455         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1456         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1457         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1458         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1459         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1460         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1461         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1462         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1463         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1464         {}
1465 };
1466
1467 static void check_msi(struct azx *chip)
1468 {
1469         const struct snd_pci_quirk *q;
1470
1471         if (enable_msi >= 0) {
1472                 chip->msi = !!enable_msi;
1473                 return;
1474         }
1475         chip->msi = 1;  /* enable MSI as default */
1476         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1477         if (q) {
1478                 dev_info(chip->card->dev,
1479                          "msi for device %04x:%04x set to %d\n",
1480                          q->subvendor, q->subdevice, q->value);
1481                 chip->msi = q->value;
1482                 return;
1483         }
1484
1485         /* NVidia chipsets seem to cause troubles with MSI */
1486         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1487                 dev_info(chip->card->dev, "Disabling MSI\n");
1488                 chip->msi = 0;
1489         }
1490 }
1491
1492 /* check the snoop mode availability */
1493 static void azx_check_snoop_available(struct azx *chip)
1494 {
1495         int snoop = hda_snoop;
1496
1497         if (snoop >= 0) {
1498                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1499                          snoop ? "snoop" : "non-snoop");
1500                 chip->snoop = snoop;
1501                 return;
1502         }
1503
1504         snoop = true;
1505         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1506             chip->driver_type == AZX_DRIVER_VIA) {
1507                 /* force to non-snoop mode for a new VIA controller
1508                  * when BIOS is set
1509                  */
1510                 u8 val;
1511                 pci_read_config_byte(chip->pci, 0x42, &val);
1512                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1513                         snoop = false;
1514         }
1515
1516         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1517                 snoop = false;
1518
1519         chip->snoop = snoop;
1520         if (!snoop)
1521                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1522 }
1523
1524 static void azx_probe_work(struct work_struct *work)
1525 {
1526         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1527         azx_probe_continue(&hda->chip);
1528 }
1529
1530 static int default_bdl_pos_adj(struct azx *chip)
1531 {
1532         /* some exceptions: Atoms seem problematic with value 1 */
1533         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1534                 switch (chip->pci->device) {
1535                 case 0x0f04: /* Baytrail */
1536                 case 0x2284: /* Braswell */
1537                         return 32;
1538                 }
1539         }
1540
1541         switch (chip->driver_type) {
1542         case AZX_DRIVER_ICH:
1543         case AZX_DRIVER_PCH:
1544                 return 1;
1545         default:
1546                 return 32;
1547         }
1548 }
1549
1550 /*
1551  * constructor
1552  */
1553 static const struct hdac_io_ops pci_hda_io_ops;
1554 static const struct hda_controller_ops pci_hda_ops;
1555
1556 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1557                       int dev, unsigned int driver_caps,
1558                       struct azx **rchip)
1559 {
1560         static struct snd_device_ops ops = {
1561                 .dev_disconnect = azx_dev_disconnect,
1562                 .dev_free = azx_dev_free,
1563         };
1564         struct hda_intel *hda;
1565         struct azx *chip;
1566         int err;
1567
1568         *rchip = NULL;
1569
1570         err = pci_enable_device(pci);
1571         if (err < 0)
1572                 return err;
1573
1574         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1575         if (!hda) {
1576                 pci_disable_device(pci);
1577                 return -ENOMEM;
1578         }
1579
1580         chip = &hda->chip;
1581         mutex_init(&chip->open_mutex);
1582         chip->card = card;
1583         chip->pci = pci;
1584         chip->ops = &pci_hda_ops;
1585         chip->driver_caps = driver_caps;
1586         chip->driver_type = driver_caps & 0xff;
1587         check_msi(chip);
1588         chip->dev_index = dev;
1589         chip->jackpoll_ms = jackpoll_ms;
1590         INIT_LIST_HEAD(&chip->pcm_list);
1591         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1592         INIT_LIST_HEAD(&hda->list);
1593         init_vga_switcheroo(chip);
1594         init_completion(&hda->probe_wait);
1595
1596         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1597
1598         check_probe_mask(chip, dev);
1599
1600         chip->single_cmd = single_cmd;
1601         azx_check_snoop_available(chip);
1602
1603         if (bdl_pos_adj[dev] < 0)
1604                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1605         else
1606                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1607
1608         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1609         if (err < 0) {
1610                 kfree(hda);
1611                 pci_disable_device(pci);
1612                 return err;
1613         }
1614
1615         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1616                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1617                 chip->bus.needs_damn_long_delay = 1;
1618         }
1619
1620         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1621         if (err < 0) {
1622                 dev_err(card->dev, "Error creating device [card]!\n");
1623                 azx_free(chip);
1624                 return err;
1625         }
1626
1627         /* continue probing in work context as may trigger request module */
1628         INIT_WORK(&hda->probe_work, azx_probe_work);
1629
1630         *rchip = chip;
1631
1632         return 0;
1633 }
1634
1635 static int azx_first_init(struct azx *chip)
1636 {
1637         int dev = chip->dev_index;
1638         struct pci_dev *pci = chip->pci;
1639         struct snd_card *card = chip->card;
1640         struct hdac_bus *bus = azx_bus(chip);
1641         int err;
1642         unsigned short gcap;
1643         unsigned int dma_bits = 64;
1644
1645 #if BITS_PER_LONG != 64
1646         /* Fix up base address on ULI M5461 */
1647         if (chip->driver_type == AZX_DRIVER_ULI) {
1648                 u16 tmp3;
1649                 pci_read_config_word(pci, 0x40, &tmp3);
1650                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1651                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1652         }
1653 #endif
1654
1655         err = pci_request_regions(pci, "ICH HD audio");
1656         if (err < 0)
1657                 return err;
1658         chip->region_requested = 1;
1659
1660         bus->addr = pci_resource_start(pci, 0);
1661         bus->remap_addr = pci_ioremap_bar(pci, 0);
1662         if (bus->remap_addr == NULL) {
1663                 dev_err(card->dev, "ioremap error\n");
1664                 return -ENXIO;
1665         }
1666
1667         if (IS_SKL_PLUS(pci))
1668                 snd_hdac_bus_parse_capabilities(bus);
1669
1670         /*
1671          * Some Intel CPUs has always running timer (ART) feature and
1672          * controller may have Global time sync reporting capability, so
1673          * check both of these before declaring synchronized time reporting
1674          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1675          */
1676         chip->gts_present = false;
1677
1678 #ifdef CONFIG_X86
1679         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1680                 chip->gts_present = true;
1681 #endif
1682
1683         if (chip->msi) {
1684                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1685                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1686                         pci->no_64bit_msi = true;
1687                 }
1688                 if (pci_enable_msi(pci) < 0)
1689                         chip->msi = 0;
1690         }
1691
1692         if (azx_acquire_irq(chip, 0) < 0)
1693                 return -EBUSY;
1694
1695         pci_set_master(pci);
1696         synchronize_irq(bus->irq);
1697
1698         gcap = azx_readw(chip, GCAP);
1699         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1700
1701         /* AMD devices support 40 or 48bit DMA, take the safe one */
1702         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1703                 dma_bits = 40;
1704
1705         /* disable SB600 64bit support for safety */
1706         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1707                 struct pci_dev *p_smbus;
1708                 dma_bits = 40;
1709                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1710                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1711                                          NULL);
1712                 if (p_smbus) {
1713                         if (p_smbus->revision < 0x30)
1714                                 gcap &= ~AZX_GCAP_64OK;
1715                         pci_dev_put(p_smbus);
1716                 }
1717         }
1718
1719         /* disable 64bit DMA address on some devices */
1720         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1721                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1722                 gcap &= ~AZX_GCAP_64OK;
1723         }
1724
1725         /* disable buffer size rounding to 128-byte multiples if supported */
1726         if (align_buffer_size >= 0)
1727                 chip->align_buffer_size = !!align_buffer_size;
1728         else {
1729                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1730                         chip->align_buffer_size = 0;
1731                 else
1732                         chip->align_buffer_size = 1;
1733         }
1734
1735         /* allow 64bit DMA address if supported by H/W */
1736         if (!(gcap & AZX_GCAP_64OK))
1737                 dma_bits = 32;
1738         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1739                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1740         } else {
1741                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1742                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1743         }
1744
1745         /* read number of streams from GCAP register instead of using
1746          * hardcoded value
1747          */
1748         chip->capture_streams = (gcap >> 8) & 0x0f;
1749         chip->playback_streams = (gcap >> 12) & 0x0f;
1750         if (!chip->playback_streams && !chip->capture_streams) {
1751                 /* gcap didn't give any info, switching to old method */
1752
1753                 switch (chip->driver_type) {
1754                 case AZX_DRIVER_ULI:
1755                         chip->playback_streams = ULI_NUM_PLAYBACK;
1756                         chip->capture_streams = ULI_NUM_CAPTURE;
1757                         break;
1758                 case AZX_DRIVER_ATIHDMI:
1759                 case AZX_DRIVER_ATIHDMI_NS:
1760                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1761                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1762                         break;
1763                 case AZX_DRIVER_GENERIC:
1764                 default:
1765                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1766                         chip->capture_streams = ICH6_NUM_CAPTURE;
1767                         break;
1768                 }
1769         }
1770         chip->capture_index_offset = 0;
1771         chip->playback_index_offset = chip->capture_streams;
1772         chip->num_streams = chip->playback_streams + chip->capture_streams;
1773
1774         /* initialize streams */
1775         err = azx_init_streams(chip);
1776         if (err < 0)
1777                 return err;
1778
1779         err = azx_alloc_stream_pages(chip);
1780         if (err < 0)
1781                 return err;
1782
1783         /* initialize chip */
1784         azx_init_pci(chip);
1785
1786         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1787                 snd_hdac_i915_set_bclk(bus);
1788
1789         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1790
1791         /* codec detection */
1792         if (!azx_bus(chip)->codec_mask) {
1793                 dev_err(card->dev, "no codecs found!\n");
1794                 return -ENODEV;
1795         }
1796
1797         strcpy(card->driver, "HDA-Intel");
1798         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1799                 sizeof(card->shortname));
1800         snprintf(card->longname, sizeof(card->longname),
1801                  "%s at 0x%lx irq %i",
1802                  card->shortname, bus->addr, bus->irq);
1803
1804         return 0;
1805 }
1806
1807 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1808 /* callback from request_firmware_nowait() */
1809 static void azx_firmware_cb(const struct firmware *fw, void *context)
1810 {
1811         struct snd_card *card = context;
1812         struct azx *chip = card->private_data;
1813         struct pci_dev *pci = chip->pci;
1814
1815         if (!fw) {
1816                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1817                 goto error;
1818         }
1819
1820         chip->fw = fw;
1821         if (!chip->disabled) {
1822                 /* continue probing */
1823                 if (azx_probe_continue(chip))
1824                         goto error;
1825         }
1826         return; /* OK */
1827
1828  error:
1829         snd_card_free(card);
1830         pci_set_drvdata(pci, NULL);
1831 }
1832 #endif
1833
1834 /*
1835  * HDA controller ops.
1836  */
1837
1838 /* PCI register access. */
1839 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1840 {
1841         writel(value, addr);
1842 }
1843
1844 static u32 pci_azx_readl(u32 __iomem *addr)
1845 {
1846         return readl(addr);
1847 }
1848
1849 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1850 {
1851         writew(value, addr);
1852 }
1853
1854 static u16 pci_azx_readw(u16 __iomem *addr)
1855 {
1856         return readw(addr);
1857 }
1858
1859 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1860 {
1861         writeb(value, addr);
1862 }
1863
1864 static u8 pci_azx_readb(u8 __iomem *addr)
1865 {
1866         return readb(addr);
1867 }
1868
1869 static int disable_msi_reset_irq(struct azx *chip)
1870 {
1871         struct hdac_bus *bus = azx_bus(chip);
1872         int err;
1873
1874         free_irq(bus->irq, chip);
1875         bus->irq = -1;
1876         pci_disable_msi(chip->pci);
1877         chip->msi = 0;
1878         err = azx_acquire_irq(chip, 1);
1879         if (err < 0)
1880                 return err;
1881
1882         return 0;
1883 }
1884
1885 /* DMA page allocation helpers.  */
1886 static int dma_alloc_pages(struct hdac_bus *bus,
1887                            int type,
1888                            size_t size,
1889                            struct snd_dma_buffer *buf)
1890 {
1891         struct azx *chip = bus_to_azx(bus);
1892         int err;
1893
1894         err = snd_dma_alloc_pages(type,
1895                                   bus->dev,
1896                                   size, buf);
1897         if (err < 0)
1898                 return err;
1899         mark_pages_wc(chip, buf, true);
1900         return 0;
1901 }
1902
1903 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1904 {
1905         struct azx *chip = bus_to_azx(bus);
1906
1907         mark_pages_wc(chip, buf, false);
1908         snd_dma_free_pages(buf);
1909 }
1910
1911 static int substream_alloc_pages(struct azx *chip,
1912                                  struct snd_pcm_substream *substream,
1913                                  size_t size)
1914 {
1915         struct azx_dev *azx_dev = get_azx_dev(substream);
1916         int ret;
1917
1918         mark_runtime_wc(chip, azx_dev, substream, false);
1919         ret = snd_pcm_lib_malloc_pages(substream, size);
1920         if (ret < 0)
1921                 return ret;
1922         mark_runtime_wc(chip, azx_dev, substream, true);
1923         return 0;
1924 }
1925
1926 static int substream_free_pages(struct azx *chip,
1927                                 struct snd_pcm_substream *substream)
1928 {
1929         struct azx_dev *azx_dev = get_azx_dev(substream);
1930         mark_runtime_wc(chip, azx_dev, substream, false);
1931         return snd_pcm_lib_free_pages(substream);
1932 }
1933
1934 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1935                              struct vm_area_struct *area)
1936 {
1937 #ifdef CONFIG_X86
1938         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1939         struct azx *chip = apcm->chip;
1940         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1941                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1942 #endif
1943 }
1944
1945 static const struct hdac_io_ops pci_hda_io_ops = {
1946         .reg_writel = pci_azx_writel,
1947         .reg_readl = pci_azx_readl,
1948         .reg_writew = pci_azx_writew,
1949         .reg_readw = pci_azx_readw,
1950         .reg_writeb = pci_azx_writeb,
1951         .reg_readb = pci_azx_readb,
1952         .dma_alloc_pages = dma_alloc_pages,
1953         .dma_free_pages = dma_free_pages,
1954 };
1955
1956 static const struct hda_controller_ops pci_hda_ops = {
1957         .disable_msi_reset_irq = disable_msi_reset_irq,
1958         .substream_alloc_pages = substream_alloc_pages,
1959         .substream_free_pages = substream_free_pages,
1960         .pcm_mmap_prepare = pcm_mmap_prepare,
1961         .position_check = azx_position_check,
1962         .link_power = azx_intel_link_power,
1963 };
1964
1965 static int azx_probe(struct pci_dev *pci,
1966                      const struct pci_device_id *pci_id)
1967 {
1968         static int dev;
1969         struct snd_card *card;
1970         struct hda_intel *hda;
1971         struct azx *chip;
1972         bool schedule_probe;
1973         int err;
1974
1975         if (dev >= SNDRV_CARDS)
1976                 return -ENODEV;
1977         if (!enable[dev]) {
1978                 dev++;
1979                 return -ENOENT;
1980         }
1981
1982         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1983                            0, &card);
1984         if (err < 0) {
1985                 dev_err(&pci->dev, "Error creating card!\n");
1986                 return err;
1987         }
1988
1989         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1990         if (err < 0)
1991                 goto out_free;
1992         card->private_data = chip;
1993         hda = container_of(chip, struct hda_intel, chip);
1994
1995         pci_set_drvdata(pci, card);
1996
1997         err = register_vga_switcheroo(chip);
1998         if (err < 0) {
1999                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2000                 goto out_free;
2001         }
2002
2003         if (check_hdmi_disabled(pci)) {
2004                 dev_info(card->dev, "VGA controller is disabled\n");
2005                 dev_info(card->dev, "Delaying initialization\n");
2006                 chip->disabled = true;
2007         }
2008
2009         schedule_probe = !chip->disabled;
2010
2011 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2012         if (patch[dev] && *patch[dev]) {
2013                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2014                          patch[dev]);
2015                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2016                                               &pci->dev, GFP_KERNEL, card,
2017                                               azx_firmware_cb);
2018                 if (err < 0)
2019                         goto out_free;
2020                 schedule_probe = false; /* continued in azx_firmware_cb() */
2021         }
2022 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2023
2024 #ifndef CONFIG_SND_HDA_I915
2025         if (CONTROLLER_IN_GPU(pci))
2026                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2027 #endif
2028
2029         if (schedule_probe)
2030                 schedule_work(&hda->probe_work);
2031
2032         dev++;
2033         if (chip->disabled)
2034                 complete_all(&hda->probe_wait);
2035         return 0;
2036
2037 out_free:
2038         snd_card_free(card);
2039         return err;
2040 }
2041
2042 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2043 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2044         [AZX_DRIVER_NVIDIA] = 8,
2045         [AZX_DRIVER_TERA] = 1,
2046 };
2047
2048 static int azx_probe_continue(struct azx *chip)
2049 {
2050         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2051         struct hdac_bus *bus = azx_bus(chip);
2052         struct pci_dev *pci = chip->pci;
2053         int dev = chip->dev_index;
2054         int err;
2055
2056         hda->probe_continued = 1;
2057
2058         /* Request display power well for the HDA controller or codec. For
2059          * Haswell/Broadwell, both the display HDA controller and codec need
2060          * this power. For other platforms, like Baytrail/Braswell, only the
2061          * display codec needs the power and it can be released after probe.
2062          */
2063         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2064                 /* HSW/BDW controllers need this power */
2065                 if (CONTROLLER_IN_GPU(pci))
2066                         hda->need_i915_power = 1;
2067
2068                 err = snd_hdac_i915_init(bus);
2069                 if (err < 0) {
2070                         /* if the controller is bound only with HDMI/DP
2071                          * (for HSW and BDW), we need to abort the probe;
2072                          * for other chips, still continue probing as other
2073                          * codecs can be on the same link.
2074                          */
2075                         if (CONTROLLER_IN_GPU(pci)) {
2076                                 dev_err(chip->card->dev,
2077                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2078                                 goto out_free;
2079                         } else
2080                                 goto skip_i915;
2081                 }
2082
2083                 err = snd_hdac_display_power(bus, true);
2084                 if (err < 0) {
2085                         dev_err(chip->card->dev,
2086                                 "Cannot turn on display power on i915\n");
2087                         goto i915_power_fail;
2088                 }
2089         }
2090
2091  skip_i915:
2092         err = azx_first_init(chip);
2093         if (err < 0)
2094                 goto out_free;
2095
2096 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2097         chip->beep_mode = beep_mode[dev];
2098 #endif
2099
2100         /* create codec instances */
2101         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2102         if (err < 0)
2103                 goto out_free;
2104
2105 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2106         if (chip->fw) {
2107                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2108                                          chip->fw->data);
2109                 if (err < 0)
2110                         goto out_free;
2111 #ifndef CONFIG_PM
2112                 release_firmware(chip->fw); /* no longer needed */
2113                 chip->fw = NULL;
2114 #endif
2115         }
2116 #endif
2117         if ((probe_only[dev] & 1) == 0) {
2118                 err = azx_codec_configure(chip);
2119                 if (err < 0)
2120                         goto out_free;
2121         }
2122
2123         err = snd_card_register(chip->card);
2124         if (err < 0)
2125                 goto out_free;
2126
2127         chip->running = 1;
2128         azx_add_card_list(chip);
2129         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2130         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2131                 pm_runtime_put_autosuspend(&pci->dev);
2132
2133 out_free:
2134         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2135                 && !hda->need_i915_power)
2136                 snd_hdac_display_power(bus, false);
2137
2138 i915_power_fail:
2139         if (err < 0)
2140                 hda->init_failed = 1;
2141         complete_all(&hda->probe_wait);
2142         return err;
2143 }
2144
2145 static void azx_remove(struct pci_dev *pci)
2146 {
2147         struct snd_card *card = pci_get_drvdata(pci);
2148         struct azx *chip;
2149         struct hda_intel *hda;
2150
2151         if (card) {
2152                 /* cancel the pending probing work */
2153                 chip = card->private_data;
2154                 hda = container_of(chip, struct hda_intel, chip);
2155                 cancel_work_sync(&hda->probe_work);
2156
2157                 snd_card_free(card);
2158         }
2159 }
2160
2161 static void azx_shutdown(struct pci_dev *pci)
2162 {
2163         struct snd_card *card = pci_get_drvdata(pci);
2164         struct azx *chip;
2165
2166         if (!card)
2167                 return;
2168         chip = card->private_data;
2169         if (chip && chip->running)
2170                 azx_stop_chip(chip);
2171 }
2172
2173 /* PCI IDs */
2174 static const struct pci_device_id azx_ids[] = {
2175         /* CPT */
2176         { PCI_DEVICE(0x8086, 0x1c20),
2177           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2178         /* PBG */
2179         { PCI_DEVICE(0x8086, 0x1d20),
2180           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2181         /* Panther Point */
2182         { PCI_DEVICE(0x8086, 0x1e20),
2183           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2184         /* Lynx Point */
2185         { PCI_DEVICE(0x8086, 0x8c20),
2186           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2187         /* 9 Series */
2188         { PCI_DEVICE(0x8086, 0x8ca0),
2189           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2190         /* Wellsburg */
2191         { PCI_DEVICE(0x8086, 0x8d20),
2192           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2193         { PCI_DEVICE(0x8086, 0x8d21),
2194           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2195         /* Lewisburg */
2196         { PCI_DEVICE(0x8086, 0xa1f0),
2197           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2198         { PCI_DEVICE(0x8086, 0xa270),
2199           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2200         /* Lynx Point-LP */
2201         { PCI_DEVICE(0x8086, 0x9c20),
2202           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2203         /* Lynx Point-LP */
2204         { PCI_DEVICE(0x8086, 0x9c21),
2205           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2206         /* Wildcat Point-LP */
2207         { PCI_DEVICE(0x8086, 0x9ca0),
2208           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2209         /* Sunrise Point */
2210         { PCI_DEVICE(0x8086, 0xa170),
2211           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2212         /* Sunrise Point-LP */
2213         { PCI_DEVICE(0x8086, 0x9d70),
2214           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2215         /* Kabylake */
2216         { PCI_DEVICE(0x8086, 0xa171),
2217           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2218         /* Kabylake-LP */
2219         { PCI_DEVICE(0x8086, 0x9d71),
2220           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2221         /* Kabylake-H */
2222         { PCI_DEVICE(0x8086, 0xa2f0),
2223           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2224         /* Broxton-P(Apollolake) */
2225         { PCI_DEVICE(0x8086, 0x5a98),
2226           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2227         /* Broxton-T */
2228         { PCI_DEVICE(0x8086, 0x1a98),
2229           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2230         /* Haswell */
2231         { PCI_DEVICE(0x8086, 0x0a0c),
2232           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2233         { PCI_DEVICE(0x8086, 0x0c0c),
2234           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2235         { PCI_DEVICE(0x8086, 0x0d0c),
2236           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2237         /* Broadwell */
2238         { PCI_DEVICE(0x8086, 0x160c),
2239           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2240         /* 5 Series/3400 */
2241         { PCI_DEVICE(0x8086, 0x3b56),
2242           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2243         /* Poulsbo */
2244         { PCI_DEVICE(0x8086, 0x811b),
2245           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2246         /* Oaktrail */
2247         { PCI_DEVICE(0x8086, 0x080a),
2248           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2249         /* BayTrail */
2250         { PCI_DEVICE(0x8086, 0x0f04),
2251           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2252         /* Braswell */
2253         { PCI_DEVICE(0x8086, 0x2284),
2254           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2255         /* ICH6 */
2256         { PCI_DEVICE(0x8086, 0x2668),
2257           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2258         /* ICH7 */
2259         { PCI_DEVICE(0x8086, 0x27d8),
2260           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2261         /* ESB2 */
2262         { PCI_DEVICE(0x8086, 0x269a),
2263           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2264         /* ICH8 */
2265         { PCI_DEVICE(0x8086, 0x284b),
2266           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2267         /* ICH9 */
2268         { PCI_DEVICE(0x8086, 0x293e),
2269           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2270         /* ICH9 */
2271         { PCI_DEVICE(0x8086, 0x293f),
2272           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2273         /* ICH10 */
2274         { PCI_DEVICE(0x8086, 0x3a3e),
2275           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2276         /* ICH10 */
2277         { PCI_DEVICE(0x8086, 0x3a6e),
2278           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2279         /* Generic Intel */
2280         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2281           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2282           .class_mask = 0xffffff,
2283           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2284         /* ATI SB 450/600/700/800/900 */
2285         { PCI_DEVICE(0x1002, 0x437b),
2286           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2287         { PCI_DEVICE(0x1002, 0x4383),
2288           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2289         /* AMD Hudson */
2290         { PCI_DEVICE(0x1022, 0x780d),
2291           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2292         /* ATI HDMI */
2293         { PCI_DEVICE(0x1002, 0x0002),
2294           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2295         { PCI_DEVICE(0x1002, 0x1308),
2296           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2297         { PCI_DEVICE(0x1002, 0x157a),
2298           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2299         { PCI_DEVICE(0x1002, 0x15b3),
2300           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2301         { PCI_DEVICE(0x1002, 0x793b),
2302           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2303         { PCI_DEVICE(0x1002, 0x7919),
2304           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2305         { PCI_DEVICE(0x1002, 0x960f),
2306           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2307         { PCI_DEVICE(0x1002, 0x970f),
2308           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2309         { PCI_DEVICE(0x1002, 0x9840),
2310           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2311         { PCI_DEVICE(0x1002, 0xaa00),
2312           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2313         { PCI_DEVICE(0x1002, 0xaa08),
2314           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2315         { PCI_DEVICE(0x1002, 0xaa10),
2316           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2317         { PCI_DEVICE(0x1002, 0xaa18),
2318           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2319         { PCI_DEVICE(0x1002, 0xaa20),
2320           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2321         { PCI_DEVICE(0x1002, 0xaa28),
2322           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2323         { PCI_DEVICE(0x1002, 0xaa30),
2324           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2325         { PCI_DEVICE(0x1002, 0xaa38),
2326           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2327         { PCI_DEVICE(0x1002, 0xaa40),
2328           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2329         { PCI_DEVICE(0x1002, 0xaa48),
2330           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2331         { PCI_DEVICE(0x1002, 0xaa50),
2332           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2333         { PCI_DEVICE(0x1002, 0xaa58),
2334           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2335         { PCI_DEVICE(0x1002, 0xaa60),
2336           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2337         { PCI_DEVICE(0x1002, 0xaa68),
2338           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2339         { PCI_DEVICE(0x1002, 0xaa80),
2340           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2341         { PCI_DEVICE(0x1002, 0xaa88),
2342           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2343         { PCI_DEVICE(0x1002, 0xaa90),
2344           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2345         { PCI_DEVICE(0x1002, 0xaa98),
2346           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2347         { PCI_DEVICE(0x1002, 0x9902),
2348           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2349         { PCI_DEVICE(0x1002, 0xaaa0),
2350           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2351         { PCI_DEVICE(0x1002, 0xaaa8),
2352           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2353         { PCI_DEVICE(0x1002, 0xaab0),
2354           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2355         { PCI_DEVICE(0x1002, 0xaac0),
2356           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2357         { PCI_DEVICE(0x1002, 0xaac8),
2358           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2359         { PCI_DEVICE(0x1002, 0xaad8),
2360           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2361         { PCI_DEVICE(0x1002, 0xaae8),
2362           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2363         { PCI_DEVICE(0x1002, 0xaae0),
2364           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2365         { PCI_DEVICE(0x1002, 0xaaf0),
2366           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2367         /* VIA VT8251/VT8237A */
2368         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2369         /* VIA GFX VT7122/VX900 */
2370         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2371         /* VIA GFX VT6122/VX11 */
2372         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2373         /* SIS966 */
2374         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2375         /* ULI M5461 */
2376         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2377         /* NVIDIA MCP */
2378         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2379           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2380           .class_mask = 0xffffff,
2381           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2382         /* Teradici */
2383         { PCI_DEVICE(0x6549, 0x1200),
2384           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2385         { PCI_DEVICE(0x6549, 0x2200),
2386           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2387         /* Creative X-Fi (CA0110-IBG) */
2388         /* CTHDA chips */
2389         { PCI_DEVICE(0x1102, 0x0010),
2390           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2391         { PCI_DEVICE(0x1102, 0x0012),
2392           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2393 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2394         /* the following entry conflicts with snd-ctxfi driver,
2395          * as ctxfi driver mutates from HD-audio to native mode with
2396          * a special command sequence.
2397          */
2398         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2399           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2400           .class_mask = 0xffffff,
2401           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2402           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2403 #else
2404         /* this entry seems still valid -- i.e. without emu20kx chip */
2405         { PCI_DEVICE(0x1102, 0x0009),
2406           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2407           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2408 #endif
2409         /* CM8888 */
2410         { PCI_DEVICE(0x13f6, 0x5011),
2411           .driver_data = AZX_DRIVER_CMEDIA |
2412           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2413         /* Vortex86MX */
2414         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2415         /* VMware HDAudio */
2416         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2417         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2418         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2419           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2420           .class_mask = 0xffffff,
2421           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2422         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2423           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2424           .class_mask = 0xffffff,
2425           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2426         { 0, }
2427 };
2428 MODULE_DEVICE_TABLE(pci, azx_ids);
2429
2430 /* pci_driver definition */
2431 static struct pci_driver azx_driver = {
2432         .name = KBUILD_MODNAME,
2433         .id_table = azx_ids,
2434         .probe = azx_probe,
2435         .remove = azx_remove,
2436         .shutdown = azx_shutdown,
2437         .driver = {
2438                 .pm = AZX_PM_OPS,
2439         },
2440 };
2441
2442 module_pci_driver(azx_driver);