2 * Common defines for the alsa driver code base for HD Audio.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __SOUND_HDA_PRIV_H
16 #define __SOUND_HDA_PRIV_H
18 #include <linux/clocksource.h>
19 #include <sound/core.h>
20 #include <sound/pcm.h>
25 #define AZX_REG_GCAP 0x00
26 #define AZX_GCAP_64OK (1 << 0) /* 64bit address support */
27 #define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */
28 #define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */
29 #define AZX_GCAP_ISS (15 << 8) /* # of input streams */
30 #define AZX_GCAP_OSS (15 << 12) /* # of output streams */
31 #define AZX_REG_VMIN 0x02
32 #define AZX_REG_VMAJ 0x03
33 #define AZX_REG_OUTPAY 0x04
34 #define AZX_REG_INPAY 0x06
35 #define AZX_REG_GCTL 0x08
36 #define AZX_GCTL_RESET (1 << 0) /* controller reset */
37 #define AZX_GCTL_FCNTRL (1 << 1) /* flush control */
38 #define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
39 #define AZX_REG_WAKEEN 0x0c
40 #define AZX_REG_STATESTS 0x0e
41 #define AZX_REG_GSTS 0x10
42 #define AZX_GSTS_FSTS (1 << 1) /* flush status */
43 #define AZX_REG_INTCTL 0x20
44 #define AZX_REG_INTSTS 0x24
45 #define AZX_REG_WALLCLK 0x30 /* 24Mhz source */
46 #define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
47 #define AZX_REG_SSYNC 0x38
48 #define AZX_REG_CORBLBASE 0x40
49 #define AZX_REG_CORBUBASE 0x44
50 #define AZX_REG_CORBWP 0x48
51 #define AZX_REG_CORBRP 0x4a
52 #define AZX_CORBRP_RST (1 << 15) /* read pointer reset */
53 #define AZX_REG_CORBCTL 0x4c
54 #define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */
55 #define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
56 #define AZX_REG_CORBSTS 0x4d
57 #define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */
58 #define AZX_REG_CORBSIZE 0x4e
60 #define AZX_REG_RIRBLBASE 0x50
61 #define AZX_REG_RIRBUBASE 0x54
62 #define AZX_REG_RIRBWP 0x58
63 #define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */
64 #define AZX_REG_RINTCNT 0x5a
65 #define AZX_REG_RIRBCTL 0x5c
66 #define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
67 #define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */
68 #define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
69 #define AZX_REG_RIRBSTS 0x5d
70 #define AZX_RBSTS_IRQ (1 << 0) /* response irq */
71 #define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */
72 #define AZX_REG_RIRBSIZE 0x5e
74 #define AZX_REG_IC 0x60
75 #define AZX_REG_IR 0x64
76 #define AZX_REG_IRS 0x68
77 #define AZX_IRS_VALID (1<<1)
78 #define AZX_IRS_BUSY (1<<0)
80 #define AZX_REG_DPLBASE 0x70
81 #define AZX_REG_DPUBASE 0x74
82 #define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */
84 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
85 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
87 /* stream register offsets from stream base */
88 #define AZX_REG_SD_CTL 0x00
89 #define AZX_REG_SD_STS 0x03
90 #define AZX_REG_SD_LPIB 0x04
91 #define AZX_REG_SD_CBL 0x08
92 #define AZX_REG_SD_LVI 0x0c
93 #define AZX_REG_SD_FIFOW 0x0e
94 #define AZX_REG_SD_FIFOSIZE 0x10
95 #define AZX_REG_SD_FORMAT 0x12
96 #define AZX_REG_SD_BDLPL 0x18
97 #define AZX_REG_SD_BDLPU 0x1c
100 #define AZX_PCIREG_TCSEL 0x44
106 /* max number of fragments - we may use more if allocating more pages for BDL */
107 #define BDL_SIZE 4096
108 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
109 #define AZX_MAX_FRAG 32
110 /* max buffer size - no h/w limit, you can increase as you like */
111 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
113 /* RIRB int mask: overrun[2], response[0] */
114 #define RIRB_INT_RESPONSE 0x01
115 #define RIRB_INT_OVERRUN 0x04
116 #define RIRB_INT_MASK 0x05
118 /* STATESTS int mask: S3,SD2,SD1,SD0 */
119 #define AZX_MAX_CODECS 8
120 #define AZX_DEFAULT_CODECS 4
121 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
124 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
125 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
126 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
127 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
128 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
129 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
130 #define SD_CTL_STREAM_TAG_SHIFT 20
132 /* SD_CTL and SD_STS */
133 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
134 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
135 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
136 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
140 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
142 /* INTCTL and INTSTS */
143 #define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */
144 #define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
145 #define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
147 /* below are so far hardcoded - should read registers in future */
148 #define AZX_MAX_CORB_ENTRIES 256
149 #define AZX_MAX_RIRB_ENTRIES 256
151 /* driver quirks (capabilities) */
152 /* bits 0-7 are used for indicating driver type */
153 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
154 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
155 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
156 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
157 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
158 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
159 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
160 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
161 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
162 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
163 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
164 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
165 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
166 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
167 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
168 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
169 #define AZX_DCAPS_REVERSE_ASSIGN (1 << 24) /* Assign devices in reverse order */
170 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
171 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
172 #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
173 #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
174 #define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */
176 /* HD Audio class code */
177 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
180 struct snd_dma_buffer bdl; /* BDL buffer */
181 u32 *posbuf; /* position buffer pointer */
183 unsigned int bufsize; /* size of the play buffer in bytes */
184 unsigned int period_bytes; /* size of the period in bytes */
185 unsigned int frags; /* number for period in the play buffer */
186 unsigned int fifo_size; /* FIFO size */
187 unsigned long start_wallclk; /* start + minimum wallclk */
188 unsigned long period_wallclk; /* wallclk for period */
190 void __iomem *sd_addr; /* stream descriptor pointer */
192 u32 sd_int_sta_mask; /* stream int status mask */
195 struct snd_pcm_substream *substream; /* assigned substream,
198 unsigned int format_val; /* format value to be set in the
199 * controller and the codec
201 unsigned char stream_tag; /* assigned stream */
202 unsigned char index; /* stream index */
203 int assigned_key; /* last device# key assigned to */
205 unsigned int opened:1;
206 unsigned int running:1;
207 unsigned int irq_pending:1;
208 unsigned int prepared:1;
209 unsigned int locked:1;
212 * A flag to ensure DMA position is 0
213 * when link position is not greater than FIFO size
215 unsigned int insufficient:1;
216 unsigned int wc_marked:1;
217 unsigned int no_period_wakeup:1;
219 struct timecounter azx_tc;
220 struct cyclecounter azx_cc;
222 int delay_negative_threshold;
224 #ifdef CONFIG_SND_HDA_DSP_LOADER
225 /* Allows dsp load to have sole access to the playback stream. */
226 struct mutex dsp_mutex;
232 u32 *buf; /* CORB/RIRB buffer
233 * Each CORB entry is 4byte, RIRB is 8byte
235 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
237 unsigned short rp, wp; /* read/write pointers */
238 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
239 u32 res[AZX_MAX_CODECS]; /* last read value */
244 /* Functions to read/write to hda registers. */
245 struct hda_controller_ops {
246 /* Register Access */
247 void (*reg_writel)(u32 value, u32 __iomem *addr);
248 u32 (*reg_readl)(u32 __iomem *addr);
249 void (*reg_writew)(u16 value, u16 __iomem *addr);
250 u16 (*reg_readw)(u16 __iomem *addr);
251 void (*reg_writeb)(u8 value, u8 __iomem *addr);
252 u8 (*reg_readb)(u8 __iomem *addr);
253 /* Disable msi if supported, PCI only */
254 int (*disable_msi_reset_irq)(struct azx *);
256 int (*dma_alloc_pages)(struct azx *chip,
259 struct snd_dma_buffer *buf);
260 void (*dma_free_pages)(struct azx *chip, struct snd_dma_buffer *buf);
261 int (*substream_alloc_pages)(struct azx *chip,
262 struct snd_pcm_substream *substream,
264 int (*substream_free_pages)(struct azx *chip,
265 struct snd_pcm_substream *substream);
266 void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream,
267 struct vm_area_struct *area);
268 /* Check if current position is acceptable */
269 int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
275 struct hda_codec *codec;
276 struct hda_pcm_stream *hinfo[2];
277 struct list_head list;
280 typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
281 typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
284 struct snd_card *card;
288 /* chip type specific */
290 unsigned int driver_caps;
291 int playback_streams;
292 int playback_index_offset;
294 int capture_index_offset;
296 const int *jackpoll_ms; /* per-card jack poll interval */
298 /* Register interaction. */
299 const struct hda_controller_ops *ops;
301 /* position adjustment callbacks */
302 azx_get_pos_callback_t get_position[2];
303 azx_get_delay_callback_t get_delay[2];
307 void __iomem *remap_addr;
312 struct mutex open_mutex; /* Prevents concurrent open/close operations */
314 /* streams (x num_streams) */
315 struct azx_dev *azx_dev;
318 struct list_head pcm_list; /* azx_pcm list */
321 unsigned short codec_mask;
322 int codec_probe_mask; /* copied from probe_mask option */
324 unsigned int beep_mode;
330 /* CORB/RIRB and position buffers */
331 struct snd_dma_buffer rb;
332 struct snd_dma_buffer posbuf;
334 #ifdef CONFIG_SND_HDA_PATCH_LOADER
335 const struct firmware *fw;
339 const int *bdl_pos_adj;
341 unsigned int running:1;
342 unsigned int initialized:1;
343 unsigned int single_cmd:1;
344 unsigned int polling_mode:1;
346 unsigned int probing:1; /* codec probing phase */
347 unsigned int snoop:1;
348 unsigned int align_buffer_size:1;
349 unsigned int region_requested:1;
350 unsigned int disabled:1; /* disabled by VGA-switcher */
353 unsigned int last_cmd[AZX_MAX_CODECS];
355 /* reboot notifier (for mysterious hangup problem at power-down) */
356 struct notifier_block reboot_notifier;
358 #ifdef CONFIG_SND_HDA_DSP_LOADER
359 struct azx_dev saved_azx_dev;
364 #define azx_snoop(chip) ((chip)->snoop)
366 #define azx_snoop(chip) true
370 * macros for easy use
373 #define azx_writel(chip, reg, value) \
374 ((chip)->ops->reg_writel(value, (chip)->remap_addr + AZX_REG_##reg))
375 #define azx_readl(chip, reg) \
376 ((chip)->ops->reg_readl((chip)->remap_addr + AZX_REG_##reg))
377 #define azx_writew(chip, reg, value) \
378 ((chip)->ops->reg_writew(value, (chip)->remap_addr + AZX_REG_##reg))
379 #define azx_readw(chip, reg) \
380 ((chip)->ops->reg_readw((chip)->remap_addr + AZX_REG_##reg))
381 #define azx_writeb(chip, reg, value) \
382 ((chip)->ops->reg_writeb(value, (chip)->remap_addr + AZX_REG_##reg))
383 #define azx_readb(chip, reg) \
384 ((chip)->ops->reg_readb((chip)->remap_addr + AZX_REG_##reg))
386 #define azx_sd_writel(chip, dev, reg, value) \
387 ((chip)->ops->reg_writel(value, (dev)->sd_addr + AZX_REG_##reg))
388 #define azx_sd_readl(chip, dev, reg) \
389 ((chip)->ops->reg_readl((dev)->sd_addr + AZX_REG_##reg))
390 #define azx_sd_writew(chip, dev, reg, value) \
391 ((chip)->ops->reg_writew(value, (dev)->sd_addr + AZX_REG_##reg))
392 #define azx_sd_readw(chip, dev, reg) \
393 ((chip)->ops->reg_readw((dev)->sd_addr + AZX_REG_##reg))
394 #define azx_sd_writeb(chip, dev, reg, value) \
395 ((chip)->ops->reg_writeb(value, (dev)->sd_addr + AZX_REG_##reg))
396 #define azx_sd_readb(chip, dev, reg) \
397 ((chip)->ops->reg_readb((dev)->sd_addr + AZX_REG_##reg))
399 #endif /* __SOUND_HDA_PRIV_H */