sound/soc/codecs/ab8500-codec.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2012
   3  *
   4  * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
   5  *         Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
   6  *         Roger Nilsson <roger.xr.nilsson@stericsson.com>,
   7  *         for ST-Ericsson.
   8  *
   9  *         Based on the early work done by:
  10  *         Mikko J. Lehto <mikko.lehto@symbio.com>,
  11  *         Mikko Sarmanne <mikko.sarmanne@symbio.com>,
  12  *         Jarmo K. Kuronen <jarmo.kuronen@symbio.com>,
  13  *         for ST-Ericsson.
  14  *
  15  * License terms:
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License version 2 as published
  19  * by the Free Software Foundation.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/device.h>
  25 #include <linux/slab.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/pm.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/mutex.h>
  32 #include <linux/mfd/abx500/ab8500.h>
  33 #include <linux/mfd/abx500.h>
  34 #include <linux/mfd/abx500/ab8500-sysctrl.h>
  35 #include <linux/mfd/abx500/ab8500-codec.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <linux/of.h>
  38
  39 #include <sound/core.h>
  40 #include <sound/pcm.h>
  41 #include <sound/pcm_params.h>
  42 #include <sound/initval.h>
  43 #include <sound/soc.h>
  44 #include <sound/soc-dapm.h>
  45 #include <sound/tlv.h>
  46
  47 #include "ab8500-codec.h"
  48
  49 /* Macrocell value definitions */
  50 #define CLK_32K_OUT2_DISABLE                    0x01
  51 #define INACTIVE_RESET_AUDIO                    0x02
  52 #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK           0x10
  53 #define ENABLE_VINTCORE12_SUPPLY                0x04
  54 #define GPIO27_DIR_OUTPUT                       0x04
  55 #define GPIO29_DIR_OUTPUT                       0x10
  56 #define GPIO31_DIR_OUTPUT                       0x40
  57
  58 /* Macrocell register definitions */
  59 #define AB8500_GPIO_DIR4_REG                    0x13 /* Bank AB8500_MISC */
  60
  61 /* Nr of FIR/IIR-coeff banks in ANC-block */
  62 #define AB8500_NR_OF_ANC_COEFF_BANKS            2
  63
  64 /* Minimum duration to keep ANC IIR Init bit high or
  65 low before proceeding with the configuration sequence */
  66 #define AB8500_ANC_SM_DELAY                     2000
  67
  68 #define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \
  69 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  70         .info = filter_control_info, \
  71         .get = filter_control_get, .put = filter_control_put, \
  72         .private_value = (unsigned long)&(struct filter_control) \
  73                 {.count = xcount, .min = xmin, .max = xmax} }
  74
  75 struct filter_control {
  76         long min, max;
  77         unsigned int count;
  78         long value[128];
  79 };
  80
  81 /* Sidetone states */
  82 static const char * const enum_sid_state[] = {
  83         "Unconfigured",
  84         "Apply FIR",
  85         "FIR is configured",
  86 };
  87 enum sid_state {
  88         SID_UNCONFIGURED = 0,
  89         SID_APPLY_FIR = 1,
  90         SID_FIR_CONFIGURED = 2,
  91 };
  92
  93 static const char * const enum_anc_state[] = {
  94         "Unconfigured",
  95         "Apply FIR and IIR",
  96         "FIR and IIR are configured",
  97         "Apply FIR",
  98         "FIR is configured",
  99         "Apply IIR",
 100         "IIR is configured"
 101 };
 102 enum anc_state {
 103         ANC_UNCONFIGURED = 0,
 104         ANC_APPLY_FIR_IIR = 1,
 105         ANC_FIR_IIR_CONFIGURED = 2,
 106         ANC_APPLY_FIR = 3,
 107         ANC_FIR_CONFIGURED = 4,
 108         ANC_APPLY_IIR = 5,
 109         ANC_IIR_CONFIGURED = 6
 110 };
 111
 112 /* Analog microphones */
 113 enum amic_idx {
 114         AMIC_IDX_1A,
 115         AMIC_IDX_1B,
 116         AMIC_IDX_2
 117 };
 118
 119 struct ab8500_codec_drvdata_dbg {
 120         struct regulator *vaud;
 121         struct regulator *vamic1;
 122         struct regulator *vamic2;
 123         struct regulator *vdmic;
 124 };
 125
 126 /* Private data for AB8500 device-driver */
 127 struct ab8500_codec_drvdata {
 128         struct regmap *regmap;
 129         struct mutex ctrl_lock;
 130
 131         /* Sidetone */
 132         long *sid_fir_values;
 133         enum sid_state sid_status;
 134
 135         /* ANC */
 136         long *anc_fir_values;
 137         long *anc_iir_values;
 138         enum anc_state anc_status;
 139 };
 140
 141 static inline const char *amic_micbias_str(enum amic_micbias micbias)
 142 {
 143         switch (micbias) {
 144         case AMIC_MICBIAS_VAMIC1:
 145                 return "VAMIC1";
 146         case AMIC_MICBIAS_VAMIC2:
 147                 return "VAMIC2";
 148         default:
 149                 return "Unknown";
 150         }
 151 }
 152
 153 static inline const char *amic_type_str(enum amic_type type)
 154 {
 155         switch (type) {
 156         case AMIC_TYPE_DIFFERENTIAL:
 157                 return "DIFFERENTIAL";
 158         case AMIC_TYPE_SINGLE_ENDED:
 159                 return "SINGLE ENDED";
 160         default:
 161                 return "Unknown";
 162         }
 163 }
 164
 165 /*
 166  * Read'n'write functions
 167  */
 168
 169 /* Read a register from the audio-bank of AB8500 */
 170 static int ab8500_codec_read_reg(void *context, unsigned int reg,
 171                                  unsigned int *value)
 172 {
 173         struct device *dev = context;
 174         int status;
 175
 176         u8 value8;
 177         status = abx500_get_register_interruptible(dev, AB8500_AUDIO,
 178                                                    reg, &value8);
 179         *value = (unsigned int)value8;
 180
 181         return status;
 182 }
 183
 184 /* Write to a register in the audio-bank of AB8500 */
 185 static int ab8500_codec_write_reg(void *context, unsigned int reg,
 186                                   unsigned int value)
 187 {
 188         struct device *dev = context;
 189
 190         return abx500_set_register_interruptible(dev, AB8500_AUDIO,
 191                                                  reg, value);
 192 }
 193
 194 static const struct regmap_config ab8500_codec_regmap = {
 195         .reg_read = ab8500_codec_read_reg,
 196         .reg_write = ab8500_codec_write_reg,
 197 };
 198
 199 /*
 200  * Controls - DAPM
 201  */
 202
 203 /* Earpiece */
 204
 205 /* Earpiece source selector */
 206 static const char * const enum_ear_lineout_source[] = {"Headset Left",
 207                                                 "Speaker Left"};
 208 static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
 209                         AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
 210 static const struct snd_kcontrol_new dapm_ear_lineout_source =
 211         SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
 212                 dapm_enum_ear_lineout_source);
 213
 214 /* LineOut */
 215
 216 /* LineOut source selector */
 217 static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
 218 static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
 219                         AB8500_ANACONF5_HSLDACTOLOL,
 220                         AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
 221 static const struct snd_kcontrol_new dapm_lineout_source[] = {
 222         SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
 223 };
 224
 225 /* Handsfree */
 226
 227 /* Speaker Left - ANC selector */
 228 static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
 229 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
 230                         AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
 231 static const struct snd_kcontrol_new dapm_HFl_select[] = {
 232         SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
 233 };
 234
 235 /* Speaker Right - ANC selector */
 236 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
 237                         AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
 238 static const struct snd_kcontrol_new dapm_HFr_select[] = {
 239         SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
 240 };
 241
 242 /* Mic 1 */
 243
 244 /* Mic 1 - Mic 1a or 1b selector */
 245 static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
 246 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
 247                         AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
 248 static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
 249         SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
 250 };
 251
 252 /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
 253 static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
 254 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
 255                         AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
 256 static const struct snd_kcontrol_new dapm_ad3_select[] = {
 257         SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
 258 };
 259
 260 /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
 261 static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
 262 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
 263                         AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
 264 static const struct snd_kcontrol_new dapm_ad6_select[] = {
 265         SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
 266 };
 267
 268 /* Mic 2 */
 269
 270 /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
 271 static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
 272 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
 273                         AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
 274 static const struct snd_kcontrol_new dapm_ad5_select[] = {
 275         SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
 276 };
 277
 278 /* LineIn */
 279
 280 /* LineIn left - AD1 - LineIn Left or DMic 1 selector */
 281 static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
 282 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
 283                         AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
 284 static const struct snd_kcontrol_new dapm_ad1_select[] = {
 285         SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
 286 };
 287
 288 /* LineIn right - Mic 2 or LineIn Right selector */
 289 static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
 290 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
 291                         AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
 292 static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
 293         SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
 294 };
 295
 296 /* LineIn right - AD2 - LineIn Right or DMic2 selector */
 297 static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
 298 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
 299                         AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
 300 static const struct snd_kcontrol_new dapm_ad2_select[] = {
 301         SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
 302 };
 303
 304
 305 /* ANC */
 306
 307 static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
 308                                         "Mic 2 / DMic 5"};
 309 static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
 310                         AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
 311 static const struct snd_kcontrol_new dapm_anc_in_select[] = {
 312         SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
 313 };
 314
 315 /* ANC - Enable/Disable */
 316 static const struct snd_kcontrol_new dapm_anc_enable[] = {
 317         SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
 318                         AB8500_ANCCONF1_ENANC, 0, 0),
 319 };
 320
 321 /* ANC to Earpiece - Mute */
 322 static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
 323         SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
 324                         AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
 325 };
 326
 327
 328
 329 /* Sidetone left */
 330
 331 /* Sidetone left - Input selector */
 332 static const char * const enum_stfir1_in_sel[] = {
 333         "LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
 334 };
 335 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
 336                         AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
 337 static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
 338         SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
 339 };
 340
 341 /* Sidetone right path */
 342
 343 /* Sidetone right - Input selector */
 344 static const char * const enum_stfir2_in_sel[] = {
 345         "LineIn Right", "Mic 1", "DMic 4", "Headset Right"
 346 };
 347 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
 348                         AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
 349 static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
 350         SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
 351 };
 352
 353 /* Vibra */
 354
 355 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
 356
 357 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
 358                         AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
 359
 360 static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
 361         SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
 362 };
 363
 364 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
 365                         AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
 366
 367 static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
 368         SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
 369 };
 370
 371 /*
 372  * DAPM-widgets
 373  */
 374
 375 static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
 376
 377         /* Clocks */
 378         SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
 379
 380         /* Regulators */
 381         SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
 382         SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
 383         SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
 384         SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
 385
 386         /* Power */
 387         SND_SOC_DAPM_SUPPLY("Audio Power",
 388                         AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
 389                         NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 390         SND_SOC_DAPM_SUPPLY("Audio Analog Power",
 391                         AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
 392                         NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 393
 394         /* Main supply node */
 395         SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
 396                         NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 397
 398         /* DA/AD */
 399
 400         SND_SOC_DAPM_INPUT("ADC Input"),
 401         SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0),
 402
 403         SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
 404         SND_SOC_DAPM_OUTPUT("DAC Output"),
 405
 406         SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
 407         SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
 408         SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
 409         SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
 410         SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
 411         SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
 412         SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
 413         SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
 414         SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
 415         SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
 416         SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
 417         SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
 418
 419         /* Headset path */
 420
 421         SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
 422                         AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
 423
 424         SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
 425                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
 426         SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
 427                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
 428
 429         SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
 430                         NULL, 0),
 431         SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
 432                         NULL, 0),
 433
 434         SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
 435                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
 436         SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
 437                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
 438         SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
 439                         AB8500_MUTECONF_MUTDACHSL, 1,
 440                         NULL, 0),
 441         SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
 442                         AB8500_MUTECONF_MUTDACHSR, 1,
 443                         NULL, 0),
 444         SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
 445                         AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
 446         SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
 447                         AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
 448
 449         SND_SOC_DAPM_MIXER("HSL Mute",
 450                         AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
 451                         NULL, 0),
 452         SND_SOC_DAPM_MIXER("HSR Mute",
 453                         AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
 454                         NULL, 0),
 455         SND_SOC_DAPM_MIXER("HSL Enable",
 456                         AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
 457                         NULL, 0),
 458         SND_SOC_DAPM_MIXER("HSR Enable",
 459                         AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
 460                         NULL, 0),
 461         SND_SOC_DAPM_PGA("HSL Volume",
 462                         SND_SOC_NOPM, 0, 0,
 463                         NULL, 0),
 464         SND_SOC_DAPM_PGA("HSR Volume",
 465                         SND_SOC_NOPM, 0, 0,
 466                         NULL, 0),
 467
 468         SND_SOC_DAPM_OUTPUT("Headset Left"),
 469         SND_SOC_DAPM_OUTPUT("Headset Right"),
 470
 471         /* LineOut path */
 472
 473         SND_SOC_DAPM_MUX("LineOut Source",
 474                         SND_SOC_NOPM, 0, 0, dapm_lineout_source),
 475
 476         SND_SOC_DAPM_MIXER("LOL Disable HFL",
 477                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
 478                         NULL, 0),
 479         SND_SOC_DAPM_MIXER("LOR Disable HFR",
 480                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
 481                         NULL, 0),
 482
 483         SND_SOC_DAPM_MIXER("LOL Enable",
 484                         AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
 485                         NULL, 0),
 486         SND_SOC_DAPM_MIXER("LOR Enable",
 487                         AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
 488                         NULL, 0),
 489
 490         SND_SOC_DAPM_OUTPUT("LineOut Left"),
 491         SND_SOC_DAPM_OUTPUT("LineOut Right"),
 492
 493         /* Earpiece path */
 494
 495         SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
 496                         SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
 497         SND_SOC_DAPM_MIXER("EAR DAC",
 498                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
 499                         NULL, 0),
 500         SND_SOC_DAPM_MIXER("EAR Mute",
 501                         AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
 502                         NULL, 0),
 503         SND_SOC_DAPM_MIXER("EAR Enable",
 504                         AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
 505                         NULL, 0),
 506
 507         SND_SOC_DAPM_OUTPUT("Earpiece"),
 508
 509         /* Handsfree path */
 510
 511         SND_SOC_DAPM_MIXER("DA3 Channel Volume",
 512                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
 513                         NULL, 0),
 514         SND_SOC_DAPM_MIXER("DA4 Channel Volume",
 515                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
 516                         NULL, 0),
 517         SND_SOC_DAPM_MUX("Speaker Left Source",
 518                         SND_SOC_NOPM, 0, 0, dapm_HFl_select),
 519         SND_SOC_DAPM_MUX("Speaker Right Source",
 520                         SND_SOC_NOPM, 0, 0, dapm_HFr_select),
 521         SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
 522                         AB8500_DAPATHCONF_ENDACHFL, 0,
 523                         NULL, 0),
 524         SND_SOC_DAPM_MIXER("HFR DAC",
 525                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
 526                         NULL, 0),
 527         SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
 528                         AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
 529                         NULL, 0),
 530         SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
 531                         AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
 532                         NULL, 0),
 533         SND_SOC_DAPM_MIXER("HFL Enable",
 534                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
 535                         NULL, 0),
 536         SND_SOC_DAPM_MIXER("HFR Enable",
 537                         AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
 538                         NULL, 0),
 539
 540         SND_SOC_DAPM_OUTPUT("Speaker Left"),
 541         SND_SOC_DAPM_OUTPUT("Speaker Right"),
 542
 543         /* Vibrator path */
 544
 545         SND_SOC_DAPM_INPUT("PWMGEN1"),
 546         SND_SOC_DAPM_INPUT("PWMGEN2"),
 547
 548         SND_SOC_DAPM_MIXER("DA5 Channel Volume",
 549                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
 550                         NULL, 0),
 551         SND_SOC_DAPM_MIXER("DA6 Channel Volume",
 552                         AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
 553                         NULL, 0),
 554         SND_SOC_DAPM_MIXER("VIB1 DAC",
 555                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
 556                         NULL, 0),
 557         SND_SOC_DAPM_MIXER("VIB2 DAC",
 558                         AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
 559                         NULL, 0),
 560         SND_SOC_DAPM_MUX("Vibra 1 Controller",
 561                         SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
 562         SND_SOC_DAPM_MUX("Vibra 2 Controller",
 563                         SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
 564         SND_SOC_DAPM_MIXER("VIB1 Enable",
 565                         AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
 566                         NULL, 0),
 567         SND_SOC_DAPM_MIXER("VIB2 Enable",
 568                         AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
 569                         NULL, 0),
 570
 571         SND_SOC_DAPM_OUTPUT("Vibra 1"),
 572         SND_SOC_DAPM_OUTPUT("Vibra 2"),
 573
 574         /* Mic 1 */
 575
 576         SND_SOC_DAPM_INPUT("Mic 1"),
 577
 578         SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
 579                         SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
 580         SND_SOC_DAPM_MIXER("MIC1 Mute",
 581                         AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
 582                         NULL, 0),
 583         SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
 584                         AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
 585                         NULL, 0),
 586         SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
 587                         AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
 588                         NULL, 0),
 589         SND_SOC_DAPM_MIXER("MIC1 ADC",
 590                         AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
 591                         NULL, 0),
 592         SND_SOC_DAPM_MUX("AD3 Source Select",
 593                         SND_SOC_NOPM, 0, 0, dapm_ad3_select),
 594         SND_SOC_DAPM_MIXER("AD3 Channel Volume",
 595                         SND_SOC_NOPM, 0, 0,
 596                         NULL, 0),
 597         SND_SOC_DAPM_MIXER("AD3 Enable",
 598                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0,
 599                         NULL, 0),
 600
 601         /* Mic 2 */
 602
 603         SND_SOC_DAPM_INPUT("Mic 2"),
 604
 605         SND_SOC_DAPM_MIXER("MIC2 Mute",
 606                         AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
 607                         NULL, 0),
 608         SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
 609                         AB8500_ANACONF2_ENMIC2, 0,
 610                         NULL, 0),
 611
 612         /* LineIn */
 613
 614         SND_SOC_DAPM_INPUT("LineIn Left"),
 615         SND_SOC_DAPM_INPUT("LineIn Right"),
 616
 617         SND_SOC_DAPM_MIXER("LINL Mute",
 618                         AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
 619                         NULL, 0),
 620         SND_SOC_DAPM_MIXER("LINR Mute",
 621                         AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
 622                         NULL, 0),
 623         SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
 624                         AB8500_ANACONF2_ENLINL, 0,
 625                         NULL, 0),
 626         SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
 627                         AB8500_ANACONF2_ENLINR, 0,
 628                         NULL, 0),
 629
 630         /* LineIn Bypass path */
 631         SND_SOC_DAPM_MIXER("LINL to HSL Volume",
 632                         SND_SOC_NOPM, 0, 0,
 633                         NULL, 0),
 634         SND_SOC_DAPM_MIXER("LINR to HSR Volume",
 635                         SND_SOC_NOPM, 0, 0,
 636                         NULL, 0),
 637
 638         /* LineIn, Mic 2 */
 639         SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
 640                         SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
 641         SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
 642                         AB8500_ANACONF3_ENADCLINL, 0,
 643                         NULL, 0),
 644         SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
 645                         AB8500_ANACONF3_ENADCLINR, 0,
 646                         NULL, 0),
 647         SND_SOC_DAPM_MUX("AD1 Source Select",
 648                         SND_SOC_NOPM, 0, 0, dapm_ad1_select),
 649         SND_SOC_DAPM_MUX("AD2 Source Select",
 650                         SND_SOC_NOPM, 0, 0, dapm_ad2_select),
 651         SND_SOC_DAPM_MIXER("AD1 Channel Volume",
 652                         SND_SOC_NOPM, 0, 0,
 653                         NULL, 0),
 654         SND_SOC_DAPM_MIXER("AD2 Channel Volume",
 655                         SND_SOC_NOPM, 0, 0,
 656                         NULL, 0),
 657
 658         SND_SOC_DAPM_MIXER("AD12 Enable",
 659                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0,
 660                         NULL, 0),
 661
 662         /* HD Capture path */
 663
 664         SND_SOC_DAPM_MUX("AD5 Source Select",
 665                         SND_SOC_NOPM, 0, 0, dapm_ad5_select),
 666         SND_SOC_DAPM_MUX("AD6 Source Select",
 667                         SND_SOC_NOPM, 0, 0, dapm_ad6_select),
 668         SND_SOC_DAPM_MIXER("AD5 Channel Volume",
 669                         SND_SOC_NOPM, 0, 0,
 670                         NULL, 0),
 671         SND_SOC_DAPM_MIXER("AD6 Channel Volume",
 672                         SND_SOC_NOPM, 0, 0,
 673                         NULL, 0),
 674         SND_SOC_DAPM_MIXER("AD57 Enable",
 675                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
 676                         NULL, 0),
 677         SND_SOC_DAPM_MIXER("AD68 Enable",
 678                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
 679                         NULL, 0),
 680
 681         /* Digital Microphone path */
 682
 683         SND_SOC_DAPM_INPUT("DMic 1"),
 684         SND_SOC_DAPM_INPUT("DMic 2"),
 685         SND_SOC_DAPM_INPUT("DMic 3"),
 686         SND_SOC_DAPM_INPUT("DMic 4"),
 687         SND_SOC_DAPM_INPUT("DMic 5"),
 688         SND_SOC_DAPM_INPUT("DMic 6"),
 689
 690         SND_SOC_DAPM_MIXER("DMIC1",
 691                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
 692                         NULL, 0),
 693         SND_SOC_DAPM_MIXER("DMIC2",
 694                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
 695                         NULL, 0),
 696         SND_SOC_DAPM_MIXER("DMIC3",
 697                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
 698                         NULL, 0),
 699         SND_SOC_DAPM_MIXER("DMIC4",
 700                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
 701                         NULL, 0),
 702         SND_SOC_DAPM_MIXER("DMIC5",
 703                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
 704                         NULL, 0),
 705         SND_SOC_DAPM_MIXER("DMIC6",
 706                         AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
 707                         NULL, 0),
 708         SND_SOC_DAPM_MIXER("AD4 Channel Volume",
 709                         SND_SOC_NOPM, 0, 0,
 710                         NULL, 0),
 711         SND_SOC_DAPM_MIXER("AD4 Enable",
 712                         AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34,
 713                         0, NULL, 0),
 714
 715         /* Acoustical Noise Cancellation path */
 716
 717         SND_SOC_DAPM_INPUT("ANC Configure Input"),
 718         SND_SOC_DAPM_OUTPUT("ANC Configure Output"),
 719
 720         SND_SOC_DAPM_MUX("ANC Source",
 721                         SND_SOC_NOPM, 0, 0,
 722                         dapm_anc_in_select),
 723         SND_SOC_DAPM_SWITCH("ANC",
 724                         SND_SOC_NOPM, 0, 0,
 725                         dapm_anc_enable),
 726         SND_SOC_DAPM_SWITCH("ANC to Earpiece",
 727                         SND_SOC_NOPM, 0, 0,
 728                         dapm_anc_ear_mute),
 729
 730         /* Sidetone Filter path */
 731
 732         SND_SOC_DAPM_MUX("Sidetone Left Source",
 733                         SND_SOC_NOPM, 0, 0,
 734                         dapm_stfir1_in_select),
 735         SND_SOC_DAPM_MUX("Sidetone Right Source",
 736                         SND_SOC_NOPM, 0, 0,
 737                         dapm_stfir2_in_select),
 738         SND_SOC_DAPM_MIXER("STFIR1 Control",
 739                         SND_SOC_NOPM, 0, 0,
 740                         NULL, 0),
 741         SND_SOC_DAPM_MIXER("STFIR2 Control",
 742                         SND_SOC_NOPM, 0, 0,
 743                         NULL, 0),
 744         SND_SOC_DAPM_MIXER("STFIR1 Volume",
 745                         SND_SOC_NOPM, 0, 0,
 746                         NULL, 0),
 747         SND_SOC_DAPM_MIXER("STFIR2 Volume",
 748                         SND_SOC_NOPM, 0, 0,
 749                         NULL, 0),
 750 };
 751
 752 /*
 753  * DAPM-routes
 754  */
 755 static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
 756         /* Power AB8500 audio-block when AD/DA is active */
 757         {"Main Supply", NULL, "V-AUD"},
 758         {"Main Supply", NULL, "audioclk"},
 759         {"Main Supply", NULL, "Audio Power"},
 760         {"Main Supply", NULL, "Audio Analog Power"},
 761
 762         {"DAC", NULL, "ab8500_0p"},
 763         {"DAC", NULL, "Main Supply"},
 764         {"ADC", NULL, "ab8500_0c"},
 765         {"ADC", NULL, "Main Supply"},
 766
 767         /* ANC Configure */
 768         {"ANC Configure Input", NULL, "Main Supply"},
 769         {"ANC Configure Output", NULL, "ANC Configure Input"},
 770
 771         /* AD/DA */
 772         {"ADC", NULL, "ADC Input"},
 773         {"DAC Output", NULL, "DAC"},
 774
 775         /* Powerup charge pump if DA1/2 is in use */
 776
 777         {"DA_IN1", NULL, "ab8500_0p"},
 778         {"DA_IN1", NULL, "Charge Pump"},
 779         {"DA_IN2", NULL, "ab8500_0p"},
 780         {"DA_IN2", NULL, "Charge Pump"},
 781
 782         /* Headset path */
 783
 784         {"DA1 Enable", NULL, "DA_IN1"},
 785         {"DA2 Enable", NULL, "DA_IN2"},
 786
 787         {"HSL Digital Volume", NULL, "DA1 Enable"},
 788         {"HSR Digital Volume", NULL, "DA2 Enable"},
 789
 790         {"HSL DAC", NULL, "HSL Digital Volume"},
 791         {"HSR DAC", NULL, "HSR Digital Volume"},
 792
 793         {"HSL DAC Mute", NULL, "HSL DAC"},
 794         {"HSR DAC Mute", NULL, "HSR DAC"},
 795
 796         {"HSL DAC Driver", NULL, "HSL DAC Mute"},
 797         {"HSR DAC Driver", NULL, "HSR DAC Mute"},
 798
 799         {"HSL Mute", NULL, "HSL DAC Driver"},
 800         {"HSR Mute", NULL, "HSR DAC Driver"},
 801
 802         {"HSL Enable", NULL, "HSL Mute"},
 803         {"HSR Enable", NULL, "HSR Mute"},
 804
 805         {"HSL Volume", NULL, "HSL Enable"},
 806         {"HSR Volume", NULL, "HSR Enable"},
 807
 808         {"Headset Left", NULL, "HSL Volume"},
 809         {"Headset Right", NULL, "HSR Volume"},
 810
 811         /* HF or LineOut path */
 812
 813         {"DA_IN3", NULL, "ab8500_0p"},
 814         {"DA3 Channel Volume", NULL, "DA_IN3"},
 815         {"DA_IN4", NULL, "ab8500_0p"},
 816         {"DA4 Channel Volume", NULL, "DA_IN4"},
 817
 818         {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
 819         {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
 820
 821         {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
 822         {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
 823
 824         /* HF path */
 825
 826         {"HFL DAC", NULL, "DA3 or ANC path to HfL"},
 827         {"HFR DAC", NULL, "DA4 or ANC path to HfR"},
 828
 829         {"HFL Enable", NULL, "HFL DAC"},
 830         {"HFR Enable", NULL, "HFR DAC"},
 831
 832         {"Speaker Left", NULL, "HFL Enable"},
 833         {"Speaker Right", NULL, "HFR Enable"},
 834
 835         /* Earpiece path */
 836
 837         {"Earpiece or LineOut Mono Source", "Headset Left",
 838                 "HSL Digital Volume"},
 839         {"Earpiece or LineOut Mono Source", "Speaker Left",
 840                 "DA3 or ANC path to HfL"},
 841
 842         {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
 843
 844         {"EAR Mute", NULL, "EAR DAC"},
 845
 846         {"EAR Enable", NULL, "EAR Mute"},
 847
 848         {"Earpiece", NULL, "EAR Enable"},
 849
 850         /* LineOut path stereo */
 851
 852         {"LineOut Source", "Stereo Path", "HSL DAC Driver"},
 853         {"LineOut Source", "Stereo Path", "HSR DAC Driver"},
 854
 855         /* LineOut path mono */
 856
 857         {"LineOut Source", "Mono Path", "EAR DAC"},
 858
 859         /* LineOut path */
 860
 861         {"LOL Disable HFL", NULL, "LineOut Source"},
 862         {"LOR Disable HFR", NULL, "LineOut Source"},
 863
 864         {"LOL Enable", NULL, "LOL Disable HFL"},
 865         {"LOR Enable", NULL, "LOR Disable HFR"},
 866
 867         {"LineOut Left", NULL, "LOL Enable"},
 868         {"LineOut Right", NULL, "LOR Enable"},
 869
 870         /* Vibrator path */
 871
 872         {"DA_IN5", NULL, "ab8500_0p"},
 873         {"DA5 Channel Volume", NULL, "DA_IN5"},
 874         {"DA_IN6", NULL, "ab8500_0p"},
 875         {"DA6 Channel Volume", NULL, "DA_IN6"},
 876
 877         {"VIB1 DAC", NULL, "DA5 Channel Volume"},
 878         {"VIB2 DAC", NULL, "DA6 Channel Volume"},
 879
 880         {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
 881         {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
 882         {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
 883         {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
 884
 885         {"VIB1 Enable", NULL, "Vibra 1 Controller"},
 886         {"VIB2 Enable", NULL, "Vibra 2 Controller"},
 887
 888         {"Vibra 1", NULL, "VIB1 Enable"},
 889         {"Vibra 2", NULL, "VIB2 Enable"},
 890
 891
 892         /* Mic 2 */
 893
 894         {"MIC2 V-AMICx Enable", NULL, "Mic 2"},
 895
 896         /* LineIn */
 897         {"LINL Mute", NULL, "LineIn Left"},
 898         {"LINR Mute", NULL, "LineIn Right"},
 899
 900         {"LINL Enable", NULL, "LINL Mute"},
 901         {"LINR Enable", NULL, "LINR Mute"},
 902
 903         /* LineIn, Mic 2 */
 904         {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
 905         {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
 906
 907         {"LINL ADC", NULL, "LINL Enable"},
 908         {"LINR ADC", NULL, "Mic 2 or LINR Select"},
 909
 910         {"AD1 Source Select", "LineIn Left", "LINL ADC"},
 911         {"AD2 Source Select", "LineIn Right", "LINR ADC"},
 912
 913         {"AD1 Channel Volume", NULL, "AD1 Source Select"},
 914         {"AD2 Channel Volume", NULL, "AD2 Source Select"},
 915
 916         {"AD12 Enable", NULL, "AD1 Channel Volume"},
 917         {"AD12 Enable", NULL, "AD2 Channel Volume"},
 918
 919         {"AD_OUT1", NULL, "ab8500_0c"},
 920         {"AD_OUT1", NULL, "AD12 Enable"},
 921         {"AD_OUT2", NULL, "ab8500_0c"},
 922         {"AD_OUT2", NULL, "AD12 Enable"},
 923
 924         /* Mic 1 */
 925
 926         {"MIC1 Mute", NULL, "Mic 1"},
 927
 928         {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
 929         {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
 930
 931         {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
 932         {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
 933
 934         {"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
 935
 936         {"AD3 Source Select", "Mic 1", "MIC1 ADC"},
 937
 938         {"AD3 Channel Volume", NULL, "AD3 Source Select"},
 939
 940         {"AD3 Enable", NULL, "AD3 Channel Volume"},
 941
 942         {"AD_OUT3", NULL, "ab8500_0c"},
 943         {"AD_OUT3", NULL, "AD3 Enable"},
 944
 945         /* HD Capture path */
 946
 947         {"AD5 Source Select", "Mic 2", "LINR ADC"},
 948         {"AD6 Source Select", "Mic 1", "MIC1 ADC"},
 949
 950         {"AD5 Channel Volume", NULL, "AD5 Source Select"},
 951         {"AD6 Channel Volume", NULL, "AD6 Source Select"},
 952
 953         {"AD57 Enable", NULL, "AD5 Channel Volume"},
 954         {"AD68 Enable", NULL, "AD6 Channel Volume"},
 955
 956         {"AD_OUT57", NULL, "ab8500_0c"},
 957         {"AD_OUT57", NULL, "AD57 Enable"},
 958         {"AD_OUT68", NULL, "ab8500_0c"},
 959         {"AD_OUT68", NULL, "AD68 Enable"},
 960
 961         /* Digital Microphone path */
 962
 963         {"DMic 1", NULL, "V-DMIC"},
 964         {"DMic 2", NULL, "V-DMIC"},
 965         {"DMic 3", NULL, "V-DMIC"},
 966         {"DMic 4", NULL, "V-DMIC"},
 967         {"DMic 5", NULL, "V-DMIC"},
 968         {"DMic 6", NULL, "V-DMIC"},
 969
 970         {"AD1 Source Select", NULL, "DMic 1"},
 971         {"AD2 Source Select", NULL, "DMic 2"},
 972         {"AD3 Source Select", NULL, "DMic 3"},
 973         {"AD5 Source Select", NULL, "DMic 5"},
 974         {"AD6 Source Select", NULL, "DMic 6"},
 975
 976         {"AD4 Channel Volume", NULL, "DMic 4"},
 977         {"AD4 Enable", NULL, "AD4 Channel Volume"},
 978
 979         {"AD_OUT4", NULL, "ab8500_0c"},
 980         {"AD_OUT4", NULL, "AD4 Enable"},
 981
 982         /* LineIn Bypass path */
 983
 984         {"LINL to HSL Volume", NULL, "LINL Enable"},
 985         {"LINR to HSR Volume", NULL, "LINR Enable"},
 986
 987         {"HSL DAC Driver", NULL, "LINL to HSL Volume"},
 988         {"HSR DAC Driver", NULL, "LINR to HSR Volume"},
 989
 990         /* ANC path (Acoustic Noise Cancellation) */
 991
 992         {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
 993         {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
 994
 995         {"ANC", "Switch", "ANC Source"},
 996
 997         {"Speaker Left Source", "ANC", "ANC"},
 998         {"Speaker Right Source", "ANC", "ANC"},
 999         {"ANC to Earpiece", "Switch", "ANC"},
1000
1001         {"HSL Digital Volume", NULL, "ANC to Earpiece"},
1002
1003         /* Sidetone Filter path */
1004
1005         {"Sidetone Left Source", "LineIn Left", "AD12 Enable"},
1006         {"Sidetone Left Source", "LineIn Right", "AD12 Enable"},
1007         {"Sidetone Left Source", "Mic 1", "AD3 Enable"},
1008         {"Sidetone Left Source", "Headset Left", "DA_IN1"},
1009         {"Sidetone Right Source", "LineIn Right", "AD12 Enable"},
1010         {"Sidetone Right Source", "Mic 1", "AD3 Enable"},
1011         {"Sidetone Right Source", "DMic 4", "AD4 Enable"},
1012         {"Sidetone Right Source", "Headset Right", "DA_IN2"},
1013
1014         {"STFIR1 Control", NULL, "Sidetone Left Source"},
1015         {"STFIR2 Control", NULL, "Sidetone Right Source"},
1016
1017         {"STFIR1 Volume", NULL, "STFIR1 Control"},
1018         {"STFIR2 Volume", NULL, "STFIR2 Control"},
1019
1020         {"DA1 Enable", NULL, "STFIR1 Volume"},
1021         {"DA2 Enable", NULL, "STFIR2 Volume"},
1022 };
1023
1024 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
1025         {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
1026         {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
1027 };
1028
1029 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
1030         {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
1031         {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
1032 };
1033
1034 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
1035         {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
1036         {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
1037 };
1038
1039 /* ANC FIR-coefficients configuration sequence */
1040 static void anc_fir(struct snd_soc_codec *codec,
1041                 unsigned int bnk, unsigned int par, unsigned int val)
1042 {
1043         if (par == 0 && bnk == 0)
1044                 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1045                         BIT(AB8500_ANCCONF1_ANCFIRUPDATE),
1046                         BIT(AB8500_ANCCONF1_ANCFIRUPDATE));
1047
1048         snd_soc_write(codec, AB8500_ANCCONF5, val >> 8 & 0xff);
1049         snd_soc_write(codec, AB8500_ANCCONF6, val &  0xff);
1050
1051         if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1)
1052                 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1053                         BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0);
1054 }
1055
1056 /* ANC IIR-coefficients configuration sequence */
1057 static void anc_iir(struct snd_soc_codec *codec, unsigned int bnk,
1058                 unsigned int par, unsigned int val)
1059 {
1060         if (par == 0) {
1061                 if (bnk == 0) {
1062                         snd_soc_update_bits(codec, AB8500_ANCCONF1,
1063                                         BIT(AB8500_ANCCONF1_ANCIIRINIT),
1064                                         BIT(AB8500_ANCCONF1_ANCIIRINIT));
1065                         usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY);
1066                         snd_soc_update_bits(codec, AB8500_ANCCONF1,
1067                                         BIT(AB8500_ANCCONF1_ANCIIRINIT), 0);
1068                         usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY);
1069                 } else {
1070                         snd_soc_update_bits(codec, AB8500_ANCCONF1,
1071                                         BIT(AB8500_ANCCONF1_ANCIIRUPDATE),
1072                                         BIT(AB8500_ANCCONF1_ANCIIRUPDATE));
1073                 }
1074         } else if (par > 3) {
1075                 snd_soc_write(codec, AB8500_ANCCONF7, 0);
1076                 snd_soc_write(codec, AB8500_ANCCONF8, val >> 16 & 0xff);
1077         }
1078
1079         snd_soc_write(codec, AB8500_ANCCONF7, val >> 8 & 0xff);
1080         snd_soc_write(codec, AB8500_ANCCONF8, val & 0xff);
1081
1082         if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1)
1083                 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1084                         BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0);
1085 }
1086
1087 /* ANC IIR-/FIR-coefficients configuration sequence */
1088 static void anc_configure(struct snd_soc_codec *codec,
1089                         bool apply_fir, bool apply_iir)
1090 {
1091         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1092         unsigned int bnk, par, val;
1093
1094         dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1095
1096         if (apply_fir)
1097                 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1098                         BIT(AB8500_ANCCONF1_ENANC), 0);
1099
1100         snd_soc_update_bits(codec, AB8500_ANCCONF1,
1101                 BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC));
1102
1103         if (apply_fir)
1104                 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1105                         for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) {
1106                                 val = snd_soc_read(codec,
1107                                                 drvdata->anc_fir_values[par]);
1108                                 anc_fir(codec, bnk, par, val);
1109                         }
1110
1111         if (apply_iir)
1112                 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1113                         for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) {
1114                                 val = snd_soc_read(codec,
1115                                                 drvdata->anc_iir_values[par]);
1116                                 anc_iir(codec, bnk, par, val);
1117                         }
1118
1119         dev_dbg(codec->dev, "%s: Exit.\n", __func__);
1120 }
1121
1122 /*
1123  * Control-events
1124  */
1125
1126 static int sid_status_control_get(struct snd_kcontrol *kcontrol,
1127                 struct snd_ctl_elem_value *ucontrol)
1128 {
1129         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1130         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1131
1132         mutex_lock(&drvdata->ctrl_lock);
1133         ucontrol->value.enumerated.item[0] = drvdata->sid_status;
1134         mutex_unlock(&drvdata->ctrl_lock);
1135
1136         return 0;
1137 }
1138
1139 /* Write sidetone FIR-coefficients configuration sequence */
1140 static int sid_status_control_put(struct snd_kcontrol *kcontrol,
1141                                 struct snd_ctl_elem_value *ucontrol)
1142 {
1143         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1144         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1145         unsigned int param, sidconf, val;
1146         int status = 1;
1147
1148         dev_dbg(codec->dev, "%s: Enter\n", __func__);
1149
1150         if (ucontrol->value.enumerated.item[0] != SID_APPLY_FIR) {
1151                 dev_err(codec->dev,
1152                         "%s: ERROR: This control supports '%s' only!\n",
1153                         __func__, enum_sid_state[SID_APPLY_FIR]);
1154                 return -EIO;
1155         }
1156
1157         mutex_lock(&drvdata->ctrl_lock);
1158
1159         sidconf = snd_soc_read(codec, AB8500_SIDFIRCONF);
1160         if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) {
1161                 if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) {
1162                         dev_err(codec->dev, "%s: Sidetone busy while off!\n",
1163                                 __func__);
1164                         status = -EPERM;
1165                 } else {
1166                         status = -EBUSY;
1167                 }
1168                 goto out;
1169         }
1170
1171         snd_soc_write(codec, AB8500_SIDFIRADR, 0);
1172
1173         for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) {
1174                 val = snd_soc_read(codec, drvdata->sid_fir_values[param]);
1175                 snd_soc_write(codec, AB8500_SIDFIRCOEF1, val >> 8 & 0xff);
1176                 snd_soc_write(codec, AB8500_SIDFIRCOEF2, val & 0xff);
1177         }
1178
1179         snd_soc_update_bits(codec, AB8500_SIDFIRADR,
1180                 BIT(AB8500_SIDFIRADR_FIRSIDSET),
1181                 BIT(AB8500_SIDFIRADR_FIRSIDSET));
1182         snd_soc_update_bits(codec, AB8500_SIDFIRADR,
1183                 BIT(AB8500_SIDFIRADR_FIRSIDSET), 0);
1184
1185         drvdata->sid_status = SID_FIR_CONFIGURED;
1186
1187 out:
1188         mutex_unlock(&drvdata->ctrl_lock);
1189
1190         dev_dbg(codec->dev, "%s: Exit\n", __func__);
1191
1192         return status;
1193 }
1194
1195 static int anc_status_control_get(struct snd_kcontrol *kcontrol,
1196                                 struct snd_ctl_elem_value *ucontrol)
1197 {
1198         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1199         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1200
1201         mutex_lock(&drvdata->ctrl_lock);
1202         ucontrol->value.enumerated.item[0] = drvdata->anc_status;
1203         mutex_unlock(&drvdata->ctrl_lock);
1204
1205         return 0;
1206 }
1207
1208 static int anc_status_control_put(struct snd_kcontrol *kcontrol,
1209                                 struct snd_ctl_elem_value *ucontrol)
1210 {
1211         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1212         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1213         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1214         struct device *dev = codec->dev;
1215         bool apply_fir, apply_iir;
1216         unsigned int req;
1217         int status;
1218
1219         dev_dbg(dev, "%s: Enter.\n", __func__);
1220
1221         mutex_lock(&drvdata->ctrl_lock);
1222
1223         req = ucontrol->value.enumerated.item[0];
1224         if (req >= ARRAY_SIZE(enum_anc_state)) {
1225                 status = -EINVAL;
1226                 goto cleanup;
1227         }
1228         if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR &&
1229                 req != ANC_APPLY_IIR) {
1230                 dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n",
1231                         __func__, enum_anc_state[req]);
1232                 status = -EINVAL;
1233                 goto cleanup;
1234         }
1235         apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR;
1236         apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR;
1237
1238         status = snd_soc_dapm_force_enable_pin(dapm, "ANC Configure Input");
1239         if (status < 0) {
1240                 dev_err(dev,
1241                         "%s: ERROR: Failed to enable power (status = %d)!\n",
1242                         __func__, status);
1243                 goto cleanup;
1244         }
1245         snd_soc_dapm_sync(dapm);
1246
1247         anc_configure(codec, apply_fir, apply_iir);
1248
1249         if (apply_fir) {
1250                 if (drvdata->anc_status == ANC_IIR_CONFIGURED)
1251                         drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1252                 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1253                         drvdata->anc_status =  ANC_FIR_CONFIGURED;
1254         }
1255         if (apply_iir) {
1256                 if (drvdata->anc_status == ANC_FIR_CONFIGURED)
1257                         drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1258                 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1259                         drvdata->anc_status =  ANC_IIR_CONFIGURED;
1260         }
1261
1262         status = snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
1263         snd_soc_dapm_sync(dapm);
1264
1265 cleanup:
1266         mutex_unlock(&drvdata->ctrl_lock);
1267
1268         if (status < 0)
1269                 dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n",
1270                         __func__, status);
1271
1272         dev_dbg(dev, "%s: Exit.\n", __func__);
1273
1274         return (status < 0) ? status : 1;
1275 }
1276
1277 static int filter_control_info(struct snd_kcontrol *kcontrol,
1278                         struct snd_ctl_elem_info *uinfo)
1279 {
1280         struct filter_control *fc =
1281                         (struct filter_control *)kcontrol->private_value;
1282
1283         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1284         uinfo->count = fc->count;
1285         uinfo->value.integer.min = fc->min;
1286         uinfo->value.integer.max = fc->max;
1287
1288         return 0;
1289 }
1290
1291 static int filter_control_get(struct snd_kcontrol *kcontrol,
1292                         struct snd_ctl_elem_value *ucontrol)
1293 {
1294         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1295         struct ab8500_codec_drvdata *drvdata = snd_soc_codec_get_drvdata(codec);
1296         struct filter_control *fc =
1297                         (struct filter_control *)kcontrol->private_value;
1298         unsigned int i;
1299
1300         mutex_lock(&drvdata->ctrl_lock);
1301         for (i = 0; i < fc->count; i++)
1302                 ucontrol->value.integer.value[i] = fc->value[i];
1303         mutex_unlock(&drvdata->ctrl_lock);
1304
1305         return 0;
1306 }
1307
1308 static int filter_control_put(struct snd_kcontrol *kcontrol,
1309                 struct snd_ctl_elem_value *ucontrol)
1310 {
1311         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1312         struct ab8500_codec_drvdata *drvdata = snd_soc_codec_get_drvdata(codec);
1313         struct filter_control *fc =
1314                         (struct filter_control *)kcontrol->private_value;
1315         unsigned int i;
1316
1317         mutex_lock(&drvdata->ctrl_lock);
1318         for (i = 0; i < fc->count; i++)
1319                 fc->value[i] = ucontrol->value.integer.value[i];
1320         mutex_unlock(&drvdata->ctrl_lock);
1321
1322         return 0;
1323 }
1324
1325 /*
1326  * Controls - Non-DAPM ASoC
1327  */
1328
1329 static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
1330 /* -32dB = Mute */
1331
1332 static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
1333 /* -63dB = Mute */
1334
1335 static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
1336 /* -1dB = Mute */
1337
1338 static const DECLARE_TLV_DB_RANGE(hs_gain_tlv,
1339         0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
1340         4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0)
1341 );
1342
1343 static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
1344
1345 static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
1346
1347 static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
1348 /* -38dB = Mute */
1349
1350 static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
1351                                         "5ms"};
1352 static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
1353         AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
1354
1355 static const char * const enum_envdetthre[] = {
1356         "250mV", "300mV", "350mV", "400mV",
1357         "450mV", "500mV", "550mV", "600mV",
1358         "650mV", "700mV", "750mV", "800mV",
1359         "850mV", "900mV", "950mV", "1.00V" };
1360 static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
1361         AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
1362 static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
1363         AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
1364 static const char * const enum_envdettime[] = {
1365         "26.6us", "53.2us", "106us",  "213us",
1366         "426us",  "851us",  "1.70ms", "3.40ms",
1367         "6.81ms", "13.6ms", "27.2ms", "54.5ms",
1368         "109ms",  "218ms",  "436ms",  "872ms" };
1369 static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
1370         AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
1371
1372 static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
1373 static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
1374                         AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
1375
1376 static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
1377 static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
1378                         AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
1379
1380 /* Earpiece */
1381
1382 static const char * const enum_lowpow[] = {"Normal", "Low Power"};
1383 static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
1384                         AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
1385 static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
1386                         AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
1387
1388 static const char * const enum_av_mode[] = {"Audio", "Voice"};
1389 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
1390         AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
1391 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
1392         AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
1393
1394 /* DA */
1395
1396 static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
1397                         AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
1398                         enum_av_mode);
1399 static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
1400                         AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
1401                         enum_av_mode);
1402 static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
1403                         AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
1404                         enum_av_mode);
1405
1406 static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
1407 static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
1408                         AB8500_DIGMULTCONF1_DATOHSLEN,
1409                         AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
1410
1411 static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
1412 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
1413                         AB8500_DMICFILTCONF_DMIC1SINC3,
1414                         AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
1415 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
1416                         AB8500_DMICFILTCONF_DMIC3SINC3,
1417                         AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
1418 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
1419                         AB8500_DMICFILTCONF_DMIC5SINC3,
1420                         AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
1421
1422 /* Digital interface - DA from slot mapping */
1423 static const char * const enum_da_from_slot_map[] = {"SLOT0",
1424                                         "SLOT1",
1425                                         "SLOT2",
1426                                         "SLOT3",
1427                                         "SLOT4",
1428                                         "SLOT5",
1429                                         "SLOT6",
1430                                         "SLOT7",
1431                                         "SLOT8",
1432                                         "SLOT9",
1433                                         "SLOT10",
1434                                         "SLOT11",
1435                                         "SLOT12",
1436                                         "SLOT13",
1437                                         "SLOT14",
1438                                         "SLOT15",
1439                                         "SLOT16",
1440                                         "SLOT17",
1441                                         "SLOT18",
1442                                         "SLOT19",
1443                                         "SLOT20",
1444                                         "SLOT21",
1445                                         "SLOT22",
1446                                         "SLOT23",
1447                                         "SLOT24",
1448                                         "SLOT25",
1449                                         "SLOT26",
1450                                         "SLOT27",
1451                                         "SLOT28",
1452                                         "SLOT29",
1453                                         "SLOT30",
1454                                         "SLOT31"};
1455 static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
1456                         AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1457                         enum_da_from_slot_map);
1458 static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
1459                         AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1460                         enum_da_from_slot_map);
1461 static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
1462                         AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1463                         enum_da_from_slot_map);
1464 static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
1465                         AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1466                         enum_da_from_slot_map);
1467 static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
1468                         AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1469                         enum_da_from_slot_map);
1470 static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
1471                         AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1472                         enum_da_from_slot_map);
1473 static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
1474                         AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1475                         enum_da_from_slot_map);
1476 static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
1477                         AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1478                         enum_da_from_slot_map);
1479
1480 /* Digital interface - AD to slot mapping */
1481 static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
1482                                         "AD_OUT2",
1483                                         "AD_OUT3",
1484                                         "AD_OUT4",
1485                                         "AD_OUT5",
1486                                         "AD_OUT6",
1487                                         "AD_OUT7",
1488                                         "AD_OUT8",
1489                                         "zeroes",
1490                                         "zeroes",
1491                                         "zeroes",
1492                                         "zeroes",
1493                                         "tristate",
1494                                         "tristate",
1495                                         "tristate",
1496                                         "tristate"};
1497 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
1498                         AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
1499                         enum_ad_to_slot_map);
1500 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
1501                         AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
1502                         enum_ad_to_slot_map);
1503 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
1504                         AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
1505                         enum_ad_to_slot_map);
1506 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
1507                         AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
1508                         enum_ad_to_slot_map);
1509 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
1510                         AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
1511                         enum_ad_to_slot_map);
1512 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
1513                         AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
1514                         enum_ad_to_slot_map);
1515 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
1516                         AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
1517                         enum_ad_to_slot_map);
1518 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
1519                         AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
1520                         enum_ad_to_slot_map);
1521 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
1522                         AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
1523                         enum_ad_to_slot_map);
1524 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
1525                         AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
1526                         enum_ad_to_slot_map);
1527 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
1528                         AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
1529                         enum_ad_to_slot_map);
1530 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
1531                         AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
1532                         enum_ad_to_slot_map);
1533 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
1534                         AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
1535                         enum_ad_to_slot_map);
1536 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
1537                         AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
1538                         enum_ad_to_slot_map);
1539 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
1540                         AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
1541                         enum_ad_to_slot_map);
1542 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
1543                         AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
1544                         enum_ad_to_slot_map);
1545 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
1546                         AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
1547                         enum_ad_to_slot_map);
1548 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
1549                         AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
1550                         enum_ad_to_slot_map);
1551 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
1552                         AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
1553                         enum_ad_to_slot_map);
1554 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
1555                         AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
1556                         enum_ad_to_slot_map);
1557 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
1558                         AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
1559                         enum_ad_to_slot_map);
1560 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
1561                         AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
1562                         enum_ad_to_slot_map);
1563 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
1564                         AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
1565                         enum_ad_to_slot_map);
1566 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
1567                         AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
1568                         enum_ad_to_slot_map);
1569 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
1570                         AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
1571                         enum_ad_to_slot_map);
1572 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
1573                         AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
1574                         enum_ad_to_slot_map);
1575 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
1576                         AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
1577                         enum_ad_to_slot_map);
1578 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
1579                         AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
1580                         enum_ad_to_slot_map);
1581 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
1582                         AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
1583                         enum_ad_to_slot_map);
1584 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
1585                         AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
1586                         enum_ad_to_slot_map);
1587 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
1588                         AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
1589                         enum_ad_to_slot_map);
1590 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
1591                         AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
1592                         enum_ad_to_slot_map);
1593
1594 /* Digital interface - Burst mode */
1595 static const char * const enum_mask[] = {"Unmasked", "Masked"};
1596 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
1597                         AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
1598                         enum_mask);
1599 static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
1600 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
1601                         AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
1602                         enum_bitclk0);
1603 static const char * const enum_slavemaster[] = {"Slave", "Master"};
1604 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
1605                         AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
1606                         enum_slavemaster);
1607
1608 /* Sidetone */
1609 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state);
1610
1611 /* ANC */
1612 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state);
1613
1614 static struct snd_kcontrol_new ab8500_ctrls[] = {
1615         /* Charge pump */
1616         SOC_ENUM("Charge Pump High Threshold For Low Voltage",
1617                 soc_enum_envdeththre),
1618         SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
1619                 soc_enum_envdetlthre),
1620         SOC_SINGLE("Charge Pump Envelope Detection Switch",
1621                 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
1622                 1, 0),
1623         SOC_ENUM("Charge Pump Envelope Detection Decay Time",
1624                 soc_enum_envdettime),
1625
1626         /* Headset */
1627         SOC_ENUM("Headset Mode", soc_enum_da12voice),
1628         SOC_SINGLE("Headset High Pass Switch",
1629                 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
1630                 1, 0),
1631         SOC_SINGLE("Headset Low Power Switch",
1632                 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
1633                 1, 0),
1634         SOC_SINGLE("Headset DAC Low Power Switch",
1635                 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
1636                 1, 0),
1637         SOC_SINGLE("Headset DAC Drv Low Power Switch",
1638                 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
1639                 1, 0),
1640         SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
1641         SOC_ENUM("Headset Source", soc_enum_da2hslr),
1642         SOC_ENUM("Headset Filter", soc_enum_hsesinc),
1643         SOC_DOUBLE_R_TLV("Headset Master Volume",
1644                 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
1645                 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1646         SOC_DOUBLE_R_TLV("Headset Digital Volume",
1647                 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
1648                 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
1649         SOC_DOUBLE_TLV("Headset Volume",
1650                 AB8500_ANAGAIN3,
1651                 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
1652                 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
1653
1654         /* Earpiece */
1655         SOC_ENUM("Earpiece DAC Mode",
1656                 soc_enum_eardaclowpow),
1657         SOC_ENUM("Earpiece DAC Drv Mode",
1658                 soc_enum_eardrvlowpow),
1659
1660         /* HandsFree */
1661         SOC_ENUM("HF Mode", soc_enum_da34voice),
1662         SOC_SINGLE("HF and Headset Swap Switch",
1663                 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
1664                 1, 0),
1665         SOC_DOUBLE("HF Low EMI Mode Switch",
1666                 AB8500_CLASSDCONF1,
1667                 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
1668                 1, 0),
1669         SOC_DOUBLE("HF FIR Bypass Switch",
1670                 AB8500_CLASSDCONF2,
1671                 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
1672                 1, 0),
1673         SOC_DOUBLE("HF High Volume Switch",
1674                 AB8500_CLASSDCONF2,
1675                 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
1676                 1, 0),
1677         SOC_SINGLE("HF L and R Bridge Switch",
1678                 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
1679                 1, 0),
1680         SOC_DOUBLE_R_TLV("HF Master Volume",
1681                 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
1682                 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1683
1684         /* Vibra */
1685         SOC_DOUBLE("Vibra High Volume Switch",
1686                 AB8500_CLASSDCONF2,
1687                 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
1688                 1, 0),
1689         SOC_DOUBLE("Vibra Low EMI Mode Switch",
1690                 AB8500_CLASSDCONF1,
1691                 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
1692                 1, 0),
1693         SOC_DOUBLE("Vibra FIR Bypass Switch",
1694                 AB8500_CLASSDCONF2,
1695                 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
1696                 1, 0),
1697         SOC_ENUM("Vibra Mode", soc_enum_da56voice),
1698         SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
1699                 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
1700                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1701                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1702         SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
1703                 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
1704                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1705                 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1706         SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
1707                 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
1708                 1, 0),
1709         SOC_DOUBLE_R_TLV("Vibra Master Volume",
1710                 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
1711                 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1712
1713         /* HandsFree, Vibra */
1714         SOC_SINGLE("ClassD High Pass Volume",
1715                 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
1716                 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
1717         SOC_SINGLE("ClassD White Volume",
1718                 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
1719                 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
1720
1721         /* Mic 1, Mic 2, LineIn */
1722         SOC_DOUBLE_R_TLV("Mic Master Volume",
1723                 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
1724                 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1725
1726         /* Mic 1 */
1727         SOC_SINGLE_TLV("Mic 1",
1728                 AB8500_ANAGAIN1,
1729                 AB8500_ANAGAINX_MICXGAIN,
1730                 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1731         SOC_SINGLE("Mic 1 Low Power Switch",
1732                 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
1733                 1, 0),
1734
1735         /* Mic 2 */
1736         SOC_DOUBLE("Mic High Pass Switch",
1737                 AB8500_ADFILTCONF,
1738                 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
1739                 1, 1),
1740         SOC_ENUM("Mic Mode", soc_enum_ad34voice),
1741         SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
1742         SOC_SINGLE_TLV("Mic 2",
1743                 AB8500_ANAGAIN2,
1744                 AB8500_ANAGAINX_MICXGAIN,
1745                 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1746         SOC_SINGLE("Mic 2 Low Power Switch",
1747                 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
1748                 1, 0),
1749
1750         /* LineIn */
1751         SOC_DOUBLE("LineIn High Pass Switch",
1752                 AB8500_ADFILTCONF,
1753                 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
1754                 1, 1),
1755         SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
1756         SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
1757         SOC_DOUBLE_R_TLV("LineIn Master Volume",
1758                 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
1759                 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1760         SOC_DOUBLE_TLV("LineIn",
1761                 AB8500_ANAGAIN4,
1762                 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
1763                 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
1764         SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
1765                 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
1766                 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
1767                 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
1768                 1, lin2hs_gain_tlv),
1769
1770         /* DMic */
1771         SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
1772         SOC_DOUBLE_R_TLV("DMic Master Volume",
1773                 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
1774                 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1775
1776         /* Digital gains */
1777         SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
1778
1779         /* Analog loopback */
1780         SOC_DOUBLE_R_TLV("Analog Loopback Volume",
1781                 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
1782                 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
1783
1784         /* Digital interface - DA from slot mapping */
1785         SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
1786         SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
1787         SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
1788         SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
1789         SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
1790         SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
1791         SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
1792         SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
1793
1794         /* Digital interface - AD to slot mapping */
1795         SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
1796         SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
1797         SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
1798         SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
1799         SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
1800         SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
1801         SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
1802         SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
1803         SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
1804         SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
1805         SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
1806         SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
1807         SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
1808         SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
1809         SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
1810         SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
1811         SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
1812         SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
1813         SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
1814         SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
1815         SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
1816         SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
1817         SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
1818         SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
1819         SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
1820         SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
1821         SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
1822         SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
1823         SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
1824         SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
1825         SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
1826         SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
1827
1828         /* Digital interface - Loopback */
1829         SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
1830                 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
1831                 1, 0),
1832         SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
1833                 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
1834                 1, 0),
1835         SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
1836                 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
1837                 1, 0),
1838         SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
1839                 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
1840                 1, 0),
1841         SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
1842                 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
1843                 1, 0),
1844         SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
1845                 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
1846                 1, 0),
1847         SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
1848                 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
1849                 1, 0),
1850         SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
1851                 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
1852                 1, 0),
1853
1854         /* Digital interface - Burst FIFO */
1855         SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
1856                 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
1857                 1, 0),
1858         SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
1859         SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
1860         SOC_SINGLE("Burst FIFO Threshold",
1861                 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
1862                 AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
1863         SOC_SINGLE("Burst FIFO Length",
1864                 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
1865                 AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
1866         SOC_SINGLE("Burst FIFO EOS Extra Slots",
1867                 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
1868                 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
1869         SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
1870                 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
1871                 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
1872         SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
1873
1874         SOC_SINGLE("Burst FIFO Interface Switch",
1875                 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
1876                 1, 0),
1877         SOC_SINGLE("Burst FIFO Switch Frame Number",
1878                 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
1879                 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
1880         SOC_SINGLE("Burst FIFO Wake Up Delay",
1881                 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
1882                 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
1883         SOC_SINGLE("Burst FIFO Samples In FIFO",
1884                 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
1885                 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
1886
1887         /* ANC */
1888         SOC_ENUM_EXT("ANC Status", soc_enum_ancstate,
1889                 anc_status_control_get, anc_status_control_put),
1890         SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
1891                 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
1892                 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
1893         SOC_SINGLE_XR_SX("ANC FIR Output Shift",
1894                 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
1895                 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
1896         SOC_SINGLE_XR_SX("ANC IIR Output Shift",
1897                 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
1898                 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
1899         SOC_SINGLE_XR_SX("ANC Warp Delay",
1900                 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
1901                 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
1902
1903         /* Sidetone */
1904         SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate,
1905                 sid_status_control_get, sid_status_control_put),
1906         SOC_SINGLE_STROBE("Sidetone Reset",
1907                 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
1908 };
1909
1910 static struct snd_kcontrol_new ab8500_filter_controls[] = {
1911         AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS,
1912                 AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX),
1913         AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS,
1914                 AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX),
1915         AB8500_FILTER_CONTROL("Sidetone FIR Coefficients",
1916                         AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN,
1917                         AB8500_SID_FIR_COEFF_MAX)
1918 };
1919 enum ab8500_filter {
1920         AB8500_FILTER_ANC_FIR = 0,
1921         AB8500_FILTER_ANC_IIR = 1,
1922         AB8500_FILTER_SID_FIR = 2,
1923 };
1924
1925 /*
1926  * Extended interface for codec-driver
1927  */
1928
1929 static int ab8500_audio_init_audioblock(struct snd_soc_codec *codec)
1930 {
1931         int status;
1932
1933         dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1934
1935         /* Reset audio-registers and disable 32kHz-clock output 2 */
1936         status = ab8500_sysctrl_write(AB8500_STW4500CTRL3,
1937                                 AB8500_STW4500CTRL3_CLK32KOUT2DIS |
1938                                         AB8500_STW4500CTRL3_RESETAUDN,
1939                                 AB8500_STW4500CTRL3_RESETAUDN);
1940         if (status < 0)
1941                 return status;
1942
1943         return 0;
1944 }
1945
1946 static int ab8500_audio_setup_mics(struct snd_soc_codec *codec,
1947                         struct amic_settings *amics)
1948 {
1949         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1950         u8 value8;
1951         unsigned int value;
1952         int status;
1953         const struct snd_soc_dapm_route *route;
1954
1955         dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1956
1957         /* Set DMic-clocks to outputs */
1958         status = abx500_get_register_interruptible(codec->dev, AB8500_MISC,
1959                                                 AB8500_GPIO_DIR4_REG,
1960                                                 &value8);
1961         if (status < 0)
1962                 return status;
1963         value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
1964                 GPIO31_DIR_OUTPUT;
1965         status = abx500_set_register_interruptible(codec->dev,
1966                                                 AB8500_MISC,
1967                                                 AB8500_GPIO_DIR4_REG,
1968                                                 value);
1969         if (status < 0)
1970                 return status;
1971
1972         /* Attach regulators to AMic DAPM-paths */
1973         dev_dbg(codec->dev, "%s: Mic 1a regulator: %s\n", __func__,
1974                 amic_micbias_str(amics->mic1a_micbias));
1975         route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
1976         status = snd_soc_dapm_add_routes(dapm, route, 1);
1977         dev_dbg(codec->dev, "%s: Mic 1b regulator: %s\n", __func__,
1978                 amic_micbias_str(amics->mic1b_micbias));
1979         route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
1980         status |= snd_soc_dapm_add_routes(dapm, route, 1);
1981         dev_dbg(codec->dev, "%s: Mic 2 regulator: %s\n", __func__,
1982                 amic_micbias_str(amics->mic2_micbias));
1983         route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
1984         status |= snd_soc_dapm_add_routes(dapm, route, 1);
1985         if (status < 0) {
1986                 dev_err(codec->dev,
1987                         "%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
1988                         __func__, status);
1989                 return status;
1990         }
1991
1992         /* Set AMic-configuration */
1993         dev_dbg(codec->dev, "%s: Mic 1 mic-type: %s\n", __func__,
1994                 amic_type_str(amics->mic1_type));
1995         snd_soc_update_bits(codec, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
1996                         amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
1997                                 0 : AB8500_ANAGAINX_ENSEMICX);
1998         dev_dbg(codec->dev, "%s: Mic 2 mic-type: %s\n", __func__,
1999                 amic_type_str(amics->mic2_type));
2000         snd_soc_update_bits(codec, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
2001                         amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
2002                                 0 : AB8500_ANAGAINX_ENSEMICX);
2003
2004         return 0;
2005 }
2006
2007 static int ab8500_audio_set_ear_cmv(struct snd_soc_codec *codec,
2008                                 enum ear_cm_voltage ear_cmv)
2009 {
2010         char *cmv_str;
2011
2012         switch (ear_cmv) {
2013         case EAR_CMV_0_95V:
2014                 cmv_str = "0.95V";
2015                 break;
2016         case EAR_CMV_1_10V:
2017                 cmv_str = "1.10V";
2018                 break;
2019         case EAR_CMV_1_27V:
2020                 cmv_str = "1.27V";
2021                 break;
2022         case EAR_CMV_1_58V:
2023                 cmv_str = "1.58V";
2024                 break;
2025         default:
2026                 dev_err(codec->dev,
2027                         "%s: Unknown earpiece CM-voltage (%d)!\n",
2028                         __func__, (int)ear_cmv);
2029                 return -EINVAL;
2030         }
2031         dev_dbg(codec->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
2032                 cmv_str);
2033         snd_soc_update_bits(codec, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
2034                         ear_cmv);
2035
2036         return 0;
2037 }
2038
2039 static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
2040                                 unsigned int delay)
2041 {
2042         unsigned int mask, val;
2043         struct snd_soc_codec *codec = dai->codec;
2044
2045         mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
2046         val = 0;
2047
2048         switch (delay) {
2049         case 0:
2050                 break;
2051         case 1:
2052                 val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
2053                 break;
2054         default:
2055                 dev_err(dai->codec->dev,
2056                         "%s: ERROR: Unsupported bit-delay (0x%x)!\n",
2057                         __func__, delay);
2058                 return -EINVAL;
2059         }
2060
2061         dev_dbg(dai->codec->dev, "%s: IF0 Bit-delay: %d bits.\n",
2062                 __func__, delay);
2063         snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2064
2065         return 0;
2066 }
2067
2068 /* Gates clocking according format mask */
2069 static int ab8500_codec_set_dai_clock_gate(struct snd_soc_codec *codec,
2070                                         unsigned int fmt)
2071 {
2072         unsigned int mask;
2073         unsigned int val;
2074
2075         mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
2076                         BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2077
2078         val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
2079
2080         switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
2081         case SND_SOC_DAIFMT_CONT: /* continuous clock */
2082                 dev_dbg(codec->dev, "%s: IF0 Clock is continuous.\n",
2083                         __func__);
2084                 val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2085                 break;
2086         case SND_SOC_DAIFMT_GATED: /* clock is gated */
2087                 dev_dbg(codec->dev, "%s: IF0 Clock is gated.\n",
2088                         __func__);
2089                 break;
2090         default:
2091                 dev_err(codec->dev,
2092                         "%s: ERROR: Unsupported clock mask (0x%x)!\n",
2093                         __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
2094                 return -EINVAL;
2095         }
2096
2097         snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val);
2098
2099         return 0;
2100 }
2101
2102 static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2103 {
2104         unsigned int mask;
2105         unsigned int val;
2106         struct snd_soc_codec *codec = dai->codec;
2107         int status;
2108
2109         dev_dbg(codec->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
2110
2111         mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
2112                         BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
2113                         BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
2114                         BIT(AB8500_DIGIFCONF3_IF0MASTER);
2115         val = 0;
2116
2117         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2118         case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & FRM master */
2119                 dev_dbg(dai->codec->dev,
2120                         "%s: IF0 Master-mode: AB8500 master.\n", __func__);
2121                 val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
2122                 break;
2123         case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & FRM slave */
2124                 dev_dbg(dai->codec->dev,
2125                         "%s: IF0 Master-mode: AB8500 slave.\n", __func__);
2126                 break;
2127         case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & FRM master */
2128         case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */
2129                 dev_err(dai->codec->dev,
2130                         "%s: ERROR: The device is either a master or a slave.\n",
2131                         __func__);
2132         default:
2133                 dev_err(dai->codec->dev,
2134                         "%s: ERROR: Unsupporter master mask 0x%x\n",
2135                         __func__, fmt & SND_SOC_DAIFMT_MASTER_MASK);
2136                 return -EINVAL;
2137         }
2138
2139         snd_soc_update_bits(codec, AB8500_DIGIFCONF3, mask, val);
2140
2141         /* Set clock gating */
2142         status = ab8500_codec_set_dai_clock_gate(codec, fmt);
2143         if (status) {
2144                 dev_err(dai->codec->dev,
2145                         "%s: ERROR: Failed to set clock gate (%d).\n",
2146                         __func__, status);
2147                 return status;
2148         }
2149
2150         /* Setting data transfer format */
2151
2152         mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
2153                 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
2154                 BIT(AB8500_DIGIFCONF2_FSYNC0P) |
2155                 BIT(AB8500_DIGIFCONF2_BITCLK0P);
2156         val = 0;
2157
2158         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2159         case SND_SOC_DAIFMT_I2S: /* I2S mode */
2160                 dev_dbg(dai->codec->dev, "%s: IF0 Protocol: I2S\n", __func__);
2161                 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
2162                 ab8500_audio_set_bit_delay(dai, 0);
2163                 break;
2164
2165         case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
2166                 dev_dbg(dai->codec->dev,
2167                         "%s: IF0 Protocol: DSP A (TDM)\n", __func__);
2168                 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2169                 ab8500_audio_set_bit_delay(dai, 1);
2170                 break;
2171
2172         case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
2173                 dev_dbg(dai->codec->dev,
2174                         "%s: IF0 Protocol: DSP B (TDM)\n", __func__);
2175                 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2176                 ab8500_audio_set_bit_delay(dai, 0);
2177                 break;
2178
2179         default:
2180                 dev_err(dai->codec->dev,
2181                         "%s: ERROR: Unsupported format (0x%x)!\n",
2182                         __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
2183                 return -EINVAL;
2184         }
2185
2186         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2187         case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
2188                 dev_dbg(dai->codec->dev,
2189                         "%s: IF0: Normal bit clock, normal frame\n",
2190                         __func__);
2191                 break;
2192         case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
2193                 dev_dbg(dai->codec->dev,
2194                         "%s: IF0: Normal bit clock, inverted frame\n",
2195                         __func__);
2196                 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2197                 break;
2198         case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
2199                 dev_dbg(dai->codec->dev,
2200                         "%s: IF0: Inverted bit clock, normal frame\n",
2201                         __func__);
2202                 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2203                 break;
2204         case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
2205                 dev_dbg(dai->codec->dev,
2206                         "%s: IF0: Inverted bit clock, inverted frame\n",
2207                         __func__);
2208                 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2209                 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2210                 break;
2211         default:
2212                 dev_err(dai->codec->dev,
2213                         "%s: ERROR: Unsupported INV mask 0x%x\n",
2214                         __func__, fmt & SND_SOC_DAIFMT_INV_MASK);
2215                 return -EINVAL;
2216         }
2217
2218         snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2219
2220         return 0;
2221 }
2222
2223 static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
2224                 unsigned int tx_mask, unsigned int rx_mask,
2225                 int slots, int slot_width)
2226 {
2227         struct snd_soc_codec *codec = dai->codec;
2228         unsigned int val, mask, slot, slots_active;
2229
2230         mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
2231                 BIT(AB8500_DIGIFCONF2_IF0WL1);
2232         val = 0;
2233
2234         switch (slot_width) {
2235         case 16:
2236                 break;
2237         case 20:
2238                 val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
2239                 break;
2240         case 24:
2241                 val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
2242                 break;
2243         case 32:
2244                 val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
2245                         BIT(AB8500_DIGIFCONF2_IF0WL0);
2246                 break;
2247         default:
2248                 dev_err(dai->codec->dev, "%s: Unsupported slot-width 0x%x\n",
2249                         __func__, slot_width);
2250                 return -EINVAL;
2251         }
2252
2253         dev_dbg(dai->codec->dev, "%s: IF0 slot-width: %d bits.\n",
2254                 __func__, slot_width);
2255         snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2256
2257         /* Setup TDM clocking according to slot count */
2258         dev_dbg(dai->codec->dev, "%s: Slots, total: %d\n", __func__, slots);
2259         mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2260                         BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2261         switch (slots) {
2262         case 2:
2263                 val = AB8500_MASK_NONE;
2264                 break;
2265         case 4:
2266                 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
2267                 break;
2268         case 8:
2269                 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2270                 break;
2271         case 16:
2272                 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2273                         BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2274                 break;
2275         default:
2276                 dev_err(dai->codec->dev,
2277                         "%s: ERROR: Unsupported number of slots (%d)!\n",
2278                         __func__, slots);
2279                 return -EINVAL;
2280         }
2281         snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val);
2282
2283         /* Setup TDM DA according to active tx slots */
2284
2285         if (tx_mask & ~0xff)
2286                 return -EINVAL;
2287
2288         mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
2289         tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET;
2290         slots_active = hweight32(tx_mask);
2291
2292         dev_dbg(dai->codec->dev, "%s: Slots, active, TX: %d\n", __func__,
2293                 slots_active);
2294
2295         switch (slots_active) {
2296         case 0:
2297                 break;
2298         case 1:
2299                 slot = ffs(tx_mask);
2300                 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot);
2301                 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot);
2302                 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot);
2303                 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot);
2304                 break;
2305         case 2:
2306                 slot = ffs(tx_mask);
2307                 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot);
2308                 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot);
2309                 slot = fls(tx_mask);
2310                 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot);
2311                 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot);
2312                 break;
2313         case 8:
2314                 dev_dbg(dai->codec->dev,
2315                         "%s: In 8-channel mode DA-from-slot mapping is set manually.",
2316                         __func__);
2317                 break;
2318         default:
2319                 dev_err(dai->codec->dev,
2320                         "%s: Unsupported number of active TX-slots (%d)!\n",
2321                         __func__, slots_active);
2322                 return -EINVAL;
2323         }
2324
2325         /* Setup TDM AD according to active RX-slots */
2326
2327         if (rx_mask & ~0xff)
2328                 return -EINVAL;
2329
2330         rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET;
2331         slots_active = hweight32(rx_mask);
2332
2333         dev_dbg(dai->codec->dev, "%s: Slots, active, RX: %d\n", __func__,
2334                 slots_active);
2335
2336         switch (slots_active) {
2337         case 0:
2338                 break;
2339         case 1:
2340                 slot = ffs(rx_mask);
2341                 snd_soc_update_bits(codec, AB8500_ADSLOTSEL(slot),
2342                                 AB8500_MASK_SLOT(slot),
2343                                 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2344                 break;
2345         case 2:
2346                 slot = ffs(rx_mask);
2347                 snd_soc_update_bits(codec,
2348                                 AB8500_ADSLOTSEL(slot),
2349                                 AB8500_MASK_SLOT(slot),
2350                                 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2351                 slot = fls(rx_mask);
2352                 snd_soc_update_bits(codec,
2353                                 AB8500_ADSLOTSEL(slot),
2354                                 AB8500_MASK_SLOT(slot),
2355                                 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot));
2356                 break;
2357         case 8:
2358                 dev_dbg(dai->codec->dev,
2359                         "%s: In 8-channel mode AD-to-slot mapping is set manually.",
2360                         __func__);
2361                 break;
2362         default:
2363                 dev_err(dai->codec->dev,
2364                         "%s: Unsupported number of active RX-slots (%d)!\n",
2365                         __func__, slots_active);
2366                 return -EINVAL;
2367         }
2368
2369         return 0;
2370 }
2371
2372 static const struct snd_soc_dai_ops ab8500_codec_ops = {
2373         .set_fmt = ab8500_codec_set_dai_fmt,
2374         .set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
2375 };
2376
2377 static struct snd_soc_dai_driver ab8500_codec_dai[] = {
2378         {
2379                 .name = "ab8500-codec-dai.0",
2380                 .id = 0,
2381                 .playback = {
2382                         .stream_name = "ab8500_0p",
2383                         .channels_min = 1,
2384                         .channels_max = 8,
2385                         .rates = AB8500_SUPPORTED_RATE,
2386                         .formats = AB8500_SUPPORTED_FMT,
2387                 },
2388                 .ops = &ab8500_codec_ops,
2389                 .symmetric_rates = 1
2390         },
2391         {
2392                 .name = "ab8500-codec-dai.1",
2393                 .id = 1,
2394                 .capture = {
2395                         .stream_name = "ab8500_0c",
2396                         .channels_min = 1,
2397                         .channels_max = 8,
2398                         .rates = AB8500_SUPPORTED_RATE,
2399                         .formats = AB8500_SUPPORTED_FMT,
2400                 },
2401                 .ops = &ab8500_codec_ops,
2402                 .symmetric_rates = 1
2403         }
2404 };
2405
2406 static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
2407                                 struct ab8500_codec_platform_data *codec)
2408 {
2409         u32 value;
2410
2411         if (of_get_property(np, "stericsson,amic1-type-single-ended", NULL))
2412                 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
2413         else
2414                 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
2415
2416         if (of_get_property(np, "stericsson,amic2-type-single-ended", NULL))
2417                 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
2418         else
2419                 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
2420
2421         /* Has a non-standard Vamic been requested? */
2422         if (of_get_property(np, "stericsson,amic1a-bias-vamic2", NULL))
2423                 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
2424         else
2425                 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
2426
2427         if (of_get_property(np, "stericsson,amic1b-bias-vamic2", NULL))
2428                 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
2429         else
2430                 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
2431
2432         if (of_get_property(np, "stericsson,amic2-bias-vamic1", NULL))
2433                 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
2434         else
2435                 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
2436
2437         if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
2438                 switch (value) {
2439                 case 950 :
2440                         codec->ear_cmv = EAR_CMV_0_95V;
2441                         break;
2442                 case 1100 :
2443                         codec->ear_cmv = EAR_CMV_1_10V;
2444                         break;
2445                 case 1270 :
2446                         codec->ear_cmv = EAR_CMV_1_27V;
2447                         break;
2448                 case 1580 :
2449                         codec->ear_cmv = EAR_CMV_1_58V;
2450                         break;
2451                 default :
2452                         codec->ear_cmv = EAR_CMV_UNKNOWN;
2453                         dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
2454                 }
2455         } else {
2456                 dev_warn(dev, "No earpiece voltage found in DT - using default\n");
2457                 codec->ear_cmv = EAR_CMV_0_95V;
2458         }
2459 }
2460
2461 static int ab8500_codec_probe(struct snd_soc_codec *codec)
2462 {
2463         struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2464         struct device *dev = codec->dev;
2465         struct device_node *np = dev->of_node;
2466         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
2467         struct ab8500_platform_data *pdata;
2468         struct filter_control *fc;
2469         int status;
2470
2471         dev_dbg(dev, "%s: Enter.\n", __func__);
2472
2473         /* Setup AB8500 according to board-settings */
2474         pdata = dev_get_platdata(dev->parent);
2475
2476         if (np) {
2477                 if (!pdata)
2478                         pdata = devm_kzalloc(dev,
2479                                         sizeof(struct ab8500_platform_data),
2480                                         GFP_KERNEL);
2481
2482                 if (pdata && !pdata->codec)
2483                         pdata->codec
2484                                 = devm_kzalloc(dev,
2485                                         sizeof(struct ab8500_codec_platform_data),
2486                                         GFP_KERNEL);
2487
2488                 if (!(pdata && pdata->codec))
2489                         return -ENOMEM;
2490
2491                 ab8500_codec_of_probe(dev, np, pdata->codec);
2492
2493         } else {
2494                 if (!(pdata && pdata->codec)) {
2495                         dev_err(dev, "No codec platform data or DT found\n");
2496                         return -EINVAL;
2497                 }
2498         }
2499
2500         status = ab8500_audio_setup_mics(codec, &pdata->codec->amics);
2501         if (status < 0) {
2502                 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
2503                 return status;
2504         }
2505         status = ab8500_audio_set_ear_cmv(codec, pdata->codec->ear_cmv);
2506         if (status < 0) {
2507                 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
2508                         __func__, status);
2509                 return status;
2510         }
2511
2512         status = ab8500_audio_init_audioblock(codec);
2513         if (status < 0) {
2514                 dev_err(dev, "%s: failed to init audio-block (%d)!\n",
2515                         __func__, status);
2516                 return status;
2517         }
2518
2519         /* Override HW-defaults */
2520         snd_soc_write(codec, AB8500_ANACONF5,
2521                       BIT(AB8500_ANACONF5_HSAUTOEN));
2522         snd_soc_write(codec, AB8500_SHORTCIRCONF,
2523                       BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
2524
2525         /* Add filter controls */
2526         status = snd_soc_add_codec_controls(codec, ab8500_filter_controls,
2527                                 ARRAY_SIZE(ab8500_filter_controls));
2528         if (status < 0) {
2529                 dev_err(dev,
2530                         "%s: failed to add ab8500 filter controls (%d).\n",
2531                         __func__, status);
2532                 return status;
2533         }
2534         fc = (struct filter_control *)
2535                 &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value;
2536         drvdata->anc_fir_values = (long *)fc->value;
2537         fc = (struct filter_control *)
2538                 &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value;
2539         drvdata->anc_iir_values = (long *)fc->value;
2540         fc = (struct filter_control *)
2541                 &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value;
2542         drvdata->sid_fir_values = (long *)fc->value;
2543
2544         snd_soc_dapm_disable_pin(dapm, "ANC Configure Input");
2545
2546         mutex_init(&drvdata->ctrl_lock);
2547
2548         return status;
2549 }
2550
2551 static struct snd_soc_codec_driver ab8500_codec_driver = {
2552         .probe =                ab8500_codec_probe,
2553         .controls =             ab8500_ctrls,
2554         .num_controls =         ARRAY_SIZE(ab8500_ctrls),
2555         .dapm_widgets =         ab8500_dapm_widgets,
2556         .num_dapm_widgets =     ARRAY_SIZE(ab8500_dapm_widgets),
2557         .dapm_routes =          ab8500_dapm_routes,
2558         .num_dapm_routes =      ARRAY_SIZE(ab8500_dapm_routes),
2559 };
2560
2561 static int ab8500_codec_driver_probe(struct platform_device *pdev)
2562 {
2563         int status;
2564         struct ab8500_codec_drvdata *drvdata;
2565
2566         dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
2567
2568         /* Create driver private-data struct */
2569         drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
2570                         GFP_KERNEL);
2571         if (!drvdata)
2572                 return -ENOMEM;
2573         drvdata->sid_status = SID_UNCONFIGURED;
2574         drvdata->anc_status = ANC_UNCONFIGURED;
2575         dev_set_drvdata(&pdev->dev, drvdata);
2576
2577         drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev,
2578                                            &ab8500_codec_regmap);
2579         if (IS_ERR(drvdata->regmap)) {
2580                 status = PTR_ERR(drvdata->regmap);
2581                 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
2582                         __func__, status);
2583                 return status;
2584         }
2585
2586         dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
2587         status = snd_soc_register_codec(&pdev->dev, &ab8500_codec_driver,
2588                                 ab8500_codec_dai,
2589                                 ARRAY_SIZE(ab8500_codec_dai));
2590         if (status < 0)
2591                 dev_err(&pdev->dev,
2592                         "%s: Error: Failed to register codec (%d).\n",
2593                         __func__, status);
2594
2595         return status;
2596 }
2597
2598 static int ab8500_codec_driver_remove(struct platform_device *pdev)
2599 {
2600         dev_dbg(&pdev->dev, "%s Enter.\n", __func__);
2601
2602         snd_soc_unregister_codec(&pdev->dev);
2603
2604         return 0;
2605 }
2606
2607 static struct platform_driver ab8500_codec_platform_driver = {
2608         .driver = {
2609                 .name   = "ab8500-codec",
2610         },
2611         .probe          = ab8500_codec_driver_probe,
2612         .remove         = ab8500_codec_driver_remove,
2613         .suspend        = NULL,
2614         .resume         = NULL,
2615 };
2616 module_platform_driver(ab8500_codec_platform_driver);
2617
2618 MODULE_LICENSE("GPL v2");