sound/soc/codecs/pcm512x.c

   1 /*
   2  * Driver for the PCM512x CODECs
   3  *
   4  * Author:      Mark Brown <broonie@linaro.org>
   5  *              Copyright 2014 Linaro Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  */
  16
  17
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/clk.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regmap.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/gcd.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/tlv.h>
  29
  30 #include "pcm512x.h"
  31
  32 #define DIV_ROUND_DOWN_ULL(ll, d) \
  33         ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
  34 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
  35         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  36
  37 #define PCM512x_NUM_SUPPLIES 3
  38 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
  39         "AVDD",
  40         "DVDD",
  41         "CPVDD",
  42 };
  43
  44 struct pcm512x_priv {
  45         struct regmap *regmap;
  46         struct clk *sclk;
  47         struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
  48         struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
  49         int fmt;
  50         int pll_in;
  51         int pll_out;
  52         int pll_r;
  53         int pll_j;
  54         int pll_d;
  55         int pll_p;
  56         unsigned long real_pll;
  57 };
  58
  59 /*
  60  * We can't use the same notifier block for more than one supply and
  61  * there's no way I can see to get from a callback to the caller
  62  * except container_of().
  63  */
  64 #define PCM512x_REGULATOR_EVENT(n) \
  65 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
  66                                       unsigned long event, void *data)    \
  67 { \
  68         struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
  69                                                     supply_nb[n]); \
  70         if (event & REGULATOR_EVENT_DISABLE) { \
  71                 regcache_mark_dirty(pcm512x->regmap);   \
  72                 regcache_cache_only(pcm512x->regmap, true);     \
  73         } \
  74         return 0; \
  75 }
  76
  77 PCM512x_REGULATOR_EVENT(0)
  78 PCM512x_REGULATOR_EVENT(1)
  79 PCM512x_REGULATOR_EVENT(2)
  80
  81 static const struct reg_default pcm512x_reg_defaults[] = {
  82         { PCM512x_RESET,             0x00 },
  83         { PCM512x_POWER,             0x00 },
  84         { PCM512x_MUTE,              0x00 },
  85         { PCM512x_DSP,               0x00 },
  86         { PCM512x_PLL_REF,           0x00 },
  87         { PCM512x_DAC_REF,           0x00 },
  88         { PCM512x_DAC_ROUTING,       0x11 },
  89         { PCM512x_DSP_PROGRAM,       0x01 },
  90         { PCM512x_CLKDET,            0x00 },
  91         { PCM512x_AUTO_MUTE,         0x00 },
  92         { PCM512x_ERROR_DETECT,      0x00 },
  93         { PCM512x_DIGITAL_VOLUME_1,  0x00 },
  94         { PCM512x_DIGITAL_VOLUME_2,  0x30 },
  95         { PCM512x_DIGITAL_VOLUME_3,  0x30 },
  96         { PCM512x_DIGITAL_MUTE_1,    0x22 },
  97         { PCM512x_DIGITAL_MUTE_2,    0x00 },
  98         { PCM512x_DIGITAL_MUTE_3,    0x07 },
  99         { PCM512x_OUTPUT_AMPLITUDE,  0x00 },
 100         { PCM512x_ANALOG_GAIN_CTRL,  0x00 },
 101         { PCM512x_UNDERVOLTAGE_PROT, 0x00 },
 102         { PCM512x_ANALOG_MUTE_CTRL,  0x00 },
 103         { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
 104         { PCM512x_VCOM_CTRL_1,       0x00 },
 105         { PCM512x_VCOM_CTRL_2,       0x01 },
 106         { PCM512x_BCLK_LRCLK_CFG,    0x00 },
 107         { PCM512x_MASTER_MODE,       0x7c },
 108         { PCM512x_GPIO_DACIN,        0x00 },
 109         { PCM512x_GPIO_PLLIN,        0x00 },
 110         { PCM512x_SYNCHRONIZE,       0x10 },
 111         { PCM512x_PLL_COEFF_0,       0x00 },
 112         { PCM512x_PLL_COEFF_1,       0x00 },
 113         { PCM512x_PLL_COEFF_2,       0x00 },
 114         { PCM512x_PLL_COEFF_3,       0x00 },
 115         { PCM512x_PLL_COEFF_4,       0x00 },
 116         { PCM512x_DSP_CLKDIV,        0x00 },
 117         { PCM512x_DAC_CLKDIV,        0x00 },
 118         { PCM512x_NCP_CLKDIV,        0x00 },
 119         { PCM512x_OSR_CLKDIV,        0x00 },
 120         { PCM512x_MASTER_CLKDIV_1,   0x00 },
 121         { PCM512x_MASTER_CLKDIV_2,   0x00 },
 122         { PCM512x_FS_SPEED_MODE,     0x00 },
 123         { PCM512x_IDAC_1,            0x01 },
 124         { PCM512x_IDAC_2,            0x00 },
 125 };
 126
 127 static bool pcm512x_readable(struct device *dev, unsigned int reg)
 128 {
 129         switch (reg) {
 130         case PCM512x_RESET:
 131         case PCM512x_POWER:
 132         case PCM512x_MUTE:
 133         case PCM512x_PLL_EN:
 134         case PCM512x_SPI_MISO_FUNCTION:
 135         case PCM512x_DSP:
 136         case PCM512x_GPIO_EN:
 137         case PCM512x_BCLK_LRCLK_CFG:
 138         case PCM512x_DSP_GPIO_INPUT:
 139         case PCM512x_MASTER_MODE:
 140         case PCM512x_PLL_REF:
 141         case PCM512x_DAC_REF:
 142         case PCM512x_GPIO_DACIN:
 143         case PCM512x_GPIO_PLLIN:
 144         case PCM512x_SYNCHRONIZE:
 145         case PCM512x_PLL_COEFF_0:
 146         case PCM512x_PLL_COEFF_1:
 147         case PCM512x_PLL_COEFF_2:
 148         case PCM512x_PLL_COEFF_3:
 149         case PCM512x_PLL_COEFF_4:
 150         case PCM512x_DSP_CLKDIV:
 151         case PCM512x_DAC_CLKDIV:
 152         case PCM512x_NCP_CLKDIV:
 153         case PCM512x_OSR_CLKDIV:
 154         case PCM512x_MASTER_CLKDIV_1:
 155         case PCM512x_MASTER_CLKDIV_2:
 156         case PCM512x_FS_SPEED_MODE:
 157         case PCM512x_IDAC_1:
 158         case PCM512x_IDAC_2:
 159         case PCM512x_ERROR_DETECT:
 160         case PCM512x_I2S_1:
 161         case PCM512x_I2S_2:
 162         case PCM512x_DAC_ROUTING:
 163         case PCM512x_DSP_PROGRAM:
 164         case PCM512x_CLKDET:
 165         case PCM512x_AUTO_MUTE:
 166         case PCM512x_DIGITAL_VOLUME_1:
 167         case PCM512x_DIGITAL_VOLUME_2:
 168         case PCM512x_DIGITAL_VOLUME_3:
 169         case PCM512x_DIGITAL_MUTE_1:
 170         case PCM512x_DIGITAL_MUTE_2:
 171         case PCM512x_DIGITAL_MUTE_3:
 172         case PCM512x_GPIO_OUTPUT_1:
 173         case PCM512x_GPIO_OUTPUT_2:
 174         case PCM512x_GPIO_OUTPUT_3:
 175         case PCM512x_GPIO_OUTPUT_4:
 176         case PCM512x_GPIO_OUTPUT_5:
 177         case PCM512x_GPIO_OUTPUT_6:
 178         case PCM512x_GPIO_CONTROL_1:
 179         case PCM512x_GPIO_CONTROL_2:
 180         case PCM512x_OVERFLOW:
 181         case PCM512x_RATE_DET_1:
 182         case PCM512x_RATE_DET_2:
 183         case PCM512x_RATE_DET_3:
 184         case PCM512x_RATE_DET_4:
 185         case PCM512x_CLOCK_STATUS:
 186         case PCM512x_ANALOG_MUTE_DET:
 187         case PCM512x_GPIN:
 188         case PCM512x_DIGITAL_MUTE_DET:
 189         case PCM512x_OUTPUT_AMPLITUDE:
 190         case PCM512x_ANALOG_GAIN_CTRL:
 191         case PCM512x_UNDERVOLTAGE_PROT:
 192         case PCM512x_ANALOG_MUTE_CTRL:
 193         case PCM512x_ANALOG_GAIN_BOOST:
 194         case PCM512x_VCOM_CTRL_1:
 195         case PCM512x_VCOM_CTRL_2:
 196         case PCM512x_CRAM_CTRL:
 197         case PCM512x_FLEX_A:
 198         case PCM512x_FLEX_B:
 199                 return true;
 200         default:
 201                 /* There are 256 raw register addresses */
 202                 return reg < 0xff;
 203         }
 204 }
 205
 206 static bool pcm512x_volatile(struct device *dev, unsigned int reg)
 207 {
 208         switch (reg) {
 209         case PCM512x_PLL_EN:
 210         case PCM512x_OVERFLOW:
 211         case PCM512x_RATE_DET_1:
 212         case PCM512x_RATE_DET_2:
 213         case PCM512x_RATE_DET_3:
 214         case PCM512x_RATE_DET_4:
 215         case PCM512x_CLOCK_STATUS:
 216         case PCM512x_ANALOG_MUTE_DET:
 217         case PCM512x_GPIN:
 218         case PCM512x_DIGITAL_MUTE_DET:
 219         case PCM512x_CRAM_CTRL:
 220                 return true;
 221         default:
 222                 /* There are 256 raw register addresses */
 223                 return reg < 0xff;
 224         }
 225 }
 226
 227 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
 228 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
 229 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
 230
 231 static const char * const pcm512x_dsp_program_texts[] = {
 232         "FIR interpolation with de-emphasis",
 233         "Low latency IIR with de-emphasis",
 234         "High attenuation with de-emphasis",
 235         "Fixed process flow",
 236         "Ringing-less low latency FIR",
 237 };
 238
 239 static const unsigned int pcm512x_dsp_program_values[] = {
 240         1,
 241         2,
 242         3,
 243         5,
 244         7,
 245 };
 246
 247 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
 248                                   PCM512x_DSP_PROGRAM, 0, 0x1f,
 249                                   pcm512x_dsp_program_texts,
 250                                   pcm512x_dsp_program_values);
 251
 252 static const char * const pcm512x_clk_missing_text[] = {
 253         "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
 254 };
 255
 256 static const struct soc_enum pcm512x_clk_missing =
 257         SOC_ENUM_SINGLE(PCM512x_CLKDET, 0,  8, pcm512x_clk_missing_text);
 258
 259 static const char * const pcm512x_autom_text[] = {
 260         "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
 261 };
 262
 263 static const struct soc_enum pcm512x_autom_l =
 264         SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
 265                         pcm512x_autom_text);
 266
 267 static const struct soc_enum pcm512x_autom_r =
 268         SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
 269                         pcm512x_autom_text);
 270
 271 static const char * const pcm512x_ramp_rate_text[] = {
 272         "1 sample/update", "2 samples/update", "4 samples/update",
 273         "Immediate"
 274 };
 275
 276 static const struct soc_enum pcm512x_vndf =
 277         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
 278                         pcm512x_ramp_rate_text);
 279
 280 static const struct soc_enum pcm512x_vnuf =
 281         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
 282                         pcm512x_ramp_rate_text);
 283
 284 static const struct soc_enum pcm512x_vedf =
 285         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
 286                         pcm512x_ramp_rate_text);
 287
 288 static const char * const pcm512x_ramp_step_text[] = {
 289         "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
 290 };
 291
 292 static const struct soc_enum pcm512x_vnds =
 293         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
 294                         pcm512x_ramp_step_text);
 295
 296 static const struct soc_enum pcm512x_vnus =
 297         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
 298                         pcm512x_ramp_step_text);
 299
 300 static const struct soc_enum pcm512x_veds =
 301         SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
 302                         pcm512x_ramp_step_text);
 303
 304 static const struct snd_kcontrol_new pcm512x_controls[] = {
 305 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
 306                  PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
 307 SOC_DOUBLE_TLV("Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
 308                PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
 309 SOC_DOUBLE_TLV("Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
 310                PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
 311 SOC_DOUBLE("Digital Playback Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT,
 312            PCM512x_RQMR_SHIFT, 1, 1),
 313
 314 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
 315 SOC_ENUM("DSP Program", pcm512x_dsp_program),
 316
 317 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
 318 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
 319 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
 320 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
 321            PCM512x_ACTL_SHIFT, 1, 0),
 322 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
 323            PCM512x_AMRE_SHIFT, 1, 0),
 324
 325 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
 326 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
 327 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
 328 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
 329 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
 330 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
 331 };
 332
 333 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
 334 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
 335 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
 336
 337 SND_SOC_DAPM_OUTPUT("OUTL"),
 338 SND_SOC_DAPM_OUTPUT("OUTR"),
 339 };
 340
 341 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
 342         { "DACL", NULL, "Playback" },
 343         { "DACR", NULL, "Playback" },
 344
 345         { "OUTL", NULL, "DACL" },
 346         { "OUTR", NULL, "DACR" },
 347 };
 348
 349 static const u32 pcm512x_dai_rates[] = {
 350         8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
 351         88200, 96000, 176400, 192000, 384000,
 352 };
 353
 354 static const struct snd_pcm_hw_constraint_list constraints_slave = {
 355         .count = ARRAY_SIZE(pcm512x_dai_rates),
 356         .list  = pcm512x_dai_rates,
 357 };
 358
 359 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
 360                                 struct snd_pcm_hw_rule *rule)
 361 {
 362         struct snd_interval ranges[2];
 363         int frame_size;
 364
 365         frame_size = snd_soc_params_to_frame_size(params);
 366         if (frame_size < 0)
 367                 return frame_size;
 368
 369         switch (frame_size) {
 370         case 32:
 371                 /* No hole when the frame size is 32. */
 372                 return 0;
 373         case 48:
 374         case 64:
 375                 /* There is only one hole in the range of supported
 376                  * rates, but it moves with the frame size.
 377                  */
 378                 memset(ranges, 0, sizeof(ranges));
 379                 ranges[0].min = 8000;
 380                 ranges[0].max = 25000000 / frame_size / 2;
 381                 ranges[1].min = DIV_ROUND_UP(16000000, frame_size);
 382                 ranges[1].max = 384000;
 383                 break;
 384         default:
 385                 return -EINVAL;
 386         }
 387
 388         return snd_interval_ranges(hw_param_interval(params, rule->var),
 389                                    ARRAY_SIZE(ranges), ranges, 0);
 390 }
 391
 392 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
 393                                       struct snd_soc_dai *dai)
 394 {
 395         struct snd_soc_codec *codec = dai->codec;
 396         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 397         struct device *dev = dai->dev;
 398         struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
 399         struct snd_ratnum *rats_no_pll;
 400
 401         if (IS_ERR(pcm512x->sclk)) {
 402                 dev_err(dev, "Need SCLK for master mode: %ld\n",
 403                         PTR_ERR(pcm512x->sclk));
 404                 return PTR_ERR(pcm512x->sclk);
 405         }
 406
 407         if (pcm512x->pll_out)
 408                 return snd_pcm_hw_rule_add(substream->runtime, 0,
 409                                            SNDRV_PCM_HW_PARAM_RATE,
 410                                            pcm512x_hw_rule_rate,
 411                                            NULL,
 412                                            SNDRV_PCM_HW_PARAM_FRAME_BITS,
 413                                            SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 414
 415         constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
 416                                           GFP_KERNEL);
 417         if (!constraints_no_pll)
 418                 return -ENOMEM;
 419         constraints_no_pll->nrats = 1;
 420         rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
 421         if (!rats_no_pll)
 422                 return -ENOMEM;
 423         constraints_no_pll->rats = rats_no_pll;
 424         rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
 425         rats_no_pll->den_min = 1;
 426         rats_no_pll->den_max = 128;
 427         rats_no_pll->den_step = 1;
 428
 429         return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
 430                                              SNDRV_PCM_HW_PARAM_RATE,
 431                                              constraints_no_pll);
 432 }
 433
 434 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
 435                                      struct snd_soc_dai *dai)
 436 {
 437         struct snd_soc_codec *codec = dai->codec;
 438         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 439         struct device *dev = dai->dev;
 440         struct regmap *regmap = pcm512x->regmap;
 441
 442         if (IS_ERR(pcm512x->sclk)) {
 443                 dev_info(dev, "No SCLK, using BCLK: %ld\n",
 444                          PTR_ERR(pcm512x->sclk));
 445
 446                 /* Disable reporting of missing SCLK as an error */
 447                 regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
 448                                    PCM512x_IDCH, PCM512x_IDCH);
 449
 450                 /* Switch PLL input to BCLK */
 451                 regmap_update_bits(regmap, PCM512x_PLL_REF,
 452                                    PCM512x_SREF, PCM512x_SREF_BCK);
 453         }
 454
 455         return snd_pcm_hw_constraint_list(substream->runtime, 0,
 456                                           SNDRV_PCM_HW_PARAM_RATE,
 457                                           &constraints_slave);
 458 }
 459
 460 static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
 461                                struct snd_soc_dai *dai)
 462 {
 463         struct snd_soc_codec *codec = dai->codec;
 464         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 465
 466         switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 467         case SND_SOC_DAIFMT_CBM_CFM:
 468         case SND_SOC_DAIFMT_CBM_CFS:
 469                 return pcm512x_dai_startup_master(substream, dai);
 470
 471         case SND_SOC_DAIFMT_CBS_CFS:
 472                 return pcm512x_dai_startup_slave(substream, dai);
 473
 474         default:
 475                 return -EINVAL;
 476         }
 477 }
 478
 479 static int pcm512x_set_bias_level(struct snd_soc_codec *codec,
 480                                   enum snd_soc_bias_level level)
 481 {
 482         struct pcm512x_priv *pcm512x = dev_get_drvdata(codec->dev);
 483         int ret;
 484
 485         switch (level) {
 486         case SND_SOC_BIAS_ON:
 487         case SND_SOC_BIAS_PREPARE:
 488                 break;
 489
 490         case SND_SOC_BIAS_STANDBY:
 491                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
 492                                          PCM512x_RQST, 0);
 493                 if (ret != 0) {
 494                         dev_err(codec->dev, "Failed to remove standby: %d\n",
 495                                 ret);
 496                         return ret;
 497                 }
 498                 break;
 499
 500         case SND_SOC_BIAS_OFF:
 501                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
 502                                          PCM512x_RQST, PCM512x_RQST);
 503                 if (ret != 0) {
 504                         dev_err(codec->dev, "Failed to request standby: %d\n",
 505                                 ret);
 506                         return ret;
 507                 }
 508                 break;
 509         }
 510
 511         codec->dapm.bias_level = level;
 512
 513         return 0;
 514 }
 515
 516 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
 517                                       unsigned long bclk_rate)
 518 {
 519         struct device *dev = dai->dev;
 520         unsigned long sck_rate;
 521         int pow2;
 522
 523         /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
 524         /* 16 MHz <= sck_rate <=  25 MHz, VREF mode */
 525
 526         /* select sck_rate as a multiple of bclk_rate but still with
 527          * as many factors of 2 as possible, as that makes it easier
 528          * to find a fast DAC rate
 529          */
 530         pow2 = 1 << fls((25000000 - 16000000) / bclk_rate);
 531         for (; pow2; pow2 >>= 1) {
 532                 sck_rate = rounddown(25000000, bclk_rate * pow2);
 533                 if (sck_rate >= 16000000)
 534                         break;
 535         }
 536         if (!pow2) {
 537                 dev_err(dev, "Impossible to generate a suitable SCK\n");
 538                 return 0;
 539         }
 540
 541         dev_dbg(dev, "sck_rate %lu\n", sck_rate);
 542         return sck_rate;
 543 }
 544
 545 /* pll_rate = pllin_rate * R * J.D / P
 546  * 1 <= R <= 16
 547  * 1 <= J <= 63
 548  * 0 <= D <= 9999
 549  * 1 <= P <= 15
 550  * 64 MHz <= pll_rate <= 100 MHz
 551  * if D == 0
 552  *     1 MHz <= pllin_rate / P <= 20 MHz
 553  * else if D > 0
 554  *     6.667 MHz <= pllin_rate / P <= 20 MHz
 555  *     4 <= J <= 11
 556  *     R = 1
 557  */
 558 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
 559                                   unsigned long pllin_rate,
 560                                   unsigned long pll_rate)
 561 {
 562         struct device *dev = dai->dev;
 563         struct snd_soc_codec *codec = dai->codec;
 564         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 565         unsigned long common;
 566         int R, J, D, P;
 567         unsigned long K; /* 10000 * J.D */
 568         unsigned long num;
 569         unsigned long den;
 570
 571         common = gcd(pll_rate, pllin_rate);
 572         dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
 573                 pll_rate, pllin_rate, common);
 574         num = pll_rate / common;
 575         den = pllin_rate / common;
 576
 577         /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
 578         if (pllin_rate / den > 20000000 && num < 8) {
 579                 num *= 20000000 / (pllin_rate / den);
 580                 den *= 20000000 / (pllin_rate / den);
 581         }
 582         dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
 583
 584         P = den;
 585         if (den <= 15 && num <= 16 * 63
 586             && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
 587                 /* Try the case with D = 0 */
 588                 D = 0;
 589                 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */
 590                 for (R = 16; R; R--) {
 591                         if (num % R)
 592                                 continue;
 593                         J = num / R;
 594                         if (J == 0 || J > 63)
 595                                 continue;
 596
 597                         dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
 598                         pcm512x->real_pll = pll_rate;
 599                         goto done;
 600                 }
 601                 /* no luck */
 602         }
 603
 604         R = 1;
 605
 606         if (num > 0xffffffffUL / 10000)
 607                 goto fallback;
 608
 609         /* Try to find an exact pll_rate using the D > 0 case */
 610         common = gcd(10000 * num, den);
 611         num = 10000 * num / common;
 612         den /= common;
 613         dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
 614
 615         for (P = den; P <= 15; P++) {
 616                 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
 617                         continue;
 618                 if (num * P % den)
 619                         continue;
 620                 K = num * P / den;
 621                 /* J == 12 is ok if D == 0 */
 622                 if (K < 40000 || K > 120000)
 623                         continue;
 624
 625                 J = K / 10000;
 626                 D = K % 10000;
 627                 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
 628                 pcm512x->real_pll = pll_rate;
 629                 goto done;
 630         }
 631
 632         /* Fall back to an approximate pll_rate */
 633
 634 fallback:
 635         /* find smallest possible P */
 636         P = DIV_ROUND_UP(pllin_rate, 20000000);
 637         if (!P)
 638                 P = 1;
 639         else if (P > 15) {
 640                 dev_err(dev, "Need a slower clock as pll-input\n");
 641                 return -EINVAL;
 642         }
 643         if (pllin_rate / P < 6667000) {
 644                 dev_err(dev, "Need a faster clock as pll-input\n");
 645                 return -EINVAL;
 646         }
 647         K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
 648         if (K < 40000)
 649                 K = 40000;
 650         /* J == 12 is ok if D == 0 */
 651         if (K > 120000)
 652                 K = 120000;
 653         J = K / 10000;
 654         D = K % 10000;
 655         dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
 656         pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
 657
 658 done:
 659         pcm512x->pll_r = R;
 660         pcm512x->pll_j = J;
 661         pcm512x->pll_d = D;
 662         pcm512x->pll_p = P;
 663         return 0;
 664 }
 665
 666 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
 667                                             unsigned long osr_rate,
 668                                             unsigned long pllin_rate)
 669 {
 670         struct snd_soc_codec *codec = dai->codec;
 671         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 672         unsigned long dac_rate;
 673
 674         if (!pcm512x->pll_out)
 675                 return 0; /* no PLL to bypass, force SCK as DAC input */
 676
 677         if (pllin_rate % osr_rate)
 678                 return 0; /* futile, quit early */
 679
 680         /* run DAC no faster than 6144000 Hz */
 681         for (dac_rate = rounddown(6144000, osr_rate);
 682              dac_rate;
 683              dac_rate -= osr_rate) {
 684
 685                 if (pllin_rate / dac_rate > 128)
 686                         return 0; /* DAC divider would be too big */
 687
 688                 if (!(pllin_rate % dac_rate))
 689                         return dac_rate;
 690
 691                 dac_rate -= osr_rate;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int pcm512x_set_dividers(struct snd_soc_dai *dai,
 698                                 struct snd_pcm_hw_params *params)
 699 {
 700         struct device *dev = dai->dev;
 701         struct snd_soc_codec *codec = dai->codec;
 702         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 703         unsigned long pllin_rate = 0;
 704         unsigned long pll_rate;
 705         unsigned long sck_rate;
 706         unsigned long mck_rate;
 707         unsigned long bclk_rate;
 708         unsigned long sample_rate;
 709         unsigned long osr_rate;
 710         unsigned long dacsrc_rate;
 711         int bclk_div;
 712         int lrclk_div;
 713         int dsp_div;
 714         int dac_div;
 715         unsigned long dac_rate;
 716         int ncp_div;
 717         int osr_div;
 718         int ret;
 719         int idac;
 720         int fssp;
 721         int gpio;
 722
 723         lrclk_div = snd_soc_params_to_frame_size(params);
 724         if (lrclk_div == 0) {
 725                 dev_err(dev, "No LRCLK?\n");
 726                 return -EINVAL;
 727         }
 728
 729         if (!pcm512x->pll_out) {
 730                 sck_rate = clk_get_rate(pcm512x->sclk);
 731                 bclk_div = params->rate_den * 64 / lrclk_div;
 732                 bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div);
 733
 734                 mck_rate = sck_rate;
 735         } else {
 736                 ret = snd_soc_params_to_bclk(params);
 737                 if (ret < 0) {
 738                         dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
 739                         return ret;
 740                 }
 741                 if (ret == 0) {
 742                         dev_err(dev, "No BCLK?\n");
 743                         return -EINVAL;
 744                 }
 745                 bclk_rate = ret;
 746
 747                 pllin_rate = clk_get_rate(pcm512x->sclk);
 748
 749                 sck_rate = pcm512x_find_sck(dai, bclk_rate);
 750                 if (!sck_rate)
 751                         return -EINVAL;
 752                 pll_rate = 4 * sck_rate;
 753
 754                 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
 755                 if (ret != 0)
 756                         return ret;
 757
 758                 ret = regmap_write(pcm512x->regmap,
 759                                    PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
 760                 if (ret != 0) {
 761                         dev_err(dev, "Failed to write PLL P: %d\n", ret);
 762                         return ret;
 763                 }
 764
 765                 ret = regmap_write(pcm512x->regmap,
 766                                    PCM512x_PLL_COEFF_1, pcm512x->pll_j);
 767                 if (ret != 0) {
 768                         dev_err(dev, "Failed to write PLL J: %d\n", ret);
 769                         return ret;
 770                 }
 771
 772                 ret = regmap_write(pcm512x->regmap,
 773                                    PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
 774                 if (ret != 0) {
 775                         dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
 776                         return ret;
 777                 }
 778
 779                 ret = regmap_write(pcm512x->regmap,
 780                                    PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
 781                 if (ret != 0) {
 782                         dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
 783                         return ret;
 784                 }
 785
 786                 ret = regmap_write(pcm512x->regmap,
 787                                    PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
 788                 if (ret != 0) {
 789                         dev_err(dev, "Failed to write PLL R: %d\n", ret);
 790                         return ret;
 791                 }
 792
 793                 mck_rate = pcm512x->real_pll;
 794
 795                 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
 796         }
 797
 798         if (bclk_div > 128) {
 799                 dev_err(dev, "Failed to find BCLK divider\n");
 800                 return -EINVAL;
 801         }
 802
 803         /* the actual rate */
 804         sample_rate = sck_rate / bclk_div / lrclk_div;
 805         osr_rate = 16 * sample_rate;
 806
 807         /* run DSP no faster than 50 MHz */
 808         dsp_div = mck_rate > 50000000 ? 2 : 1;
 809
 810         dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
 811         if (dac_rate) {
 812                 /* the desired clock rate is "compatible" with the pll input
 813                  * clock, so use that clock as dac input instead of the pll
 814                  * output clock since the pll will introduce jitter and thus
 815                  * noise.
 816                  */
 817                 dev_dbg(dev, "using pll input as dac input\n");
 818                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
 819                                          PCM512x_SDAC, PCM512x_SDAC_GPIO);
 820                 if (ret != 0) {
 821                         dev_err(codec->dev,
 822                                 "Failed to set gpio as dacref: %d\n", ret);
 823                         return ret;
 824                 }
 825
 826                 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
 827                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
 828                                          PCM512x_GREF, gpio);
 829                 if (ret != 0) {
 830                         dev_err(codec->dev,
 831                                 "Failed to set gpio %d as dacin: %d\n",
 832                                 pcm512x->pll_in, ret);
 833                         return ret;
 834                 }
 835
 836                 dacsrc_rate = pllin_rate;
 837         } else {
 838                 /* run DAC no faster than 6144000 Hz */
 839                 unsigned long dac_mul = 6144000 / osr_rate;
 840                 unsigned long sck_mul = sck_rate / osr_rate;
 841
 842                 for (; dac_mul; dac_mul--) {
 843                         if (!(sck_mul % dac_mul))
 844                                 break;
 845                 }
 846                 if (!dac_mul) {
 847                         dev_err(dev, "Failed to find DAC rate\n");
 848                         return -EINVAL;
 849                 }
 850
 851                 dac_rate = dac_mul * osr_rate;
 852                 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
 853                         dac_rate, sample_rate);
 854
 855                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
 856                                          PCM512x_SDAC, PCM512x_SDAC_SCK);
 857                 if (ret != 0) {
 858                         dev_err(codec->dev,
 859                                 "Failed to set sck as dacref: %d\n", ret);
 860                         return ret;
 861                 }
 862
 863                 dacsrc_rate = sck_rate;
 864         }
 865
 866         dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
 867         if (dac_div > 128) {
 868                 dev_err(dev, "Failed to find DAC divider\n");
 869                 return -EINVAL;
 870         }
 871
 872         ncp_div = DIV_ROUND_CLOSEST(dacsrc_rate / dac_div, 1536000);
 873         if (ncp_div > 128 || dacsrc_rate / dac_div / ncp_div > 2048000) {
 874                 /* run NCP no faster than 2048000 Hz, but why? */
 875                 ncp_div = DIV_ROUND_UP(dacsrc_rate / dac_div, 2048000);
 876                 if (ncp_div > 128) {
 877                         dev_err(dev, "Failed to find NCP divider\n");
 878                         return -EINVAL;
 879                 }
 880         }
 881
 882         osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
 883         if (osr_div > 128) {
 884                 dev_err(dev, "Failed to find OSR divider\n");
 885                 return -EINVAL;
 886         }
 887
 888         idac = mck_rate / (dsp_div * sample_rate);
 889
 890         ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
 891         if (ret != 0) {
 892                 dev_err(dev, "Failed to write DSP divider: %d\n", ret);
 893                 return ret;
 894         }
 895
 896         ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
 897         if (ret != 0) {
 898                 dev_err(dev, "Failed to write DAC divider: %d\n", ret);
 899                 return ret;
 900         }
 901
 902         ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
 903         if (ret != 0) {
 904                 dev_err(dev, "Failed to write NCP divider: %d\n", ret);
 905                 return ret;
 906         }
 907
 908         ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
 909         if (ret != 0) {
 910                 dev_err(dev, "Failed to write OSR divider: %d\n", ret);
 911                 return ret;
 912         }
 913
 914         ret = regmap_write(pcm512x->regmap,
 915                            PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
 916         if (ret != 0) {
 917                 dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
 918                 return ret;
 919         }
 920
 921         ret = regmap_write(pcm512x->regmap,
 922                            PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
 923         if (ret != 0) {
 924                 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
 925                 return ret;
 926         }
 927
 928         ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
 929         if (ret != 0) {
 930                 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
 931                 return ret;
 932         }
 933
 934         ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
 935         if (ret != 0) {
 936                 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
 937                 return ret;
 938         }
 939
 940         if (sample_rate <= 48000)
 941                 fssp = PCM512x_FSSP_48KHZ;
 942         else if (sample_rate <= 96000)
 943                 fssp = PCM512x_FSSP_96KHZ;
 944         else if (sample_rate <= 192000)
 945                 fssp = PCM512x_FSSP_192KHZ;
 946         else
 947                 fssp = PCM512x_FSSP_384KHZ;
 948         ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
 949                                  PCM512x_FSSP, fssp);
 950         if (ret != 0) {
 951                 dev_err(codec->dev, "Failed to set fs speed: %d\n", ret);
 952                 return ret;
 953         }
 954
 955         dev_dbg(codec->dev, "DSP divider %d\n", dsp_div);
 956         dev_dbg(codec->dev, "DAC divider %d\n", dac_div);
 957         dev_dbg(codec->dev, "NCP divider %d\n", ncp_div);
 958         dev_dbg(codec->dev, "OSR divider %d\n", osr_div);
 959         dev_dbg(codec->dev, "BCK divider %d\n", bclk_div);
 960         dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div);
 961         dev_dbg(codec->dev, "IDAC %d\n", idac);
 962         dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp);
 963
 964         return 0;
 965 }
 966
 967 static int pcm512x_hw_params(struct snd_pcm_substream *substream,
 968                              struct snd_pcm_hw_params *params,
 969                              struct snd_soc_dai *dai)
 970 {
 971         struct snd_soc_codec *codec = dai->codec;
 972         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
 973         int alen;
 974         int gpio;
 975         int clock_output;
 976         int master_mode;
 977         int ret;
 978
 979         dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
 980                 params_rate(params),
 981                 params_channels(params));
 982
 983         switch (snd_pcm_format_width(params_format(params))) {
 984         case 16:
 985                 alen = PCM512x_ALEN_16;
 986                 break;
 987         case 20:
 988                 alen = PCM512x_ALEN_20;
 989                 break;
 990         case 24:
 991                 alen = PCM512x_ALEN_24;
 992                 break;
 993         case 32:
 994                 alen = PCM512x_ALEN_32;
 995                 break;
 996         default:
 997                 dev_err(codec->dev, "Bad frame size: %d\n",
 998                         snd_pcm_format_width(params_format(params)));
 999                 return -EINVAL;
1000         }
1001
1002         switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1003         case SND_SOC_DAIFMT_CBS_CFS:
1004                 ret = regmap_update_bits(pcm512x->regmap,
1005                                          PCM512x_BCLK_LRCLK_CFG,
1006                                          PCM512x_BCKP
1007                                          | PCM512x_BCKO | PCM512x_LRKO,
1008                                          0);
1009                 if (ret != 0) {
1010                         dev_err(codec->dev,
1011                                 "Failed to enable slave mode: %d\n", ret);
1012                         return ret;
1013                 }
1014
1015                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1016                                          PCM512x_DCAS, 0);
1017                 if (ret != 0) {
1018                         dev_err(codec->dev,
1019                                 "Failed to enable clock divider autoset: %d\n",
1020                                 ret);
1021                         return ret;
1022                 }
1023                 return 0;
1024         case SND_SOC_DAIFMT_CBM_CFM:
1025                 clock_output = PCM512x_BCKO | PCM512x_LRKO;
1026                 master_mode = PCM512x_RLRK | PCM512x_RBCK;
1027                 break;
1028         case SND_SOC_DAIFMT_CBM_CFS:
1029                 clock_output = PCM512x_BCKO;
1030                 master_mode = PCM512x_RBCK;
1031                 break;
1032         default:
1033                 return -EINVAL;
1034         }
1035
1036         ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1037                                  PCM512x_ALEN, alen);
1038         if (ret != 0) {
1039                 dev_err(codec->dev, "Failed to set frame size: %d\n", ret);
1040                 return ret;
1041         }
1042
1043         if (pcm512x->pll_out) {
1044                 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
1045                 if (ret != 0) {
1046                         dev_err(codec->dev, "Failed to set FLEX_A: %d\n", ret);
1047                         return ret;
1048                 }
1049
1050                 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
1051                 if (ret != 0) {
1052                         dev_err(codec->dev, "Failed to set FLEX_B: %d\n", ret);
1053                         return ret;
1054                 }
1055
1056                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1057                                          PCM512x_IDFS | PCM512x_IDBK
1058                                          | PCM512x_IDSK | PCM512x_IDCH
1059                                          | PCM512x_IDCM | PCM512x_DCAS
1060                                          | PCM512x_IPLK,
1061                                          PCM512x_IDFS | PCM512x_IDBK
1062                                          | PCM512x_IDSK | PCM512x_IDCH
1063                                          | PCM512x_DCAS);
1064                 if (ret != 0) {
1065                         dev_err(codec->dev,
1066                                 "Failed to ignore auto-clock failures: %d\n",
1067                                 ret);
1068                         return ret;
1069                 }
1070         } else {
1071                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1072                                          PCM512x_IDFS | PCM512x_IDBK
1073                                          | PCM512x_IDSK | PCM512x_IDCH
1074                                          | PCM512x_IDCM | PCM512x_DCAS
1075                                          | PCM512x_IPLK,
1076                                          PCM512x_IDFS | PCM512x_IDBK
1077                                          | PCM512x_IDSK | PCM512x_IDCH
1078                                          | PCM512x_DCAS | PCM512x_IPLK);
1079                 if (ret != 0) {
1080                         dev_err(codec->dev,
1081                                 "Failed to ignore auto-clock failures: %d\n",
1082                                 ret);
1083                         return ret;
1084                 }
1085
1086                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1087                                          PCM512x_PLLE, 0);
1088                 if (ret != 0) {
1089                         dev_err(codec->dev, "Failed to disable pll: %d\n", ret);
1090                         return ret;
1091                 }
1092         }
1093
1094         ret = pcm512x_set_dividers(dai, params);
1095         if (ret != 0)
1096                 return ret;
1097
1098         if (pcm512x->pll_out) {
1099                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
1100                                          PCM512x_SREF, PCM512x_SREF_GPIO);
1101                 if (ret != 0) {
1102                         dev_err(codec->dev,
1103                                 "Failed to set gpio as pllref: %d\n", ret);
1104                         return ret;
1105                 }
1106
1107                 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1108                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
1109                                          PCM512x_GREF, gpio);
1110                 if (ret != 0) {
1111                         dev_err(codec->dev,
1112                                 "Failed to set gpio %d as pllin: %d\n",
1113                                 pcm512x->pll_in, ret);
1114                         return ret;
1115                 }
1116
1117                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1118                                          PCM512x_PLLE, PCM512x_PLLE);
1119                 if (ret != 0) {
1120                         dev_err(codec->dev, "Failed to enable pll: %d\n", ret);
1121                         return ret;
1122                 }
1123         }
1124
1125         ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
1126                                  PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
1127                                  clock_output);
1128         if (ret != 0) {
1129                 dev_err(codec->dev, "Failed to enable clock output: %d\n", ret);
1130                 return ret;
1131         }
1132
1133         ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
1134                                  PCM512x_RLRK | PCM512x_RBCK,
1135                                  master_mode);
1136         if (ret != 0) {
1137                 dev_err(codec->dev, "Failed to enable master mode: %d\n", ret);
1138                 return ret;
1139         }
1140
1141         if (pcm512x->pll_out) {
1142                 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
1143                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1144                                          gpio, gpio);
1145                 if (ret != 0) {
1146                         dev_err(codec->dev, "Failed to enable gpio %d: %d\n",
1147                                 pcm512x->pll_out, ret);
1148                         return ret;
1149                 }
1150
1151                 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
1152                 ret = regmap_update_bits(pcm512x->regmap, gpio,
1153                                          PCM512x_GxSL, PCM512x_GxSL_PLLCK);
1154                 if (ret != 0) {
1155                         dev_err(codec->dev, "Failed to output pll on %d: %d\n",
1156                                 ret, pcm512x->pll_out);
1157                         return ret;
1158                 }
1159
1160                 gpio = PCM512x_G1OE << (4 - 1);
1161                 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1162                                          gpio, gpio);
1163                 if (ret != 0) {
1164                         dev_err(codec->dev, "Failed to enable gpio %d: %d\n",
1165                                 4, ret);
1166                         return ret;
1167                 }
1168
1169                 gpio = PCM512x_GPIO_OUTPUT_1 + 4 - 1;
1170                 ret = regmap_update_bits(pcm512x->regmap, gpio,
1171                                          PCM512x_GxSL, PCM512x_GxSL_PLLLK);
1172                 if (ret != 0) {
1173                         dev_err(codec->dev,
1174                                 "Failed to output pll lock on %d: %d\n",
1175                                 ret, 4);
1176                         return ret;
1177                 }
1178         }
1179
1180         ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1181                                  PCM512x_RQSY, PCM512x_RQSY_HALT);
1182         if (ret != 0) {
1183                 dev_err(codec->dev, "Failed to halt clocks: %d\n", ret);
1184                 return ret;
1185         }
1186
1187         ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1188                                  PCM512x_RQSY, PCM512x_RQSY_RESUME);
1189         if (ret != 0) {
1190                 dev_err(codec->dev, "Failed to resume clocks: %d\n", ret);
1191                 return ret;
1192         }
1193
1194         return 0;
1195 }
1196
1197 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1198 {
1199         struct snd_soc_codec *codec = dai->codec;
1200         struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
1201
1202         pcm512x->fmt = fmt;
1203
1204         return 0;
1205 }
1206
1207 static const struct snd_soc_dai_ops pcm512x_dai_ops = {
1208         .startup = pcm512x_dai_startup,
1209         .hw_params = pcm512x_hw_params,
1210         .set_fmt = pcm512x_set_fmt,
1211 };
1212
1213 static struct snd_soc_dai_driver pcm512x_dai = {
1214         .name = "pcm512x-hifi",
1215         .playback = {
1216                 .stream_name = "Playback",
1217                 .channels_min = 2,
1218                 .channels_max = 2,
1219                 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1220                 .rate_min = 8000,
1221                 .rate_max = 384000,
1222                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1223                            SNDRV_PCM_FMTBIT_S24_LE |
1224                            SNDRV_PCM_FMTBIT_S32_LE
1225         },
1226         .ops = &pcm512x_dai_ops,
1227 };
1228
1229 static struct snd_soc_codec_driver pcm512x_codec_driver = {
1230         .set_bias_level = pcm512x_set_bias_level,
1231         .idle_bias_off = true,
1232
1233         .controls = pcm512x_controls,
1234         .num_controls = ARRAY_SIZE(pcm512x_controls),
1235         .dapm_widgets = pcm512x_dapm_widgets,
1236         .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
1237         .dapm_routes = pcm512x_dapm_routes,
1238         .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
1239 };
1240
1241 static const struct regmap_range_cfg pcm512x_range = {
1242         .name = "Pages", .range_min = PCM512x_VIRT_BASE,
1243         .range_max = PCM512x_MAX_REGISTER,
1244         .selector_reg = PCM512x_PAGE,
1245         .selector_mask = 0xff,
1246         .window_start = 0, .window_len = 0x100,
1247 };
1248
1249 const struct regmap_config pcm512x_regmap = {
1250         .reg_bits = 8,
1251         .val_bits = 8,
1252
1253         .readable_reg = pcm512x_readable,
1254         .volatile_reg = pcm512x_volatile,
1255
1256         .ranges = &pcm512x_range,
1257         .num_ranges = 1,
1258
1259         .max_register = PCM512x_MAX_REGISTER,
1260         .reg_defaults = pcm512x_reg_defaults,
1261         .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
1262         .cache_type = REGCACHE_RBTREE,
1263 };
1264 EXPORT_SYMBOL_GPL(pcm512x_regmap);
1265
1266 int pcm512x_probe(struct device *dev, struct regmap *regmap)
1267 {
1268         struct pcm512x_priv *pcm512x;
1269         int i, ret;
1270
1271         pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
1272         if (!pcm512x)
1273                 return -ENOMEM;
1274
1275         dev_set_drvdata(dev, pcm512x);
1276         pcm512x->regmap = regmap;
1277
1278         for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
1279                 pcm512x->supplies[i].supply = pcm512x_supply_names[i];
1280
1281         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
1282                                       pcm512x->supplies);
1283         if (ret != 0) {
1284                 dev_err(dev, "Failed to get supplies: %d\n", ret);
1285                 return ret;
1286         }
1287
1288         pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
1289         pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
1290         pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
1291
1292         for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
1293                 ret = regulator_register_notifier(pcm512x->supplies[i].consumer,
1294                                                   &pcm512x->supply_nb[i]);
1295                 if (ret != 0) {
1296                         dev_err(dev,
1297                                 "Failed to register regulator notifier: %d\n",
1298                                 ret);
1299                 }
1300         }
1301
1302         ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1303                                     pcm512x->supplies);
1304         if (ret != 0) {
1305                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1306                 return ret;
1307         }
1308
1309         /* Reset the device, verifying I/O in the process for I2C */
1310         ret = regmap_write(regmap, PCM512x_RESET,
1311                            PCM512x_RSTM | PCM512x_RSTR);
1312         if (ret != 0) {
1313                 dev_err(dev, "Failed to reset device: %d\n", ret);
1314                 goto err;
1315         }
1316
1317         ret = regmap_write(regmap, PCM512x_RESET, 0);
1318         if (ret != 0) {
1319                 dev_err(dev, "Failed to reset device: %d\n", ret);
1320                 goto err;
1321         }
1322
1323         pcm512x->sclk = devm_clk_get(dev, NULL);
1324         if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
1325                 return -EPROBE_DEFER;
1326         if (!IS_ERR(pcm512x->sclk)) {
1327                 ret = clk_prepare_enable(pcm512x->sclk);
1328                 if (ret != 0) {
1329                         dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1330                         return ret;
1331                 }
1332         }
1333
1334         /* Default to standby mode */
1335         ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1336                                  PCM512x_RQST, PCM512x_RQST);
1337         if (ret != 0) {
1338                 dev_err(dev, "Failed to request standby: %d\n",
1339                         ret);
1340                 goto err_clk;
1341         }
1342
1343         pm_runtime_set_active(dev);
1344         pm_runtime_enable(dev);
1345         pm_runtime_idle(dev);
1346
1347 #ifdef CONFIG_OF
1348         if (dev->of_node) {
1349                 const struct device_node *np = dev->of_node;
1350                 u32 val;
1351
1352                 if (of_property_read_u32(np, "pll-in", &val) >= 0) {
1353                         if (val > 6) {
1354                                 dev_err(dev, "Invalid pll-in\n");
1355                                 ret = -EINVAL;
1356                                 goto err_clk;
1357                         }
1358                         pcm512x->pll_in = val;
1359                 }
1360
1361                 if (of_property_read_u32(np, "pll-out", &val) >= 0) {
1362                         if (val > 6) {
1363                                 dev_err(dev, "Invalid pll-out\n");
1364                                 ret = -EINVAL;
1365                                 goto err_clk;
1366                         }
1367                         pcm512x->pll_out = val;
1368                 }
1369
1370                 if (!pcm512x->pll_in != !pcm512x->pll_out) {
1371                         dev_err(dev,
1372                                 "Error: both pll-in and pll-out, or none\n");
1373                         ret = -EINVAL;
1374                         goto err_clk;
1375                 }
1376                 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
1377                         dev_err(dev, "Error: pll-in == pll-out\n");
1378                         ret = -EINVAL;
1379                         goto err_clk;
1380                 }
1381         }
1382 #endif
1383
1384         ret = snd_soc_register_codec(dev, &pcm512x_codec_driver,
1385                                     &pcm512x_dai, 1);
1386         if (ret != 0) {
1387                 dev_err(dev, "Failed to register CODEC: %d\n", ret);
1388                 goto err_pm;
1389         }
1390
1391         return 0;
1392
1393 err_pm:
1394         pm_runtime_disable(dev);
1395 err_clk:
1396         if (!IS_ERR(pcm512x->sclk))
1397                 clk_disable_unprepare(pcm512x->sclk);
1398 err:
1399         regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1400                                      pcm512x->supplies);
1401         return ret;
1402 }
1403 EXPORT_SYMBOL_GPL(pcm512x_probe);
1404
1405 void pcm512x_remove(struct device *dev)
1406 {
1407         struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1408
1409         snd_soc_unregister_codec(dev);
1410         pm_runtime_disable(dev);
1411         if (!IS_ERR(pcm512x->sclk))
1412                 clk_disable_unprepare(pcm512x->sclk);
1413         regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1414                                pcm512x->supplies);
1415 }
1416 EXPORT_SYMBOL_GPL(pcm512x_remove);
1417
1418 #ifdef CONFIG_PM
1419 static int pcm512x_suspend(struct device *dev)
1420 {
1421         struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1422         int ret;
1423
1424         ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1425                                  PCM512x_RQPD, PCM512x_RQPD);
1426         if (ret != 0) {
1427                 dev_err(dev, "Failed to request power down: %d\n", ret);
1428                 return ret;
1429         }
1430
1431         ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1432                                      pcm512x->supplies);
1433         if (ret != 0) {
1434                 dev_err(dev, "Failed to disable supplies: %d\n", ret);
1435                 return ret;
1436         }
1437
1438         if (!IS_ERR(pcm512x->sclk))
1439                 clk_disable_unprepare(pcm512x->sclk);
1440
1441         return 0;
1442 }
1443
1444 static int pcm512x_resume(struct device *dev)
1445 {
1446         struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1447         int ret;
1448
1449         if (!IS_ERR(pcm512x->sclk)) {
1450                 ret = clk_prepare_enable(pcm512x->sclk);
1451                 if (ret != 0) {
1452                         dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1453                         return ret;
1454                 }
1455         }
1456
1457         ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1458                                     pcm512x->supplies);
1459         if (ret != 0) {
1460                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1461                 return ret;
1462         }
1463
1464         regcache_cache_only(pcm512x->regmap, false);
1465         ret = regcache_sync(pcm512x->regmap);
1466         if (ret != 0) {
1467                 dev_err(dev, "Failed to sync cache: %d\n", ret);
1468                 return ret;
1469         }
1470
1471         ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1472                                  PCM512x_RQPD, 0);
1473         if (ret != 0) {
1474                 dev_err(dev, "Failed to remove power down: %d\n", ret);
1475                 return ret;
1476         }
1477
1478         return 0;
1479 }
1480 #endif
1481
1482 const struct dev_pm_ops pcm512x_pm_ops = {
1483         SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
1484 };
1485 EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
1486
1487 MODULE_DESCRIPTION("ASoC PCM512x codec driver");
1488 MODULE_AUTHOR("Mark Brown <broonie@linaro.org>");
1489 MODULE_LICENSE("GPL v2");