2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/of_gpio.h>
19 #include <linux/regmap.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/firmware.h>
24 #include <linux/gpio.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
35 #include "rt5677-spi.h"
37 #define RT5677_DEVICE_ID 0x6327
39 #define RT5677_PR_RANGE_BASE (0xff + 1)
40 #define RT5677_PR_SPACING 0x100
42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
44 static const struct regmap_range_cfg rt5677_ranges[] = {
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
57 static const struct reg_default init_list[] = {
58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
66 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
68 static const struct reg_default rt5677_reg[] = {
69 {RT5677_RESET , 0x0000},
70 {RT5677_LOUT1 , 0xa800},
71 {RT5677_IN1 , 0x0000},
72 {RT5677_MICBIAS , 0x0000},
73 {RT5677_SLIMBUS_PARAM , 0x0000},
74 {RT5677_SLIMBUS_RX , 0x0000},
75 {RT5677_SLIMBUS_CTRL , 0x0000},
76 {RT5677_SIDETONE_CTRL , 0x000b},
77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
79 {RT5677_DAC4_DIG_VOL , 0xafaf},
80 {RT5677_DAC3_DIG_VOL , 0xafaf},
81 {RT5677_DAC1_DIG_VOL , 0xafaf},
82 {RT5677_DAC2_DIG_VOL , 0xafaf},
83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO1_2_ADC_BST , 0x0000},
87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_ADC_BST_CTRL2 , 0x0000},
89 {RT5677_STO3_4_ADC_BST , 0x0000},
90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
92 {RT5677_STO4_ADC_MIXER , 0xd4c0},
93 {RT5677_STO3_ADC_MIXER , 0xd4c0},
94 {RT5677_STO2_ADC_MIXER , 0xd4c0},
95 {RT5677_STO1_ADC_MIXER , 0xd4c0},
96 {RT5677_MONO_ADC_MIXER , 0xd4d1},
97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
98 {RT5677_STO1_DAC_MIXER , 0xaaaa},
99 {RT5677_MONO_DAC_MIXER , 0xaaaa},
100 {RT5677_DD1_MIXER , 0xaaaa},
101 {RT5677_DD2_MIXER , 0xaaaa},
102 {RT5677_IF3_DATA , 0x0000},
103 {RT5677_IF4_DATA , 0x0000},
104 {RT5677_PDM_OUT_CTRL , 0x8888},
105 {RT5677_PDM_DATA_CTRL1 , 0x0000},
106 {RT5677_PDM_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
113 {RT5677_TDM1_CTRL1 , 0x0300},
114 {RT5677_TDM1_CTRL2 , 0x0000},
115 {RT5677_TDM1_CTRL3 , 0x4000},
116 {RT5677_TDM1_CTRL4 , 0x0123},
117 {RT5677_TDM1_CTRL5 , 0x4567},
118 {RT5677_TDM2_CTRL1 , 0x0300},
119 {RT5677_TDM2_CTRL2 , 0x0000},
120 {RT5677_TDM2_CTRL3 , 0x4000},
121 {RT5677_TDM2_CTRL4 , 0x0123},
122 {RT5677_TDM2_CTRL5 , 0x4567},
123 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
124 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
131 {RT5677_DMIC_CTRL1 , 0x1505},
132 {RT5677_DMIC_CTRL2 , 0x0055},
133 {RT5677_HAP_GENE_CTRL1 , 0x0111},
134 {RT5677_HAP_GENE_CTRL2 , 0x0064},
135 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL9 , 0xf000},
142 {RT5677_HAP_GENE_CTRL10 , 0x0000},
143 {RT5677_PWR_DIG1 , 0x0000},
144 {RT5677_PWR_DIG2 , 0x0000},
145 {RT5677_PWR_ANLG1 , 0x0055},
146 {RT5677_PWR_ANLG2 , 0x0000},
147 {RT5677_PWR_DSP1 , 0x0001},
148 {RT5677_PWR_DSP_ST , 0x0000},
149 {RT5677_PWR_DSP2 , 0x0000},
150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
151 {RT5677_PRIV_INDEX , 0x0000},
152 {RT5677_PRIV_DATA , 0x0000},
153 {RT5677_I2S4_SDP , 0x8000},
154 {RT5677_I2S1_SDP , 0x8000},
155 {RT5677_I2S2_SDP , 0x8000},
156 {RT5677_I2S3_SDP , 0x8000},
157 {RT5677_CLK_TREE_CTRL1 , 0x1111},
158 {RT5677_CLK_TREE_CTRL2 , 0x1111},
159 {RT5677_CLK_TREE_CTRL3 , 0x0000},
160 {RT5677_PLL1_CTRL1 , 0x0000},
161 {RT5677_PLL1_CTRL2 , 0x0000},
162 {RT5677_PLL2_CTRL1 , 0x0c60},
163 {RT5677_PLL2_CTRL2 , 0x2000},
164 {RT5677_GLB_CLK1 , 0x0000},
165 {RT5677_GLB_CLK2 , 0x0000},
166 {RT5677_ASRC_1 , 0x0000},
167 {RT5677_ASRC_2 , 0x0000},
168 {RT5677_ASRC_3 , 0x0000},
169 {RT5677_ASRC_4 , 0x0000},
170 {RT5677_ASRC_5 , 0x0000},
171 {RT5677_ASRC_6 , 0x0000},
172 {RT5677_ASRC_7 , 0x0000},
173 {RT5677_ASRC_8 , 0x0000},
174 {RT5677_ASRC_9 , 0x0000},
175 {RT5677_ASRC_10 , 0x0000},
176 {RT5677_ASRC_11 , 0x0000},
177 {RT5677_ASRC_12 , 0x0018},
178 {RT5677_ASRC_13 , 0x0000},
179 {RT5677_ASRC_14 , 0x0000},
180 {RT5677_ASRC_15 , 0x0000},
181 {RT5677_ASRC_16 , 0x0000},
182 {RT5677_ASRC_17 , 0x0000},
183 {RT5677_ASRC_18 , 0x0000},
184 {RT5677_ASRC_19 , 0x0000},
185 {RT5677_ASRC_20 , 0x0000},
186 {RT5677_ASRC_21 , 0x000c},
187 {RT5677_ASRC_22 , 0x0000},
188 {RT5677_ASRC_23 , 0x0000},
189 {RT5677_VAD_CTRL1 , 0x2184},
190 {RT5677_VAD_CTRL2 , 0x010a},
191 {RT5677_VAD_CTRL3 , 0x0aea},
192 {RT5677_VAD_CTRL4 , 0x000c},
193 {RT5677_VAD_CTRL5 , 0x0000},
194 {RT5677_DSP_INB_CTRL1 , 0x0000},
195 {RT5677_DSP_INB_CTRL2 , 0x0000},
196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
201 {RT5677_ADC_EQ_CTRL1 , 0x6000},
202 {RT5677_ADC_EQ_CTRL2 , 0x0000},
203 {RT5677_EQ_CTRL1 , 0xc000},
204 {RT5677_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL3 , 0x0000},
206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
207 {RT5677_JD_CTRL1 , 0x0000},
208 {RT5677_JD_CTRL2 , 0x0000},
209 {RT5677_JD_CTRL3 , 0x0000},
210 {RT5677_IRQ_CTRL1 , 0x0000},
211 {RT5677_IRQ_CTRL2 , 0x0000},
212 {RT5677_GPIO_ST , 0x0000},
213 {RT5677_GPIO_CTRL1 , 0x0000},
214 {RT5677_GPIO_CTRL2 , 0x0000},
215 {RT5677_GPIO_CTRL3 , 0x0000},
216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_MB_DRC_CTRL1 , 0x0f20},
227 {RT5677_DRC1_CTRL1 , 0x001f},
228 {RT5677_DRC1_CTRL2 , 0x020c},
229 {RT5677_DRC1_CTRL3 , 0x1f00},
230 {RT5677_DRC1_CTRL4 , 0x0000},
231 {RT5677_DRC1_CTRL5 , 0x0000},
232 {RT5677_DRC1_CTRL6 , 0x0029},
233 {RT5677_DRC2_CTRL1 , 0x001f},
234 {RT5677_DRC2_CTRL2 , 0x020c},
235 {RT5677_DRC2_CTRL3 , 0x1f00},
236 {RT5677_DRC2_CTRL4 , 0x0000},
237 {RT5677_DRC2_CTRL5 , 0x0000},
238 {RT5677_DRC2_CTRL6 , 0x0029},
239 {RT5677_DRC1_HL_CTRL1 , 0x8000},
240 {RT5677_DRC1_HL_CTRL2 , 0x0200},
241 {RT5677_DRC2_HL_CTRL1 , 0x8000},
242 {RT5677_DRC2_HL_CTRL2 , 0x0200},
243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
266 {RT5677_DIG_MISC , 0x0000},
267 {RT5677_GEN_CTRL1 , 0x0000},
268 {RT5677_GEN_CTRL2 , 0x0000},
269 {RT5677_VENDOR_ID , 0x0000},
270 {RT5677_VENDOR_ID1 , 0x10ec},
271 {RT5677_VENDOR_ID2 , 0x6327},
274 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
279 if (reg >= rt5677_ranges[i].range_min &&
280 reg <= rt5677_ranges[i].range_max) {
287 case RT5677_SLIMBUS_PARAM:
288 case RT5677_PDM_DATA_CTRL1:
289 case RT5677_PDM_DATA_CTRL2:
290 case RT5677_PDM1_DATA_CTRL4:
291 case RT5677_PDM2_DATA_CTRL4:
292 case RT5677_I2C_MASTER_CTRL1:
293 case RT5677_I2C_MASTER_CTRL7:
294 case RT5677_I2C_MASTER_CTRL8:
295 case RT5677_HAP_GENE_CTRL2:
296 case RT5677_PWR_DSP_ST:
297 case RT5677_PRIV_DATA:
298 case RT5677_PLL1_CTRL2:
299 case RT5677_PLL2_CTRL2:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
322 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
545 * @rt5677: Private Data.
546 * @addr: Address index.
547 * @value: Address data.
550 * Returns 0 for success or negative error code.
552 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
553 unsigned int addr, unsigned int value, unsigned int opcode)
555 struct snd_soc_codec *codec = rt5677->codec;
558 mutex_lock(&rt5677->dsp_cmd_lock);
560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
596 mutex_unlock(&rt5677->dsp_cmd_lock);
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
603 * rt5677: Private Data.
604 * @addr: Address index.
605 * @value: Address data.
608 * Returns 0 for success or negative error code.
610 static int rt5677_dsp_mode_i2c_read_addr(
611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
613 struct snd_soc_codec *codec = rt5677->codec;
615 unsigned int msb, lsb;
617 mutex_lock(&rt5677->dsp_cmd_lock);
619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
642 *value = (msb << 16) | lsb;
645 mutex_unlock(&rt5677->dsp_cmd_lock);
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
652 * rt5677: Private Data.
653 * @reg: Register index.
654 * @value: Register data.
657 * Returns 0 for success or negative error code.
659 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
660 unsigned int reg, unsigned int value)
662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
670 * @value: Register data.
673 * Returns 0 for success or negative error code.
675 static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
686 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
699 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
705 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
708 if (on && !activity) {
711 regcache_cache_only(rt5677->regmap, false);
712 regcache_cache_bypass(rt5677->regmap, true);
714 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
715 regmap_update_bits(rt5677->regmap,
716 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
717 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
718 RT5677_LDO1_SEL_MASK, 0x0);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
720 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
721 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
722 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
723 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
724 RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK,
725 RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS);
726 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
727 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
728 rt5677_set_dsp_mode(codec, true);
730 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
733 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
734 release_firmware(rt5677->fw1);
737 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
740 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
741 release_firmware(rt5677->fw2);
744 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
746 regcache_cache_bypass(rt5677->regmap, false);
747 regcache_cache_only(rt5677->regmap, true);
748 } else if (!on && activity) {
751 regcache_cache_only(rt5677->regmap, false);
752 regcache_cache_bypass(rt5677->regmap, true);
754 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
755 rt5677_set_dsp_mode(codec, false);
756 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
758 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
760 regcache_cache_bypass(rt5677->regmap, false);
761 regcache_mark_dirty(rt5677->regmap);
762 regcache_sync(rt5677->regmap);
768 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
769 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
770 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
771 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
772 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
773 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
775 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
776 static unsigned int bst_tlv[] = {
777 TLV_DB_RANGE_HEAD(7),
778 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
779 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
780 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
781 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
782 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
783 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
784 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
787 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
788 struct snd_ctl_elem_value *ucontrol)
790 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
791 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
793 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
798 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
799 struct snd_ctl_elem_value *ucontrol)
801 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
802 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
804 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
806 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
807 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
812 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
814 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
815 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
816 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
817 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
818 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
819 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
821 /* DAC Digital Volume */
822 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
823 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
824 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
825 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
826 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
827 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
828 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
829 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
831 /* IN1/IN2 Control */
832 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
833 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
835 /* ADC Digital Volume Control */
836 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
837 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
838 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
839 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
840 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
841 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
842 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
843 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
844 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
845 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
847 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
848 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
850 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
851 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
853 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
854 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
856 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
857 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
859 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
860 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
863 /* Sidetone Control */
864 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
865 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
867 /* ADC Boost Volume Control */
868 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
869 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
871 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
872 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
874 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
875 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
877 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
878 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
880 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
881 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
884 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
885 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
889 * set_dmic_clk - Set parameter of dmic.
892 * @kcontrol: The kcontrol of this widget.
895 * Choose dmic clock between 1MHz and 3MHz.
896 * It is better for clock to approximate 3MHz.
898 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
899 struct snd_kcontrol *kcontrol, int event)
901 struct snd_soc_codec *codec = w->codec;
902 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
903 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
906 dev_err(codec->dev, "Failed to set DMIC clock\n");
908 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
909 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
913 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
914 struct snd_soc_dapm_widget *sink)
916 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
919 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
920 val &= RT5677_SCLK_SRC_MASK;
921 if (val == RT5677_SCLK_SRC_PLL1)
927 static int is_using_asrc(struct snd_soc_dapm_widget *source,
928 struct snd_soc_dapm_widget *sink)
930 struct snd_soc_codec *codec = source->codec;
931 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
932 unsigned int reg, shift, val;
934 if (source->reg == RT5677_ASRC_1) {
935 switch (source->shift) {
956 switch (source->shift) {
998 regmap_read(rt5677->regmap, reg, &val);
999 val = (val >> shift) & 0xf;
1010 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1011 struct snd_soc_dapm_widget *sink)
1013 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1014 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1016 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1023 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1024 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1025 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1026 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1027 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1030 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1031 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1032 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1033 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1034 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1037 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1038 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1039 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1040 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1041 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1044 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1045 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1046 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1047 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1048 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1051 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1052 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1053 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1054 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1055 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1058 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1059 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1060 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1061 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1062 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1065 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1066 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1067 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1068 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1069 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1072 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1073 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1074 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1075 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1076 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1079 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1080 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1081 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1082 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1083 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1086 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1087 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1088 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1089 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1090 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1093 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1094 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1095 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1096 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1097 RT5677_M_DAC1_L_SFT, 1, 1),
1100 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1101 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1102 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1103 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1104 RT5677_M_DAC1_R_SFT, 1, 1),
1107 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1108 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1109 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1110 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1111 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1112 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1113 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1114 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1115 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1118 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1119 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1120 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1121 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1122 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1123 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1124 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1125 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1126 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1129 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1130 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1131 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1132 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1133 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1134 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1135 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1136 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1137 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1140 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1141 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1142 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1143 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1144 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1145 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1146 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1147 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1148 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1151 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1152 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1153 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1154 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1155 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1156 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1157 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1158 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1159 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1162 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1163 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1164 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1165 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1166 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1167 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1168 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1169 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1170 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1173 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1174 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1175 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1176 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1177 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1178 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1179 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1180 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1181 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1184 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1185 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1186 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1187 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1188 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1189 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1190 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1191 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1192 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1195 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1196 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1197 RT5677_DSP_IB_01_H_SFT, 1, 1),
1198 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1199 RT5677_DSP_IB_23_H_SFT, 1, 1),
1200 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1201 RT5677_DSP_IB_45_H_SFT, 1, 1),
1202 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1203 RT5677_DSP_IB_6_H_SFT, 1, 1),
1204 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1205 RT5677_DSP_IB_7_H_SFT, 1, 1),
1206 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1207 RT5677_DSP_IB_8_H_SFT, 1, 1),
1208 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1209 RT5677_DSP_IB_9_H_SFT, 1, 1),
1212 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1213 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1214 RT5677_DSP_IB_01_L_SFT, 1, 1),
1215 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1216 RT5677_DSP_IB_23_L_SFT, 1, 1),
1217 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1218 RT5677_DSP_IB_45_L_SFT, 1, 1),
1219 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1220 RT5677_DSP_IB_6_L_SFT, 1, 1),
1221 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1222 RT5677_DSP_IB_7_L_SFT, 1, 1),
1223 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1224 RT5677_DSP_IB_8_L_SFT, 1, 1),
1225 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1226 RT5677_DSP_IB_9_L_SFT, 1, 1),
1229 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1230 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1231 RT5677_DSP_IB_01_H_SFT, 1, 1),
1232 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1233 RT5677_DSP_IB_23_H_SFT, 1, 1),
1234 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1235 RT5677_DSP_IB_45_H_SFT, 1, 1),
1236 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1237 RT5677_DSP_IB_6_H_SFT, 1, 1),
1238 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1239 RT5677_DSP_IB_7_H_SFT, 1, 1),
1240 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1241 RT5677_DSP_IB_8_H_SFT, 1, 1),
1242 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1243 RT5677_DSP_IB_9_H_SFT, 1, 1),
1246 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1247 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1248 RT5677_DSP_IB_01_L_SFT, 1, 1),
1249 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1250 RT5677_DSP_IB_23_L_SFT, 1, 1),
1251 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1252 RT5677_DSP_IB_45_L_SFT, 1, 1),
1253 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1254 RT5677_DSP_IB_6_L_SFT, 1, 1),
1255 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1256 RT5677_DSP_IB_7_L_SFT, 1, 1),
1257 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1258 RT5677_DSP_IB_8_L_SFT, 1, 1),
1259 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1260 RT5677_DSP_IB_9_L_SFT, 1, 1),
1263 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1264 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1265 RT5677_DSP_IB_01_H_SFT, 1, 1),
1266 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1267 RT5677_DSP_IB_23_H_SFT, 1, 1),
1268 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1269 RT5677_DSP_IB_45_H_SFT, 1, 1),
1270 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1271 RT5677_DSP_IB_6_H_SFT, 1, 1),
1272 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1273 RT5677_DSP_IB_7_H_SFT, 1, 1),
1274 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1275 RT5677_DSP_IB_8_H_SFT, 1, 1),
1276 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1277 RT5677_DSP_IB_9_H_SFT, 1, 1),
1280 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1281 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1282 RT5677_DSP_IB_01_L_SFT, 1, 1),
1283 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1284 RT5677_DSP_IB_23_L_SFT, 1, 1),
1285 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1286 RT5677_DSP_IB_45_L_SFT, 1, 1),
1287 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1288 RT5677_DSP_IB_6_L_SFT, 1, 1),
1289 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1290 RT5677_DSP_IB_7_L_SFT, 1, 1),
1291 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1292 RT5677_DSP_IB_8_L_SFT, 1, 1),
1293 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1294 RT5677_DSP_IB_9_L_SFT, 1, 1),
1299 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1300 static const char * const rt5677_dac1_src[] = {
1301 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1305 static SOC_ENUM_SINGLE_DECL(
1306 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1307 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1309 static const struct snd_kcontrol_new rt5677_dac1_mux =
1310 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1312 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1313 static const char * const rt5677_adda1_src[] = {
1314 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1317 static SOC_ENUM_SINGLE_DECL(
1318 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1319 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1321 static const struct snd_kcontrol_new rt5677_adda1_mux =
1322 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1325 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1326 static const char * const rt5677_dac2l_src[] = {
1327 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1331 static SOC_ENUM_SINGLE_DECL(
1332 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1333 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1335 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1336 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1338 static const char * const rt5677_dac2r_src[] = {
1339 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1340 "OB 3", "Haptic Generator", "VAD ADC"
1343 static SOC_ENUM_SINGLE_DECL(
1344 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1345 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1347 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1348 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1350 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1351 static const char * const rt5677_dac3l_src[] = {
1352 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1356 static SOC_ENUM_SINGLE_DECL(
1357 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1358 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1360 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1361 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1363 static const char * const rt5677_dac3r_src[] = {
1364 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1368 static SOC_ENUM_SINGLE_DECL(
1369 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1370 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1372 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1373 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1375 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1376 static const char * const rt5677_dac4l_src[] = {
1377 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1381 static SOC_ENUM_SINGLE_DECL(
1382 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1383 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1385 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1386 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1388 static const char * const rt5677_dac4r_src[] = {
1389 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1393 static SOC_ENUM_SINGLE_DECL(
1394 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1395 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1397 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1398 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1400 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1401 static const char * const rt5677_iob_bypass_src[] = {
1402 "Bypass", "Pass SRC"
1405 static SOC_ENUM_SINGLE_DECL(
1406 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1407 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1409 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1410 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1412 static SOC_ENUM_SINGLE_DECL(
1413 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1414 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1416 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1417 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1419 static SOC_ENUM_SINGLE_DECL(
1420 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1421 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1423 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1424 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1426 static SOC_ENUM_SINGLE_DECL(
1427 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1428 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1430 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1431 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1433 static SOC_ENUM_SINGLE_DECL(
1434 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1435 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1437 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1438 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1440 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1441 static const char * const rt5677_stereo_adc2_src[] = {
1442 "DD MIX1", "DMIC", "Stereo DAC MIX"
1445 static SOC_ENUM_SINGLE_DECL(
1446 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1447 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1449 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1450 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1452 static SOC_ENUM_SINGLE_DECL(
1453 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1454 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1456 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1457 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1459 static SOC_ENUM_SINGLE_DECL(
1460 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1461 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1463 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1464 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1466 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1467 static const char * const rt5677_dmic_src[] = {
1468 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1471 static SOC_ENUM_SINGLE_DECL(
1472 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1473 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1475 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1476 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1478 static SOC_ENUM_SINGLE_DECL(
1479 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1480 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1482 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1483 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1485 static SOC_ENUM_SINGLE_DECL(
1486 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1487 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1489 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1490 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1492 static SOC_ENUM_SINGLE_DECL(
1493 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1494 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1496 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1497 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1499 static SOC_ENUM_SINGLE_DECL(
1500 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1501 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1503 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1504 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1506 static SOC_ENUM_SINGLE_DECL(
1507 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1508 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1510 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1511 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1513 /* Stereo2 ADC Source */ /* MX-26 [0] */
1514 static const char * const rt5677_stereo2_adc_lr_src[] = {
1518 static SOC_ENUM_SINGLE_DECL(
1519 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1520 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1522 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1523 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1525 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1526 static const char * const rt5677_stereo_adc1_src[] = {
1527 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1530 static SOC_ENUM_SINGLE_DECL(
1531 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1532 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1534 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1535 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1537 static SOC_ENUM_SINGLE_DECL(
1538 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1539 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1541 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1542 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1544 static SOC_ENUM_SINGLE_DECL(
1545 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1546 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1548 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1549 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1551 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1552 static const char * const rt5677_mono_adc2_l_src[] = {
1553 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1556 static SOC_ENUM_SINGLE_DECL(
1557 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1558 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1560 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1561 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1563 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1564 static const char * const rt5677_mono_adc1_l_src[] = {
1565 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1568 static SOC_ENUM_SINGLE_DECL(
1569 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1570 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1572 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1573 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1575 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1576 static const char * const rt5677_mono_adc2_r_src[] = {
1577 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1580 static SOC_ENUM_SINGLE_DECL(
1581 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1582 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1584 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1585 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1587 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1588 static const char * const rt5677_mono_adc1_r_src[] = {
1589 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1592 static SOC_ENUM_SINGLE_DECL(
1593 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1594 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1596 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1597 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1599 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1600 static const char * const rt5677_stereo4_adc2_src[] = {
1601 "DD MIX1", "DMIC", "DD MIX2"
1604 static SOC_ENUM_SINGLE_DECL(
1605 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1606 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1608 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1609 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1612 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1613 static const char * const rt5677_stereo4_adc1_src[] = {
1614 "DD MIX1", "ADC1/2", "DD MIX2"
1617 static SOC_ENUM_SINGLE_DECL(
1618 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1619 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1621 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1622 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1624 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1625 static const char * const rt5677_inbound01_src[] = {
1626 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1630 static SOC_ENUM_SINGLE_DECL(
1631 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1632 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1634 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1635 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1637 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1638 static const char * const rt5677_inbound23_src[] = {
1639 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1640 "DAC1 FS", "IF4 DAC"
1643 static SOC_ENUM_SINGLE_DECL(
1644 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1645 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1647 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1648 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1650 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1651 static const char * const rt5677_inbound45_src[] = {
1652 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1656 static SOC_ENUM_SINGLE_DECL(
1657 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1658 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1660 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1661 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1663 /* InBound6 Source */ /* MX-A3 [2:0] */
1664 static const char * const rt5677_inbound6_src[] = {
1665 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1666 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1669 static SOC_ENUM_SINGLE_DECL(
1670 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1671 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1673 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1674 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1676 /* InBound7 Source */ /* MX-A4 [14:12] */
1677 static const char * const rt5677_inbound7_src[] = {
1678 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1679 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1682 static SOC_ENUM_SINGLE_DECL(
1683 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1684 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1686 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1687 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1689 /* InBound8 Source */ /* MX-A4 [10:8] */
1690 static const char * const rt5677_inbound8_src[] = {
1691 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1692 "MONO ADC MIX L", "DACL1 FS"
1695 static SOC_ENUM_SINGLE_DECL(
1696 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1697 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1699 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1700 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1702 /* InBound9 Source */ /* MX-A4 [6:4] */
1703 static const char * const rt5677_inbound9_src[] = {
1704 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1705 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1708 static SOC_ENUM_SINGLE_DECL(
1709 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1710 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1712 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1713 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1715 /* VAD Source */ /* MX-9F [6:4] */
1716 static const char * const rt5677_vad_src[] = {
1717 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1721 static SOC_ENUM_SINGLE_DECL(
1722 rt5677_vad_enum, RT5677_VAD_CTRL4,
1723 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1725 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1726 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1728 /* Sidetone Source */ /* MX-13 [11:9] */
1729 static const char * const rt5677_sidetone_src[] = {
1730 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1733 static SOC_ENUM_SINGLE_DECL(
1734 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1735 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1737 static const struct snd_kcontrol_new rt5677_sidetone_mux =
1738 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1740 /* DAC1/2 Source */ /* MX-15 [1:0] */
1741 static const char * const rt5677_dac12_src[] = {
1742 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1745 static SOC_ENUM_SINGLE_DECL(
1746 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1747 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1749 static const struct snd_kcontrol_new rt5677_dac12_mux =
1750 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1752 /* DAC3 Source */ /* MX-15 [5:4] */
1753 static const char * const rt5677_dac3_src[] = {
1754 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1757 static SOC_ENUM_SINGLE_DECL(
1758 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1759 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1761 static const struct snd_kcontrol_new rt5677_dac3_mux =
1762 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1764 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1765 static const char * const rt5677_pdm_src[] = {
1766 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1769 static SOC_ENUM_SINGLE_DECL(
1770 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1771 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1773 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1774 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
1776 static SOC_ENUM_SINGLE_DECL(
1777 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1778 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1780 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1781 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
1783 static SOC_ENUM_SINGLE_DECL(
1784 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1785 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1787 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1788 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
1790 static SOC_ENUM_SINGLE_DECL(
1791 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1792 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1794 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1795 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1797 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
1798 static const char * const rt5677_if12_adc1_src[] = {
1799 "STO1 ADC MIX", "OB01", "VAD ADC"
1802 static SOC_ENUM_SINGLE_DECL(
1803 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1804 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1806 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1807 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
1809 static SOC_ENUM_SINGLE_DECL(
1810 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1811 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1813 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1814 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
1816 static SOC_ENUM_SINGLE_DECL(
1817 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1818 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1820 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1821 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
1823 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1824 static const char * const rt5677_if12_adc2_src[] = {
1825 "STO2 ADC MIX", "OB23"
1828 static SOC_ENUM_SINGLE_DECL(
1829 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1830 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1832 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1833 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
1835 static SOC_ENUM_SINGLE_DECL(
1836 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1837 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1839 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1840 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
1842 static SOC_ENUM_SINGLE_DECL(
1843 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1844 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1846 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1847 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
1849 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1850 static const char * const rt5677_if12_adc3_src[] = {
1851 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1854 static SOC_ENUM_SINGLE_DECL(
1855 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1856 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1858 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1859 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
1861 static SOC_ENUM_SINGLE_DECL(
1862 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1863 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1865 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1866 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
1868 static SOC_ENUM_SINGLE_DECL(
1869 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1870 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1872 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1873 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
1875 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1876 static const char * const rt5677_if12_adc4_src[] = {
1877 "STO4 ADC MIX", "OB67", "OB01"
1880 static SOC_ENUM_SINGLE_DECL(
1881 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1882 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1884 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1885 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
1887 static SOC_ENUM_SINGLE_DECL(
1888 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1889 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1891 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1892 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
1894 static SOC_ENUM_SINGLE_DECL(
1895 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1896 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1898 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1899 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
1901 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
1902 static const char * const rt5677_if34_adc_src[] = {
1903 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1904 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1907 static SOC_ENUM_SINGLE_DECL(
1908 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1909 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1911 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1912 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
1914 static SOC_ENUM_SINGLE_DECL(
1915 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1916 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1918 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1919 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
1921 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
1922 static const char * const rt5677_if12_adc_swap_src[] = {
1923 "L/R", "R/L", "L/L", "R/R"
1926 static SOC_ENUM_SINGLE_DECL(
1927 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
1928 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
1930 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
1931 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
1933 static SOC_ENUM_SINGLE_DECL(
1934 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
1935 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1937 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
1938 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
1940 static SOC_ENUM_SINGLE_DECL(
1941 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
1942 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1944 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
1945 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
1947 static SOC_ENUM_SINGLE_DECL(
1948 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
1949 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1951 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
1952 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
1954 static SOC_ENUM_SINGLE_DECL(
1955 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
1956 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1958 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
1959 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
1961 static SOC_ENUM_SINGLE_DECL(
1962 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
1963 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1965 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
1966 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
1968 static SOC_ENUM_SINGLE_DECL(
1969 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
1970 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1972 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
1973 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
1975 static SOC_ENUM_SINGLE_DECL(
1976 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
1977 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1979 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
1980 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
1982 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
1983 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
1984 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1985 "3/1/2/4", "3/4/1/2"
1988 static SOC_ENUM_SINGLE_DECL(
1989 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
1990 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
1992 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
1993 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
1995 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
1996 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
1997 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1998 "2/3/1/4", "3/4/1/2"
2001 static SOC_ENUM_SINGLE_DECL(
2002 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2003 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2005 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2006 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2008 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2009 MX-3F[14:12][10:8][6:4][2:0]
2010 MX-43[14:12][10:8][6:4][2:0]
2011 MX-44[14:12][10:8][6:4][2:0] */
2012 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2013 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2016 static SOC_ENUM_SINGLE_DECL(
2017 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2018 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2020 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2021 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2023 static SOC_ENUM_SINGLE_DECL(
2024 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2025 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2027 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2028 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2030 static SOC_ENUM_SINGLE_DECL(
2031 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2032 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2034 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2035 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2037 static SOC_ENUM_SINGLE_DECL(
2038 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2039 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2041 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2042 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2044 static SOC_ENUM_SINGLE_DECL(
2045 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2046 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2048 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2049 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2051 static SOC_ENUM_SINGLE_DECL(
2052 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2053 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2055 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2056 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2058 static SOC_ENUM_SINGLE_DECL(
2059 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2060 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2062 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2063 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2065 static SOC_ENUM_SINGLE_DECL(
2066 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2067 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2069 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2070 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2072 static SOC_ENUM_SINGLE_DECL(
2073 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2074 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2076 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2077 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2079 static SOC_ENUM_SINGLE_DECL(
2080 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2081 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2083 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2084 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2086 static SOC_ENUM_SINGLE_DECL(
2087 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2088 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2090 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2091 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2093 static SOC_ENUM_SINGLE_DECL(
2094 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2095 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2097 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2098 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2100 static SOC_ENUM_SINGLE_DECL(
2101 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2102 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2104 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2105 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2107 static SOC_ENUM_SINGLE_DECL(
2108 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2109 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2111 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2112 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2114 static SOC_ENUM_SINGLE_DECL(
2115 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2116 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2118 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2119 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2121 static SOC_ENUM_SINGLE_DECL(
2122 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2123 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2125 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2126 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2128 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2129 struct snd_kcontrol *kcontrol, int event)
2131 struct snd_soc_codec *codec = w->codec;
2132 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2135 case SND_SOC_DAPM_POST_PMU:
2136 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2137 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2140 case SND_SOC_DAPM_PRE_PMD:
2141 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2142 RT5677_PWR_BST1_P, 0);
2152 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2153 struct snd_kcontrol *kcontrol, int event)
2155 struct snd_soc_codec *codec = w->codec;
2156 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2159 case SND_SOC_DAPM_POST_PMU:
2160 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2161 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2164 case SND_SOC_DAPM_PRE_PMD:
2165 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2166 RT5677_PWR_BST2_P, 0);
2176 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2177 struct snd_kcontrol *kcontrol, int event)
2179 struct snd_soc_codec *codec = w->codec;
2180 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2183 case SND_SOC_DAPM_POST_PMU:
2184 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2185 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2194 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2195 struct snd_kcontrol *kcontrol, int event)
2197 struct snd_soc_codec *codec = w->codec;
2198 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2201 case SND_SOC_DAPM_POST_PMU:
2202 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2203 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2212 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2213 struct snd_kcontrol *kcontrol, int event)
2215 struct snd_soc_codec *codec = w->codec;
2216 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2219 case SND_SOC_DAPM_POST_PMU:
2220 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2221 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2222 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2223 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2226 case SND_SOC_DAPM_PRE_PMD:
2227 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2228 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2229 RT5677_PWR_CLK_MB, 0);
2239 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2240 struct snd_kcontrol *kcontrol, int event)
2242 struct snd_soc_codec *codec = w->codec;
2243 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2247 case SND_SOC_DAPM_PRE_PMU:
2248 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2249 if (value & RT5677_IF1_ADC_CTRL_MASK)
2250 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2251 RT5677_IF1_ADC_MODE_MASK,
2252 RT5677_IF1_ADC_MODE_TDM);
2262 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2263 struct snd_kcontrol *kcontrol, int event)
2265 struct snd_soc_codec *codec = w->codec;
2266 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2270 case SND_SOC_DAPM_PRE_PMU:
2271 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2272 if (value & RT5677_IF2_ADC_CTRL_MASK)
2273 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2274 RT5677_IF2_ADC_MODE_MASK,
2275 RT5677_IF2_ADC_MODE_TDM);
2285 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2286 struct snd_kcontrol *kcontrol, int event)
2288 struct snd_soc_codec *codec = w->codec;
2289 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2292 case SND_SOC_DAPM_POST_PMU:
2293 if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2294 !rt5677->is_vref_slow) {
2296 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2297 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2298 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2299 rt5677->is_vref_slow = true;
2310 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2311 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2312 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
2313 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2314 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
2317 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2318 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2319 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2320 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2321 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2322 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2324 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2326 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2328 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2330 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2332 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2334 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2336 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2338 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2340 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2342 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2344 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2346 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2347 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2348 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2349 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2350 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2352 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2357 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2358 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2359 SND_SOC_DAPM_POST_PMU),
2362 SND_SOC_DAPM_INPUT("DMIC L1"),
2363 SND_SOC_DAPM_INPUT("DMIC R1"),
2364 SND_SOC_DAPM_INPUT("DMIC L2"),
2365 SND_SOC_DAPM_INPUT("DMIC R2"),
2366 SND_SOC_DAPM_INPUT("DMIC L3"),
2367 SND_SOC_DAPM_INPUT("DMIC R3"),
2368 SND_SOC_DAPM_INPUT("DMIC L4"),
2369 SND_SOC_DAPM_INPUT("DMIC R4"),
2371 SND_SOC_DAPM_INPUT("IN1P"),
2372 SND_SOC_DAPM_INPUT("IN1N"),
2373 SND_SOC_DAPM_INPUT("IN2P"),
2374 SND_SOC_DAPM_INPUT("IN2N"),
2376 SND_SOC_DAPM_INPUT("Haptic Generator"),
2378 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2379 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2380 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2381 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2383 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2384 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2385 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2386 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2387 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2388 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2389 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2390 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2392 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2393 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2396 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2397 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2398 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2399 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2400 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2401 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2404 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2406 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2408 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2410 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2411 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2412 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2413 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2414 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2415 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2416 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2417 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2420 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2421 &rt5677_sto1_dmic_mux),
2422 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2423 &rt5677_sto1_adc1_mux),
2424 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2425 &rt5677_sto1_adc2_mux),
2426 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2427 &rt5677_sto2_dmic_mux),
2428 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2429 &rt5677_sto2_adc1_mux),
2430 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2431 &rt5677_sto2_adc2_mux),
2432 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2433 &rt5677_sto2_adc_lr_mux),
2434 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2435 &rt5677_sto3_dmic_mux),
2436 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2437 &rt5677_sto3_adc1_mux),
2438 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2439 &rt5677_sto3_adc2_mux),
2440 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2441 &rt5677_sto4_dmic_mux),
2442 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2443 &rt5677_sto4_adc1_mux),
2444 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2445 &rt5677_sto4_adc2_mux),
2446 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2447 &rt5677_mono_dmic_l_mux),
2448 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2449 &rt5677_mono_dmic_r_mux),
2450 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2451 &rt5677_mono_adc2_l_mux),
2452 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2453 &rt5677_mono_adc1_l_mux),
2454 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2455 &rt5677_mono_adc1_r_mux),
2456 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2457 &rt5677_mono_adc2_r_mux),
2460 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2461 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2462 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2463 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2464 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2465 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2466 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2467 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2468 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2469 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2470 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2471 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2472 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2473 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2474 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2475 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2476 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2477 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2478 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2479 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2480 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2481 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2482 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2483 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2484 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2485 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2486 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2487 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2488 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2489 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2490 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2491 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2494 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2495 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2496 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2497 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2498 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2499 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2500 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2501 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2502 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2503 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2504 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2505 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2506 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2507 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2508 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2509 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2512 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2513 &rt5677_ib9_src_mux),
2514 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2515 &rt5677_ib8_src_mux),
2516 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2517 &rt5677_ib7_src_mux),
2518 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2519 &rt5677_ib6_src_mux),
2520 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2521 &rt5677_ib45_src_mux),
2522 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2523 &rt5677_ib23_src_mux),
2524 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2525 &rt5677_ib01_src_mux),
2526 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2527 &rt5677_ib45_bypass_src_mux),
2528 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2529 &rt5677_ib23_bypass_src_mux),
2530 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2531 &rt5677_ib01_bypass_src_mux),
2532 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2533 &rt5677_ob23_bypass_src_mux),
2534 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2535 &rt5677_ob01_bypass_src_mux),
2537 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2538 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2540 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2541 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2542 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2543 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2544 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2545 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2547 /* Digital Interface */
2548 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2549 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2550 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2551 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2552 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2553 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2554 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2555 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2556 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2557 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2558 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2559 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2560 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2561 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2562 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2563 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2564 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2565 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2567 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2568 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2569 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2570 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2571 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2572 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2573 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2574 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2575 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2576 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2577 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2578 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2579 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2580 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2581 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2582 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2583 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2584 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2586 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2587 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2588 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2589 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2590 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2591 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2592 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2593 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2595 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2596 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2597 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2598 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2599 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2600 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2601 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2602 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2604 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2605 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2606 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2607 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2608 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2609 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2610 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2611 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2612 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2613 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2614 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2615 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2616 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2617 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2618 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2619 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2620 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2621 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2623 /* Digital Interface Select */
2624 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2625 &rt5677_if1_adc1_mux),
2626 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2627 &rt5677_if1_adc2_mux),
2628 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2629 &rt5677_if1_adc3_mux),
2630 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2631 &rt5677_if1_adc4_mux),
2632 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2633 &rt5677_if1_adc1_swap_mux),
2634 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2635 &rt5677_if1_adc2_swap_mux),
2636 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2637 &rt5677_if1_adc3_swap_mux),
2638 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2639 &rt5677_if1_adc4_swap_mux),
2640 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2641 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2642 SND_SOC_DAPM_PRE_PMU),
2643 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2644 &rt5677_if2_adc1_mux),
2645 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2646 &rt5677_if2_adc2_mux),
2647 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2648 &rt5677_if2_adc3_mux),
2649 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2650 &rt5677_if2_adc4_mux),
2651 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2652 &rt5677_if2_adc1_swap_mux),
2653 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2654 &rt5677_if2_adc2_swap_mux),
2655 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2656 &rt5677_if2_adc3_swap_mux),
2657 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2658 &rt5677_if2_adc4_swap_mux),
2659 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2660 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2661 SND_SOC_DAPM_PRE_PMU),
2662 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2663 &rt5677_if3_adc_mux),
2664 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2665 &rt5677_if4_adc_mux),
2666 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2667 &rt5677_slb_adc1_mux),
2668 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2669 &rt5677_slb_adc2_mux),
2670 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2671 &rt5677_slb_adc3_mux),
2672 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2673 &rt5677_slb_adc4_mux),
2675 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2676 &rt5677_if1_dac0_tdm_sel_mux),
2677 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2678 &rt5677_if1_dac1_tdm_sel_mux),
2679 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2680 &rt5677_if1_dac2_tdm_sel_mux),
2681 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2682 &rt5677_if1_dac3_tdm_sel_mux),
2683 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2684 &rt5677_if1_dac4_tdm_sel_mux),
2685 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2686 &rt5677_if1_dac5_tdm_sel_mux),
2687 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2688 &rt5677_if1_dac6_tdm_sel_mux),
2689 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2690 &rt5677_if1_dac7_tdm_sel_mux),
2692 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2693 &rt5677_if2_dac0_tdm_sel_mux),
2694 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2695 &rt5677_if2_dac1_tdm_sel_mux),
2696 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2697 &rt5677_if2_dac2_tdm_sel_mux),
2698 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2699 &rt5677_if2_dac3_tdm_sel_mux),
2700 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2701 &rt5677_if2_dac4_tdm_sel_mux),
2702 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2703 &rt5677_if2_dac5_tdm_sel_mux),
2704 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2705 &rt5677_if2_dac6_tdm_sel_mux),
2706 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2707 &rt5677_if2_dac7_tdm_sel_mux),
2709 /* Audio Interface */
2710 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2711 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2712 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2713 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2714 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2715 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2716 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2717 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2718 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2719 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2722 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2723 &rt5677_sidetone_mux),
2724 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2725 RT5677_ST_EN_SFT, 0, NULL, 0),
2728 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2729 &rt5677_vad_src_mux),
2732 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2733 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2734 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2735 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2736 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2737 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2738 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2739 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2740 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2741 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2742 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2743 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2744 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2747 /* DAC mixer before sound effect */
2748 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2749 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2750 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2751 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2752 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2755 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2757 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2759 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2761 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2764 /* DAC2 channel Mux */
2765 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2766 &rt5677_dac2_l_mux),
2767 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2768 &rt5677_dac2_r_mux),
2770 /* DAC3 channel Mux */
2771 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2772 &rt5677_dac3_l_mux),
2773 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2774 &rt5677_dac3_r_mux),
2776 /* DAC4 channel Mux */
2777 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2778 &rt5677_dac4_l_mux),
2779 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2780 &rt5677_dac4_r_mux),
2783 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2784 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2785 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
2786 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2787 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
2788 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2789 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
2790 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
2791 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
2792 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
2793 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
2794 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
2795 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
2796 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
2798 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2799 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2800 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2801 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2802 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2803 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2804 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2805 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2806 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2807 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2808 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2809 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2810 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2811 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2812 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2813 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2814 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2815 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2816 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2817 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2820 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2821 RT5677_PWR_DAC1_BIT, 0),
2822 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2823 RT5677_PWR_DAC2_BIT, 0),
2824 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2825 RT5677_PWR_DAC3_BIT, 0),
2828 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2829 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2830 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2831 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2833 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2834 1, &rt5677_pdm1_l_mux),
2835 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2836 1, &rt5677_pdm1_r_mux),
2837 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2838 1, &rt5677_pdm2_l_mux),
2839 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2840 1, &rt5677_pdm2_r_mux),
2842 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2844 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2846 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2849 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
2850 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2851 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
2852 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2853 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
2854 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2857 SND_SOC_DAPM_OUTPUT("LOUT1"),
2858 SND_SOC_DAPM_OUTPUT("LOUT2"),
2859 SND_SOC_DAPM_OUTPUT("LOUT3"),
2860 SND_SOC_DAPM_OUTPUT("PDM1L"),
2861 SND_SOC_DAPM_OUTPUT("PDM1R"),
2862 SND_SOC_DAPM_OUTPUT("PDM2L"),
2863 SND_SOC_DAPM_OUTPUT("PDM2R"),
2865 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
2868 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2869 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
2870 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
2871 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", can_use_asrc },
2872 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", can_use_asrc },
2873 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
2874 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
2875 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
2876 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
2877 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
2878 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
2880 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2881 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
2882 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
2883 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
2884 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
2885 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
2886 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
2887 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2888 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
2889 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
2890 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
2891 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2892 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2894 { "DMIC1", NULL, "DMIC L1" },
2895 { "DMIC1", NULL, "DMIC R1" },
2896 { "DMIC2", NULL, "DMIC L2" },
2897 { "DMIC2", NULL, "DMIC R2" },
2898 { "DMIC3", NULL, "DMIC L3" },
2899 { "DMIC3", NULL, "DMIC R3" },
2900 { "DMIC4", NULL, "DMIC L4" },
2901 { "DMIC4", NULL, "DMIC R4" },
2903 { "DMIC L1", NULL, "DMIC CLK" },
2904 { "DMIC R1", NULL, "DMIC CLK" },
2905 { "DMIC L2", NULL, "DMIC CLK" },
2906 { "DMIC R2", NULL, "DMIC CLK" },
2907 { "DMIC L3", NULL, "DMIC CLK" },
2908 { "DMIC R3", NULL, "DMIC CLK" },
2909 { "DMIC L4", NULL, "DMIC CLK" },
2910 { "DMIC R4", NULL, "DMIC CLK" },
2912 { "DMIC L1", NULL, "DMIC1 power" },
2913 { "DMIC R1", NULL, "DMIC1 power" },
2914 { "DMIC L3", NULL, "DMIC3 power" },
2915 { "DMIC R3", NULL, "DMIC3 power" },
2916 { "DMIC L4", NULL, "DMIC4 power" },
2917 { "DMIC R4", NULL, "DMIC4 power" },
2919 { "BST1", NULL, "IN1P" },
2920 { "BST1", NULL, "IN1N" },
2921 { "BST2", NULL, "IN2P" },
2922 { "BST2", NULL, "IN2N" },
2924 { "IN1P", NULL, "MICBIAS1" },
2925 { "IN1N", NULL, "MICBIAS1" },
2926 { "IN2P", NULL, "MICBIAS1" },
2927 { "IN2N", NULL, "MICBIAS1" },
2929 { "ADC 1", NULL, "BST1" },
2930 { "ADC 1", NULL, "ADC 1 power" },
2931 { "ADC 1", NULL, "ADC1 clock" },
2932 { "ADC 2", NULL, "BST2" },
2933 { "ADC 2", NULL, "ADC 2 power" },
2934 { "ADC 2", NULL, "ADC2 clock" },
2936 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2937 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2938 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2939 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2941 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2942 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2943 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2944 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2946 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2947 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2948 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2949 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2951 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2952 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2953 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2954 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2956 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2957 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2958 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2959 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2961 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2962 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2963 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2964 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2966 { "ADC 1_2", NULL, "ADC 1" },
2967 { "ADC 1_2", NULL, "ADC 2" },
2969 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2970 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2971 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2973 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2974 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2975 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2977 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2978 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2979 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2981 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2982 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2983 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2985 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2986 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2987 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2989 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2990 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2991 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2993 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2994 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2995 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2997 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2998 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2999 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3001 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3002 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3003 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3005 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3006 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3007 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3009 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3010 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3011 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3013 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3014 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3015 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3017 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3018 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3019 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3020 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3022 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3023 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3024 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3025 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3026 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3028 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3029 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3031 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3032 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3033 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3034 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3036 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3037 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3039 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3040 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3042 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3043 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3044 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3045 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3046 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3048 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3049 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3051 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3052 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3053 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3054 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3056 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3057 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3058 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3059 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3060 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3062 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3063 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3065 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3066 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3067 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3068 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3070 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3071 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3072 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3073 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3074 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3076 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3077 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3079 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3080 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3081 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3082 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3084 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3085 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3086 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3087 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3089 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3090 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3092 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3093 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3094 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3095 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3096 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3098 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3099 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3100 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3102 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3103 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3105 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3106 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3107 { "IF1 ADC3 Mux", "OB45", "OB45" },
3109 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3110 { "IF1 ADC4 Mux", "OB67", "OB67" },
3111 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3113 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3114 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3115 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3116 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3118 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3119 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3120 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3121 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3123 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3124 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3125 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3126 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3128 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3129 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3130 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3131 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3133 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3134 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3135 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3136 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3138 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3139 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3140 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3141 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3142 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3143 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3144 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3145 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3147 { "AIF1TX", NULL, "I2S1" },
3148 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3150 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3151 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3152 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3154 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3155 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3157 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3158 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3159 { "IF2 ADC3 Mux", "OB45", "OB45" },
3161 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3162 { "IF2 ADC4 Mux", "OB67", "OB67" },
3163 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3165 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3166 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3167 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3168 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3170 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3171 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3172 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3173 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3175 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3176 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3177 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3178 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3180 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3181 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3182 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3183 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3185 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3186 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3187 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3188 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3190 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3191 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3192 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3193 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3194 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3195 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3196 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3197 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3199 { "AIF2TX", NULL, "I2S2" },
3200 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3202 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3203 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3204 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3205 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3206 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3207 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3208 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3209 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3211 { "AIF3TX", NULL, "I2S3" },
3212 { "AIF3TX", NULL, "IF3 ADC Mux" },
3214 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3215 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3216 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3217 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3218 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3219 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3220 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3221 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3223 { "AIF4TX", NULL, "I2S4" },
3224 { "AIF4TX", NULL, "IF4 ADC Mux" },
3226 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3227 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3228 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3230 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3231 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3233 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3234 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3235 { "SLB ADC3 Mux", "OB45", "OB45" },
3237 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3238 { "SLB ADC4 Mux", "OB67", "OB67" },
3239 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3241 { "SLBTX", NULL, "SLB" },
3242 { "SLBTX", NULL, "SLB ADC1 Mux" },
3243 { "SLBTX", NULL, "SLB ADC2 Mux" },
3244 { "SLBTX", NULL, "SLB ADC3 Mux" },
3245 { "SLBTX", NULL, "SLB ADC4 Mux" },
3247 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3248 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3249 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3250 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3251 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3253 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3254 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3256 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3257 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3258 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3259 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3260 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3261 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3263 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3264 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3266 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3267 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3268 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3269 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3270 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3272 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3273 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3275 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
3276 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
3277 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3278 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3279 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3280 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3281 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3282 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3284 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
3285 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
3286 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3287 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3288 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3289 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3290 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3291 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3293 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3294 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3295 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3296 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3297 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3298 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3300 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3301 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3302 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3303 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3304 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3305 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3306 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3308 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3309 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3310 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3311 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3312 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3313 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3314 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3316 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3317 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3318 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3319 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3320 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3321 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3322 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3324 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3325 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3326 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3327 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3328 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3329 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3330 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3332 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3333 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3334 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3335 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3336 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3337 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3338 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3340 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3341 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3342 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3343 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3344 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3345 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3346 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3348 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3349 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3350 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3351 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3352 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3353 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3354 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3356 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3357 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3358 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3359 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3361 { "OutBound2", NULL, "OB23 Bypass Mux" },
3362 { "OutBound3", NULL, "OB23 Bypass Mux" },
3363 { "OutBound4", NULL, "OB4 MIX" },
3364 { "OutBound5", NULL, "OB5 MIX" },
3365 { "OutBound6", NULL, "OB6 MIX" },
3366 { "OutBound7", NULL, "OB7 MIX" },
3368 { "OB45", NULL, "OutBound4" },
3369 { "OB45", NULL, "OutBound5" },
3370 { "OB67", NULL, "OutBound6" },
3371 { "OB67", NULL, "OutBound7" },
3373 { "IF1 DAC0", NULL, "AIF1RX" },
3374 { "IF1 DAC1", NULL, "AIF1RX" },
3375 { "IF1 DAC2", NULL, "AIF1RX" },
3376 { "IF1 DAC3", NULL, "AIF1RX" },
3377 { "IF1 DAC4", NULL, "AIF1RX" },
3378 { "IF1 DAC5", NULL, "AIF1RX" },
3379 { "IF1 DAC6", NULL, "AIF1RX" },
3380 { "IF1 DAC7", NULL, "AIF1RX" },
3381 { "IF1 DAC0", NULL, "I2S1" },
3382 { "IF1 DAC1", NULL, "I2S1" },
3383 { "IF1 DAC2", NULL, "I2S1" },
3384 { "IF1 DAC3", NULL, "I2S1" },
3385 { "IF1 DAC4", NULL, "I2S1" },
3386 { "IF1 DAC5", NULL, "I2S1" },
3387 { "IF1 DAC6", NULL, "I2S1" },
3388 { "IF1 DAC7", NULL, "I2S1" },
3390 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3391 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3392 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3393 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3394 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3395 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3396 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3397 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3399 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3400 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3401 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3402 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3403 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3404 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3405 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3406 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3408 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3409 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3410 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3411 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3412 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3413 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3414 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3415 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3417 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3418 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3419 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3420 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3421 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3422 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3423 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3424 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3426 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3427 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3428 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3429 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3430 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3431 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3432 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3433 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3435 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3436 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3437 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3438 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3439 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3440 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3441 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3442 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3444 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3445 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3446 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3447 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3448 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3449 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3450 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3451 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3453 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3454 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3455 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3456 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3457 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3458 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3459 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3460 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3462 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3463 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3464 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3465 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3466 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3467 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3468 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3469 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3471 { "IF2 DAC0", NULL, "AIF2RX" },
3472 { "IF2 DAC1", NULL, "AIF2RX" },
3473 { "IF2 DAC2", NULL, "AIF2RX" },
3474 { "IF2 DAC3", NULL, "AIF2RX" },
3475 { "IF2 DAC4", NULL, "AIF2RX" },
3476 { "IF2 DAC5", NULL, "AIF2RX" },
3477 { "IF2 DAC6", NULL, "AIF2RX" },
3478 { "IF2 DAC7", NULL, "AIF2RX" },
3479 { "IF2 DAC0", NULL, "I2S2" },
3480 { "IF2 DAC1", NULL, "I2S2" },
3481 { "IF2 DAC2", NULL, "I2S2" },
3482 { "IF2 DAC3", NULL, "I2S2" },
3483 { "IF2 DAC4", NULL, "I2S2" },
3484 { "IF2 DAC5", NULL, "I2S2" },
3485 { "IF2 DAC6", NULL, "I2S2" },
3486 { "IF2 DAC7", NULL, "I2S2" },
3488 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3489 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3490 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3491 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3492 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3493 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3494 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3495 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3497 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3498 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3499 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3500 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3501 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3502 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3503 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3504 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3506 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3507 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3508 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3509 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3510 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3511 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3512 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3513 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3515 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3516 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3517 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3518 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3519 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3520 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3521 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3522 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3524 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3525 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3526 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3527 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3528 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3529 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3530 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3531 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3533 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3534 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3535 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3536 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3537 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3538 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3539 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3540 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3542 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3543 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3544 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3545 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3546 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3547 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3548 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3549 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3551 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3552 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3553 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3554 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3555 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3556 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3557 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3558 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3560 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3561 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3562 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3563 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3564 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3565 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3566 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3567 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3569 { "IF3 DAC", NULL, "AIF3RX" },
3570 { "IF3 DAC", NULL, "I2S3" },
3572 { "IF4 DAC", NULL, "AIF4RX" },
3573 { "IF4 DAC", NULL, "I2S4" },
3575 { "IF3 DAC L", NULL, "IF3 DAC" },
3576 { "IF3 DAC R", NULL, "IF3 DAC" },
3578 { "IF4 DAC L", NULL, "IF4 DAC" },
3579 { "IF4 DAC R", NULL, "IF4 DAC" },
3581 { "SLB DAC0", NULL, "SLBRX" },
3582 { "SLB DAC1", NULL, "SLBRX" },
3583 { "SLB DAC2", NULL, "SLBRX" },
3584 { "SLB DAC3", NULL, "SLBRX" },
3585 { "SLB DAC4", NULL, "SLBRX" },
3586 { "SLB DAC5", NULL, "SLBRX" },
3587 { "SLB DAC6", NULL, "SLBRX" },
3588 { "SLB DAC7", NULL, "SLBRX" },
3589 { "SLB DAC0", NULL, "SLB" },
3590 { "SLB DAC1", NULL, "SLB" },
3591 { "SLB DAC2", NULL, "SLB" },
3592 { "SLB DAC3", NULL, "SLB" },
3593 { "SLB DAC4", NULL, "SLB" },
3594 { "SLB DAC5", NULL, "SLB" },
3595 { "SLB DAC6", NULL, "SLB" },
3596 { "SLB DAC7", NULL, "SLB" },
3598 { "SLB DAC01", NULL, "SLB DAC0" },
3599 { "SLB DAC01", NULL, "SLB DAC1" },
3600 { "SLB DAC23", NULL, "SLB DAC2" },
3601 { "SLB DAC23", NULL, "SLB DAC3" },
3602 { "SLB DAC45", NULL, "SLB DAC4" },
3603 { "SLB DAC45", NULL, "SLB DAC5" },
3604 { "SLB DAC67", NULL, "SLB DAC6" },
3605 { "SLB DAC67", NULL, "SLB DAC7" },
3607 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3608 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3609 { "ADDA1 Mux", "OB 67", "OB67" },
3611 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3612 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3613 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3614 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3615 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3616 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3618 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3619 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3620 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3621 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3623 { "DAC1 FS", NULL, "DAC1 MIXL" },
3624 { "DAC1 FS", NULL, "DAC1 MIXR" },
3626 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
3627 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
3628 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3629 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3630 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3631 { "DAC2 L Mux", "OB 2", "OutBound2" },
3633 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
3634 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
3635 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3636 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3637 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3638 { "DAC2 R Mux", "OB 3", "OutBound3" },
3639 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3640 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3642 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
3643 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
3644 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3645 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3646 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3647 { "DAC3 L Mux", "OB 4", "OutBound4" },
3649 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
3650 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
3651 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3652 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3653 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3654 { "DAC3 R Mux", "OB 5", "OutBound5" },
3656 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
3657 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
3658 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3659 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3660 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3661 { "DAC4 L Mux", "OB 6", "OutBound6" },
3663 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
3664 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
3665 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3666 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3667 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3668 { "DAC4 R Mux", "OB 7", "OutBound7" },
3670 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3671 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3672 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3673 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3674 { "Sidetone Mux", "ADC1", "ADC 1" },
3675 { "Sidetone Mux", "ADC2", "ADC 2" },
3676 { "Sidetone Mux", NULL, "Sidetone Power" },
3678 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3679 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3680 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3681 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3682 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3683 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3684 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3685 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3686 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3687 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3688 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3690 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3691 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3692 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3693 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3694 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3695 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3696 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3697 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3698 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3699 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3700 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3701 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3703 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3704 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3705 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3706 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3707 { "DD1 MIXL", NULL, "dac mono3 left filter" },
3708 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3709 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3710 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3711 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3712 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
3713 { "DD1 MIXR", NULL, "dac mono3 right filter" },
3714 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3716 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3717 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3718 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3719 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
3720 { "DD2 MIXL", NULL, "dac mono4 left filter" },
3721 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3722 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3723 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3724 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3725 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
3726 { "DD2 MIXR", NULL, "dac mono4 right filter" },
3727 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3729 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3730 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3731 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3732 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3733 { "DD1 MIX", NULL, "DD1 MIXL" },
3734 { "DD1 MIX", NULL, "DD1 MIXR" },
3735 { "DD2 MIX", NULL, "DD2 MIXL" },
3736 { "DD2 MIX", NULL, "DD2 MIXR" },
3738 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3739 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3740 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3741 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3743 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3744 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3745 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3746 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3748 { "DAC 1", NULL, "DAC12 SRC Mux" },
3749 { "DAC 2", NULL, "DAC12 SRC Mux" },
3750 { "DAC 3", NULL, "DAC3 SRC Mux" },
3752 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3753 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3754 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3755 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3756 { "PDM1 L Mux", NULL, "PDM1 Power" },
3757 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3758 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3759 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3760 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3761 { "PDM1 R Mux", NULL, "PDM1 Power" },
3762 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3763 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3764 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3765 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3766 { "PDM2 L Mux", NULL, "PDM2 Power" },
3767 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3768 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3769 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3770 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3771 { "PDM2 R Mux", NULL, "PDM2 Power" },
3773 { "LOUT1 amp", NULL, "DAC 1" },
3774 { "LOUT2 amp", NULL, "DAC 2" },
3775 { "LOUT3 amp", NULL, "DAC 3" },
3777 { "LOUT1 vref", NULL, "LOUT1 amp" },
3778 { "LOUT2 vref", NULL, "LOUT2 amp" },
3779 { "LOUT3 vref", NULL, "LOUT3 amp" },
3781 { "LOUT1", NULL, "LOUT1 vref" },
3782 { "LOUT2", NULL, "LOUT2 vref" },
3783 { "LOUT3", NULL, "LOUT3 vref" },
3785 { "PDM1L", NULL, "PDM1 L Mux" },
3786 { "PDM1R", NULL, "PDM1 R Mux" },
3787 { "PDM2L", NULL, "PDM2 L Mux" },
3788 { "PDM2R", NULL, "PDM2 R Mux" },
3791 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3792 { "DMIC L2", NULL, "DMIC1 power" },
3793 { "DMIC R2", NULL, "DMIC1 power" },
3796 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3797 { "DMIC L2", NULL, "DMIC2 power" },
3798 { "DMIC R2", NULL, "DMIC2 power" },
3801 static int rt5677_hw_params(struct snd_pcm_substream *substream,
3802 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3804 struct snd_soc_codec *codec = dai->codec;
3805 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3806 unsigned int val_len = 0, val_clk, mask_clk;
3807 int pre_div, bclk_ms, frame_size;
3809 rt5677->lrck[dai->id] = params_rate(params);
3810 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
3812 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3813 rt5677->sysclk, rt5677->lrck[dai->id]);
3816 frame_size = snd_soc_params_to_frame_size(params);
3817 if (frame_size < 0) {
3818 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3821 bclk_ms = frame_size > 32;
3822 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
3824 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
3825 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
3826 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
3827 bclk_ms, pre_div, dai->id);
3829 switch (params_width(params)) {
3833 val_len |= RT5677_I2S_DL_20;
3836 val_len |= RT5677_I2S_DL_24;
3839 val_len |= RT5677_I2S_DL_8;
3847 mask_clk = RT5677_I2S_PD1_MASK;
3848 val_clk = pre_div << RT5677_I2S_PD1_SFT;
3849 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3850 RT5677_I2S_DL_MASK, val_len);
3851 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3855 mask_clk = RT5677_I2S_PD2_MASK;
3856 val_clk = pre_div << RT5677_I2S_PD2_SFT;
3857 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3858 RT5677_I2S_DL_MASK, val_len);
3859 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3863 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
3864 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
3865 pre_div << RT5677_I2S_PD3_SFT;
3866 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3867 RT5677_I2S_DL_MASK, val_len);
3868 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3872 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
3873 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
3874 pre_div << RT5677_I2S_PD4_SFT;
3875 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3876 RT5677_I2S_DL_MASK, val_len);
3877 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3887 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3889 struct snd_soc_codec *codec = dai->codec;
3890 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3891 unsigned int reg_val = 0;
3893 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3894 case SND_SOC_DAIFMT_CBM_CFM:
3895 rt5677->master[dai->id] = 1;
3897 case SND_SOC_DAIFMT_CBS_CFS:
3898 reg_val |= RT5677_I2S_MS_S;
3899 rt5677->master[dai->id] = 0;
3905 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3906 case SND_SOC_DAIFMT_NB_NF:
3908 case SND_SOC_DAIFMT_IB_NF:
3909 reg_val |= RT5677_I2S_BP_INV;
3915 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3916 case SND_SOC_DAIFMT_I2S:
3918 case SND_SOC_DAIFMT_LEFT_J:
3919 reg_val |= RT5677_I2S_DF_LEFT;
3921 case SND_SOC_DAIFMT_DSP_A:
3922 reg_val |= RT5677_I2S_DF_PCM_A;
3924 case SND_SOC_DAIFMT_DSP_B:
3925 reg_val |= RT5677_I2S_DF_PCM_B;
3933 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3934 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3935 RT5677_I2S_DF_MASK, reg_val);
3938 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3939 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3940 RT5677_I2S_DF_MASK, reg_val);
3943 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3944 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3945 RT5677_I2S_DF_MASK, reg_val);
3948 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3949 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3950 RT5677_I2S_DF_MASK, reg_val);
3960 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3961 int clk_id, unsigned int freq, int dir)
3963 struct snd_soc_codec *codec = dai->codec;
3964 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3965 unsigned int reg_val = 0;
3967 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
3971 case RT5677_SCLK_S_MCLK:
3972 reg_val |= RT5677_SCLK_SRC_MCLK;
3974 case RT5677_SCLK_S_PLL1:
3975 reg_val |= RT5677_SCLK_SRC_PLL1;
3977 case RT5677_SCLK_S_RCCLK:
3978 reg_val |= RT5677_SCLK_SRC_RCCLK;
3981 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3984 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3985 RT5677_SCLK_SRC_MASK, reg_val);
3986 rt5677->sysclk = freq;
3987 rt5677->sysclk_src = clk_id;
3989 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3995 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3996 * @freq_in: external clock provided to codec.
3997 * @freq_out: target clock which codec works on.
3998 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4000 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4002 * Returns 0 for success or negative error code.
4004 static int rt5677_pll_calc(const unsigned int freq_in,
4005 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4007 if (RT5677_PLL_INP_MIN > freq_in)
4010 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4013 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4014 unsigned int freq_in, unsigned int freq_out)
4016 struct snd_soc_codec *codec = dai->codec;
4017 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4018 struct rl6231_pll_code pll_code;
4021 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4022 freq_out == rt5677->pll_out)
4025 if (!freq_in || !freq_out) {
4026 dev_dbg(codec->dev, "PLL disabled\n");
4029 rt5677->pll_out = 0;
4030 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4031 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4036 case RT5677_PLL1_S_MCLK:
4037 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4038 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4040 case RT5677_PLL1_S_BCLK1:
4041 case RT5677_PLL1_S_BCLK2:
4042 case RT5677_PLL1_S_BCLK3:
4043 case RT5677_PLL1_S_BCLK4:
4046 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4047 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4050 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4051 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4054 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4055 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4058 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4059 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4066 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4070 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4072 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4076 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4077 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4078 pll_code.n_code, pll_code.k_code);
4080 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4081 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4082 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4083 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4084 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4086 rt5677->pll_in = freq_in;
4087 rt5677->pll_out = freq_out;
4088 rt5677->pll_src = source;
4093 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4094 unsigned int rx_mask, int slots, int slot_width)
4096 struct snd_soc_codec *codec = dai->codec;
4097 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4098 unsigned int val = 0, slot_width_25 = 0;
4100 if (rx_mask || tx_mask)
4118 switch (slot_width) {
4123 slot_width_25 = 0x8080;
4137 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4139 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4143 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4145 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4155 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4156 enum snd_soc_bias_level level)
4158 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4161 case SND_SOC_BIAS_ON:
4164 case SND_SOC_BIAS_PREPARE:
4165 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
4166 rt5677_set_dsp_vad(codec, false);
4168 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4169 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4171 regmap_update_bits(rt5677->regmap,
4172 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4174 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4175 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4176 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4177 RT5677_PWR_BG | RT5677_PWR_VREF2,
4178 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4179 RT5677_PWR_BG | RT5677_PWR_VREF2);
4180 rt5677->is_vref_slow = false;
4181 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4182 RT5677_PWR_CORE, RT5677_PWR_CORE);
4183 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4188 case SND_SOC_BIAS_STANDBY:
4191 case SND_SOC_BIAS_OFF:
4192 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4193 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4194 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4195 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4196 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4197 regmap_update_bits(rt5677->regmap,
4198 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4200 if (rt5677->dsp_vad_en)
4201 rt5677_set_dsp_vad(codec, true);
4207 codec->dapm.bias_level = level;
4212 #ifdef CONFIG_GPIOLIB
4213 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4215 return container_of(chip, struct rt5677_priv, gpio_chip);
4218 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4220 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4223 case RT5677_GPIO1 ... RT5677_GPIO5:
4224 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4225 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4229 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4230 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4238 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4239 unsigned offset, int value)
4241 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4244 case RT5677_GPIO1 ... RT5677_GPIO5:
4245 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4246 0x3 << (offset * 3 + 1),
4247 (0x2 | !!value) << (offset * 3 + 1));
4251 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4252 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4253 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4263 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4265 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4268 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4272 return (value & (0x1 << offset)) >> offset;
4275 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4277 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4280 case RT5677_GPIO1 ... RT5677_GPIO5:
4281 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4282 0x1 << (offset * 3 + 2), 0x0);
4286 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4287 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4297 /** Configures the gpio as
4302 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4308 case RT5677_GPIO1 ... RT5677_GPIO2:
4309 shift = 2 * (1 - offset);
4310 regmap_update_bits(rt5677->regmap,
4311 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4313 (value & 0x3) << shift);
4316 case RT5677_GPIO3 ... RT5677_GPIO6:
4317 shift = 2 * (9 - offset);
4318 regmap_update_bits(rt5677->regmap,
4319 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4321 (value & 0x3) << shift);
4329 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4331 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4332 struct regmap_irq_chip_data *data = rt5677->irq_data;
4335 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4336 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4337 (rt5677->pdata.jd1_gpio == 2 &&
4338 offset == RT5677_GPIO2) ||
4339 (rt5677->pdata.jd1_gpio == 3 &&
4340 offset == RT5677_GPIO3)) {
4341 irq = RT5677_IRQ_JD1;
4347 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4348 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4349 (rt5677->pdata.jd2_gpio == 2 &&
4350 offset == RT5677_GPIO5) ||
4351 (rt5677->pdata.jd2_gpio == 3 &&
4352 offset == RT5677_GPIO6)) {
4353 irq = RT5677_IRQ_JD2;
4354 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4355 offset == RT5677_GPIO4) ||
4356 (rt5677->pdata.jd3_gpio == 2 &&
4357 offset == RT5677_GPIO5) ||
4358 (rt5677->pdata.jd3_gpio == 3 &&
4359 offset == RT5677_GPIO6)) {
4360 irq = RT5677_IRQ_JD3;
4366 return regmap_irq_get_virq(data, irq);
4369 static struct gpio_chip rt5677_template_chip = {
4371 .owner = THIS_MODULE,
4372 .direction_output = rt5677_gpio_direction_out,
4373 .set = rt5677_gpio_set,
4374 .direction_input = rt5677_gpio_direction_in,
4375 .get = rt5677_gpio_get,
4376 .to_irq = rt5677_to_irq,
4380 static void rt5677_init_gpio(struct i2c_client *i2c)
4382 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4385 rt5677->gpio_chip = rt5677_template_chip;
4386 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4387 rt5677->gpio_chip.dev = &i2c->dev;
4388 rt5677->gpio_chip.base = -1;
4390 ret = gpiochip_add(&rt5677->gpio_chip);
4392 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4395 static void rt5677_free_gpio(struct i2c_client *i2c)
4397 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4399 gpiochip_remove(&rt5677->gpio_chip);
4402 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4407 static void rt5677_init_gpio(struct i2c_client *i2c)
4411 static void rt5677_free_gpio(struct i2c_client *i2c)
4416 static int rt5677_probe(struct snd_soc_codec *codec)
4418 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4421 rt5677->codec = codec;
4423 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4424 snd_soc_dapm_add_routes(&codec->dapm,
4426 ARRAY_SIZE(rt5677_dmic2_clk_2));
4427 } else { /*use dmic1 clock by default*/
4428 snd_soc_dapm_add_routes(&codec->dapm,
4430 ARRAY_SIZE(rt5677_dmic2_clk_1));
4433 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
4435 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4436 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4438 for (i = 0; i < RT5677_GPIO_NUM; i++)
4439 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4441 if (rt5677->irq_data) {
4442 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4444 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4447 if (rt5677->pdata.jd1_gpio)
4448 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4449 RT5677_SEL_GPIO_JD1_MASK,
4450 rt5677->pdata.jd1_gpio <<
4451 RT5677_SEL_GPIO_JD1_SFT);
4453 if (rt5677->pdata.jd2_gpio)
4454 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4455 RT5677_SEL_GPIO_JD2_MASK,
4456 rt5677->pdata.jd2_gpio <<
4457 RT5677_SEL_GPIO_JD2_SFT);
4459 if (rt5677->pdata.jd3_gpio)
4460 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4461 RT5677_SEL_GPIO_JD3_MASK,
4462 rt5677->pdata.jd3_gpio <<
4463 RT5677_SEL_GPIO_JD3_SFT);
4466 mutex_init(&rt5677->dsp_cmd_lock);
4467 mutex_init(&rt5677->dsp_pri_lock);
4472 static int rt5677_remove(struct snd_soc_codec *codec)
4474 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4476 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4477 if (gpio_is_valid(rt5677->pow_ldo2))
4478 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4484 static int rt5677_suspend(struct snd_soc_codec *codec)
4486 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4488 if (!rt5677->dsp_vad_en) {
4489 regcache_cache_only(rt5677->regmap, true);
4490 regcache_mark_dirty(rt5677->regmap);
4493 if (gpio_is_valid(rt5677->pow_ldo2))
4494 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4499 static int rt5677_resume(struct snd_soc_codec *codec)
4501 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4503 if (gpio_is_valid(rt5677->pow_ldo2)) {
4504 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4508 if (!rt5677->dsp_vad_en) {
4509 regcache_cache_only(rt5677->regmap, false);
4510 regcache_sync(rt5677->regmap);
4516 #define rt5677_suspend NULL
4517 #define rt5677_resume NULL
4520 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4522 struct i2c_client *client = context;
4523 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4525 if (rt5677->is_dsp_mode) {
4527 mutex_lock(&rt5677->dsp_pri_lock);
4528 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4530 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4531 mutex_unlock(&rt5677->dsp_pri_lock);
4533 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4536 regmap_read(rt5677->regmap_physical, reg, val);
4542 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4544 struct i2c_client *client = context;
4545 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4547 if (rt5677->is_dsp_mode) {
4549 mutex_lock(&rt5677->dsp_pri_lock);
4550 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4552 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4554 mutex_unlock(&rt5677->dsp_pri_lock);
4556 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4559 regmap_write(rt5677->regmap_physical, reg, val);
4565 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4566 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4567 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4569 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4570 .hw_params = rt5677_hw_params,
4571 .set_fmt = rt5677_set_dai_fmt,
4572 .set_sysclk = rt5677_set_dai_sysclk,
4573 .set_pll = rt5677_set_dai_pll,
4574 .set_tdm_slot = rt5677_set_tdm_slot,
4577 static struct snd_soc_dai_driver rt5677_dai[] = {
4579 .name = "rt5677-aif1",
4582 .stream_name = "AIF1 Playback",
4585 .rates = RT5677_STEREO_RATES,
4586 .formats = RT5677_FORMATS,
4589 .stream_name = "AIF1 Capture",
4592 .rates = RT5677_STEREO_RATES,
4593 .formats = RT5677_FORMATS,
4595 .ops = &rt5677_aif_dai_ops,
4598 .name = "rt5677-aif2",
4601 .stream_name = "AIF2 Playback",
4604 .rates = RT5677_STEREO_RATES,
4605 .formats = RT5677_FORMATS,
4608 .stream_name = "AIF2 Capture",
4611 .rates = RT5677_STEREO_RATES,
4612 .formats = RT5677_FORMATS,
4614 .ops = &rt5677_aif_dai_ops,
4617 .name = "rt5677-aif3",
4620 .stream_name = "AIF3 Playback",
4623 .rates = RT5677_STEREO_RATES,
4624 .formats = RT5677_FORMATS,
4627 .stream_name = "AIF3 Capture",
4630 .rates = RT5677_STEREO_RATES,
4631 .formats = RT5677_FORMATS,
4633 .ops = &rt5677_aif_dai_ops,
4636 .name = "rt5677-aif4",
4639 .stream_name = "AIF4 Playback",
4642 .rates = RT5677_STEREO_RATES,
4643 .formats = RT5677_FORMATS,
4646 .stream_name = "AIF4 Capture",
4649 .rates = RT5677_STEREO_RATES,
4650 .formats = RT5677_FORMATS,
4652 .ops = &rt5677_aif_dai_ops,
4655 .name = "rt5677-slimbus",
4658 .stream_name = "SLIMBus Playback",
4661 .rates = RT5677_STEREO_RATES,
4662 .formats = RT5677_FORMATS,
4665 .stream_name = "SLIMBus Capture",
4668 .rates = RT5677_STEREO_RATES,
4669 .formats = RT5677_FORMATS,
4671 .ops = &rt5677_aif_dai_ops,
4675 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4676 .probe = rt5677_probe,
4677 .remove = rt5677_remove,
4678 .suspend = rt5677_suspend,
4679 .resume = rt5677_resume,
4680 .set_bias_level = rt5677_set_bias_level,
4681 .idle_bias_off = true,
4682 .controls = rt5677_snd_controls,
4683 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4684 .dapm_widgets = rt5677_dapm_widgets,
4685 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4686 .dapm_routes = rt5677_dapm_routes,
4687 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4690 static const struct regmap_config rt5677_regmap_physical = {
4695 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4697 .readable_reg = rt5677_readable_register,
4699 .cache_type = REGCACHE_NONE,
4700 .ranges = rt5677_ranges,
4701 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4704 static const struct regmap_config rt5677_regmap = {
4708 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4711 .volatile_reg = rt5677_volatile_register,
4712 .readable_reg = rt5677_readable_register,
4713 .reg_read = rt5677_read,
4714 .reg_write = rt5677_write,
4716 .cache_type = REGCACHE_RBTREE,
4717 .reg_defaults = rt5677_reg,
4718 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4719 .ranges = rt5677_ranges,
4720 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4723 static const struct i2c_device_id rt5677_i2c_id[] = {
4727 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4729 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4731 rt5677->pdata.in1_diff = of_property_read_bool(np,
4732 "realtek,in1-differential");
4733 rt5677->pdata.in2_diff = of_property_read_bool(np,
4734 "realtek,in2-differential");
4735 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4736 "realtek,lout1-differential");
4737 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4738 "realtek,lout2-differential");
4739 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4740 "realtek,lout3-differential");
4742 rt5677->pow_ldo2 = of_get_named_gpio(np,
4743 "realtek,pow-ldo2-gpio", 0);
4746 * POW_LDO2 is optional (it may be statically tied on the board).
4747 * -ENOENT means that the property doesn't exist, i.e. there is no
4748 * GPIO, so is not an error. Any other error code means the property
4749 * exists, but could not be parsed.
4751 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4752 (rt5677->pow_ldo2 != -ENOENT))
4753 return rt5677->pow_ldo2;
4755 of_property_read_u8_array(np, "realtek,gpio-config",
4756 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4758 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4759 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4760 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4765 static struct regmap_irq rt5677_irqs[] = {
4766 [RT5677_IRQ_JD1] = {
4768 .mask = RT5677_EN_IRQ_GPIO_JD1,
4770 [RT5677_IRQ_JD2] = {
4772 .mask = RT5677_EN_IRQ_GPIO_JD2,
4774 [RT5677_IRQ_JD3] = {
4776 .mask = RT5677_EN_IRQ_GPIO_JD3,
4780 static struct regmap_irq_chip rt5677_irq_chip = {
4782 .irqs = rt5677_irqs,
4783 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4786 .status_base = RT5677_IRQ_CTRL1,
4787 .mask_base = RT5677_IRQ_CTRL1,
4791 static int rt5677_init_irq(struct i2c_client *i2c)
4794 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4796 if (!rt5677->pdata.jd1_gpio &&
4797 !rt5677->pdata.jd2_gpio &&
4798 !rt5677->pdata.jd3_gpio)
4802 dev_err(&i2c->dev, "No interrupt specified\n");
4806 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4807 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4808 &rt5677_irq_chip, &rt5677->irq_data);
4811 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
4818 static void rt5677_free_irq(struct i2c_client *i2c)
4820 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4822 if (rt5677->irq_data)
4823 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
4826 static int rt5677_i2c_probe(struct i2c_client *i2c,
4827 const struct i2c_device_id *id)
4829 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
4830 struct rt5677_priv *rt5677;
4834 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
4839 i2c_set_clientdata(i2c, rt5677);
4842 rt5677->pdata = *pdata;
4844 if (i2c->dev.of_node) {
4845 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
4847 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
4852 rt5677->pow_ldo2 = -EINVAL;
4855 if (gpio_is_valid(rt5677->pow_ldo2)) {
4856 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
4857 GPIOF_OUT_INIT_HIGH,
4860 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
4861 rt5677->pow_ldo2, ret);
4864 /* Wait a while until I2C bus becomes available. The datasheet
4865 * does not specify the exact we should wait but startup
4866 * sequence mentiones at least a few milliseconds.
4871 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
4872 &rt5677_regmap_physical);
4873 if (IS_ERR(rt5677->regmap_physical)) {
4874 ret = PTR_ERR(rt5677->regmap_physical);
4875 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4880 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
4881 if (IS_ERR(rt5677->regmap)) {
4882 ret = PTR_ERR(rt5677->regmap);
4883 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4888 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
4889 if (val != RT5677_DEVICE_ID) {
4891 "Device with ID register %x is not rt5677\n", val);
4895 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4897 ret = regmap_register_patch(rt5677->regmap, init_list,
4898 ARRAY_SIZE(init_list));
4900 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4902 if (rt5677->pdata.in1_diff)
4903 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4904 RT5677_IN_DF1, RT5677_IN_DF1);
4906 if (rt5677->pdata.in2_diff)
4907 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4908 RT5677_IN_DF2, RT5677_IN_DF2);
4910 if (rt5677->pdata.lout1_diff)
4911 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4912 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
4914 if (rt5677->pdata.lout2_diff)
4915 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4916 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
4918 if (rt5677->pdata.lout3_diff)
4919 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4920 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
4922 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4923 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
4924 RT5677_GPIO5_FUNC_MASK,
4925 RT5677_GPIO5_FUNC_DMIC);
4926 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4927 RT5677_GPIO5_DIR_MASK,
4928 RT5677_GPIO5_DIR_OUT);
4931 if (rt5677->pdata.micbias1_vdd_3v3)
4932 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
4933 RT5677_MICBIAS1_CTRL_VDD_MASK,
4934 RT5677_MICBIAS1_CTRL_VDD_3_3V);
4936 rt5677_init_gpio(i2c);
4937 rt5677_init_irq(i2c);
4939 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
4940 rt5677_dai, ARRAY_SIZE(rt5677_dai));
4943 static int rt5677_i2c_remove(struct i2c_client *i2c)
4945 snd_soc_unregister_codec(&i2c->dev);
4946 rt5677_free_irq(i2c);
4947 rt5677_free_gpio(i2c);
4952 static struct i2c_driver rt5677_i2c_driver = {
4955 .owner = THIS_MODULE,
4957 .probe = rt5677_i2c_probe,
4958 .remove = rt5677_i2c_remove,
4959 .id_table = rt5677_i2c_id,
4961 module_i2c_driver(rt5677_i2c_driver);
4963 MODULE_DESCRIPTION("ASoC RT5677 driver");
4964 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
4965 MODULE_LICENSE("GPL v2");