2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/of_gpio.h>
19 #include <linux/regmap.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/firmware.h>
24 #include <linux/gpio.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
35 #include "rt5677-spi.h"
37 #define RT5677_DEVICE_ID 0x6327
39 #define RT5677_PR_RANGE_BASE (0xff + 1)
40 #define RT5677_PR_SPACING 0x100
42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
44 static const struct regmap_range_cfg rt5677_ranges[] = {
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
57 static const struct reg_default init_list[] = {
58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
66 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
68 static const struct reg_default rt5677_reg[] = {
69 {RT5677_RESET , 0x0000},
70 {RT5677_LOUT1 , 0xa800},
71 {RT5677_IN1 , 0x0000},
72 {RT5677_MICBIAS , 0x0000},
73 {RT5677_SLIMBUS_PARAM , 0x0000},
74 {RT5677_SLIMBUS_RX , 0x0000},
75 {RT5677_SLIMBUS_CTRL , 0x0000},
76 {RT5677_SIDETONE_CTRL , 0x000b},
77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
79 {RT5677_DAC4_DIG_VOL , 0xafaf},
80 {RT5677_DAC3_DIG_VOL , 0xafaf},
81 {RT5677_DAC1_DIG_VOL , 0xafaf},
82 {RT5677_DAC2_DIG_VOL , 0xafaf},
83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO1_2_ADC_BST , 0x0000},
87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_ADC_BST_CTRL2 , 0x0000},
89 {RT5677_STO3_4_ADC_BST , 0x0000},
90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
92 {RT5677_STO4_ADC_MIXER , 0xd4c0},
93 {RT5677_STO3_ADC_MIXER , 0xd4c0},
94 {RT5677_STO2_ADC_MIXER , 0xd4c0},
95 {RT5677_STO1_ADC_MIXER , 0xd4c0},
96 {RT5677_MONO_ADC_MIXER , 0xd4d1},
97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
98 {RT5677_STO1_DAC_MIXER , 0xaaaa},
99 {RT5677_MONO_DAC_MIXER , 0xaaaa},
100 {RT5677_DD1_MIXER , 0xaaaa},
101 {RT5677_DD2_MIXER , 0xaaaa},
102 {RT5677_IF3_DATA , 0x0000},
103 {RT5677_IF4_DATA , 0x0000},
104 {RT5677_PDM_OUT_CTRL , 0x8888},
105 {RT5677_PDM_DATA_CTRL1 , 0x0000},
106 {RT5677_PDM_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
113 {RT5677_TDM1_CTRL1 , 0x0300},
114 {RT5677_TDM1_CTRL2 , 0x0000},
115 {RT5677_TDM1_CTRL3 , 0x4000},
116 {RT5677_TDM1_CTRL4 , 0x0123},
117 {RT5677_TDM1_CTRL5 , 0x4567},
118 {RT5677_TDM2_CTRL1 , 0x0300},
119 {RT5677_TDM2_CTRL2 , 0x0000},
120 {RT5677_TDM2_CTRL3 , 0x4000},
121 {RT5677_TDM2_CTRL4 , 0x0123},
122 {RT5677_TDM2_CTRL5 , 0x4567},
123 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
124 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
131 {RT5677_DMIC_CTRL1 , 0x1505},
132 {RT5677_DMIC_CTRL2 , 0x0055},
133 {RT5677_HAP_GENE_CTRL1 , 0x0111},
134 {RT5677_HAP_GENE_CTRL2 , 0x0064},
135 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL9 , 0xf000},
142 {RT5677_HAP_GENE_CTRL10 , 0x0000},
143 {RT5677_PWR_DIG1 , 0x0000},
144 {RT5677_PWR_DIG2 , 0x0000},
145 {RT5677_PWR_ANLG1 , 0x0055},
146 {RT5677_PWR_ANLG2 , 0x0000},
147 {RT5677_PWR_DSP1 , 0x0001},
148 {RT5677_PWR_DSP_ST , 0x0000},
149 {RT5677_PWR_DSP2 , 0x0000},
150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
151 {RT5677_PRIV_INDEX , 0x0000},
152 {RT5677_PRIV_DATA , 0x0000},
153 {RT5677_I2S4_SDP , 0x8000},
154 {RT5677_I2S1_SDP , 0x8000},
155 {RT5677_I2S2_SDP , 0x8000},
156 {RT5677_I2S3_SDP , 0x8000},
157 {RT5677_CLK_TREE_CTRL1 , 0x1111},
158 {RT5677_CLK_TREE_CTRL2 , 0x1111},
159 {RT5677_CLK_TREE_CTRL3 , 0x0000},
160 {RT5677_PLL1_CTRL1 , 0x0000},
161 {RT5677_PLL1_CTRL2 , 0x0000},
162 {RT5677_PLL2_CTRL1 , 0x0c60},
163 {RT5677_PLL2_CTRL2 , 0x2000},
164 {RT5677_GLB_CLK1 , 0x0000},
165 {RT5677_GLB_CLK2 , 0x0000},
166 {RT5677_ASRC_1 , 0x0000},
167 {RT5677_ASRC_2 , 0x0000},
168 {RT5677_ASRC_3 , 0x0000},
169 {RT5677_ASRC_4 , 0x0000},
170 {RT5677_ASRC_5 , 0x0000},
171 {RT5677_ASRC_6 , 0x0000},
172 {RT5677_ASRC_7 , 0x0000},
173 {RT5677_ASRC_8 , 0x0000},
174 {RT5677_ASRC_9 , 0x0000},
175 {RT5677_ASRC_10 , 0x0000},
176 {RT5677_ASRC_11 , 0x0000},
177 {RT5677_ASRC_12 , 0x0018},
178 {RT5677_ASRC_13 , 0x0000},
179 {RT5677_ASRC_14 , 0x0000},
180 {RT5677_ASRC_15 , 0x0000},
181 {RT5677_ASRC_16 , 0x0000},
182 {RT5677_ASRC_17 , 0x0000},
183 {RT5677_ASRC_18 , 0x0000},
184 {RT5677_ASRC_19 , 0x0000},
185 {RT5677_ASRC_20 , 0x0000},
186 {RT5677_ASRC_21 , 0x000c},
187 {RT5677_ASRC_22 , 0x0000},
188 {RT5677_ASRC_23 , 0x0000},
189 {RT5677_VAD_CTRL1 , 0x2184},
190 {RT5677_VAD_CTRL2 , 0x010a},
191 {RT5677_VAD_CTRL3 , 0x0aea},
192 {RT5677_VAD_CTRL4 , 0x000c},
193 {RT5677_VAD_CTRL5 , 0x0000},
194 {RT5677_DSP_INB_CTRL1 , 0x0000},
195 {RT5677_DSP_INB_CTRL2 , 0x0000},
196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
201 {RT5677_ADC_EQ_CTRL1 , 0x6000},
202 {RT5677_ADC_EQ_CTRL2 , 0x0000},
203 {RT5677_EQ_CTRL1 , 0xc000},
204 {RT5677_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL3 , 0x0000},
206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
207 {RT5677_JD_CTRL1 , 0x0000},
208 {RT5677_JD_CTRL2 , 0x0000},
209 {RT5677_JD_CTRL3 , 0x0000},
210 {RT5677_IRQ_CTRL1 , 0x0000},
211 {RT5677_IRQ_CTRL2 , 0x0000},
212 {RT5677_GPIO_ST , 0x0000},
213 {RT5677_GPIO_CTRL1 , 0x0000},
214 {RT5677_GPIO_CTRL2 , 0x0000},
215 {RT5677_GPIO_CTRL3 , 0x0000},
216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_MB_DRC_CTRL1 , 0x0f20},
227 {RT5677_DRC1_CTRL1 , 0x001f},
228 {RT5677_DRC1_CTRL2 , 0x020c},
229 {RT5677_DRC1_CTRL3 , 0x1f00},
230 {RT5677_DRC1_CTRL4 , 0x0000},
231 {RT5677_DRC1_CTRL5 , 0x0000},
232 {RT5677_DRC1_CTRL6 , 0x0029},
233 {RT5677_DRC2_CTRL1 , 0x001f},
234 {RT5677_DRC2_CTRL2 , 0x020c},
235 {RT5677_DRC2_CTRL3 , 0x1f00},
236 {RT5677_DRC2_CTRL4 , 0x0000},
237 {RT5677_DRC2_CTRL5 , 0x0000},
238 {RT5677_DRC2_CTRL6 , 0x0029},
239 {RT5677_DRC1_HL_CTRL1 , 0x8000},
240 {RT5677_DRC1_HL_CTRL2 , 0x0200},
241 {RT5677_DRC2_HL_CTRL1 , 0x8000},
242 {RT5677_DRC2_HL_CTRL2 , 0x0200},
243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
266 {RT5677_DIG_MISC , 0x0000},
267 {RT5677_GEN_CTRL1 , 0x0000},
268 {RT5677_GEN_CTRL2 , 0x0000},
269 {RT5677_VENDOR_ID , 0x0000},
270 {RT5677_VENDOR_ID1 , 0x10ec},
271 {RT5677_VENDOR_ID2 , 0x6327},
274 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
279 if (reg >= rt5677_ranges[i].range_min &&
280 reg <= rt5677_ranges[i].range_max) {
287 case RT5677_SLIMBUS_PARAM:
288 case RT5677_PDM_DATA_CTRL1:
289 case RT5677_PDM_DATA_CTRL2:
290 case RT5677_PDM1_DATA_CTRL4:
291 case RT5677_PDM2_DATA_CTRL4:
292 case RT5677_I2C_MASTER_CTRL1:
293 case RT5677_I2C_MASTER_CTRL7:
294 case RT5677_I2C_MASTER_CTRL8:
295 case RT5677_HAP_GENE_CTRL2:
296 case RT5677_PWR_DSP_ST:
297 case RT5677_PRIV_DATA:
298 case RT5677_PLL1_CTRL2:
299 case RT5677_PLL2_CTRL2:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
322 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
545 * @rt5677: Private Data.
546 * @addr: Address index.
547 * @value: Address data.
550 * Returns 0 for success or negative error code.
552 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
553 unsigned int addr, unsigned int value, unsigned int opcode)
555 struct snd_soc_codec *codec = rt5677->codec;
558 mutex_lock(&rt5677->dsp_cmd_lock);
560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
596 mutex_unlock(&rt5677->dsp_cmd_lock);
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
603 * rt5677: Private Data.
604 * @addr: Address index.
605 * @value: Address data.
608 * Returns 0 for success or negative error code.
610 static int rt5677_dsp_mode_i2c_read_addr(
611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
613 struct snd_soc_codec *codec = rt5677->codec;
615 unsigned int msb, lsb;
617 mutex_lock(&rt5677->dsp_cmd_lock);
619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
642 *value = (msb << 16) | lsb;
645 mutex_unlock(&rt5677->dsp_cmd_lock);
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
652 * rt5677: Private Data.
653 * @reg: Register index.
654 * @value: Register data.
657 * Returns 0 for success or negative error code.
659 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
660 unsigned int reg, unsigned int value)
662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
670 * @value: Register data.
673 * Returns 0 for success or negative error code.
675 static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
686 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
699 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
705 if (on && !activity) {
708 regcache_cache_only(rt5677->regmap, false);
709 regcache_cache_bypass(rt5677->regmap, true);
711 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
712 regmap_update_bits(rt5677->regmap,
713 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
714 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
715 RT5677_LDO1_SEL_MASK, 0x0);
716 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
717 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
718 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
719 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
720 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
721 RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK,
722 RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS);
723 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
724 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
725 rt5677_set_dsp_mode(codec, true);
727 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
730 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
731 release_firmware(rt5677->fw1);
734 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
737 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
738 release_firmware(rt5677->fw2);
741 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
743 regcache_cache_bypass(rt5677->regmap, false);
744 regcache_cache_only(rt5677->regmap, true);
745 } else if (!on && activity) {
748 regcache_cache_only(rt5677->regmap, false);
749 regcache_cache_bypass(rt5677->regmap, true);
751 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
752 rt5677_set_dsp_mode(codec, false);
753 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
755 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
757 regcache_cache_bypass(rt5677->regmap, false);
758 regcache_mark_dirty(rt5677->regmap);
759 regcache_sync(rt5677->regmap);
765 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
766 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
767 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
768 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
769 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
770 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
772 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
773 static unsigned int bst_tlv[] = {
774 TLV_DB_RANGE_HEAD(7),
775 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
776 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
777 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
778 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
779 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
780 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
781 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
784 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
785 struct snd_ctl_elem_value *ucontrol)
787 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
788 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
790 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
795 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
796 struct snd_ctl_elem_value *ucontrol)
798 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
799 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
800 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
802 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
804 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
805 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
810 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
812 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
813 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
814 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
815 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
816 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
817 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
819 /* DAC Digital Volume */
820 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
821 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
822 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
823 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
824 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
825 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
826 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
827 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
829 /* IN1/IN2 Control */
830 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
831 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
833 /* ADC Digital Volume Control */
834 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
835 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
836 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
837 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
838 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
839 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
840 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
841 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
842 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
843 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
845 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
846 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
848 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
849 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
851 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
852 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
854 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
855 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
857 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
858 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
861 /* Sidetone Control */
862 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
863 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
865 /* ADC Boost Volume Control */
866 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
867 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
869 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
870 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
872 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
873 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
875 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
876 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
878 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
879 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
882 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
883 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
887 * set_dmic_clk - Set parameter of dmic.
890 * @kcontrol: The kcontrol of this widget.
893 * Choose dmic clock between 1MHz and 3MHz.
894 * It is better for clock to approximate 3MHz.
896 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
897 struct snd_kcontrol *kcontrol, int event)
899 struct snd_soc_codec *codec = w->codec;
900 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
901 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
904 dev_err(codec->dev, "Failed to set DMIC clock\n");
906 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
907 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
911 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
912 struct snd_soc_dapm_widget *sink)
914 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
917 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
918 val &= RT5677_SCLK_SRC_MASK;
919 if (val == RT5677_SCLK_SRC_PLL1)
925 static int is_using_asrc(struct snd_soc_dapm_widget *source,
926 struct snd_soc_dapm_widget *sink)
928 unsigned int reg, shift, val;
930 if (source->reg == RT5677_ASRC_1) {
931 switch (source->shift) {
952 switch (source->shift) {
994 val = (snd_soc_read(source->codec, reg) >> shift) & 0xf;
1004 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1005 struct snd_soc_dapm_widget *sink)
1007 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1008 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1010 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1017 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1018 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1019 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1020 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1021 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1024 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1025 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1026 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1027 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1028 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1031 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1032 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1033 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1034 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1035 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1038 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1039 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1040 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1041 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1042 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1045 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1046 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1047 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1048 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1049 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1052 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1053 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1054 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1055 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1056 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1059 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1060 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1061 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1062 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1063 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1066 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1067 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1068 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1069 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1070 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1073 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1074 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1075 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1076 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1077 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1080 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1081 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1082 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1083 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1084 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1087 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1088 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1089 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1090 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1091 RT5677_M_DAC1_L_SFT, 1, 1),
1094 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1095 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1096 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1097 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1098 RT5677_M_DAC1_R_SFT, 1, 1),
1101 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1102 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1103 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1104 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1105 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1106 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1107 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1108 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1109 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1112 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1113 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1114 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1115 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1116 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1117 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1118 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1119 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1120 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1123 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1124 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1125 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1126 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1127 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1128 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1129 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1130 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1131 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1134 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1135 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1136 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1137 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1138 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1139 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1140 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1141 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1142 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1145 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1146 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1147 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1148 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1149 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1150 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1151 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1152 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1153 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1156 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1157 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1158 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1159 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1160 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1161 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1162 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1163 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1164 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1167 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1168 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1169 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1170 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1171 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1172 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1173 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1174 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1175 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1178 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1179 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1180 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1181 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1182 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1183 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1184 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1185 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1186 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1189 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1190 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1191 RT5677_DSP_IB_01_H_SFT, 1, 1),
1192 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1193 RT5677_DSP_IB_23_H_SFT, 1, 1),
1194 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1195 RT5677_DSP_IB_45_H_SFT, 1, 1),
1196 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1197 RT5677_DSP_IB_6_H_SFT, 1, 1),
1198 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1199 RT5677_DSP_IB_7_H_SFT, 1, 1),
1200 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1201 RT5677_DSP_IB_8_H_SFT, 1, 1),
1202 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1203 RT5677_DSP_IB_9_H_SFT, 1, 1),
1206 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1207 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1208 RT5677_DSP_IB_01_L_SFT, 1, 1),
1209 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1210 RT5677_DSP_IB_23_L_SFT, 1, 1),
1211 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1212 RT5677_DSP_IB_45_L_SFT, 1, 1),
1213 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1214 RT5677_DSP_IB_6_L_SFT, 1, 1),
1215 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1216 RT5677_DSP_IB_7_L_SFT, 1, 1),
1217 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1218 RT5677_DSP_IB_8_L_SFT, 1, 1),
1219 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1220 RT5677_DSP_IB_9_L_SFT, 1, 1),
1223 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1224 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1225 RT5677_DSP_IB_01_H_SFT, 1, 1),
1226 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1227 RT5677_DSP_IB_23_H_SFT, 1, 1),
1228 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1229 RT5677_DSP_IB_45_H_SFT, 1, 1),
1230 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1231 RT5677_DSP_IB_6_H_SFT, 1, 1),
1232 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1233 RT5677_DSP_IB_7_H_SFT, 1, 1),
1234 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1235 RT5677_DSP_IB_8_H_SFT, 1, 1),
1236 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1237 RT5677_DSP_IB_9_H_SFT, 1, 1),
1240 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1241 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1242 RT5677_DSP_IB_01_L_SFT, 1, 1),
1243 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1244 RT5677_DSP_IB_23_L_SFT, 1, 1),
1245 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1246 RT5677_DSP_IB_45_L_SFT, 1, 1),
1247 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1248 RT5677_DSP_IB_6_L_SFT, 1, 1),
1249 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1250 RT5677_DSP_IB_7_L_SFT, 1, 1),
1251 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1252 RT5677_DSP_IB_8_L_SFT, 1, 1),
1253 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1254 RT5677_DSP_IB_9_L_SFT, 1, 1),
1257 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1258 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1259 RT5677_DSP_IB_01_H_SFT, 1, 1),
1260 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1261 RT5677_DSP_IB_23_H_SFT, 1, 1),
1262 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1263 RT5677_DSP_IB_45_H_SFT, 1, 1),
1264 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1265 RT5677_DSP_IB_6_H_SFT, 1, 1),
1266 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1267 RT5677_DSP_IB_7_H_SFT, 1, 1),
1268 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1269 RT5677_DSP_IB_8_H_SFT, 1, 1),
1270 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1271 RT5677_DSP_IB_9_H_SFT, 1, 1),
1274 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1275 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1276 RT5677_DSP_IB_01_L_SFT, 1, 1),
1277 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1278 RT5677_DSP_IB_23_L_SFT, 1, 1),
1279 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1280 RT5677_DSP_IB_45_L_SFT, 1, 1),
1281 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1282 RT5677_DSP_IB_6_L_SFT, 1, 1),
1283 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1284 RT5677_DSP_IB_7_L_SFT, 1, 1),
1285 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1286 RT5677_DSP_IB_8_L_SFT, 1, 1),
1287 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1288 RT5677_DSP_IB_9_L_SFT, 1, 1),
1293 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1294 static const char * const rt5677_dac1_src[] = {
1295 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1299 static SOC_ENUM_SINGLE_DECL(
1300 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1301 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1303 static const struct snd_kcontrol_new rt5677_dac1_mux =
1304 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1306 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1307 static const char * const rt5677_adda1_src[] = {
1308 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1311 static SOC_ENUM_SINGLE_DECL(
1312 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1313 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1315 static const struct snd_kcontrol_new rt5677_adda1_mux =
1316 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1319 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1320 static const char * const rt5677_dac2l_src[] = {
1321 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1325 static SOC_ENUM_SINGLE_DECL(
1326 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1327 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1329 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1330 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1332 static const char * const rt5677_dac2r_src[] = {
1333 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1334 "OB 3", "Haptic Generator", "VAD ADC"
1337 static SOC_ENUM_SINGLE_DECL(
1338 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1339 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1341 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1342 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1344 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1345 static const char * const rt5677_dac3l_src[] = {
1346 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1350 static SOC_ENUM_SINGLE_DECL(
1351 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1352 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1354 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1355 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1357 static const char * const rt5677_dac3r_src[] = {
1358 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1362 static SOC_ENUM_SINGLE_DECL(
1363 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1364 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1366 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1367 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1369 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1370 static const char * const rt5677_dac4l_src[] = {
1371 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1375 static SOC_ENUM_SINGLE_DECL(
1376 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1377 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1379 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1380 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1382 static const char * const rt5677_dac4r_src[] = {
1383 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1387 static SOC_ENUM_SINGLE_DECL(
1388 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1389 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1391 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1392 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1394 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1395 static const char * const rt5677_iob_bypass_src[] = {
1396 "Bypass", "Pass SRC"
1399 static SOC_ENUM_SINGLE_DECL(
1400 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1401 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1403 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1404 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1406 static SOC_ENUM_SINGLE_DECL(
1407 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1408 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1410 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1411 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1413 static SOC_ENUM_SINGLE_DECL(
1414 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1415 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1417 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1418 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1420 static SOC_ENUM_SINGLE_DECL(
1421 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1422 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1424 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1425 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1427 static SOC_ENUM_SINGLE_DECL(
1428 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1429 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1431 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1432 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1434 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1435 static const char * const rt5677_stereo_adc2_src[] = {
1436 "DD MIX1", "DMIC", "Stereo DAC MIX"
1439 static SOC_ENUM_SINGLE_DECL(
1440 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1441 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1443 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1444 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1446 static SOC_ENUM_SINGLE_DECL(
1447 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1448 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1450 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1451 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1453 static SOC_ENUM_SINGLE_DECL(
1454 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1455 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1457 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1458 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1460 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1461 static const char * const rt5677_dmic_src[] = {
1462 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1465 static SOC_ENUM_SINGLE_DECL(
1466 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1467 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1469 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1470 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1472 static SOC_ENUM_SINGLE_DECL(
1473 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1474 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1476 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1477 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1479 static SOC_ENUM_SINGLE_DECL(
1480 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1481 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1483 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1484 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1486 static SOC_ENUM_SINGLE_DECL(
1487 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1488 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1490 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1491 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1493 static SOC_ENUM_SINGLE_DECL(
1494 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1495 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1497 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1498 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1500 static SOC_ENUM_SINGLE_DECL(
1501 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1502 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1504 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1505 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1507 /* Stereo2 ADC Source */ /* MX-26 [0] */
1508 static const char * const rt5677_stereo2_adc_lr_src[] = {
1512 static SOC_ENUM_SINGLE_DECL(
1513 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1514 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1516 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1517 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1519 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1520 static const char * const rt5677_stereo_adc1_src[] = {
1521 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1524 static SOC_ENUM_SINGLE_DECL(
1525 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1526 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1528 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1529 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1531 static SOC_ENUM_SINGLE_DECL(
1532 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1533 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1535 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1536 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1538 static SOC_ENUM_SINGLE_DECL(
1539 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1540 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1542 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1543 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1545 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1546 static const char * const rt5677_mono_adc2_l_src[] = {
1547 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1550 static SOC_ENUM_SINGLE_DECL(
1551 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1552 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1554 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1555 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1557 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1558 static const char * const rt5677_mono_adc1_l_src[] = {
1559 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1562 static SOC_ENUM_SINGLE_DECL(
1563 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1564 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1566 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1567 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1569 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1570 static const char * const rt5677_mono_adc2_r_src[] = {
1571 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1574 static SOC_ENUM_SINGLE_DECL(
1575 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1576 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1578 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1579 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1581 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1582 static const char * const rt5677_mono_adc1_r_src[] = {
1583 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1586 static SOC_ENUM_SINGLE_DECL(
1587 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1588 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1590 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1591 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1593 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1594 static const char * const rt5677_stereo4_adc2_src[] = {
1595 "DD MIX1", "DMIC", "DD MIX2"
1598 static SOC_ENUM_SINGLE_DECL(
1599 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1600 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1602 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1603 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1606 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1607 static const char * const rt5677_stereo4_adc1_src[] = {
1608 "DD MIX1", "ADC1/2", "DD MIX2"
1611 static SOC_ENUM_SINGLE_DECL(
1612 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1613 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1615 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1616 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1618 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1619 static const char * const rt5677_inbound01_src[] = {
1620 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1624 static SOC_ENUM_SINGLE_DECL(
1625 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1626 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1628 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1629 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1631 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1632 static const char * const rt5677_inbound23_src[] = {
1633 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1634 "DAC1 FS", "IF4 DAC"
1637 static SOC_ENUM_SINGLE_DECL(
1638 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1639 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1641 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1642 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1644 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1645 static const char * const rt5677_inbound45_src[] = {
1646 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1650 static SOC_ENUM_SINGLE_DECL(
1651 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1652 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1654 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1655 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1657 /* InBound6 Source */ /* MX-A3 [2:0] */
1658 static const char * const rt5677_inbound6_src[] = {
1659 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1660 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1663 static SOC_ENUM_SINGLE_DECL(
1664 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1665 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1667 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1668 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1670 /* InBound7 Source */ /* MX-A4 [14:12] */
1671 static const char * const rt5677_inbound7_src[] = {
1672 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1673 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1676 static SOC_ENUM_SINGLE_DECL(
1677 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1678 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1680 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1681 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1683 /* InBound8 Source */ /* MX-A4 [10:8] */
1684 static const char * const rt5677_inbound8_src[] = {
1685 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1686 "MONO ADC MIX L", "DACL1 FS"
1689 static SOC_ENUM_SINGLE_DECL(
1690 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1691 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1693 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1694 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1696 /* InBound9 Source */ /* MX-A4 [6:4] */
1697 static const char * const rt5677_inbound9_src[] = {
1698 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1699 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1702 static SOC_ENUM_SINGLE_DECL(
1703 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1704 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1706 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1707 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1709 /* VAD Source */ /* MX-9F [6:4] */
1710 static const char * const rt5677_vad_src[] = {
1711 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1715 static SOC_ENUM_SINGLE_DECL(
1716 rt5677_vad_enum, RT5677_VAD_CTRL4,
1717 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1719 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1720 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1722 /* Sidetone Source */ /* MX-13 [11:9] */
1723 static const char * const rt5677_sidetone_src[] = {
1724 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1727 static SOC_ENUM_SINGLE_DECL(
1728 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1729 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1731 static const struct snd_kcontrol_new rt5677_sidetone_mux =
1732 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1734 /* DAC1/2 Source */ /* MX-15 [1:0] */
1735 static const char * const rt5677_dac12_src[] = {
1736 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1739 static SOC_ENUM_SINGLE_DECL(
1740 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1741 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1743 static const struct snd_kcontrol_new rt5677_dac12_mux =
1744 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1746 /* DAC3 Source */ /* MX-15 [5:4] */
1747 static const char * const rt5677_dac3_src[] = {
1748 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1751 static SOC_ENUM_SINGLE_DECL(
1752 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1753 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1755 static const struct snd_kcontrol_new rt5677_dac3_mux =
1756 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1758 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1759 static const char * const rt5677_pdm_src[] = {
1760 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1763 static SOC_ENUM_SINGLE_DECL(
1764 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1765 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1767 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1768 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
1770 static SOC_ENUM_SINGLE_DECL(
1771 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1772 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1774 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1775 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
1777 static SOC_ENUM_SINGLE_DECL(
1778 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1779 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1781 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1782 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
1784 static SOC_ENUM_SINGLE_DECL(
1785 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1786 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1788 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1789 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1791 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
1792 static const char * const rt5677_if12_adc1_src[] = {
1793 "STO1 ADC MIX", "OB01", "VAD ADC"
1796 static SOC_ENUM_SINGLE_DECL(
1797 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1798 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1800 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1801 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
1803 static SOC_ENUM_SINGLE_DECL(
1804 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1805 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1807 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1808 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
1810 static SOC_ENUM_SINGLE_DECL(
1811 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1812 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1814 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1815 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
1817 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1818 static const char * const rt5677_if12_adc2_src[] = {
1819 "STO2 ADC MIX", "OB23"
1822 static SOC_ENUM_SINGLE_DECL(
1823 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1824 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1826 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1827 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
1829 static SOC_ENUM_SINGLE_DECL(
1830 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1831 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1833 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1834 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
1836 static SOC_ENUM_SINGLE_DECL(
1837 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1838 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1840 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1841 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
1843 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1844 static const char * const rt5677_if12_adc3_src[] = {
1845 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1848 static SOC_ENUM_SINGLE_DECL(
1849 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1850 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1852 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1853 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
1855 static SOC_ENUM_SINGLE_DECL(
1856 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1857 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1859 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1860 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
1862 static SOC_ENUM_SINGLE_DECL(
1863 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1864 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1866 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1867 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
1869 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1870 static const char * const rt5677_if12_adc4_src[] = {
1871 "STO4 ADC MIX", "OB67", "OB01"
1874 static SOC_ENUM_SINGLE_DECL(
1875 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1876 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1878 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1879 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
1881 static SOC_ENUM_SINGLE_DECL(
1882 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1883 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1885 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1886 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
1888 static SOC_ENUM_SINGLE_DECL(
1889 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1890 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1892 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1893 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
1895 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
1896 static const char * const rt5677_if34_adc_src[] = {
1897 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1898 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1901 static SOC_ENUM_SINGLE_DECL(
1902 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1903 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1905 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1906 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
1908 static SOC_ENUM_SINGLE_DECL(
1909 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1910 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1912 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1913 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
1915 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
1916 static const char * const rt5677_if12_adc_swap_src[] = {
1917 "L/R", "R/L", "L/L", "R/R"
1920 static SOC_ENUM_SINGLE_DECL(
1921 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
1922 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
1924 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
1925 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
1927 static SOC_ENUM_SINGLE_DECL(
1928 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
1929 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1931 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
1932 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
1934 static SOC_ENUM_SINGLE_DECL(
1935 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
1936 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1938 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
1939 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
1941 static SOC_ENUM_SINGLE_DECL(
1942 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
1943 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1945 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
1946 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
1948 static SOC_ENUM_SINGLE_DECL(
1949 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
1950 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1952 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
1953 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
1955 static SOC_ENUM_SINGLE_DECL(
1956 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
1957 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1959 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
1960 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
1962 static SOC_ENUM_SINGLE_DECL(
1963 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
1964 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1966 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
1967 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
1969 static SOC_ENUM_SINGLE_DECL(
1970 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
1971 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1973 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
1974 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
1976 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
1977 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
1978 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1979 "3/1/2/4", "3/4/1/2"
1982 static SOC_ENUM_SINGLE_DECL(
1983 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
1984 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
1986 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
1987 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
1989 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
1990 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
1991 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1992 "2/3/1/4", "3/4/1/2"
1995 static SOC_ENUM_SINGLE_DECL(
1996 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
1997 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
1999 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2000 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2002 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2003 MX-3F[14:12][10:8][6:4][2:0]
2004 MX-43[14:12][10:8][6:4][2:0]
2005 MX-44[14:12][10:8][6:4][2:0] */
2006 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2007 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2010 static SOC_ENUM_SINGLE_DECL(
2011 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2012 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2014 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2015 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2017 static SOC_ENUM_SINGLE_DECL(
2018 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2019 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2021 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2022 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2024 static SOC_ENUM_SINGLE_DECL(
2025 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2026 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2028 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2029 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2031 static SOC_ENUM_SINGLE_DECL(
2032 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2033 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2035 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2036 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2038 static SOC_ENUM_SINGLE_DECL(
2039 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2040 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2042 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2043 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2045 static SOC_ENUM_SINGLE_DECL(
2046 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2047 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2049 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2050 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2052 static SOC_ENUM_SINGLE_DECL(
2053 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2054 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2056 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2057 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2059 static SOC_ENUM_SINGLE_DECL(
2060 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2061 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2063 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2064 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2066 static SOC_ENUM_SINGLE_DECL(
2067 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2068 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2070 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2071 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2073 static SOC_ENUM_SINGLE_DECL(
2074 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2075 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2077 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2078 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2080 static SOC_ENUM_SINGLE_DECL(
2081 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2082 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2084 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2085 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2087 static SOC_ENUM_SINGLE_DECL(
2088 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2089 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2091 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2092 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2094 static SOC_ENUM_SINGLE_DECL(
2095 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2096 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2098 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2099 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2101 static SOC_ENUM_SINGLE_DECL(
2102 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2103 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2105 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2106 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2108 static SOC_ENUM_SINGLE_DECL(
2109 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2110 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2112 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2113 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2115 static SOC_ENUM_SINGLE_DECL(
2116 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2117 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2119 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2120 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2122 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2123 struct snd_kcontrol *kcontrol, int event)
2125 struct snd_soc_codec *codec = w->codec;
2126 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2129 case SND_SOC_DAPM_POST_PMU:
2130 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2131 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2134 case SND_SOC_DAPM_PRE_PMD:
2135 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2136 RT5677_PWR_BST1_P, 0);
2146 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2147 struct snd_kcontrol *kcontrol, int event)
2149 struct snd_soc_codec *codec = w->codec;
2150 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2153 case SND_SOC_DAPM_POST_PMU:
2154 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2155 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2158 case SND_SOC_DAPM_PRE_PMD:
2159 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2160 RT5677_PWR_BST2_P, 0);
2170 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2171 struct snd_kcontrol *kcontrol, int event)
2173 struct snd_soc_codec *codec = w->codec;
2174 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2177 case SND_SOC_DAPM_POST_PMU:
2178 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2179 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2188 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2189 struct snd_kcontrol *kcontrol, int event)
2191 struct snd_soc_codec *codec = w->codec;
2192 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2195 case SND_SOC_DAPM_POST_PMU:
2196 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2197 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2206 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2207 struct snd_kcontrol *kcontrol, int event)
2209 struct snd_soc_codec *codec = w->codec;
2210 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2213 case SND_SOC_DAPM_POST_PMU:
2214 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2215 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2216 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2217 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2220 case SND_SOC_DAPM_PRE_PMD:
2221 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2222 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2223 RT5677_PWR_CLK_MB, 0);
2233 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2234 struct snd_kcontrol *kcontrol, int event)
2236 struct snd_soc_codec *codec = w->codec;
2237 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2241 case SND_SOC_DAPM_PRE_PMU:
2242 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2243 if (value & RT5677_IF1_ADC_CTRL_MASK)
2244 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2245 RT5677_IF1_ADC_MODE_MASK,
2246 RT5677_IF1_ADC_MODE_TDM);
2256 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2257 struct snd_kcontrol *kcontrol, int event)
2259 struct snd_soc_codec *codec = w->codec;
2260 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2264 case SND_SOC_DAPM_PRE_PMU:
2265 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2266 if (value & RT5677_IF2_ADC_CTRL_MASK)
2267 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2268 RT5677_IF2_ADC_MODE_MASK,
2269 RT5677_IF2_ADC_MODE_TDM);
2279 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2280 struct snd_kcontrol *kcontrol, int event)
2282 struct snd_soc_codec *codec = w->codec;
2283 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2286 case SND_SOC_DAPM_POST_PMU:
2287 if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2288 !rt5677->is_vref_slow) {
2290 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2291 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2292 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2293 rt5677->is_vref_slow = true;
2304 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2305 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2306 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
2307 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2308 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
2311 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2312 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2313 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2314 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2315 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2316 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2318 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2320 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2322 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2324 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2326 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2328 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2330 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2332 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2334 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2336 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2338 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2340 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2341 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2342 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2343 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2344 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2346 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2351 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2352 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2353 SND_SOC_DAPM_POST_PMU),
2356 SND_SOC_DAPM_INPUT("DMIC L1"),
2357 SND_SOC_DAPM_INPUT("DMIC R1"),
2358 SND_SOC_DAPM_INPUT("DMIC L2"),
2359 SND_SOC_DAPM_INPUT("DMIC R2"),
2360 SND_SOC_DAPM_INPUT("DMIC L3"),
2361 SND_SOC_DAPM_INPUT("DMIC R3"),
2362 SND_SOC_DAPM_INPUT("DMIC L4"),
2363 SND_SOC_DAPM_INPUT("DMIC R4"),
2365 SND_SOC_DAPM_INPUT("IN1P"),
2366 SND_SOC_DAPM_INPUT("IN1N"),
2367 SND_SOC_DAPM_INPUT("IN2P"),
2368 SND_SOC_DAPM_INPUT("IN2N"),
2370 SND_SOC_DAPM_INPUT("Haptic Generator"),
2372 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2373 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2374 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2375 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2377 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2378 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2379 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2380 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2381 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2382 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2383 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2384 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2386 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2387 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2390 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2391 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2392 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2393 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2394 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2395 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2398 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2400 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2402 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2404 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2405 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2406 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2407 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2408 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2409 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2410 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2411 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2414 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2415 &rt5677_sto1_dmic_mux),
2416 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2417 &rt5677_sto1_adc1_mux),
2418 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2419 &rt5677_sto1_adc2_mux),
2420 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2421 &rt5677_sto2_dmic_mux),
2422 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2423 &rt5677_sto2_adc1_mux),
2424 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2425 &rt5677_sto2_adc2_mux),
2426 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2427 &rt5677_sto2_adc_lr_mux),
2428 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2429 &rt5677_sto3_dmic_mux),
2430 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2431 &rt5677_sto3_adc1_mux),
2432 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2433 &rt5677_sto3_adc2_mux),
2434 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2435 &rt5677_sto4_dmic_mux),
2436 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2437 &rt5677_sto4_adc1_mux),
2438 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2439 &rt5677_sto4_adc2_mux),
2440 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2441 &rt5677_mono_dmic_l_mux),
2442 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2443 &rt5677_mono_dmic_r_mux),
2444 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2445 &rt5677_mono_adc2_l_mux),
2446 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2447 &rt5677_mono_adc1_l_mux),
2448 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2449 &rt5677_mono_adc1_r_mux),
2450 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2451 &rt5677_mono_adc2_r_mux),
2454 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2455 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2456 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2457 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2458 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2459 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2460 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2461 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2462 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2463 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2464 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2465 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2466 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2467 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2468 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2469 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2470 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2471 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2472 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2473 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2474 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2475 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2476 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2477 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2478 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2479 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2480 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2481 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2482 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2483 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2484 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2485 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2488 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2489 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2490 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2491 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2492 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2493 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2494 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2495 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2496 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2497 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2498 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2499 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2500 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2501 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2502 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2503 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2506 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2507 &rt5677_ib9_src_mux),
2508 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2509 &rt5677_ib8_src_mux),
2510 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2511 &rt5677_ib7_src_mux),
2512 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2513 &rt5677_ib6_src_mux),
2514 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2515 &rt5677_ib45_src_mux),
2516 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2517 &rt5677_ib23_src_mux),
2518 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2519 &rt5677_ib01_src_mux),
2520 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2521 &rt5677_ib45_bypass_src_mux),
2522 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2523 &rt5677_ib23_bypass_src_mux),
2524 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2525 &rt5677_ib01_bypass_src_mux),
2526 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2527 &rt5677_ob23_bypass_src_mux),
2528 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2529 &rt5677_ob01_bypass_src_mux),
2531 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2532 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2534 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2535 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2536 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2537 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2538 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2539 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2541 /* Digital Interface */
2542 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2543 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2544 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2545 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2546 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2547 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2548 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2549 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2550 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2551 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2552 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2553 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2554 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2555 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2556 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2557 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2558 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2559 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2561 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2562 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2563 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2564 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2565 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2566 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2567 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2568 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2569 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2570 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2571 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2572 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2573 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2574 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2575 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2576 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2577 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2578 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2580 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2581 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2582 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2583 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2584 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2585 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2586 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2587 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2589 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2590 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2591 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2592 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2593 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2594 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2595 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2596 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2598 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2599 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2600 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2601 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2602 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2603 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2604 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2605 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2606 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2607 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2608 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2609 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2610 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2611 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2612 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2613 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2614 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2615 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2617 /* Digital Interface Select */
2618 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2619 &rt5677_if1_adc1_mux),
2620 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2621 &rt5677_if1_adc2_mux),
2622 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2623 &rt5677_if1_adc3_mux),
2624 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2625 &rt5677_if1_adc4_mux),
2626 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2627 &rt5677_if1_adc1_swap_mux),
2628 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2629 &rt5677_if1_adc2_swap_mux),
2630 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2631 &rt5677_if1_adc3_swap_mux),
2632 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2633 &rt5677_if1_adc4_swap_mux),
2634 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2635 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2636 SND_SOC_DAPM_PRE_PMU),
2637 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2638 &rt5677_if2_adc1_mux),
2639 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2640 &rt5677_if2_adc2_mux),
2641 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2642 &rt5677_if2_adc3_mux),
2643 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2644 &rt5677_if2_adc4_mux),
2645 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2646 &rt5677_if2_adc1_swap_mux),
2647 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2648 &rt5677_if2_adc2_swap_mux),
2649 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2650 &rt5677_if2_adc3_swap_mux),
2651 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2652 &rt5677_if2_adc4_swap_mux),
2653 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2654 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2655 SND_SOC_DAPM_PRE_PMU),
2656 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2657 &rt5677_if3_adc_mux),
2658 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2659 &rt5677_if4_adc_mux),
2660 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2661 &rt5677_slb_adc1_mux),
2662 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2663 &rt5677_slb_adc2_mux),
2664 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2665 &rt5677_slb_adc3_mux),
2666 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2667 &rt5677_slb_adc4_mux),
2669 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2670 &rt5677_if1_dac0_tdm_sel_mux),
2671 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2672 &rt5677_if1_dac1_tdm_sel_mux),
2673 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2674 &rt5677_if1_dac2_tdm_sel_mux),
2675 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2676 &rt5677_if1_dac3_tdm_sel_mux),
2677 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2678 &rt5677_if1_dac4_tdm_sel_mux),
2679 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2680 &rt5677_if1_dac5_tdm_sel_mux),
2681 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2682 &rt5677_if1_dac6_tdm_sel_mux),
2683 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2684 &rt5677_if1_dac7_tdm_sel_mux),
2686 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2687 &rt5677_if2_dac0_tdm_sel_mux),
2688 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2689 &rt5677_if2_dac1_tdm_sel_mux),
2690 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2691 &rt5677_if2_dac2_tdm_sel_mux),
2692 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2693 &rt5677_if2_dac3_tdm_sel_mux),
2694 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2695 &rt5677_if2_dac4_tdm_sel_mux),
2696 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2697 &rt5677_if2_dac5_tdm_sel_mux),
2698 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2699 &rt5677_if2_dac6_tdm_sel_mux),
2700 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2701 &rt5677_if2_dac7_tdm_sel_mux),
2703 /* Audio Interface */
2704 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2705 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2706 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2707 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2708 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2709 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2710 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2711 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2712 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2713 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2716 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2717 &rt5677_sidetone_mux),
2718 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2719 RT5677_ST_EN_SFT, 0, NULL, 0),
2722 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2723 &rt5677_vad_src_mux),
2726 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2727 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2728 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2729 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2730 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2731 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2732 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2733 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2734 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2735 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2736 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2737 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2738 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2741 /* DAC mixer before sound effect */
2742 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2743 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2744 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2745 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2746 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2749 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2751 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2753 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2755 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2758 /* DAC2 channel Mux */
2759 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2760 &rt5677_dac2_l_mux),
2761 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2762 &rt5677_dac2_r_mux),
2764 /* DAC3 channel Mux */
2765 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2766 &rt5677_dac3_l_mux),
2767 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2768 &rt5677_dac3_r_mux),
2770 /* DAC4 channel Mux */
2771 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2772 &rt5677_dac4_l_mux),
2773 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2774 &rt5677_dac4_r_mux),
2777 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2778 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2779 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
2780 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2781 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
2782 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2783 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
2784 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
2785 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
2786 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
2787 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
2788 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
2789 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
2790 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
2792 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2793 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2794 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2795 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2796 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2797 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2798 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2799 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2800 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2801 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2802 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2803 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2804 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2805 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2806 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2807 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2808 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2809 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2810 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2811 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2814 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2815 RT5677_PWR_DAC1_BIT, 0),
2816 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2817 RT5677_PWR_DAC2_BIT, 0),
2818 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2819 RT5677_PWR_DAC3_BIT, 0),
2822 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2823 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2824 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2825 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2827 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2828 1, &rt5677_pdm1_l_mux),
2829 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2830 1, &rt5677_pdm1_r_mux),
2831 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2832 1, &rt5677_pdm2_l_mux),
2833 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2834 1, &rt5677_pdm2_r_mux),
2836 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2838 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2840 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2843 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
2844 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2845 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
2846 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2847 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
2848 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2851 SND_SOC_DAPM_OUTPUT("LOUT1"),
2852 SND_SOC_DAPM_OUTPUT("LOUT2"),
2853 SND_SOC_DAPM_OUTPUT("LOUT3"),
2854 SND_SOC_DAPM_OUTPUT("PDM1L"),
2855 SND_SOC_DAPM_OUTPUT("PDM1R"),
2856 SND_SOC_DAPM_OUTPUT("PDM2L"),
2857 SND_SOC_DAPM_OUTPUT("PDM2R"),
2859 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
2862 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2863 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
2864 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
2865 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", can_use_asrc },
2866 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", can_use_asrc },
2867 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
2868 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
2869 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
2870 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
2871 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
2872 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
2874 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2875 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
2876 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
2877 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
2878 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
2879 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
2880 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
2881 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2882 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
2883 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
2884 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
2885 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2886 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2888 { "DMIC1", NULL, "DMIC L1" },
2889 { "DMIC1", NULL, "DMIC R1" },
2890 { "DMIC2", NULL, "DMIC L2" },
2891 { "DMIC2", NULL, "DMIC R2" },
2892 { "DMIC3", NULL, "DMIC L3" },
2893 { "DMIC3", NULL, "DMIC R3" },
2894 { "DMIC4", NULL, "DMIC L4" },
2895 { "DMIC4", NULL, "DMIC R4" },
2897 { "DMIC L1", NULL, "DMIC CLK" },
2898 { "DMIC R1", NULL, "DMIC CLK" },
2899 { "DMIC L2", NULL, "DMIC CLK" },
2900 { "DMIC R2", NULL, "DMIC CLK" },
2901 { "DMIC L3", NULL, "DMIC CLK" },
2902 { "DMIC R3", NULL, "DMIC CLK" },
2903 { "DMIC L4", NULL, "DMIC CLK" },
2904 { "DMIC R4", NULL, "DMIC CLK" },
2906 { "DMIC L1", NULL, "DMIC1 power" },
2907 { "DMIC R1", NULL, "DMIC1 power" },
2908 { "DMIC L3", NULL, "DMIC3 power" },
2909 { "DMIC R3", NULL, "DMIC3 power" },
2910 { "DMIC L4", NULL, "DMIC4 power" },
2911 { "DMIC R4", NULL, "DMIC4 power" },
2913 { "BST1", NULL, "IN1P" },
2914 { "BST1", NULL, "IN1N" },
2915 { "BST2", NULL, "IN2P" },
2916 { "BST2", NULL, "IN2N" },
2918 { "IN1P", NULL, "MICBIAS1" },
2919 { "IN1N", NULL, "MICBIAS1" },
2920 { "IN2P", NULL, "MICBIAS1" },
2921 { "IN2N", NULL, "MICBIAS1" },
2923 { "ADC 1", NULL, "BST1" },
2924 { "ADC 1", NULL, "ADC 1 power" },
2925 { "ADC 1", NULL, "ADC1 clock" },
2926 { "ADC 2", NULL, "BST2" },
2927 { "ADC 2", NULL, "ADC 2 power" },
2928 { "ADC 2", NULL, "ADC2 clock" },
2930 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2931 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2932 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2933 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2935 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2936 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2937 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2938 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2940 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2941 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2942 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2943 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2945 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2946 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2947 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2948 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2950 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2951 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2952 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2953 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2955 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2956 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2957 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2958 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2960 { "ADC 1_2", NULL, "ADC 1" },
2961 { "ADC 1_2", NULL, "ADC 2" },
2963 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2964 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2965 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2967 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2968 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2969 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2971 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2972 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2973 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2975 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2976 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2977 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2979 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2980 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2981 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2983 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2984 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2985 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2987 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2988 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2989 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2991 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2992 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2993 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2995 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2996 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2997 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2999 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3000 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3001 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3003 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3004 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3005 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3007 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3008 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3009 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3011 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3012 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3013 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3014 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3016 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3017 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3018 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3019 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3020 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3022 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3023 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3025 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3026 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3027 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3028 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3030 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3031 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3033 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3034 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3036 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3037 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3038 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3039 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3040 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3042 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3043 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3045 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3046 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3047 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3048 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3050 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3051 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3052 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3053 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3054 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3056 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3057 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3059 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3060 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3061 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3062 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3064 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3065 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3066 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3067 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3068 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3070 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3071 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3073 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3074 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3075 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3076 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3078 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3079 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3080 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3081 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3083 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3084 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3086 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3087 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3088 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3089 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3090 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3092 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3093 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3094 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3096 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3097 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3099 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3100 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3101 { "IF1 ADC3 Mux", "OB45", "OB45" },
3103 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3104 { "IF1 ADC4 Mux", "OB67", "OB67" },
3105 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3107 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3108 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3109 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3110 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3112 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3113 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3114 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3115 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3117 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3118 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3119 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3120 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3122 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3123 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3124 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3125 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3127 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3128 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3129 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3130 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3132 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3133 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3134 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3135 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3136 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3137 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3138 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3139 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3141 { "AIF1TX", NULL, "I2S1" },
3142 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3144 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3145 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3146 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3148 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3149 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3151 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3152 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3153 { "IF2 ADC3 Mux", "OB45", "OB45" },
3155 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3156 { "IF2 ADC4 Mux", "OB67", "OB67" },
3157 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3159 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3160 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3161 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3162 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3164 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3165 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3166 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3167 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3169 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3170 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3171 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3172 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3174 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3175 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3176 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3177 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3179 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3180 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3181 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3182 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3184 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3185 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3186 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3187 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3188 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3189 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3190 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3191 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3193 { "AIF2TX", NULL, "I2S2" },
3194 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3196 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3197 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3198 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3199 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3200 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3201 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3202 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3203 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3205 { "AIF3TX", NULL, "I2S3" },
3206 { "AIF3TX", NULL, "IF3 ADC Mux" },
3208 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3209 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3210 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3211 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3212 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3213 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3214 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3215 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3217 { "AIF4TX", NULL, "I2S4" },
3218 { "AIF4TX", NULL, "IF4 ADC Mux" },
3220 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3221 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3222 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3224 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3225 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3227 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3228 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3229 { "SLB ADC3 Mux", "OB45", "OB45" },
3231 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3232 { "SLB ADC4 Mux", "OB67", "OB67" },
3233 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3235 { "SLBTX", NULL, "SLB" },
3236 { "SLBTX", NULL, "SLB ADC1 Mux" },
3237 { "SLBTX", NULL, "SLB ADC2 Mux" },
3238 { "SLBTX", NULL, "SLB ADC3 Mux" },
3239 { "SLBTX", NULL, "SLB ADC4 Mux" },
3241 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3242 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3243 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3244 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3245 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3247 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3248 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3250 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3251 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3252 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3253 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3254 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3255 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3257 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3258 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3260 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3261 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3262 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3263 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3264 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3266 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3267 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3269 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
3270 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
3271 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3272 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3273 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3274 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3275 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3276 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3278 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
3279 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
3280 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3281 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3282 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3283 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3284 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3285 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3287 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3288 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3289 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3290 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3291 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3292 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3294 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3295 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3296 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3297 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3298 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3299 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3300 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3302 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3303 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3304 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3305 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3306 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3307 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3308 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3310 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3311 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3312 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3313 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3314 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3315 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3316 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3318 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3319 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3320 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3321 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3322 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3323 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3324 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3326 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3327 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3328 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3329 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3330 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3331 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3332 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3334 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3335 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3336 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3337 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3338 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3339 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3340 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3342 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3343 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3344 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3345 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3346 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3347 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3348 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3350 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3351 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3352 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3353 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3355 { "OutBound2", NULL, "OB23 Bypass Mux" },
3356 { "OutBound3", NULL, "OB23 Bypass Mux" },
3357 { "OutBound4", NULL, "OB4 MIX" },
3358 { "OutBound5", NULL, "OB5 MIX" },
3359 { "OutBound6", NULL, "OB6 MIX" },
3360 { "OutBound7", NULL, "OB7 MIX" },
3362 { "OB45", NULL, "OutBound4" },
3363 { "OB45", NULL, "OutBound5" },
3364 { "OB67", NULL, "OutBound6" },
3365 { "OB67", NULL, "OutBound7" },
3367 { "IF1 DAC0", NULL, "AIF1RX" },
3368 { "IF1 DAC1", NULL, "AIF1RX" },
3369 { "IF1 DAC2", NULL, "AIF1RX" },
3370 { "IF1 DAC3", NULL, "AIF1RX" },
3371 { "IF1 DAC4", NULL, "AIF1RX" },
3372 { "IF1 DAC5", NULL, "AIF1RX" },
3373 { "IF1 DAC6", NULL, "AIF1RX" },
3374 { "IF1 DAC7", NULL, "AIF1RX" },
3375 { "IF1 DAC0", NULL, "I2S1" },
3376 { "IF1 DAC1", NULL, "I2S1" },
3377 { "IF1 DAC2", NULL, "I2S1" },
3378 { "IF1 DAC3", NULL, "I2S1" },
3379 { "IF1 DAC4", NULL, "I2S1" },
3380 { "IF1 DAC5", NULL, "I2S1" },
3381 { "IF1 DAC6", NULL, "I2S1" },
3382 { "IF1 DAC7", NULL, "I2S1" },
3384 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3385 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3386 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3387 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3388 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3389 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3390 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3391 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3393 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3394 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3395 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3396 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3397 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3398 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3399 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3400 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3402 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3403 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3404 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3405 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3406 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3407 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3408 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3409 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3411 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3412 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3413 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3414 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3415 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3416 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3417 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3418 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3420 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3421 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3422 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3423 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3424 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3425 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3426 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3427 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3429 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3430 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3431 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3432 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3433 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3434 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3435 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3436 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3438 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3439 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3440 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3441 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3442 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3443 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3444 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3445 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3447 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3448 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3449 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3450 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3451 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3452 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3453 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3454 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3456 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3457 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3458 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3459 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3460 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3461 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3462 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3463 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3465 { "IF2 DAC0", NULL, "AIF2RX" },
3466 { "IF2 DAC1", NULL, "AIF2RX" },
3467 { "IF2 DAC2", NULL, "AIF2RX" },
3468 { "IF2 DAC3", NULL, "AIF2RX" },
3469 { "IF2 DAC4", NULL, "AIF2RX" },
3470 { "IF2 DAC5", NULL, "AIF2RX" },
3471 { "IF2 DAC6", NULL, "AIF2RX" },
3472 { "IF2 DAC7", NULL, "AIF2RX" },
3473 { "IF2 DAC0", NULL, "I2S2" },
3474 { "IF2 DAC1", NULL, "I2S2" },
3475 { "IF2 DAC2", NULL, "I2S2" },
3476 { "IF2 DAC3", NULL, "I2S2" },
3477 { "IF2 DAC4", NULL, "I2S2" },
3478 { "IF2 DAC5", NULL, "I2S2" },
3479 { "IF2 DAC6", NULL, "I2S2" },
3480 { "IF2 DAC7", NULL, "I2S2" },
3482 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3483 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3484 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3485 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3486 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3487 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3488 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3489 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3491 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3492 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3493 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3494 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3495 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3496 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3497 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3498 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3500 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3501 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3502 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3503 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3504 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3505 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3506 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3507 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3509 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3510 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3511 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3512 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3513 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3514 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3515 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3516 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3518 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3519 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3520 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3521 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3522 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3523 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3524 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3525 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3527 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3528 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3529 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3530 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3531 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3532 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3533 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3534 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3536 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3537 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3538 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3539 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3540 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3541 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3542 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3543 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3545 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3546 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3547 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3548 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3549 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3550 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3551 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3552 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3554 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3555 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3556 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3557 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3558 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3559 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3560 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3561 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3563 { "IF3 DAC", NULL, "AIF3RX" },
3564 { "IF3 DAC", NULL, "I2S3" },
3566 { "IF4 DAC", NULL, "AIF4RX" },
3567 { "IF4 DAC", NULL, "I2S4" },
3569 { "IF3 DAC L", NULL, "IF3 DAC" },
3570 { "IF3 DAC R", NULL, "IF3 DAC" },
3572 { "IF4 DAC L", NULL, "IF4 DAC" },
3573 { "IF4 DAC R", NULL, "IF4 DAC" },
3575 { "SLB DAC0", NULL, "SLBRX" },
3576 { "SLB DAC1", NULL, "SLBRX" },
3577 { "SLB DAC2", NULL, "SLBRX" },
3578 { "SLB DAC3", NULL, "SLBRX" },
3579 { "SLB DAC4", NULL, "SLBRX" },
3580 { "SLB DAC5", NULL, "SLBRX" },
3581 { "SLB DAC6", NULL, "SLBRX" },
3582 { "SLB DAC7", NULL, "SLBRX" },
3583 { "SLB DAC0", NULL, "SLB" },
3584 { "SLB DAC1", NULL, "SLB" },
3585 { "SLB DAC2", NULL, "SLB" },
3586 { "SLB DAC3", NULL, "SLB" },
3587 { "SLB DAC4", NULL, "SLB" },
3588 { "SLB DAC5", NULL, "SLB" },
3589 { "SLB DAC6", NULL, "SLB" },
3590 { "SLB DAC7", NULL, "SLB" },
3592 { "SLB DAC01", NULL, "SLB DAC0" },
3593 { "SLB DAC01", NULL, "SLB DAC1" },
3594 { "SLB DAC23", NULL, "SLB DAC2" },
3595 { "SLB DAC23", NULL, "SLB DAC3" },
3596 { "SLB DAC45", NULL, "SLB DAC4" },
3597 { "SLB DAC45", NULL, "SLB DAC5" },
3598 { "SLB DAC67", NULL, "SLB DAC6" },
3599 { "SLB DAC67", NULL, "SLB DAC7" },
3601 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3602 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3603 { "ADDA1 Mux", "OB 67", "OB67" },
3605 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3606 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3607 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3608 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3609 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3610 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3612 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3613 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3614 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3615 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3617 { "DAC1 FS", NULL, "DAC1 MIXL" },
3618 { "DAC1 FS", NULL, "DAC1 MIXR" },
3620 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
3621 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
3622 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3623 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3624 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3625 { "DAC2 L Mux", "OB 2", "OutBound2" },
3627 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
3628 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
3629 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3630 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3631 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3632 { "DAC2 R Mux", "OB 3", "OutBound3" },
3633 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3634 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3636 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
3637 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
3638 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3639 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3640 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3641 { "DAC3 L Mux", "OB 4", "OutBound4" },
3643 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
3644 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
3645 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3646 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3647 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3648 { "DAC3 R Mux", "OB 5", "OutBound5" },
3650 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
3651 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
3652 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3653 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3654 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3655 { "DAC4 L Mux", "OB 6", "OutBound6" },
3657 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
3658 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
3659 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3660 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3661 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3662 { "DAC4 R Mux", "OB 7", "OutBound7" },
3664 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3665 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3666 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3667 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3668 { "Sidetone Mux", "ADC1", "ADC 1" },
3669 { "Sidetone Mux", "ADC2", "ADC 2" },
3670 { "Sidetone Mux", NULL, "Sidetone Power" },
3672 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3673 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3674 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3675 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3676 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3677 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3678 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3679 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3680 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3681 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3682 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3684 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3685 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3686 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3687 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3688 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3689 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3690 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3691 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3692 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3693 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3694 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3695 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3697 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3698 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3699 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3700 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3701 { "DD1 MIXL", NULL, "dac mono3 left filter" },
3702 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3703 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3704 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3705 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3706 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
3707 { "DD1 MIXR", NULL, "dac mono3 right filter" },
3708 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3710 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3711 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3712 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3713 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
3714 { "DD2 MIXL", NULL, "dac mono4 left filter" },
3715 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3716 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3717 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3718 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3719 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
3720 { "DD2 MIXR", NULL, "dac mono4 right filter" },
3721 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3723 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3724 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3725 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3726 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3727 { "DD1 MIX", NULL, "DD1 MIXL" },
3728 { "DD1 MIX", NULL, "DD1 MIXR" },
3729 { "DD2 MIX", NULL, "DD2 MIXL" },
3730 { "DD2 MIX", NULL, "DD2 MIXR" },
3732 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3733 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3734 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3735 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3737 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3738 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3739 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3740 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3742 { "DAC 1", NULL, "DAC12 SRC Mux" },
3743 { "DAC 2", NULL, "DAC12 SRC Mux" },
3744 { "DAC 3", NULL, "DAC3 SRC Mux" },
3746 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3747 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3748 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3749 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3750 { "PDM1 L Mux", NULL, "PDM1 Power" },
3751 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3752 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3753 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3754 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3755 { "PDM1 R Mux", NULL, "PDM1 Power" },
3756 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3757 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3758 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3759 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3760 { "PDM2 L Mux", NULL, "PDM2 Power" },
3761 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3762 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3763 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3764 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3765 { "PDM2 R Mux", NULL, "PDM2 Power" },
3767 { "LOUT1 amp", NULL, "DAC 1" },
3768 { "LOUT2 amp", NULL, "DAC 2" },
3769 { "LOUT3 amp", NULL, "DAC 3" },
3771 { "LOUT1 vref", NULL, "LOUT1 amp" },
3772 { "LOUT2 vref", NULL, "LOUT2 amp" },
3773 { "LOUT3 vref", NULL, "LOUT3 amp" },
3775 { "LOUT1", NULL, "LOUT1 vref" },
3776 { "LOUT2", NULL, "LOUT2 vref" },
3777 { "LOUT3", NULL, "LOUT3 vref" },
3779 { "PDM1L", NULL, "PDM1 L Mux" },
3780 { "PDM1R", NULL, "PDM1 R Mux" },
3781 { "PDM2L", NULL, "PDM2 L Mux" },
3782 { "PDM2R", NULL, "PDM2 R Mux" },
3785 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3786 { "DMIC L2", NULL, "DMIC1 power" },
3787 { "DMIC R2", NULL, "DMIC1 power" },
3790 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3791 { "DMIC L2", NULL, "DMIC2 power" },
3792 { "DMIC R2", NULL, "DMIC2 power" },
3795 static int rt5677_hw_params(struct snd_pcm_substream *substream,
3796 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3798 struct snd_soc_codec *codec = dai->codec;
3799 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3800 unsigned int val_len = 0, val_clk, mask_clk;
3801 int pre_div, bclk_ms, frame_size;
3803 rt5677->lrck[dai->id] = params_rate(params);
3804 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
3806 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3807 rt5677->sysclk, rt5677->lrck[dai->id]);
3810 frame_size = snd_soc_params_to_frame_size(params);
3811 if (frame_size < 0) {
3812 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3815 bclk_ms = frame_size > 32;
3816 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
3818 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
3819 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
3820 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
3821 bclk_ms, pre_div, dai->id);
3823 switch (params_width(params)) {
3827 val_len |= RT5677_I2S_DL_20;
3830 val_len |= RT5677_I2S_DL_24;
3833 val_len |= RT5677_I2S_DL_8;
3841 mask_clk = RT5677_I2S_PD1_MASK;
3842 val_clk = pre_div << RT5677_I2S_PD1_SFT;
3843 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3844 RT5677_I2S_DL_MASK, val_len);
3845 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3849 mask_clk = RT5677_I2S_PD2_MASK;
3850 val_clk = pre_div << RT5677_I2S_PD2_SFT;
3851 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3852 RT5677_I2S_DL_MASK, val_len);
3853 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3857 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
3858 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
3859 pre_div << RT5677_I2S_PD3_SFT;
3860 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3861 RT5677_I2S_DL_MASK, val_len);
3862 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3866 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
3867 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
3868 pre_div << RT5677_I2S_PD4_SFT;
3869 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3870 RT5677_I2S_DL_MASK, val_len);
3871 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3881 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3883 struct snd_soc_codec *codec = dai->codec;
3884 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3885 unsigned int reg_val = 0;
3887 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3888 case SND_SOC_DAIFMT_CBM_CFM:
3889 rt5677->master[dai->id] = 1;
3891 case SND_SOC_DAIFMT_CBS_CFS:
3892 reg_val |= RT5677_I2S_MS_S;
3893 rt5677->master[dai->id] = 0;
3899 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3900 case SND_SOC_DAIFMT_NB_NF:
3902 case SND_SOC_DAIFMT_IB_NF:
3903 reg_val |= RT5677_I2S_BP_INV;
3909 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3910 case SND_SOC_DAIFMT_I2S:
3912 case SND_SOC_DAIFMT_LEFT_J:
3913 reg_val |= RT5677_I2S_DF_LEFT;
3915 case SND_SOC_DAIFMT_DSP_A:
3916 reg_val |= RT5677_I2S_DF_PCM_A;
3918 case SND_SOC_DAIFMT_DSP_B:
3919 reg_val |= RT5677_I2S_DF_PCM_B;
3927 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3928 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3929 RT5677_I2S_DF_MASK, reg_val);
3932 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3933 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3934 RT5677_I2S_DF_MASK, reg_val);
3937 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3938 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3939 RT5677_I2S_DF_MASK, reg_val);
3942 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3943 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3944 RT5677_I2S_DF_MASK, reg_val);
3954 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3955 int clk_id, unsigned int freq, int dir)
3957 struct snd_soc_codec *codec = dai->codec;
3958 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3959 unsigned int reg_val = 0;
3961 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
3965 case RT5677_SCLK_S_MCLK:
3966 reg_val |= RT5677_SCLK_SRC_MCLK;
3968 case RT5677_SCLK_S_PLL1:
3969 reg_val |= RT5677_SCLK_SRC_PLL1;
3971 case RT5677_SCLK_S_RCCLK:
3972 reg_val |= RT5677_SCLK_SRC_RCCLK;
3975 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3978 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3979 RT5677_SCLK_SRC_MASK, reg_val);
3980 rt5677->sysclk = freq;
3981 rt5677->sysclk_src = clk_id;
3983 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3989 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3990 * @freq_in: external clock provided to codec.
3991 * @freq_out: target clock which codec works on.
3992 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3994 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3996 * Returns 0 for success or negative error code.
3998 static int rt5677_pll_calc(const unsigned int freq_in,
3999 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4001 if (RT5677_PLL_INP_MIN > freq_in)
4004 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4007 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4008 unsigned int freq_in, unsigned int freq_out)
4010 struct snd_soc_codec *codec = dai->codec;
4011 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4012 struct rl6231_pll_code pll_code;
4015 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4016 freq_out == rt5677->pll_out)
4019 if (!freq_in || !freq_out) {
4020 dev_dbg(codec->dev, "PLL disabled\n");
4023 rt5677->pll_out = 0;
4024 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4025 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4030 case RT5677_PLL1_S_MCLK:
4031 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4032 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4034 case RT5677_PLL1_S_BCLK1:
4035 case RT5677_PLL1_S_BCLK2:
4036 case RT5677_PLL1_S_BCLK3:
4037 case RT5677_PLL1_S_BCLK4:
4040 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4041 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4044 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4045 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4048 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4049 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4052 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4053 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4060 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4064 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4066 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4070 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4071 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4072 pll_code.n_code, pll_code.k_code);
4074 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4075 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4076 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4077 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4078 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4080 rt5677->pll_in = freq_in;
4081 rt5677->pll_out = freq_out;
4082 rt5677->pll_src = source;
4087 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4088 unsigned int rx_mask, int slots, int slot_width)
4090 struct snd_soc_codec *codec = dai->codec;
4091 unsigned int val = 0;
4093 if (rx_mask || tx_mask)
4111 switch (slot_width) {
4128 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val);
4131 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val);
4140 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4141 enum snd_soc_bias_level level)
4143 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4146 case SND_SOC_BIAS_ON:
4149 case SND_SOC_BIAS_PREPARE:
4150 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
4151 rt5677_set_dsp_vad(codec, false);
4153 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4154 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4156 regmap_update_bits(rt5677->regmap,
4157 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4159 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4160 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4161 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4162 RT5677_PWR_BG | RT5677_PWR_VREF2,
4163 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4164 RT5677_PWR_BG | RT5677_PWR_VREF2);
4165 rt5677->is_vref_slow = false;
4166 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4167 RT5677_PWR_CORE, RT5677_PWR_CORE);
4168 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4173 case SND_SOC_BIAS_STANDBY:
4176 case SND_SOC_BIAS_OFF:
4177 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4178 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4179 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4180 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4181 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4182 regmap_update_bits(rt5677->regmap,
4183 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4185 if (rt5677->dsp_vad_en)
4186 rt5677_set_dsp_vad(codec, true);
4192 codec->dapm.bias_level = level;
4197 #ifdef CONFIG_GPIOLIB
4198 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4200 return container_of(chip, struct rt5677_priv, gpio_chip);
4203 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4205 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4208 case RT5677_GPIO1 ... RT5677_GPIO5:
4209 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4210 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4214 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4215 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4223 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4224 unsigned offset, int value)
4226 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4229 case RT5677_GPIO1 ... RT5677_GPIO5:
4230 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4231 0x3 << (offset * 3 + 1),
4232 (0x2 | !!value) << (offset * 3 + 1));
4236 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4237 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4238 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4248 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4250 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4253 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4257 return (value & (0x1 << offset)) >> offset;
4260 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4262 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4265 case RT5677_GPIO1 ... RT5677_GPIO5:
4266 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4267 0x1 << (offset * 3 + 2), 0x0);
4271 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4272 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4282 /** Configures the gpio as
4287 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4293 case RT5677_GPIO1 ... RT5677_GPIO2:
4294 shift = 2 * (1 - offset);
4295 regmap_update_bits(rt5677->regmap,
4296 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4298 (value & 0x3) << shift);
4301 case RT5677_GPIO3 ... RT5677_GPIO6:
4302 shift = 2 * (9 - offset);
4303 regmap_update_bits(rt5677->regmap,
4304 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4306 (value & 0x3) << shift);
4314 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4316 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4317 struct regmap_irq_chip_data *data = rt5677->irq_data;
4320 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4321 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4322 (rt5677->pdata.jd1_gpio == 2 &&
4323 offset == RT5677_GPIO2) ||
4324 (rt5677->pdata.jd1_gpio == 3 &&
4325 offset == RT5677_GPIO3)) {
4326 irq = RT5677_IRQ_JD1;
4332 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4333 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4334 (rt5677->pdata.jd2_gpio == 2 &&
4335 offset == RT5677_GPIO5) ||
4336 (rt5677->pdata.jd2_gpio == 3 &&
4337 offset == RT5677_GPIO6)) {
4338 irq = RT5677_IRQ_JD2;
4339 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4340 offset == RT5677_GPIO4) ||
4341 (rt5677->pdata.jd3_gpio == 2 &&
4342 offset == RT5677_GPIO5) ||
4343 (rt5677->pdata.jd3_gpio == 3 &&
4344 offset == RT5677_GPIO6)) {
4345 irq = RT5677_IRQ_JD3;
4351 return regmap_irq_get_virq(data, irq);
4354 static struct gpio_chip rt5677_template_chip = {
4356 .owner = THIS_MODULE,
4357 .direction_output = rt5677_gpio_direction_out,
4358 .set = rt5677_gpio_set,
4359 .direction_input = rt5677_gpio_direction_in,
4360 .get = rt5677_gpio_get,
4361 .to_irq = rt5677_to_irq,
4365 static void rt5677_init_gpio(struct i2c_client *i2c)
4367 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4370 rt5677->gpio_chip = rt5677_template_chip;
4371 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4372 rt5677->gpio_chip.dev = &i2c->dev;
4373 rt5677->gpio_chip.base = -1;
4375 ret = gpiochip_add(&rt5677->gpio_chip);
4377 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4380 static void rt5677_free_gpio(struct i2c_client *i2c)
4382 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4384 gpiochip_remove(&rt5677->gpio_chip);
4387 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4392 static void rt5677_init_gpio(struct i2c_client *i2c)
4396 static void rt5677_free_gpio(struct i2c_client *i2c)
4401 static int rt5677_probe(struct snd_soc_codec *codec)
4403 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4406 rt5677->codec = codec;
4408 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4409 snd_soc_dapm_add_routes(&codec->dapm,
4411 ARRAY_SIZE(rt5677_dmic2_clk_2));
4412 } else { /*use dmic1 clock by default*/
4413 snd_soc_dapm_add_routes(&codec->dapm,
4415 ARRAY_SIZE(rt5677_dmic2_clk_1));
4418 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
4420 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4421 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4423 for (i = 0; i < RT5677_GPIO_NUM; i++)
4424 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4426 if (rt5677->irq_data) {
4427 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4429 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4432 if (rt5677->pdata.jd1_gpio)
4433 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4434 RT5677_SEL_GPIO_JD1_MASK,
4435 rt5677->pdata.jd1_gpio <<
4436 RT5677_SEL_GPIO_JD1_SFT);
4438 if (rt5677->pdata.jd2_gpio)
4439 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4440 RT5677_SEL_GPIO_JD2_MASK,
4441 rt5677->pdata.jd2_gpio <<
4442 RT5677_SEL_GPIO_JD2_SFT);
4444 if (rt5677->pdata.jd3_gpio)
4445 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4446 RT5677_SEL_GPIO_JD3_MASK,
4447 rt5677->pdata.jd3_gpio <<
4448 RT5677_SEL_GPIO_JD3_SFT);
4451 mutex_init(&rt5677->dsp_cmd_lock);
4452 mutex_init(&rt5677->dsp_pri_lock);
4457 static int rt5677_remove(struct snd_soc_codec *codec)
4459 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4461 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4462 if (gpio_is_valid(rt5677->pow_ldo2))
4463 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4469 static int rt5677_suspend(struct snd_soc_codec *codec)
4471 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4473 if (!rt5677->dsp_vad_en) {
4474 regcache_cache_only(rt5677->regmap, true);
4475 regcache_mark_dirty(rt5677->regmap);
4478 if (gpio_is_valid(rt5677->pow_ldo2))
4479 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4484 static int rt5677_resume(struct snd_soc_codec *codec)
4486 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4488 if (gpio_is_valid(rt5677->pow_ldo2)) {
4489 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4493 if (!rt5677->dsp_vad_en) {
4494 regcache_cache_only(rt5677->regmap, false);
4495 regcache_sync(rt5677->regmap);
4501 #define rt5677_suspend NULL
4502 #define rt5677_resume NULL
4505 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4507 struct i2c_client *client = context;
4508 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4510 if (rt5677->is_dsp_mode) {
4512 mutex_lock(&rt5677->dsp_pri_lock);
4513 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4515 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4516 mutex_unlock(&rt5677->dsp_pri_lock);
4518 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4521 regmap_read(rt5677->regmap_physical, reg, val);
4527 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4529 struct i2c_client *client = context;
4530 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4532 if (rt5677->is_dsp_mode) {
4534 mutex_lock(&rt5677->dsp_pri_lock);
4535 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4537 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4539 mutex_unlock(&rt5677->dsp_pri_lock);
4541 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4544 regmap_write(rt5677->regmap_physical, reg, val);
4550 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4551 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4552 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4554 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4555 .hw_params = rt5677_hw_params,
4556 .set_fmt = rt5677_set_dai_fmt,
4557 .set_sysclk = rt5677_set_dai_sysclk,
4558 .set_pll = rt5677_set_dai_pll,
4559 .set_tdm_slot = rt5677_set_tdm_slot,
4562 static struct snd_soc_dai_driver rt5677_dai[] = {
4564 .name = "rt5677-aif1",
4567 .stream_name = "AIF1 Playback",
4570 .rates = RT5677_STEREO_RATES,
4571 .formats = RT5677_FORMATS,
4574 .stream_name = "AIF1 Capture",
4577 .rates = RT5677_STEREO_RATES,
4578 .formats = RT5677_FORMATS,
4580 .ops = &rt5677_aif_dai_ops,
4583 .name = "rt5677-aif2",
4586 .stream_name = "AIF2 Playback",
4589 .rates = RT5677_STEREO_RATES,
4590 .formats = RT5677_FORMATS,
4593 .stream_name = "AIF2 Capture",
4596 .rates = RT5677_STEREO_RATES,
4597 .formats = RT5677_FORMATS,
4599 .ops = &rt5677_aif_dai_ops,
4602 .name = "rt5677-aif3",
4605 .stream_name = "AIF3 Playback",
4608 .rates = RT5677_STEREO_RATES,
4609 .formats = RT5677_FORMATS,
4612 .stream_name = "AIF3 Capture",
4615 .rates = RT5677_STEREO_RATES,
4616 .formats = RT5677_FORMATS,
4618 .ops = &rt5677_aif_dai_ops,
4621 .name = "rt5677-aif4",
4624 .stream_name = "AIF4 Playback",
4627 .rates = RT5677_STEREO_RATES,
4628 .formats = RT5677_FORMATS,
4631 .stream_name = "AIF4 Capture",
4634 .rates = RT5677_STEREO_RATES,
4635 .formats = RT5677_FORMATS,
4637 .ops = &rt5677_aif_dai_ops,
4640 .name = "rt5677-slimbus",
4643 .stream_name = "SLIMBus Playback",
4646 .rates = RT5677_STEREO_RATES,
4647 .formats = RT5677_FORMATS,
4650 .stream_name = "SLIMBus Capture",
4653 .rates = RT5677_STEREO_RATES,
4654 .formats = RT5677_FORMATS,
4656 .ops = &rt5677_aif_dai_ops,
4660 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4661 .probe = rt5677_probe,
4662 .remove = rt5677_remove,
4663 .suspend = rt5677_suspend,
4664 .resume = rt5677_resume,
4665 .set_bias_level = rt5677_set_bias_level,
4666 .idle_bias_off = true,
4667 .controls = rt5677_snd_controls,
4668 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4669 .dapm_widgets = rt5677_dapm_widgets,
4670 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4671 .dapm_routes = rt5677_dapm_routes,
4672 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4675 static const struct regmap_config rt5677_regmap_physical = {
4680 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4682 .readable_reg = rt5677_readable_register,
4684 .cache_type = REGCACHE_NONE,
4685 .ranges = rt5677_ranges,
4686 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4689 static const struct regmap_config rt5677_regmap = {
4693 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4696 .volatile_reg = rt5677_volatile_register,
4697 .readable_reg = rt5677_readable_register,
4698 .reg_read = rt5677_read,
4699 .reg_write = rt5677_write,
4701 .cache_type = REGCACHE_RBTREE,
4702 .reg_defaults = rt5677_reg,
4703 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4704 .ranges = rt5677_ranges,
4705 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4708 static const struct i2c_device_id rt5677_i2c_id[] = {
4712 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4714 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4716 rt5677->pdata.in1_diff = of_property_read_bool(np,
4717 "realtek,in1-differential");
4718 rt5677->pdata.in2_diff = of_property_read_bool(np,
4719 "realtek,in2-differential");
4720 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4721 "realtek,lout1-differential");
4722 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4723 "realtek,lout2-differential");
4724 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4725 "realtek,lout3-differential");
4727 rt5677->pow_ldo2 = of_get_named_gpio(np,
4728 "realtek,pow-ldo2-gpio", 0);
4731 * POW_LDO2 is optional (it may be statically tied on the board).
4732 * -ENOENT means that the property doesn't exist, i.e. there is no
4733 * GPIO, so is not an error. Any other error code means the property
4734 * exists, but could not be parsed.
4736 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4737 (rt5677->pow_ldo2 != -ENOENT))
4738 return rt5677->pow_ldo2;
4740 of_property_read_u8_array(np, "realtek,gpio-config",
4741 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4743 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4744 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4745 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4750 static struct regmap_irq rt5677_irqs[] = {
4751 [RT5677_IRQ_JD1] = {
4753 .mask = RT5677_EN_IRQ_GPIO_JD1,
4755 [RT5677_IRQ_JD2] = {
4757 .mask = RT5677_EN_IRQ_GPIO_JD2,
4759 [RT5677_IRQ_JD3] = {
4761 .mask = RT5677_EN_IRQ_GPIO_JD3,
4765 static struct regmap_irq_chip rt5677_irq_chip = {
4767 .irqs = rt5677_irqs,
4768 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4771 .status_base = RT5677_IRQ_CTRL1,
4772 .mask_base = RT5677_IRQ_CTRL1,
4776 static int rt5677_init_irq(struct i2c_client *i2c)
4779 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4781 if (!rt5677->pdata.jd1_gpio &&
4782 !rt5677->pdata.jd2_gpio &&
4783 !rt5677->pdata.jd3_gpio)
4787 dev_err(&i2c->dev, "No interrupt specified\n");
4791 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4792 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4793 &rt5677_irq_chip, &rt5677->irq_data);
4796 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
4803 static void rt5677_free_irq(struct i2c_client *i2c)
4805 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4807 if (rt5677->irq_data)
4808 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
4811 static int rt5677_i2c_probe(struct i2c_client *i2c,
4812 const struct i2c_device_id *id)
4814 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
4815 struct rt5677_priv *rt5677;
4819 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
4824 i2c_set_clientdata(i2c, rt5677);
4827 rt5677->pdata = *pdata;
4829 if (i2c->dev.of_node) {
4830 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
4832 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
4837 rt5677->pow_ldo2 = -EINVAL;
4840 if (gpio_is_valid(rt5677->pow_ldo2)) {
4841 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
4842 GPIOF_OUT_INIT_HIGH,
4845 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
4846 rt5677->pow_ldo2, ret);
4849 /* Wait a while until I2C bus becomes available. The datasheet
4850 * does not specify the exact we should wait but startup
4851 * sequence mentiones at least a few milliseconds.
4856 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
4857 &rt5677_regmap_physical);
4858 if (IS_ERR(rt5677->regmap_physical)) {
4859 ret = PTR_ERR(rt5677->regmap_physical);
4860 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4865 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
4866 if (IS_ERR(rt5677->regmap)) {
4867 ret = PTR_ERR(rt5677->regmap);
4868 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4873 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
4874 if (val != RT5677_DEVICE_ID) {
4876 "Device with ID register %x is not rt5677\n", val);
4880 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4882 ret = regmap_register_patch(rt5677->regmap, init_list,
4883 ARRAY_SIZE(init_list));
4885 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4887 if (rt5677->pdata.in1_diff)
4888 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4889 RT5677_IN_DF1, RT5677_IN_DF1);
4891 if (rt5677->pdata.in2_diff)
4892 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4893 RT5677_IN_DF2, RT5677_IN_DF2);
4895 if (rt5677->pdata.lout1_diff)
4896 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4897 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
4899 if (rt5677->pdata.lout2_diff)
4900 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4901 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
4903 if (rt5677->pdata.lout3_diff)
4904 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4905 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
4907 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4908 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
4909 RT5677_GPIO5_FUNC_MASK,
4910 RT5677_GPIO5_FUNC_DMIC);
4911 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4912 RT5677_GPIO5_DIR_MASK,
4913 RT5677_GPIO5_DIR_OUT);
4916 rt5677_init_gpio(i2c);
4917 rt5677_init_irq(i2c);
4919 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
4920 rt5677_dai, ARRAY_SIZE(rt5677_dai));
4923 static int rt5677_i2c_remove(struct i2c_client *i2c)
4925 snd_soc_unregister_codec(&i2c->dev);
4926 rt5677_free_irq(i2c);
4927 rt5677_free_gpio(i2c);
4932 static struct i2c_driver rt5677_i2c_driver = {
4935 .owner = THIS_MODULE,
4937 .probe = rt5677_i2c_probe,
4938 .remove = rt5677_i2c_remove,
4939 .id_table = rt5677_i2c_id,
4941 module_i2c_driver(rt5677_i2c_driver);
4943 MODULE_DESCRIPTION("ASoC RT5677 driver");
4944 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
4945 MODULE_LICENSE("GPL v2");