sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/gpio.h>
  32 #include <linux/regulator/consumer.h>
  33 #include <linux/slab.h>
  34 #include <sound/core.h>
  35 #include <sound/pcm.h>
  36 #include <sound/pcm_params.h>
  37 #include <sound/soc.h>
  38 #include <sound/initval.h>
  39 #include <sound/tlv.h>
  40
  41 #include <sound/tlv320dac33-plat.h>
  42 #include "tlv320dac33.h"
  43
  44 /*
  45  * The internal FIFO is 24576 bytes long
  46  * It can be configured to hold 16bit or 24bit samples
  47  * In 16bit configuration the FIFO can hold 6144 stereo samples
  48  * In 24bit configuration the FIFO can hold 4096 stereo samples
  49  */
  50 #define DAC33_FIFO_SIZE_16BIT   6144
  51 #define DAC33_FIFO_SIZE_24BIT   4096
  52 #define DAC33_MODE7_MARGIN      10      /* Safety margin for FIFO in Mode7 */
  53
  54 #define BURST_BASEFREQ_HZ       49152000
  55
  56 #define SAMPLES_TO_US(rate, samples) \
  57         (1000000000 / (((rate) * 1000) / (samples)))
  58
  59 #define US_TO_SAMPLES(rate, us) \
  60         ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000)))
  61
  62 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  63         (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
  64
  65 static void dac33_calculate_times(struct snd_pcm_substream *substream,
  66                                   struct snd_soc_codec *codec);
  67 static int dac33_prepare_chip(struct snd_pcm_substream *substream,
  68                               struct snd_soc_codec *codec);
  69
  70 enum dac33_state {
  71         DAC33_IDLE = 0,
  72         DAC33_PREFILL,
  73         DAC33_PLAYBACK,
  74         DAC33_FLUSH,
  75 };
  76
  77 enum dac33_fifo_modes {
  78         DAC33_FIFO_BYPASS = 0,
  79         DAC33_FIFO_MODE1,
  80         DAC33_FIFO_MODE7,
  81         DAC33_FIFO_LAST_MODE,
  82 };
  83
  84 #define DAC33_NUM_SUPPLIES 3
  85 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  86         "AVDD",
  87         "DVDD",
  88         "IOVDD",
  89 };
  90
  91 struct tlv320dac33_priv {
  92         struct mutex mutex;
  93         struct workqueue_struct *dac33_wq;
  94         struct work_struct work;
  95         struct snd_soc_codec *codec;
  96         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  97         struct snd_pcm_substream *substream;
  98         int power_gpio;
  99         int chip_power;
 100         int irq;
 101         unsigned int refclk;
 102
 103         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 104         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 105         unsigned int fifo_size;         /* Size of the FIFO in samples */
 106         unsigned int nsample;           /* burst read amount from host */
 107         int mode1_latency;              /* latency caused by the i2c writes in
 108                                          * us */
 109         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 110         unsigned int burst_rate;        /* Interface speed in Burst modes */
 111
 112         int keep_bclk;                  /* Keep the BCLK continuously running
 113                                          * in FIFO modes */
 114         spinlock_t lock;
 115         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 116         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 117
 118         unsigned int mode1_us_burst;    /* Time to burst read n number of
 119                                          * samples */
 120         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 121
 122         unsigned int uthr;
 123
 124         enum dac33_state state;
 125         void *control_data;
 126 };
 127
 128 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 129 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 130 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 131 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 132 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 133 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 134 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 136 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 137 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 138 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 140 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 141 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 142 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 143 0x00, 0x00,             /* 0x38 - 0x39 */
 144 /* Registers 0x3a - 0x3f are reserved  */
 145             0x00, 0x00, /* 0x3a - 0x3b */
 146 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 147
 148 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 149 0x00, 0x80,             /* 0x44 - 0x45 */
 150 /* Registers 0x46 - 0x47 are reserved  */
 151             0x80, 0x80, /* 0x46 - 0x47 */
 152
 153 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 154 /* Registers 0x4b - 0x7c are reserved  */
 155                   0x00, /* 0x4b        */
 156 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 157 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 158 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 159 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 160 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 161 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 162 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 163 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 164 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 165 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 166 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 167 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 168 0x00,                   /* 0x7c        */
 169
 170       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 171 };
 172
 173 /* Register read and write */
 174 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 175                                                 unsigned reg)
 176 {
 177         u8 *cache = codec->reg_cache;
 178         if (reg >= DAC33_CACHEREGNUM)
 179                 return 0;
 180
 181         return cache[reg];
 182 }
 183
 184 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 185                                          u8 reg, u8 value)
 186 {
 187         u8 *cache = codec->reg_cache;
 188         if (reg >= DAC33_CACHEREGNUM)
 189                 return;
 190
 191         cache[reg] = value;
 192 }
 193
 194 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 195                       u8 *value)
 196 {
 197         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 198         int val, ret = 0;
 199
 200         *value = reg & 0xff;
 201
 202         /* If powered off, return the cached value */
 203         if (dac33->chip_power) {
 204                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 205                 if (val < 0) {
 206                         dev_err(codec->dev, "Read failed (%d)\n", val);
 207                         value[0] = dac33_read_reg_cache(codec, reg);
 208                         ret = val;
 209                 } else {
 210                         value[0] = val;
 211                         dac33_write_reg_cache(codec, reg, val);
 212                 }
 213         } else {
 214                 value[0] = dac33_read_reg_cache(codec, reg);
 215         }
 216
 217         return ret;
 218 }
 219
 220 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 221                        unsigned int value)
 222 {
 223         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 224         u8 data[2];
 225         int ret = 0;
 226
 227         /*
 228          * data is
 229          *   D15..D8 dac33 register offset
 230          *   D7...D0 register data
 231          */
 232         data[0] = reg & 0xff;
 233         data[1] = value & 0xff;
 234
 235         dac33_write_reg_cache(codec, data[0], data[1]);
 236         if (dac33->chip_power) {
 237                 ret = codec->hw_write(codec->control_data, data, 2);
 238                 if (ret != 2)
 239                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 240                 else
 241                         ret = 0;
 242         }
 243
 244         return ret;
 245 }
 246
 247 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 248                        unsigned int value)
 249 {
 250         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 251         int ret;
 252
 253         mutex_lock(&dac33->mutex);
 254         ret = dac33_write(codec, reg, value);
 255         mutex_unlock(&dac33->mutex);
 256
 257         return ret;
 258 }
 259
 260 #define DAC33_I2C_ADDR_AUTOINC  0x80
 261 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 262                        unsigned int value)
 263 {
 264         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 265         u8 data[3];
 266         int ret = 0;
 267
 268         /*
 269          * data is
 270          *   D23..D16 dac33 register offset
 271          *   D15..D8  register data MSB
 272          *   D7...D0  register data LSB
 273          */
 274         data[0] = reg & 0xff;
 275         data[1] = (value >> 8) & 0xff;
 276         data[2] = value & 0xff;
 277
 278         dac33_write_reg_cache(codec, data[0], data[1]);
 279         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 280
 281         if (dac33->chip_power) {
 282                 /* We need to set autoincrement mode for 16 bit writes */
 283                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 284                 ret = codec->hw_write(codec->control_data, data, 3);
 285                 if (ret != 3)
 286                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 287                 else
 288                         ret = 0;
 289         }
 290
 291         return ret;
 292 }
 293
 294 static void dac33_init_chip(struct snd_soc_codec *codec)
 295 {
 296         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 297
 298         if (unlikely(!dac33->chip_power))
 299                 return;
 300
 301         /* A : DAC sample rate Fsref/1.5 */
 302         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 303         /* B : DAC src=normal, not muted */
 304         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 305                                              DAC33_DACSRCL_LEFT);
 306         /* C : (defaults) */
 307         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 308
 309         /* 73 : volume soft stepping control,
 310          clock source = internal osc (?) */
 311         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 312
 313         /* Restore only selected registers (gains mostly) */
 314         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 315                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 316         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 317                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 318
 319         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 320                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 321         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 322                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 323
 324         dac33_write(codec, DAC33_OUT_AMP_CTRL,
 325                     dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL));
 326
 327         dac33_write(codec, DAC33_LDAC_PWR_CTRL,
 328                     dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL));
 329         dac33_write(codec, DAC33_RDAC_PWR_CTRL,
 330                     dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL));
 331 }
 332
 333 static inline int dac33_read_id(struct snd_soc_codec *codec)
 334 {
 335         int i, ret = 0;
 336         u8 reg;
 337
 338         for (i = 0; i < 3; i++) {
 339                 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
 340                 if (ret < 0)
 341                         break;
 342         }
 343
 344         return ret;
 345 }
 346
 347 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 348 {
 349         u8 reg;
 350
 351         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 352         if (power)
 353                 reg |= DAC33_PDNALLB;
 354         else
 355                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 356                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 357         dac33_write(codec, DAC33_PWR_CTRL, reg);
 358 }
 359
 360 static inline void dac33_disable_digital(struct snd_soc_codec *codec)
 361 {
 362         u8 reg;
 363
 364         /* Stop the DAI clock */
 365         reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 366         reg &= ~DAC33_BCLKON;
 367         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
 368
 369         /* Power down the Oscillator, and DACs */
 370         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 371         reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
 372         dac33_write(codec, DAC33_PWR_CTRL, reg);
 373 }
 374
 375 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 376 {
 377         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 378         int ret = 0;
 379
 380         mutex_lock(&dac33->mutex);
 381
 382         /* Safety check */
 383         if (unlikely(power == dac33->chip_power)) {
 384                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 385                         power ? "ON" : "OFF");
 386                 goto exit;
 387         }
 388
 389         if (power) {
 390                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 391                                           dac33->supplies);
 392                 if (ret != 0) {
 393                         dev_err(codec->dev,
 394                                 "Failed to enable supplies: %d\n", ret);
 395                                 goto exit;
 396                 }
 397
 398                 if (dac33->power_gpio >= 0)
 399                         gpio_set_value(dac33->power_gpio, 1);
 400
 401                 dac33->chip_power = 1;
 402         } else {
 403                 dac33_soft_power(codec, 0);
 404                 if (dac33->power_gpio >= 0)
 405                         gpio_set_value(dac33->power_gpio, 0);
 406
 407                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 408                                              dac33->supplies);
 409                 if (ret != 0) {
 410                         dev_err(codec->dev,
 411                                 "Failed to disable supplies: %d\n", ret);
 412                         goto exit;
 413                 }
 414
 415                 dac33->chip_power = 0;
 416         }
 417
 418 exit:
 419         mutex_unlock(&dac33->mutex);
 420         return ret;
 421 }
 422
 423 static int dac33_playback_event(struct snd_soc_dapm_widget *w,
 424                 struct snd_kcontrol *kcontrol, int event)
 425 {
 426         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 427         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 428
 429         switch (event) {
 430         case SND_SOC_DAPM_PRE_PMU:
 431                 if (likely(dac33->substream)) {
 432                         dac33_calculate_times(dac33->substream, codec);
 433                         dac33_prepare_chip(dac33->substream, codec);
 434                 }
 435                 break;
 436         case SND_SOC_DAPM_POST_PMD:
 437                 dac33_disable_digital(codec);
 438                 break;
 439         }
 440         return 0;
 441 }
 442
 443 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 444                          struct snd_ctl_elem_value *ucontrol)
 445 {
 446         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 447         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 448
 449         ucontrol->value.enumerated.item[0] = dac33->fifo_mode;
 450
 451         return 0;
 452 }
 453
 454 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 455                          struct snd_ctl_elem_value *ucontrol)
 456 {
 457         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 458         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 459         int ret = 0;
 460
 461         if (dac33->fifo_mode == ucontrol->value.enumerated.item[0])
 462                 return 0;
 463         /* Do not allow changes while stream is running*/
 464         if (snd_soc_codec_is_active(codec))
 465                 return -EPERM;
 466
 467         if (ucontrol->value.enumerated.item[0] >= DAC33_FIFO_LAST_MODE)
 468                 ret = -EINVAL;
 469         else
 470                 dac33->fifo_mode = ucontrol->value.enumerated.item[0];
 471
 472         return ret;
 473 }
 474
 475 /* Codec operation modes */
 476 static const char *dac33_fifo_mode_texts[] = {
 477         "Bypass", "Mode 1", "Mode 7"
 478 };
 479
 480 static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts);
 481
 482 /* L/R Line Output Gain */
 483 static const char *lr_lineout_gain_texts[] = {
 484         "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
 485         "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
 486 };
 487
 488 static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum,
 489                             DAC33_LDAC_PWR_CTRL, 0,
 490                             lr_lineout_gain_texts);
 491
 492 static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum,
 493                             DAC33_RDAC_PWR_CTRL, 0,
 494                             lr_lineout_gain_texts);
 495
 496 /*
 497  * DACL/R digital volume control:
 498  * from 0 dB to -63.5 in 0.5 dB steps
 499  * Need to be inverted later on:
 500  * 0x00 == 0 dB
 501  * 0x7f == -63.5 dB
 502  */
 503 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 504
 505 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 506         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 507                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 508                 0, 0x7f, 1, dac_digivol_tlv),
 509         SOC_DOUBLE_R("DAC Digital Playback Switch",
 510                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 511         SOC_DOUBLE_R("Line to Line Out Volume",
 512                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 513         SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
 514         SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
 515 };
 516
 517 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
 518         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 519                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 520 };
 521
 522 /* Analog bypass */
 523 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 524         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 525
 526 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 527         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 528
 529 /* LOP L/R invert selection */
 530 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
 531
 532 static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum,
 533                             DAC33_OUT_AMP_CTRL, 3,
 534                             dac33_lr_lom_texts);
 535
 536 static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
 537 SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
 538
 539 static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum,
 540                             DAC33_OUT_AMP_CTRL, 2,
 541                             dac33_lr_lom_texts);
 542
 543 static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
 544 SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
 545
 546 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 547         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 548         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 549
 550         SND_SOC_DAPM_INPUT("LINEL"),
 551         SND_SOC_DAPM_INPUT("LINER"),
 552
 553         SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
 554         SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
 555
 556         /* Analog bypass */
 557         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 558                                 &dac33_dapm_abypassl_control),
 559         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 560                                 &dac33_dapm_abypassr_control),
 561
 562         SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
 563                 &dac33_dapm_left_lom_control),
 564         SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
 565                 &dac33_dapm_right_lom_control),
 566         /*
 567          * For DAPM path, when only the anlog bypass path is enabled, and the
 568          * LOP inverted from the corresponding DAC side.
 569          * This is needed, so we can attach the DAC power supply in this case.
 570          */
 571         SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
 572         SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
 573
 574         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
 575                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 576         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
 577                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 578
 579         SND_SOC_DAPM_SUPPLY("Left DAC Power",
 580                             DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
 581         SND_SOC_DAPM_SUPPLY("Right DAC Power",
 582                             DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
 583
 584         SND_SOC_DAPM_SUPPLY("Codec Power",
 585                             DAC33_PWR_CTRL, 4, 0, NULL, 0),
 586
 587         SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
 588         SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
 589 };
 590
 591 static const struct snd_soc_dapm_route audio_map[] = {
 592         /* Analog bypass */
 593         {"Analog Left Bypass", "Switch", "LINEL"},
 594         {"Analog Right Bypass", "Switch", "LINER"},
 595
 596         {"Output Left Amplifier", NULL, "DACL"},
 597         {"Output Right Amplifier", NULL, "DACR"},
 598
 599         {"Left Bypass PGA", NULL, "Analog Left Bypass"},
 600         {"Right Bypass PGA", NULL, "Analog Right Bypass"},
 601
 602         {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
 603         {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
 604         {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
 605         {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
 606
 607         {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
 608         {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
 609
 610         {"DACL", NULL, "Left DAC Power"},
 611         {"DACR", NULL, "Right DAC Power"},
 612
 613         {"Left Bypass PGA", NULL, "Left DAC Power"},
 614         {"Right Bypass PGA", NULL, "Right DAC Power"},
 615
 616         /* output */
 617         {"LEFT_LO", NULL, "Output Left Amplifier"},
 618         {"RIGHT_LO", NULL, "Output Right Amplifier"},
 619
 620         {"LEFT_LO", NULL, "Codec Power"},
 621         {"RIGHT_LO", NULL, "Codec Power"},
 622 };
 623
 624 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 625                                 enum snd_soc_bias_level level)
 626 {
 627         int ret;
 628
 629         switch (level) {
 630         case SND_SOC_BIAS_ON:
 631                 break;
 632         case SND_SOC_BIAS_PREPARE:
 633                 break;
 634         case SND_SOC_BIAS_STANDBY:
 635                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 636                         /* Coming from OFF, switch on the codec */
 637                         ret = dac33_hard_power(codec, 1);
 638                         if (ret != 0)
 639                                 return ret;
 640
 641                         dac33_init_chip(codec);
 642                 }
 643                 break;
 644         case SND_SOC_BIAS_OFF:
 645                 /* Do not power off, when the codec is already off */
 646                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
 647                         return 0;
 648                 ret = dac33_hard_power(codec, 0);
 649                 if (ret != 0)
 650                         return ret;
 651                 break;
 652         }
 653
 654         return 0;
 655 }
 656
 657 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 658 {
 659         struct snd_soc_codec *codec = dac33->codec;
 660         unsigned int delay;
 661         unsigned long flags;
 662
 663         switch (dac33->fifo_mode) {
 664         case DAC33_FIFO_MODE1:
 665                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 666                         DAC33_THRREG(dac33->nsample));
 667
 668                 /* Take the timestamps */
 669                 spin_lock_irqsave(&dac33->lock, flags);
 670                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 671                 dac33->t_stamp1 = dac33->t_stamp2;
 672                 spin_unlock_irqrestore(&dac33->lock, flags);
 673
 674                 dac33_write16(codec, DAC33_PREFILL_MSB,
 675                                 DAC33_THRREG(dac33->alarm_threshold));
 676                 /* Enable Alarm Threshold IRQ with a delay */
 677                 delay = SAMPLES_TO_US(dac33->burst_rate,
 678                                      dac33->alarm_threshold) + 1000;
 679                 usleep_range(delay, delay + 500);
 680                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 681                 break;
 682         case DAC33_FIFO_MODE7:
 683                 /* Take the timestamp */
 684                 spin_lock_irqsave(&dac33->lock, flags);
 685                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 686                 /* Move back the timestamp with drain time */
 687                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 688                 spin_unlock_irqrestore(&dac33->lock, flags);
 689
 690                 dac33_write16(codec, DAC33_PREFILL_MSB,
 691                                 DAC33_THRREG(DAC33_MODE7_MARGIN));
 692
 693                 /* Enable Upper Threshold IRQ */
 694                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 695                 break;
 696         default:
 697                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 698                                                         dac33->fifo_mode);
 699                 break;
 700         }
 701 }
 702
 703 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 704 {
 705         struct snd_soc_codec *codec = dac33->codec;
 706         unsigned long flags;
 707
 708         switch (dac33->fifo_mode) {
 709         case DAC33_FIFO_MODE1:
 710                 /* Take the timestamp */
 711                 spin_lock_irqsave(&dac33->lock, flags);
 712                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 713                 spin_unlock_irqrestore(&dac33->lock, flags);
 714
 715                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 716                                 DAC33_THRREG(dac33->nsample));
 717                 break;
 718         case DAC33_FIFO_MODE7:
 719                 /* At the moment we are not using interrupts in mode7 */
 720                 break;
 721         default:
 722                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 723                                                         dac33->fifo_mode);
 724                 break;
 725         }
 726 }
 727
 728 static void dac33_work(struct work_struct *work)
 729 {
 730         struct snd_soc_codec *codec;
 731         struct tlv320dac33_priv *dac33;
 732         u8 reg;
 733
 734         dac33 = container_of(work, struct tlv320dac33_priv, work);
 735         codec = dac33->codec;
 736
 737         mutex_lock(&dac33->mutex);
 738         switch (dac33->state) {
 739         case DAC33_PREFILL:
 740                 dac33->state = DAC33_PLAYBACK;
 741                 dac33_prefill_handler(dac33);
 742                 break;
 743         case DAC33_PLAYBACK:
 744                 dac33_playback_handler(dac33);
 745                 break;
 746         case DAC33_IDLE:
 747                 break;
 748         case DAC33_FLUSH:
 749                 dac33->state = DAC33_IDLE;
 750                 /* Mask all interrupts from dac33 */
 751                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 752
 753                 /* flush fifo */
 754                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 755                 reg |= DAC33_FIFOFLUSH;
 756                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 757                 break;
 758         }
 759         mutex_unlock(&dac33->mutex);
 760 }
 761
 762 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 763 {
 764         struct snd_soc_codec *codec = dev;
 765         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 766         unsigned long flags;
 767
 768         spin_lock_irqsave(&dac33->lock, flags);
 769         dac33->t_stamp1 = ktime_to_us(ktime_get());
 770         spin_unlock_irqrestore(&dac33->lock, flags);
 771
 772         /* Do not schedule the workqueue in Mode7 */
 773         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 774                 queue_work(dac33->dac33_wq, &dac33->work);
 775
 776         return IRQ_HANDLED;
 777 }
 778
 779 static void dac33_oscwait(struct snd_soc_codec *codec)
 780 {
 781         int timeout = 60;
 782         u8 reg;
 783
 784         do {
 785                 usleep_range(1000, 2000);
 786                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 787         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 788         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 789                 dev_err(codec->dev,
 790                         "internal oscillator calibration failed\n");
 791 }
 792
 793 static int dac33_startup(struct snd_pcm_substream *substream,
 794                            struct snd_soc_dai *dai)
 795 {
 796         struct snd_soc_codec *codec = dai->codec;
 797         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 798
 799         /* Stream started, save the substream pointer */
 800         dac33->substream = substream;
 801
 802         return 0;
 803 }
 804
 805 static void dac33_shutdown(struct snd_pcm_substream *substream,
 806                              struct snd_soc_dai *dai)
 807 {
 808         struct snd_soc_codec *codec = dai->codec;
 809         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 810
 811         dac33->substream = NULL;
 812 }
 813
 814 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
 815         (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
 816 static int dac33_hw_params(struct snd_pcm_substream *substream,
 817                            struct snd_pcm_hw_params *params,
 818                            struct snd_soc_dai *dai)
 819 {
 820         struct snd_soc_codec *codec = dai->codec;
 821         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 822
 823         /* Check parameters for validity */
 824         switch (params_rate(params)) {
 825         case 44100:
 826         case 48000:
 827                 break;
 828         default:
 829                 dev_err(codec->dev, "unsupported rate %d\n",
 830                         params_rate(params));
 831                 return -EINVAL;
 832         }
 833
 834         switch (params_width(params)) {
 835         case 16:
 836                 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
 837                 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
 838                 break;
 839         case 32:
 840                 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
 841                 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
 842                 break;
 843         default:
 844                 dev_err(codec->dev, "unsupported width %d\n",
 845                         params_width(params));
 846                 return -EINVAL;
 847         }
 848
 849         return 0;
 850 }
 851
 852 #define CALC_OSCSET(rate, refclk) ( \
 853         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 854 #define CALC_RATIOSET(rate, refclk) ( \
 855         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 856
 857 /*
 858  * tlv320dac33 is strict on the sequence of the register writes, if the register
 859  * writes happens in different order, than dac33 might end up in unknown state.
 860  * Use the known, working sequence of register writes to initialize the dac33.
 861  */
 862 static int dac33_prepare_chip(struct snd_pcm_substream *substream,
 863                               struct snd_soc_codec *codec)
 864 {
 865         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 866         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 867         u8 aictrl_a, aictrl_b, fifoctrl_a;
 868
 869         switch (substream->runtime->rate) {
 870         case 44100:
 871         case 48000:
 872                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 873                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 874                                          dac33->refclk);
 875                 break;
 876         default:
 877                 dev_err(codec->dev, "unsupported rate %d\n",
 878                         substream->runtime->rate);
 879                 return -EINVAL;
 880         }
 881
 882
 883         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 884         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 885         /* Read FIFO control A, and clear FIFO flush bit */
 886         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 887         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 888
 889         fifoctrl_a &= ~DAC33_WIDTH;
 890         switch (substream->runtime->format) {
 891         case SNDRV_PCM_FORMAT_S16_LE:
 892                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 893                 fifoctrl_a |= DAC33_WIDTH;
 894                 break;
 895         case SNDRV_PCM_FORMAT_S32_LE:
 896                 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
 897                 break;
 898         default:
 899                 dev_err(codec->dev, "unsupported format %d\n",
 900                         substream->runtime->format);
 901                 return -EINVAL;
 902         }
 903
 904         mutex_lock(&dac33->mutex);
 905
 906         if (!dac33->chip_power) {
 907                 /*
 908                  * Chip is not powered yet.
 909                  * Do the init in the dac33_set_bias_level later.
 910                  */
 911                 mutex_unlock(&dac33->mutex);
 912                 return 0;
 913         }
 914
 915         dac33_soft_power(codec, 0);
 916         dac33_soft_power(codec, 1);
 917
 918         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 919         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 920
 921         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 922         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 923
 924         /* OSC calibration time */
 925         dac33_write(codec, DAC33_CALIB_TIME, 96);
 926
 927         /* adjustment treshold & step */
 928         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 929                                                  DAC33_ADJSTEP(1));
 930
 931         /* div=4 / gain=1 / div */
 932         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 933
 934         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 935         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 936         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 937
 938         dac33_oscwait(codec);
 939
 940         if (dac33->fifo_mode) {
 941                 /* Generic for all FIFO modes */
 942                 /* 50-51 : ASRC Control registers */
 943                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 944                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 945
 946                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 947                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 948
 949                 /* Set interrupts to high active */
 950                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 951         } else {
 952                 /* FIFO bypass mode */
 953                 /* 50-51 : ASRC Control registers */
 954                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 955                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 956         }
 957
 958         /* Interrupt behaviour configuration */
 959         switch (dac33->fifo_mode) {
 960         case DAC33_FIFO_MODE1:
 961                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 962                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 963                 break;
 964         case DAC33_FIFO_MODE7:
 965                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
 966                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
 967                 break;
 968         default:
 969                 /* in FIFO bypass mode, the interrupts are not used */
 970                 break;
 971         }
 972
 973         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 974
 975         switch (dac33->fifo_mode) {
 976         case DAC33_FIFO_MODE1:
 977                 /*
 978                  * For mode1:
 979                  * Disable the FIFO bypass (Enable the use of FIFO)
 980                  * Select nSample mode
 981                  * BCLK is only running when data is needed by DAC33
 982                  */
 983                 fifoctrl_a &= ~DAC33_FBYPAS;
 984                 fifoctrl_a &= ~DAC33_FAUTO;
 985                 if (dac33->keep_bclk)
 986                         aictrl_b |= DAC33_BCLKON;
 987                 else
 988                         aictrl_b &= ~DAC33_BCLKON;
 989                 break;
 990         case DAC33_FIFO_MODE7:
 991                 /*
 992                  * For mode1:
 993                  * Disable the FIFO bypass (Enable the use of FIFO)
 994                  * Select Threshold mode
 995                  * BCLK is only running when data is needed by DAC33
 996                  */
 997                 fifoctrl_a &= ~DAC33_FBYPAS;
 998                 fifoctrl_a |= DAC33_FAUTO;
 999                 if (dac33->keep_bclk)
1000                         aictrl_b |= DAC33_BCLKON;
1001                 else
1002                         aictrl_b &= ~DAC33_BCLKON;
1003                 break;
1004         default:
1005                 /*
1006                  * For FIFO bypass mode:
1007                  * Enable the FIFO bypass (Disable the FIFO use)
1008                  * Set the BCLK as continuous
1009                  */
1010                 fifoctrl_a |= DAC33_FBYPAS;
1011                 aictrl_b |= DAC33_BCLKON;
1012                 break;
1013         }
1014
1015         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1016         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1017         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1018
1019         /*
1020          * BCLK divide ratio
1021          * 0: 1.5
1022          * 1: 1
1023          * 2: 2
1024          * ...
1025          * 254: 254
1026          * 255: 255
1027          */
1028         if (dac33->fifo_mode)
1029                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1030                                                         dac33->burst_bclkdiv);
1031         else
1032                 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1033                         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1034                 else
1035                         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
1036
1037         switch (dac33->fifo_mode) {
1038         case DAC33_FIFO_MODE1:
1039                 dac33_write16(codec, DAC33_ATHR_MSB,
1040                               DAC33_THRREG(dac33->alarm_threshold));
1041                 break;
1042         case DAC33_FIFO_MODE7:
1043                 /*
1044                  * Configure the threshold levels, and leave 10 sample space
1045                  * at the bottom, and also at the top of the FIFO
1046                  */
1047                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1048                 dac33_write16(codec, DAC33_LTHR_MSB,
1049                               DAC33_THRREG(DAC33_MODE7_MARGIN));
1050                 break;
1051         default:
1052                 break;
1053         }
1054
1055         mutex_unlock(&dac33->mutex);
1056
1057         return 0;
1058 }
1059
1060 static void dac33_calculate_times(struct snd_pcm_substream *substream,
1061                                   struct snd_soc_codec *codec)
1062 {
1063         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1064         unsigned int period_size = substream->runtime->period_size;
1065         unsigned int rate = substream->runtime->rate;
1066         unsigned int nsample_limit;
1067
1068         /* In bypass mode we don't need to calculate */
1069         if (!dac33->fifo_mode)
1070                 return;
1071
1072         switch (dac33->fifo_mode) {
1073         case DAC33_FIFO_MODE1:
1074                 /* Number of samples under i2c latency */
1075                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1076                                                 dac33->mode1_latency);
1077                 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1078
1079                 if (period_size <= dac33->alarm_threshold)
1080                         /*
1081                          * Configure nSamaple to number of periods,
1082                          * which covers the latency requironment.
1083                          */
1084                         dac33->nsample = period_size *
1085                                 ((dac33->alarm_threshold / period_size) +
1086                                 (dac33->alarm_threshold % period_size ?
1087                                 1 : 0));
1088                 else if (period_size > nsample_limit)
1089                         dac33->nsample = nsample_limit;
1090                 else
1091                         dac33->nsample = period_size;
1092
1093                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1094                                                       dac33->nsample);
1095                 dac33->t_stamp1 = 0;
1096                 dac33->t_stamp2 = 0;
1097                 break;
1098         case DAC33_FIFO_MODE7:
1099                 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1100                                                     dac33->burst_rate) + 9;
1101                 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1102                         dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1103                 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1104                         dac33->uthr = (DAC33_MODE7_MARGIN + 10);
1105
1106                 dac33->mode7_us_to_lthr =
1107                                 SAMPLES_TO_US(substream->runtime->rate,
1108                                         dac33->uthr - DAC33_MODE7_MARGIN + 1);
1109                 dac33->t_stamp1 = 0;
1110                 break;
1111         default:
1112                 break;
1113         }
1114
1115 }
1116
1117 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1118                              struct snd_soc_dai *dai)
1119 {
1120         struct snd_soc_codec *codec = dai->codec;
1121         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1122         int ret = 0;
1123
1124         switch (cmd) {
1125         case SNDRV_PCM_TRIGGER_START:
1126         case SNDRV_PCM_TRIGGER_RESUME:
1127         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1128                 if (dac33->fifo_mode) {
1129                         dac33->state = DAC33_PREFILL;
1130                         queue_work(dac33->dac33_wq, &dac33->work);
1131                 }
1132                 break;
1133         case SNDRV_PCM_TRIGGER_STOP:
1134         case SNDRV_PCM_TRIGGER_SUSPEND:
1135         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1136                 if (dac33->fifo_mode) {
1137                         dac33->state = DAC33_FLUSH;
1138                         queue_work(dac33->dac33_wq, &dac33->work);
1139                 }
1140                 break;
1141         default:
1142                 ret = -EINVAL;
1143         }
1144
1145         return ret;
1146 }
1147
1148 static snd_pcm_sframes_t dac33_dai_delay(
1149                         struct snd_pcm_substream *substream,
1150                         struct snd_soc_dai *dai)
1151 {
1152         struct snd_soc_codec *codec = dai->codec;
1153         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1154         unsigned long long t0, t1, t_now;
1155         unsigned int time_delta, uthr;
1156         int samples_out, samples_in, samples;
1157         snd_pcm_sframes_t delay = 0;
1158         unsigned long flags;
1159
1160         switch (dac33->fifo_mode) {
1161         case DAC33_FIFO_BYPASS:
1162                 break;
1163         case DAC33_FIFO_MODE1:
1164                 spin_lock_irqsave(&dac33->lock, flags);
1165                 t0 = dac33->t_stamp1;
1166                 t1 = dac33->t_stamp2;
1167                 spin_unlock_irqrestore(&dac33->lock, flags);
1168                 t_now = ktime_to_us(ktime_get());
1169
1170                 /* We have not started to fill the FIFO yet, delay is 0 */
1171                 if (!t1)
1172                         goto out;
1173
1174                 if (t0 > t1) {
1175                         /*
1176                          * Phase 1:
1177                          * After Alarm threshold, and before nSample write
1178                          */
1179                         time_delta = t_now - t0;
1180                         samples_out = time_delta ? US_TO_SAMPLES(
1181                                                 substream->runtime->rate,
1182                                                 time_delta) : 0;
1183
1184                         if (likely(dac33->alarm_threshold > samples_out))
1185                                 delay = dac33->alarm_threshold - samples_out;
1186                         else
1187                                 delay = 0;
1188                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1189                         /*
1190                          * Phase 2:
1191                          * After nSample write (during burst operation)
1192                          */
1193                         time_delta = t_now - t0;
1194                         samples_out = time_delta ? US_TO_SAMPLES(
1195                                                 substream->runtime->rate,
1196                                                 time_delta) : 0;
1197
1198                         time_delta = t_now - t1;
1199                         samples_in = time_delta ? US_TO_SAMPLES(
1200                                                 dac33->burst_rate,
1201                                                 time_delta) : 0;
1202
1203                         samples = dac33->alarm_threshold;
1204                         samples += (samples_in - samples_out);
1205
1206                         if (likely(samples > 0))
1207                                 delay = samples;
1208                         else
1209                                 delay = 0;
1210                 } else {
1211                         /*
1212                          * Phase 3:
1213                          * After burst operation, before next alarm threshold
1214                          */
1215                         time_delta = t_now - t0;
1216                         samples_out = time_delta ? US_TO_SAMPLES(
1217                                                 substream->runtime->rate,
1218                                                 time_delta) : 0;
1219
1220                         samples_in = dac33->nsample;
1221                         samples = dac33->alarm_threshold;
1222                         samples += (samples_in - samples_out);
1223
1224                         if (likely(samples > 0))
1225                                 delay = samples > dac33->fifo_size ?
1226                                         dac33->fifo_size : samples;
1227                         else
1228                                 delay = 0;
1229                 }
1230                 break;
1231         case DAC33_FIFO_MODE7:
1232                 spin_lock_irqsave(&dac33->lock, flags);
1233                 t0 = dac33->t_stamp1;
1234                 uthr = dac33->uthr;
1235                 spin_unlock_irqrestore(&dac33->lock, flags);
1236                 t_now = ktime_to_us(ktime_get());
1237
1238                 /* We have not started to fill the FIFO yet, delay is 0 */
1239                 if (!t0)
1240                         goto out;
1241
1242                 if (t_now <= t0) {
1243                         /*
1244                          * Either the timestamps are messed or equal. Report
1245                          * maximum delay
1246                          */
1247                         delay = uthr;
1248                         goto out;
1249                 }
1250
1251                 time_delta = t_now - t0;
1252                 if (time_delta <= dac33->mode7_us_to_lthr) {
1253                         /*
1254                         * Phase 1:
1255                         * After burst (draining phase)
1256                         */
1257                         samples_out = US_TO_SAMPLES(
1258                                         substream->runtime->rate,
1259                                         time_delta);
1260
1261                         if (likely(uthr > samples_out))
1262                                 delay = uthr - samples_out;
1263                         else
1264                                 delay = 0;
1265                 } else {
1266                         /*
1267                         * Phase 2:
1268                         * During burst operation
1269                         */
1270                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1271
1272                         samples_out = US_TO_SAMPLES(
1273                                         substream->runtime->rate,
1274                                         time_delta);
1275                         samples_in = US_TO_SAMPLES(
1276                                         dac33->burst_rate,
1277                                         time_delta);
1278                         delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
1279
1280                         if (unlikely(delay > uthr))
1281                                 delay = uthr;
1282                 }
1283                 break;
1284         default:
1285                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1286                                                         dac33->fifo_mode);
1287                 break;
1288         }
1289 out:
1290         return delay;
1291 }
1292
1293 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1294                 int clk_id, unsigned int freq, int dir)
1295 {
1296         struct snd_soc_codec *codec = codec_dai->codec;
1297         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1298         u8 ioc_reg, asrcb_reg;
1299
1300         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1301         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1302         switch (clk_id) {
1303         case TLV320DAC33_MCLK:
1304                 ioc_reg |= DAC33_REFSEL;
1305                 asrcb_reg |= DAC33_SRCREFSEL;
1306                 break;
1307         case TLV320DAC33_SLEEPCLK:
1308                 ioc_reg &= ~DAC33_REFSEL;
1309                 asrcb_reg &= ~DAC33_SRCREFSEL;
1310                 break;
1311         default:
1312                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1313                 break;
1314         }
1315         dac33->refclk = freq;
1316
1317         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1318         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1319
1320         return 0;
1321 }
1322
1323 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1324                              unsigned int fmt)
1325 {
1326         struct snd_soc_codec *codec = codec_dai->codec;
1327         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1328         u8 aictrl_a, aictrl_b;
1329
1330         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1331         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1332         /* set master/slave audio interface */
1333         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1334         case SND_SOC_DAIFMT_CBM_CFM:
1335                 /* Codec Master */
1336                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1337                 break;
1338         case SND_SOC_DAIFMT_CBS_CFS:
1339                 /* Codec Slave */
1340                 if (dac33->fifo_mode) {
1341                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1342                         return -EINVAL;
1343                 } else
1344                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1345                 break;
1346         default:
1347                 return -EINVAL;
1348         }
1349
1350         aictrl_a &= ~DAC33_AFMT_MASK;
1351         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1352         case SND_SOC_DAIFMT_I2S:
1353                 aictrl_a |= DAC33_AFMT_I2S;
1354                 break;
1355         case SND_SOC_DAIFMT_DSP_A:
1356                 aictrl_a |= DAC33_AFMT_DSP;
1357                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1358                 aictrl_b |= DAC33_DATA_DELAY(0);
1359                 break;
1360         case SND_SOC_DAIFMT_RIGHT_J:
1361                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1362                 break;
1363         case SND_SOC_DAIFMT_LEFT_J:
1364                 aictrl_a |= DAC33_AFMT_LEFT_J;
1365                 break;
1366         default:
1367                 dev_err(codec->dev, "Unsupported format (%u)\n",
1368                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1369                 return -EINVAL;
1370         }
1371
1372         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1373         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1374
1375         return 0;
1376 }
1377
1378 static int dac33_soc_probe(struct snd_soc_codec *codec)
1379 {
1380         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1381         int ret = 0;
1382
1383         codec->control_data = dac33->control_data;
1384         codec->hw_write = (hw_write_t) i2c_master_send;
1385         dac33->codec = codec;
1386
1387         /* Read the tlv320dac33 ID registers */
1388         ret = dac33_hard_power(codec, 1);
1389         if (ret != 0) {
1390                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1391                 goto err_power;
1392         }
1393         ret = dac33_read_id(codec);
1394         dac33_hard_power(codec, 0);
1395
1396         if (ret < 0) {
1397                 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1398                 ret = -ENODEV;
1399                 goto err_power;
1400         }
1401
1402         /* Check if the IRQ number is valid and request it */
1403         if (dac33->irq >= 0) {
1404                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1405                                   IRQF_TRIGGER_RISING,
1406                                   codec->component.name, codec);
1407                 if (ret < 0) {
1408                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1409                                                 dac33->irq, ret);
1410                         dac33->irq = -1;
1411                 }
1412                 if (dac33->irq != -1) {
1413                         /* Setup work queue */
1414                         dac33->dac33_wq =
1415                                 create_singlethread_workqueue("tlv320dac33");
1416                         if (dac33->dac33_wq == NULL) {
1417                                 free_irq(dac33->irq, codec);
1418                                 return -ENOMEM;
1419                         }
1420
1421                         INIT_WORK(&dac33->work, dac33_work);
1422                 }
1423         }
1424
1425         /* Only add the FIFO controls, if we have valid IRQ number */
1426         if (dac33->irq >= 0)
1427                 snd_soc_add_codec_controls(codec, dac33_mode_snd_controls,
1428                                      ARRAY_SIZE(dac33_mode_snd_controls));
1429
1430 err_power:
1431         return ret;
1432 }
1433
1434 static int dac33_soc_remove(struct snd_soc_codec *codec)
1435 {
1436         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1437
1438         if (dac33->irq >= 0) {
1439                 free_irq(dac33->irq, dac33->codec);
1440                 destroy_workqueue(dac33->dac33_wq);
1441         }
1442         return 0;
1443 }
1444
1445 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1446         .read = dac33_read_reg_cache,
1447         .write = dac33_write_locked,
1448         .set_bias_level = dac33_set_bias_level,
1449         .idle_bias_off = true,
1450         .reg_cache_size = ARRAY_SIZE(dac33_reg),
1451         .reg_word_size = sizeof(u8),
1452         .reg_cache_default = dac33_reg,
1453         .probe = dac33_soc_probe,
1454         .remove = dac33_soc_remove,
1455
1456         .component_driver = {
1457                 .controls               = dac33_snd_controls,
1458                 .num_controls           = ARRAY_SIZE(dac33_snd_controls),
1459                 .dapm_widgets           = dac33_dapm_widgets,
1460                 .num_dapm_widgets       = ARRAY_SIZE(dac33_dapm_widgets),
1461                 .dapm_routes            = audio_map,
1462                 .num_dapm_routes        = ARRAY_SIZE(audio_map),
1463         },
1464 };
1465
1466 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1467                          SNDRV_PCM_RATE_48000)
1468 #define DAC33_FORMATS   (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1469
1470 static const struct snd_soc_dai_ops dac33_dai_ops = {
1471         .startup        = dac33_startup,
1472         .shutdown       = dac33_shutdown,
1473         .hw_params      = dac33_hw_params,
1474         .trigger        = dac33_pcm_trigger,
1475         .delay          = dac33_dai_delay,
1476         .set_sysclk     = dac33_set_dai_sysclk,
1477         .set_fmt        = dac33_set_dai_fmt,
1478 };
1479
1480 static struct snd_soc_dai_driver dac33_dai = {
1481         .name = "tlv320dac33-hifi",
1482         .playback = {
1483                 .stream_name = "Playback",
1484                 .channels_min = 2,
1485                 .channels_max = 2,
1486                 .rates = DAC33_RATES,
1487                 .formats = DAC33_FORMATS,
1488                 .sig_bits = 24,
1489         },
1490         .ops = &dac33_dai_ops,
1491 };
1492
1493 static int dac33_i2c_probe(struct i2c_client *client,
1494                            const struct i2c_device_id *id)
1495 {
1496         struct tlv320dac33_platform_data *pdata;
1497         struct tlv320dac33_priv *dac33;
1498         int ret, i;
1499
1500         if (client->dev.platform_data == NULL) {
1501                 dev_err(&client->dev, "Platform data not set\n");
1502                 return -ENODEV;
1503         }
1504         pdata = client->dev.platform_data;
1505
1506         dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv),
1507                              GFP_KERNEL);
1508         if (dac33 == NULL)
1509                 return -ENOMEM;
1510
1511         dac33->control_data = client;
1512         mutex_init(&dac33->mutex);
1513         spin_lock_init(&dac33->lock);
1514
1515         i2c_set_clientdata(client, dac33);
1516
1517         dac33->power_gpio = pdata->power_gpio;
1518         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1519         dac33->keep_bclk = pdata->keep_bclk;
1520         dac33->mode1_latency = pdata->mode1_latency;
1521         if (!dac33->mode1_latency)
1522                 dac33->mode1_latency = 10000; /* 10ms */
1523         dac33->irq = client->irq;
1524         /* Disable FIFO use by default */
1525         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1526
1527         /* Check if the reset GPIO number is valid and request it */
1528         if (dac33->power_gpio >= 0) {
1529                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1530                 if (ret < 0) {
1531                         dev_err(&client->dev,
1532                                 "Failed to request reset GPIO (%d)\n",
1533                                 dac33->power_gpio);
1534                         goto err_gpio;
1535                 }
1536                 gpio_direction_output(dac33->power_gpio, 0);
1537         }
1538
1539         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1540                 dac33->supplies[i].supply = dac33_supply_names[i];
1541
1542         ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1543                                  dac33->supplies);
1544
1545         if (ret != 0) {
1546                 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1547                 goto err_get;
1548         }
1549
1550         ret = snd_soc_register_codec(&client->dev,
1551                         &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1552         if (ret < 0)
1553                 goto err_get;
1554
1555         return ret;
1556 err_get:
1557         if (dac33->power_gpio >= 0)
1558                 gpio_free(dac33->power_gpio);
1559 err_gpio:
1560         return ret;
1561 }
1562
1563 static int dac33_i2c_remove(struct i2c_client *client)
1564 {
1565         struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1566
1567         if (unlikely(dac33->chip_power))
1568                 dac33_hard_power(dac33->codec, 0);
1569
1570         if (dac33->power_gpio >= 0)
1571                 gpio_free(dac33->power_gpio);
1572
1573         snd_soc_unregister_codec(&client->dev);
1574         return 0;
1575 }
1576
1577 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1578         {
1579                 .name = "tlv320dac33",
1580                 .driver_data = 0,
1581         },
1582         { },
1583 };
1584 MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id);
1585
1586 static struct i2c_driver tlv320dac33_i2c_driver = {
1587         .driver = {
1588                 .name = "tlv320dac33-codec",
1589         },
1590         .probe          = dac33_i2c_probe,
1591         .remove         = dac33_i2c_remove,
1592         .id_table       = tlv320dac33_i2c_id,
1593 };
1594
1595 module_i2c_driver(tlv320dac33_i2c_driver);
1596
1597 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1598 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1599 MODULE_LICENSE("GPL");