2 * skl-sst-ipc.c - Intel skl IPC Support
4 * Copyright (C) 2014-15, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as version 2, as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 #include <linux/device.h>
17 #include "../common/sst-dsp.h"
18 #include "../common/sst-dsp-priv.h"
20 #include "skl-sst-dsp.h"
21 #include "skl-sst-ipc.h"
22 #include "sound/hdaudio_ext.h"
25 #define IPC_IXC_STATUS_BITS 24
27 /* Global Message - Generic */
28 #define IPC_GLB_TYPE_SHIFT 24
29 #define IPC_GLB_TYPE_MASK (0xf << IPC_GLB_TYPE_SHIFT)
30 #define IPC_GLB_TYPE(x) ((x) << IPC_GLB_TYPE_SHIFT)
32 /* Global Message - Reply */
33 #define IPC_GLB_REPLY_STATUS_SHIFT 24
34 #define IPC_GLB_REPLY_STATUS_MASK ((0x1 << IPC_GLB_REPLY_STATUS_SHIFT) - 1)
35 #define IPC_GLB_REPLY_STATUS(x) ((x) << IPC_GLB_REPLY_STATUS_SHIFT)
37 #define IPC_TIMEOUT_MSECS 3000
39 #define IPC_EMPTY_LIST_SIZE 8
41 #define IPC_MSG_TARGET_SHIFT 30
42 #define IPC_MSG_TARGET_MASK 0x1
43 #define IPC_MSG_TARGET(x) (((x) & IPC_MSG_TARGET_MASK) \
44 << IPC_MSG_TARGET_SHIFT)
46 #define IPC_MSG_DIR_SHIFT 29
47 #define IPC_MSG_DIR_MASK 0x1
48 #define IPC_MSG_DIR(x) (((x) & IPC_MSG_DIR_MASK) \
50 /* Global Notification Message */
51 #define IPC_GLB_NOTIFY_TYPE_SHIFT 16
52 #define IPC_GLB_NOTIFY_TYPE_MASK 0xFF
53 #define IPC_GLB_NOTIFY_TYPE(x) (((x) >> IPC_GLB_NOTIFY_TYPE_SHIFT) \
54 & IPC_GLB_NOTIFY_TYPE_MASK)
56 #define IPC_GLB_NOTIFY_MSG_TYPE_SHIFT 24
57 #define IPC_GLB_NOTIFY_MSG_TYPE_MASK 0x1F
58 #define IPC_GLB_NOTIFY_MSG_TYPE(x) (((x) >> IPC_GLB_NOTIFY_MSG_TYPE_SHIFT) \
59 & IPC_GLB_NOTIFY_MSG_TYPE_MASK)
61 #define IPC_GLB_NOTIFY_RSP_SHIFT 29
62 #define IPC_GLB_NOTIFY_RSP_MASK 0x1
63 #define IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> IPC_GLB_NOTIFY_RSP_SHIFT) \
64 & IPC_GLB_NOTIFY_RSP_MASK)
66 /* Pipeline operations */
68 /* Create pipeline message */
69 #define IPC_PPL_MEM_SIZE_SHIFT 0
70 #define IPC_PPL_MEM_SIZE_MASK 0x7FF
71 #define IPC_PPL_MEM_SIZE(x) (((x) & IPC_PPL_MEM_SIZE_MASK) \
72 << IPC_PPL_MEM_SIZE_SHIFT)
74 #define IPC_PPL_TYPE_SHIFT 11
75 #define IPC_PPL_TYPE_MASK 0x1F
76 #define IPC_PPL_TYPE(x) (((x) & IPC_PPL_TYPE_MASK) \
77 << IPC_PPL_TYPE_SHIFT)
79 #define IPC_INSTANCE_ID_SHIFT 16
80 #define IPC_INSTANCE_ID_MASK 0xFF
81 #define IPC_INSTANCE_ID(x) (((x) & IPC_INSTANCE_ID_MASK) \
82 << IPC_INSTANCE_ID_SHIFT)
84 /* Set pipeline state message */
85 #define IPC_PPL_STATE_SHIFT 0
86 #define IPC_PPL_STATE_MASK 0x1F
87 #define IPC_PPL_STATE(x) (((x) & IPC_PPL_STATE_MASK) \
88 << IPC_PPL_STATE_SHIFT)
90 /* Module operations primary register */
91 #define IPC_MOD_ID_SHIFT 0
92 #define IPC_MOD_ID_MASK 0xFFFF
93 #define IPC_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
96 #define IPC_MOD_INSTANCE_ID_SHIFT 16
97 #define IPC_MOD_INSTANCE_ID_MASK 0xFF
98 #define IPC_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
99 << IPC_MOD_INSTANCE_ID_SHIFT)
101 /* Init instance message extension register */
102 #define IPC_PARAM_BLOCK_SIZE_SHIFT 0
103 #define IPC_PARAM_BLOCK_SIZE_MASK 0xFFFF
104 #define IPC_PARAM_BLOCK_SIZE(x) (((x) & IPC_PARAM_BLOCK_SIZE_MASK) \
105 << IPC_PARAM_BLOCK_SIZE_SHIFT)
107 #define IPC_PPL_INSTANCE_ID_SHIFT 16
108 #define IPC_PPL_INSTANCE_ID_MASK 0xFF
109 #define IPC_PPL_INSTANCE_ID(x) (((x) & IPC_PPL_INSTANCE_ID_MASK) \
110 << IPC_PPL_INSTANCE_ID_SHIFT)
112 #define IPC_CORE_ID_SHIFT 24
113 #define IPC_CORE_ID_MASK 0x1F
114 #define IPC_CORE_ID(x) (((x) & IPC_CORE_ID_MASK) \
115 << IPC_CORE_ID_SHIFT)
117 #define IPC_DOMAIN_SHIFT 28
118 #define IPC_DOMAIN_MASK 0x1
119 #define IPC_DOMAIN(x) (((x) & IPC_DOMAIN_MASK) \
122 /* Bind/Unbind message extension register */
123 #define IPC_DST_MOD_ID_SHIFT 0
124 #define IPC_DST_MOD_ID(x) (((x) & IPC_MOD_ID_MASK) \
125 << IPC_DST_MOD_ID_SHIFT)
127 #define IPC_DST_MOD_INSTANCE_ID_SHIFT 16
128 #define IPC_DST_MOD_INSTANCE_ID(x) (((x) & IPC_MOD_INSTANCE_ID_MASK) \
129 << IPC_DST_MOD_INSTANCE_ID_SHIFT)
131 #define IPC_DST_QUEUE_SHIFT 24
132 #define IPC_DST_QUEUE_MASK 0x7
133 #define IPC_DST_QUEUE(x) (((x) & IPC_DST_QUEUE_MASK) \
134 << IPC_DST_QUEUE_SHIFT)
136 #define IPC_SRC_QUEUE_SHIFT 27
137 #define IPC_SRC_QUEUE_MASK 0x7
138 #define IPC_SRC_QUEUE(x) (((x) & IPC_SRC_QUEUE_MASK) \
139 << IPC_SRC_QUEUE_SHIFT)
140 /* Load Module count */
141 #define IPC_LOAD_MODULE_SHIFT 0
142 #define IPC_LOAD_MODULE_MASK 0xFF
143 #define IPC_LOAD_MODULE_CNT(x) (((x) & IPC_LOAD_MODULE_MASK) \
144 << IPC_LOAD_MODULE_SHIFT)
146 /* Save pipeline messgae extension register */
147 #define IPC_DMA_ID_SHIFT 0
148 #define IPC_DMA_ID_MASK 0x1F
149 #define IPC_DMA_ID(x) (((x) & IPC_DMA_ID_MASK) \
151 /* Large Config message extension register */
152 #define IPC_DATA_OFFSET_SZ_SHIFT 0
153 #define IPC_DATA_OFFSET_SZ_MASK 0xFFFFF
154 #define IPC_DATA_OFFSET_SZ(x) (((x) & IPC_DATA_OFFSET_SZ_MASK) \
155 << IPC_DATA_OFFSET_SZ_SHIFT)
156 #define IPC_DATA_OFFSET_SZ_CLEAR ~(IPC_DATA_OFFSET_SZ_MASK \
157 << IPC_DATA_OFFSET_SZ_SHIFT)
159 #define IPC_LARGE_PARAM_ID_SHIFT 20
160 #define IPC_LARGE_PARAM_ID_MASK 0xFF
161 #define IPC_LARGE_PARAM_ID(x) (((x) & IPC_LARGE_PARAM_ID_MASK) \
162 << IPC_LARGE_PARAM_ID_SHIFT)
164 #define IPC_FINAL_BLOCK_SHIFT 28
165 #define IPC_FINAL_BLOCK_MASK 0x1
166 #define IPC_FINAL_BLOCK(x) (((x) & IPC_FINAL_BLOCK_MASK) \
167 << IPC_FINAL_BLOCK_SHIFT)
169 #define IPC_INITIAL_BLOCK_SHIFT 29
170 #define IPC_INITIAL_BLOCK_MASK 0x1
171 #define IPC_INITIAL_BLOCK(x) (((x) & IPC_INITIAL_BLOCK_MASK) \
172 << IPC_INITIAL_BLOCK_SHIFT)
173 #define IPC_INITIAL_BLOCK_CLEAR ~(IPC_INITIAL_BLOCK_MASK \
174 << IPC_INITIAL_BLOCK_SHIFT)
176 enum skl_ipc_msg_target {
181 enum skl_ipc_msg_direction {
186 /* Global Message Types */
187 enum skl_ipc_glb_type {
188 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
189 IPC_GLB_LOAD_MULTIPLE_MODS = 15,
190 IPC_GLB_UNLOAD_MULTIPLE_MODS = 16,
191 IPC_GLB_CREATE_PPL = 17,
192 IPC_GLB_DELETE_PPL = 18,
193 IPC_GLB_SET_PPL_STATE = 19,
194 IPC_GLB_GET_PPL_STATE = 20,
195 IPC_GLB_GET_PPL_CONTEXT_SIZE = 21,
196 IPC_GLB_SAVE_PPL = 22,
197 IPC_GLB_RESTORE_PPL = 23,
198 IPC_GLB_LOAD_LIBRARY = 24,
200 IPC_GLB_MAX_IPC_MSG_NUMBER = 31 /* Maximum message number */
203 enum skl_ipc_glb_reply {
204 IPC_GLB_REPLY_SUCCESS = 0,
206 IPC_GLB_REPLY_UNKNOWN_MSG_TYPE = 1,
207 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 2,
209 IPC_GLB_REPLY_BUSY = 3,
210 IPC_GLB_REPLY_PENDING = 4,
211 IPC_GLB_REPLY_FAILURE = 5,
212 IPC_GLB_REPLY_INVALID_REQUEST = 6,
214 IPC_GLB_REPLY_OUT_OF_MEMORY = 7,
215 IPC_GLB_REPLY_OUT_OF_MIPS = 8,
217 IPC_GLB_REPLY_INVALID_RESOURCE_ID = 9,
218 IPC_GLB_REPLY_INVALID_RESOURCE_STATE = 10,
220 IPC_GLB_REPLY_MOD_MGMT_ERROR = 100,
221 IPC_GLB_REPLY_MOD_LOAD_CL_FAILED = 101,
222 IPC_GLB_REPLY_MOD_LOAD_INVALID_HASH = 102,
224 IPC_GLB_REPLY_MOD_UNLOAD_INST_EXIST = 103,
225 IPC_GLB_REPLY_MOD_NOT_INITIALIZED = 104,
227 IPC_GLB_REPLY_INVALID_CONFIG_PARAM_ID = 120,
228 IPC_GLB_REPLY_INVALID_CONFIG_DATA_LEN = 121,
229 IPC_GLB_REPLY_GATEWAY_NOT_INITIALIZED = 140,
230 IPC_GLB_REPLY_GATEWAY_NOT_EXIST = 141,
232 IPC_GLB_REPLY_PPL_NOT_INITIALIZED = 160,
233 IPC_GLB_REPLY_PPL_NOT_EXIST = 161,
234 IPC_GLB_REPLY_PPL_SAVE_FAILED = 162,
235 IPC_GLB_REPLY_PPL_RESTORE_FAILED = 163,
237 IPC_MAX_STATUS = ((1<<IPC_IXC_STATUS_BITS)-1)
240 enum skl_ipc_notification_type {
241 IPC_GLB_NOTIFY_GLITCH = 0,
242 IPC_GLB_NOTIFY_OVERRUN = 1,
243 IPC_GLB_NOTIFY_UNDERRUN = 2,
244 IPC_GLB_NOTIFY_END_STREAM = 3,
245 IPC_GLB_NOTIFY_PHRASE_DETECTED = 4,
246 IPC_GLB_NOTIFY_RESOURCE_EVENT = 5,
247 IPC_GLB_NOTIFY_LOG_BUFFER_STATUS = 6,
248 IPC_GLB_NOTIFY_TIMESTAMP_CAPTURED = 7,
249 IPC_GLB_NOTIFY_FW_READY = 8
252 /* Module Message Types */
253 enum skl_ipc_module_msg {
254 IPC_MOD_INIT_INSTANCE = 0,
255 IPC_MOD_CONFIG_GET = 1,
256 IPC_MOD_CONFIG_SET = 2,
257 IPC_MOD_LARGE_CONFIG_GET = 3,
258 IPC_MOD_LARGE_CONFIG_SET = 4,
264 static void skl_ipc_tx_data_copy(struct ipc_message *msg, char *tx_data,
268 memcpy(msg->tx_data, tx_data, tx_size);
271 static bool skl_ipc_is_dsp_busy(struct sst_dsp *dsp)
275 hipci = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCI);
276 return (hipci & SKL_ADSP_REG_HIPCI_BUSY);
279 /* Lock to be held by caller */
280 static void skl_ipc_tx_msg(struct sst_generic_ipc *ipc, struct ipc_message *msg)
282 struct skl_ipc_header *header = (struct skl_ipc_header *)(&msg->header);
285 sst_dsp_outbox_write(ipc->dsp, msg->tx_data, msg->tx_size);
286 sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCIE,
288 sst_dsp_shim_write_unlocked(ipc->dsp, SKL_ADSP_REG_HIPCI,
289 header->primary | SKL_ADSP_REG_HIPCI_BUSY);
292 static struct ipc_message *skl_ipc_reply_get_msg(struct sst_generic_ipc *ipc,
295 struct ipc_message *msg = NULL;
296 struct skl_ipc_header *header = (struct skl_ipc_header *)(&ipc_header);
298 if (list_empty(&ipc->rx_list)) {
299 dev_err(ipc->dev, "ipc: rx list is empty but received 0x%x\n",
304 msg = list_first_entry(&ipc->rx_list, struct ipc_message, list);
311 static int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
312 struct skl_ipc_header header)
314 struct skl_sst *skl = container_of(ipc, struct skl_sst, ipc);
316 if (IPC_GLB_NOTIFY_MSG_TYPE(header.primary)) {
317 switch (IPC_GLB_NOTIFY_TYPE(header.primary)) {
319 case IPC_GLB_NOTIFY_UNDERRUN:
320 dev_err(ipc->dev, "FW Underrun %x\n", header.primary);
323 case IPC_GLB_NOTIFY_RESOURCE_EVENT:
324 dev_err(ipc->dev, "MCPS Budget Violation: %x\n",
328 case IPC_GLB_NOTIFY_FW_READY:
329 skl->boot_complete = true;
330 wake_up(&skl->boot_wait);
333 case IPC_GLB_NOTIFY_PHRASE_DETECTED:
334 dev_dbg(ipc->dev, "***** Phrase Detected **********\n");
337 * Per HW recomendation, After phrase detection,
338 * clear the CGCTL.MISCBDCGE.
340 * This will be set back on stream closure
342 skl->enable_miscbdcge(ipc->dev, false);
343 skl->miscbdcg_disabled = true;
347 dev_err(ipc->dev, "ipc: Unhandled error msg=%x\n",
356 static void skl_ipc_process_reply(struct sst_generic_ipc *ipc,
357 struct skl_ipc_header header)
359 struct ipc_message *msg;
360 u32 reply = header.primary & IPC_GLB_REPLY_STATUS_MASK;
361 u64 *ipc_header = (u64 *)(&header);
363 msg = skl_ipc_reply_get_msg(ipc, *ipc_header);
365 dev_dbg(ipc->dev, "ipc: rx list is empty\n");
369 /* first process the header */
371 case IPC_GLB_REPLY_SUCCESS:
372 dev_dbg(ipc->dev, "ipc FW reply %x: success\n", header.primary);
373 /* copy the rx data from the mailbox */
374 sst_dsp_inbox_read(ipc->dsp, msg->rx_data, msg->rx_size);
377 case IPC_GLB_REPLY_OUT_OF_MEMORY:
378 dev_err(ipc->dev, "ipc fw reply: %x: no memory\n", header.primary);
379 msg->errno = -ENOMEM;
382 case IPC_GLB_REPLY_BUSY:
383 dev_err(ipc->dev, "ipc fw reply: %x: Busy\n", header.primary);
388 dev_err(ipc->dev, "Unknown ipc reply: 0x%x\n", reply);
389 msg->errno = -EINVAL;
393 if (reply != IPC_GLB_REPLY_SUCCESS) {
394 dev_err(ipc->dev, "ipc FW reply: reply=%d\n", reply);
395 dev_err(ipc->dev, "FW Error Code: %u\n",
396 ipc->dsp->fw_ops.get_fw_errcode(ipc->dsp));
399 list_del(&msg->list);
400 sst_ipc_tx_msg_reply_complete(ipc, msg);
403 irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context)
405 struct sst_dsp *dsp = context;
406 struct skl_sst *skl = sst_dsp_get_thread_context(dsp);
407 struct sst_generic_ipc *ipc = &skl->ipc;
408 struct skl_ipc_header header = {0};
409 u32 hipcie, hipct, hipcte;
412 if (dsp->intr_status & SKL_ADSPIS_CL_DMA)
413 skl_cldma_process_intr(dsp);
415 /* Here we handle IPC interrupts only */
416 if (!(dsp->intr_status & SKL_ADSPIS_IPC))
419 hipcie = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCIE);
420 hipct = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCT);
422 /* reply message from DSP */
423 if (hipcie & SKL_ADSP_REG_HIPCIE_DONE) {
424 sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL,
425 SKL_ADSP_REG_HIPCCTL_DONE, 0);
427 /* clear DONE bit - tell DSP we have completed the operation */
428 sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCIE,
429 SKL_ADSP_REG_HIPCIE_DONE, SKL_ADSP_REG_HIPCIE_DONE);
433 /* unmask Done interrupt */
434 sst_dsp_shim_update_bits(dsp, SKL_ADSP_REG_HIPCCTL,
435 SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE);
438 /* New message from DSP */
439 if (hipct & SKL_ADSP_REG_HIPCT_BUSY) {
440 hipcte = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCTE);
441 header.primary = hipct;
442 header.extension = hipcte;
443 dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x\n",
445 dev_dbg(dsp->dev, "IPC irq: Firmware respond extension:%x\n",
448 if (IPC_GLB_NOTIFY_RSP_TYPE(header.primary)) {
449 /* Handle Immediate reply from DSP Core */
450 skl_ipc_process_reply(ipc, header);
452 dev_dbg(dsp->dev, "IPC irq: Notification from firmware\n");
453 skl_ipc_process_notification(ipc, header);
455 /* clear busy interrupt */
456 sst_dsp_shim_update_bits_forced(dsp, SKL_ADSP_REG_HIPCT,
457 SKL_ADSP_REG_HIPCT_BUSY, SKL_ADSP_REG_HIPCT_BUSY);
464 skl_ipc_int_enable(dsp);
466 /* continue to send any remaining messages... */
467 kthread_queue_work(&ipc->kworker, &ipc->kwork);
472 void skl_ipc_int_enable(struct sst_dsp *ctx)
474 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_ADSPIC,
475 SKL_ADSPIC_IPC, SKL_ADSPIC_IPC);
478 void skl_ipc_int_disable(struct sst_dsp *ctx)
480 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
484 void skl_ipc_op_int_enable(struct sst_dsp *ctx)
486 /* enable IPC DONE interrupt */
487 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL,
488 SKL_ADSP_REG_HIPCCTL_DONE, SKL_ADSP_REG_HIPCCTL_DONE);
490 /* Enable IPC BUSY interrupt */
491 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCCTL,
492 SKL_ADSP_REG_HIPCCTL_BUSY, SKL_ADSP_REG_HIPCCTL_BUSY);
495 void skl_ipc_op_int_disable(struct sst_dsp *ctx)
497 /* disable IPC DONE interrupt */
498 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL,
499 SKL_ADSP_REG_HIPCCTL_DONE, 0);
501 /* Disable IPC BUSY interrupt */
502 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL,
503 SKL_ADSP_REG_HIPCCTL_BUSY, 0);
507 bool skl_ipc_int_status(struct sst_dsp *ctx)
509 return sst_dsp_shim_read_unlocked(ctx,
510 SKL_ADSP_REG_ADSPIS) & SKL_ADSPIS_IPC;
513 int skl_ipc_init(struct device *dev, struct skl_sst *skl)
515 struct sst_generic_ipc *ipc;
522 ipc->tx_data_max_size = SKL_ADSP_W1_SZ;
523 ipc->rx_data_max_size = SKL_ADSP_W0_UP_SZ;
525 err = sst_ipc_init(ipc);
529 ipc->ops.tx_msg = skl_ipc_tx_msg;
530 ipc->ops.tx_data_copy = skl_ipc_tx_data_copy;
531 ipc->ops.is_dsp_busy = skl_ipc_is_dsp_busy;
536 void skl_ipc_free(struct sst_generic_ipc *ipc)
538 /* Disable IPC DONE interrupt */
539 sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,
540 SKL_ADSP_REG_HIPCCTL_DONE, 0);
542 /* Disable IPC BUSY interrupt */
543 sst_dsp_shim_update_bits(ipc->dsp, SKL_ADSP_REG_HIPCCTL,
544 SKL_ADSP_REG_HIPCCTL_BUSY, 0);
549 int skl_ipc_create_pipeline(struct sst_generic_ipc *ipc,
550 u16 ppl_mem_size, u8 ppl_type, u8 instance_id)
552 struct skl_ipc_header header = {0};
553 u64 *ipc_header = (u64 *)(&header);
556 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
557 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
558 header.primary |= IPC_GLB_TYPE(IPC_GLB_CREATE_PPL);
559 header.primary |= IPC_INSTANCE_ID(instance_id);
560 header.primary |= IPC_PPL_TYPE(ppl_type);
561 header.primary |= IPC_PPL_MEM_SIZE(ppl_mem_size);
563 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
564 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
566 dev_err(ipc->dev, "ipc: create pipeline fail, err: %d\n", ret);
572 EXPORT_SYMBOL_GPL(skl_ipc_create_pipeline);
574 int skl_ipc_delete_pipeline(struct sst_generic_ipc *ipc, u8 instance_id)
576 struct skl_ipc_header header = {0};
577 u64 *ipc_header = (u64 *)(&header);
580 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
581 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
582 header.primary |= IPC_GLB_TYPE(IPC_GLB_DELETE_PPL);
583 header.primary |= IPC_INSTANCE_ID(instance_id);
585 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
586 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
588 dev_err(ipc->dev, "ipc: delete pipeline failed, err %d\n", ret);
594 EXPORT_SYMBOL_GPL(skl_ipc_delete_pipeline);
596 int skl_ipc_set_pipeline_state(struct sst_generic_ipc *ipc,
597 u8 instance_id, enum skl_ipc_pipeline_state state)
599 struct skl_ipc_header header = {0};
600 u64 *ipc_header = (u64 *)(&header);
603 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
604 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
605 header.primary |= IPC_GLB_TYPE(IPC_GLB_SET_PPL_STATE);
606 header.primary |= IPC_INSTANCE_ID(instance_id);
607 header.primary |= IPC_PPL_STATE(state);
609 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
610 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
612 dev_err(ipc->dev, "ipc: set pipeline state failed, err: %d\n", ret);
617 EXPORT_SYMBOL_GPL(skl_ipc_set_pipeline_state);
620 skl_ipc_save_pipeline(struct sst_generic_ipc *ipc, u8 instance_id, int dma_id)
622 struct skl_ipc_header header = {0};
623 u64 *ipc_header = (u64 *)(&header);
626 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
627 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
628 header.primary |= IPC_GLB_TYPE(IPC_GLB_SAVE_PPL);
629 header.primary |= IPC_INSTANCE_ID(instance_id);
631 header.extension = IPC_DMA_ID(dma_id);
632 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
633 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
635 dev_err(ipc->dev, "ipc: save pipeline failed, err: %d\n", ret);
641 EXPORT_SYMBOL_GPL(skl_ipc_save_pipeline);
643 int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id)
645 struct skl_ipc_header header = {0};
646 u64 *ipc_header = (u64 *)(&header);
649 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
650 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
651 header.primary |= IPC_GLB_TYPE(IPC_GLB_RESTORE_PPL);
652 header.primary |= IPC_INSTANCE_ID(instance_id);
654 dev_dbg(ipc->dev, "In %s header=%d\n", __func__, header.primary);
655 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
657 dev_err(ipc->dev, "ipc: restore pipeline failed, err: %d\n", ret);
663 EXPORT_SYMBOL_GPL(skl_ipc_restore_pipeline);
665 int skl_ipc_set_dx(struct sst_generic_ipc *ipc, u8 instance_id,
666 u16 module_id, struct skl_ipc_dxstate_info *dx)
668 struct skl_ipc_header header = {0};
669 u64 *ipc_header = (u64 *)(&header);
672 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
673 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
674 header.primary |= IPC_GLB_TYPE(IPC_MOD_SET_DX);
675 header.primary |= IPC_MOD_INSTANCE_ID(instance_id);
676 header.primary |= IPC_MOD_ID(module_id);
678 dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__,
679 header.primary, header.extension);
680 ret = sst_ipc_tx_message_wait(ipc, *ipc_header,
681 dx, sizeof(*dx), NULL, 0);
683 dev_err(ipc->dev, "ipc: set dx failed, err %d\n", ret);
689 EXPORT_SYMBOL_GPL(skl_ipc_set_dx);
691 int skl_ipc_init_instance(struct sst_generic_ipc *ipc,
692 struct skl_ipc_init_instance_msg *msg, void *param_data)
694 struct skl_ipc_header header = {0};
695 u64 *ipc_header = (u64 *)(&header);
697 u32 *buffer = (u32 *)param_data;
698 /* param_block_size must be in dwords */
699 u16 param_block_size = msg->param_data_size / sizeof(u32);
701 print_hex_dump_debug("Param data:", DUMP_PREFIX_NONE,
702 16, 4, buffer, param_block_size, false);
704 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
705 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
706 header.primary |= IPC_GLB_TYPE(IPC_MOD_INIT_INSTANCE);
707 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
708 header.primary |= IPC_MOD_ID(msg->module_id);
710 header.extension = IPC_CORE_ID(msg->core_id);
711 header.extension |= IPC_PPL_INSTANCE_ID(msg->ppl_instance_id);
712 header.extension |= IPC_PARAM_BLOCK_SIZE(param_block_size);
713 header.extension |= IPC_DOMAIN(msg->domain);
715 dev_dbg(ipc->dev, "In %s primary =%x ext=%x\n", __func__,
716 header.primary, header.extension);
717 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, param_data,
718 msg->param_data_size, NULL, 0);
721 dev_err(ipc->dev, "ipc: init instance failed\n");
727 EXPORT_SYMBOL_GPL(skl_ipc_init_instance);
729 int skl_ipc_bind_unbind(struct sst_generic_ipc *ipc,
730 struct skl_ipc_bind_unbind_msg *msg)
732 struct skl_ipc_header header = {0};
733 u64 *ipc_header = (u64 *)(&header);
734 u8 bind_unbind = msg->bind ? IPC_MOD_BIND : IPC_MOD_UNBIND;
737 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
738 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
739 header.primary |= IPC_GLB_TYPE(bind_unbind);
740 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
741 header.primary |= IPC_MOD_ID(msg->module_id);
743 header.extension = IPC_DST_MOD_ID(msg->dst_module_id);
744 header.extension |= IPC_DST_MOD_INSTANCE_ID(msg->dst_instance_id);
745 header.extension |= IPC_DST_QUEUE(msg->dst_queue);
746 header.extension |= IPC_SRC_QUEUE(msg->src_queue);
748 dev_dbg(ipc->dev, "In %s hdr=%x ext=%x\n", __func__, header.primary,
750 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
752 dev_err(ipc->dev, "ipc: bind/unbind failed\n");
758 EXPORT_SYMBOL_GPL(skl_ipc_bind_unbind);
761 * In order to load a module we need to send IPC to initiate that. DMA will
762 * performed to load the module memory. The FW supports multiple module load
763 * at single shot, so we can send IPC with N modules represented by
766 int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
767 u8 module_cnt, void *data)
769 struct skl_ipc_header header = {0};
770 u64 *ipc_header = (u64 *)(&header);
773 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
774 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
775 header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_MULTIPLE_MODS);
776 header.primary |= IPC_LOAD_MODULE_CNT(module_cnt);
778 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, data,
779 (sizeof(u16) * module_cnt), NULL, 0);
781 dev_err(ipc->dev, "ipc: load modules failed :%d\n", ret);
785 EXPORT_SYMBOL_GPL(skl_ipc_load_modules);
787 int skl_ipc_unload_modules(struct sst_generic_ipc *ipc, u8 module_cnt,
790 struct skl_ipc_header header = {0};
791 u64 *ipc_header = (u64 *)(&header);
794 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
795 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
796 header.primary |= IPC_GLB_TYPE(IPC_GLB_UNLOAD_MULTIPLE_MODS);
797 header.primary |= IPC_LOAD_MODULE_CNT(module_cnt);
799 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, data,
800 (sizeof(u16) * module_cnt), NULL, 0);
802 dev_err(ipc->dev, "ipc: unload modules failed :%d\n", ret);
806 EXPORT_SYMBOL_GPL(skl_ipc_unload_modules);
808 int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
809 struct skl_ipc_large_config_msg *msg, u32 *param)
811 struct skl_ipc_header header = {0};
812 u64 *ipc_header = (u64 *)(&header);
814 size_t sz_remaining, tx_size, data_offset;
816 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
817 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
818 header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_SET);
819 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
820 header.primary |= IPC_MOD_ID(msg->module_id);
822 header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size);
823 header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id);
824 header.extension |= IPC_FINAL_BLOCK(0);
825 header.extension |= IPC_INITIAL_BLOCK(1);
827 sz_remaining = msg->param_data_size;
829 while (sz_remaining != 0) {
830 tx_size = sz_remaining > SKL_ADSP_W1_SZ
831 ? SKL_ADSP_W1_SZ : sz_remaining;
832 if (tx_size == sz_remaining)
833 header.extension |= IPC_FINAL_BLOCK(1);
835 dev_dbg(ipc->dev, "In %s primary=%#x ext=%#x\n", __func__,
836 header.primary, header.extension);
837 dev_dbg(ipc->dev, "transmitting offset: %#x, size: %#x\n",
838 (unsigned)data_offset, (unsigned)tx_size);
839 ret = sst_ipc_tx_message_wait(ipc, *ipc_header,
840 ((char *)param) + data_offset,
844 "ipc: set large config fail, err: %d\n", ret);
847 sz_remaining -= tx_size;
848 data_offset = msg->param_data_size - sz_remaining;
850 /* clear the fields */
851 header.extension &= IPC_INITIAL_BLOCK_CLEAR;
852 header.extension &= IPC_DATA_OFFSET_SZ_CLEAR;
853 /* fill the fields */
854 header.extension |= IPC_INITIAL_BLOCK(0);
855 header.extension |= IPC_DATA_OFFSET_SZ(data_offset);
860 EXPORT_SYMBOL_GPL(skl_ipc_set_large_config);
862 int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
863 struct skl_ipc_large_config_msg *msg, u32 *param)
865 struct skl_ipc_header header = {0};
866 u64 *ipc_header = (u64 *)(&header);
868 size_t sz_remaining, rx_size, data_offset;
870 header.primary = IPC_MSG_TARGET(IPC_MOD_MSG);
871 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
872 header.primary |= IPC_GLB_TYPE(IPC_MOD_LARGE_CONFIG_GET);
873 header.primary |= IPC_MOD_INSTANCE_ID(msg->instance_id);
874 header.primary |= IPC_MOD_ID(msg->module_id);
876 header.extension = IPC_DATA_OFFSET_SZ(msg->param_data_size);
877 header.extension |= IPC_LARGE_PARAM_ID(msg->large_param_id);
878 header.extension |= IPC_FINAL_BLOCK(1);
879 header.extension |= IPC_INITIAL_BLOCK(1);
881 sz_remaining = msg->param_data_size;
884 while (sz_remaining != 0) {
885 rx_size = sz_remaining > SKL_ADSP_W1_SZ
886 ? SKL_ADSP_W1_SZ : sz_remaining;
887 if (rx_size == sz_remaining)
888 header.extension |= IPC_FINAL_BLOCK(1);
890 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0,
891 ((char *)param) + data_offset,
892 msg->param_data_size);
895 "ipc: get large config fail, err: %d\n", ret);
898 sz_remaining -= rx_size;
899 data_offset = msg->param_data_size - sz_remaining;
901 /* clear the fields */
902 header.extension &= IPC_INITIAL_BLOCK_CLEAR;
903 header.extension &= IPC_DATA_OFFSET_SZ_CLEAR;
904 /* fill the fields */
905 header.extension |= IPC_INITIAL_BLOCK(1);
906 header.extension |= IPC_DATA_OFFSET_SZ(data_offset);
911 EXPORT_SYMBOL_GPL(skl_ipc_get_large_config);
913 int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
914 u8 dma_id, u8 table_id)
916 struct skl_ipc_header header = {0};
917 u64 *ipc_header = (u64 *)(&header);
920 header.primary = IPC_MSG_TARGET(IPC_FW_GEN_MSG);
921 header.primary |= IPC_MSG_DIR(IPC_MSG_REQUEST);
922 header.primary |= IPC_GLB_TYPE(IPC_GLB_LOAD_LIBRARY);
923 header.primary |= IPC_MOD_INSTANCE_ID(table_id);
924 header.primary |= IPC_MOD_ID(dma_id);
926 ret = sst_ipc_tx_message_wait(ipc, *ipc_header, NULL, 0, NULL, 0);
929 dev_err(ipc->dev, "ipc: load lib failed\n");
933 EXPORT_SYMBOL_GPL(skl_sst_ipc_load_library);