sound/soc/intel/sst-haswell-ipc.c

   1 /*
   2  *  Intel SST Haswell/Broadwell IPC Support
   3  *
   4  * Copyright (C) 2013, Intel Corporation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License version
   8  * 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/kernel.h>
  19 #include <linux/list.h>
  20 #include <linux/device.h>
  21 #include <linux/wait.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/export.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/kthread.h>
  30 #include <linux/firmware.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/debugfs.h>
  33
  34 #include "sst-haswell-ipc.h"
  35 #include "sst-dsp.h"
  36 #include "sst-dsp-priv.h"
  37
  38 /* Global Message - Generic */
  39 #define IPC_GLB_TYPE_SHIFT      24
  40 #define IPC_GLB_TYPE_MASK       (0x1f << IPC_GLB_TYPE_SHIFT)
  41 #define IPC_GLB_TYPE(x)         (x << IPC_GLB_TYPE_SHIFT)
  42
  43 /* Global Message - Reply */
  44 #define IPC_GLB_REPLY_SHIFT     0
  45 #define IPC_GLB_REPLY_MASK      (0x1f << IPC_GLB_REPLY_SHIFT)
  46 #define IPC_GLB_REPLY_TYPE(x)   (x << IPC_GLB_REPLY_TYPE_SHIFT)
  47
  48 /* Stream Message - Generic */
  49 #define IPC_STR_TYPE_SHIFT      20
  50 #define IPC_STR_TYPE_MASK       (0xf << IPC_STR_TYPE_SHIFT)
  51 #define IPC_STR_TYPE(x)         (x << IPC_STR_TYPE_SHIFT)
  52 #define IPC_STR_ID_SHIFT        16
  53 #define IPC_STR_ID_MASK         (0xf << IPC_STR_ID_SHIFT)
  54 #define IPC_STR_ID(x)           (x << IPC_STR_ID_SHIFT)
  55
  56 /* Stream Message - Reply */
  57 #define IPC_STR_REPLY_SHIFT     0
  58 #define IPC_STR_REPLY_MASK      (0x1f << IPC_STR_REPLY_SHIFT)
  59
  60 /* Stream Stage Message - Generic */
  61 #define IPC_STG_TYPE_SHIFT      12
  62 #define IPC_STG_TYPE_MASK       (0xf << IPC_STG_TYPE_SHIFT)
  63 #define IPC_STG_TYPE(x)         (x << IPC_STG_TYPE_SHIFT)
  64 #define IPC_STG_ID_SHIFT        10
  65 #define IPC_STG_ID_MASK         (0x3 << IPC_STG_ID_SHIFT)
  66 #define IPC_STG_ID(x)           (x << IPC_STG_ID_SHIFT)
  67
  68 /* Stream Stage Message - Reply */
  69 #define IPC_STG_REPLY_SHIFT     0
  70 #define IPC_STG_REPLY_MASK      (0x1f << IPC_STG_REPLY_SHIFT)
  71
  72 /* Debug Log Message - Generic */
  73 #define IPC_LOG_OP_SHIFT        20
  74 #define IPC_LOG_OP_MASK         (0xf << IPC_LOG_OP_SHIFT)
  75 #define IPC_LOG_OP_TYPE(x)      (x << IPC_LOG_OP_SHIFT)
  76 #define IPC_LOG_ID_SHIFT        16
  77 #define IPC_LOG_ID_MASK         (0xf << IPC_LOG_ID_SHIFT)
  78 #define IPC_LOG_ID(x)           (x << IPC_LOG_ID_SHIFT)
  79
  80 /* IPC message timeout (msecs) */
  81 #define IPC_TIMEOUT_MSECS       300
  82 #define IPC_BOOT_MSECS          200
  83 #define IPC_MSG_WAIT            0
  84 #define IPC_MSG_NOWAIT          1
  85
  86 /* Firmware Ready Message */
  87 #define IPC_FW_READY            (0x1 << 29)
  88 #define IPC_STATUS_MASK         (0x3 << 30)
  89
  90 #define IPC_EMPTY_LIST_SIZE     8
  91 #define IPC_MAX_STREAMS         4
  92
  93 /* Mailbox */
  94 #define IPC_MAX_MAILBOX_BYTES   256
  95
  96 /* Global Message - Types and Replies */
  97 enum ipc_glb_type {
  98         IPC_GLB_GET_FW_VERSION = 0,             /* Retrieves firmware version */
  99         IPC_GLB_PERFORMANCE_MONITOR = 1,        /* Performance monitoring actions */
 100         IPC_GLB_ALLOCATE_STREAM = 3,            /* Request to allocate new stream */
 101         IPC_GLB_FREE_STREAM = 4,                /* Request to free stream */
 102         IPC_GLB_GET_FW_CAPABILITIES = 5,        /* Retrieves firmware capabilities */
 103         IPC_GLB_STREAM_MESSAGE = 6,             /* Message directed to stream or its stages */
 104         /* Request to store firmware context during D0->D3 transition */
 105         IPC_GLB_REQUEST_DUMP = 7,
 106         /* Request to restore firmware context during D3->D0 transition */
 107         IPC_GLB_RESTORE_CONTEXT = 8,
 108         IPC_GLB_GET_DEVICE_FORMATS = 9,         /* Set device format */
 109         IPC_GLB_SET_DEVICE_FORMATS = 10,        /* Get device format */
 110         IPC_GLB_SHORT_REPLY = 11,
 111         IPC_GLB_ENTER_DX_STATE = 12,
 112         IPC_GLB_GET_MIXER_STREAM_INFO = 13,     /* Request mixer stream params */
 113         IPC_GLB_DEBUG_LOG_MESSAGE = 14,         /* Message to or from the debug logger. */
 114         IPC_GLB_REQUEST_TRANSFER = 16,          /* < Request Transfer for host */
 115         IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17,      /* Maximum message number */
 116 };
 117
 118 enum ipc_glb_reply {
 119         IPC_GLB_REPLY_SUCCESS = 0,              /* The operation was successful. */
 120         IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1,  /* Invalid parameter was passed. */
 121         IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
 122         IPC_GLB_REPLY_OUT_OF_RESOURCES = 3,     /* No resources to satisfy the request. */
 123         IPC_GLB_REPLY_BUSY = 4,                 /* The system or resource is busy. */
 124         IPC_GLB_REPLY_PENDING = 5,              /* The action was scheduled for processing.  */
 125         IPC_GLB_REPLY_FAILURE = 6,              /* Critical error happened. */
 126         IPC_GLB_REPLY_INVALID_REQUEST = 7,      /* Request can not be completed. */
 127         IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8,  /* Processing stage was uninitialized. */
 128         IPC_GLB_REPLY_NOT_FOUND = 9,            /* Required resource can not be found. */
 129         IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10,  /* Source was not started. */
 130 };
 131
 132 /* Stream Message - Types */
 133 enum ipc_str_operation {
 134         IPC_STR_RESET = 0,
 135         IPC_STR_PAUSE = 1,
 136         IPC_STR_RESUME = 2,
 137         IPC_STR_STAGE_MESSAGE = 3,
 138         IPC_STR_NOTIFICATION = 4,
 139         IPC_STR_MAX_MESSAGE
 140 };
 141
 142 /* Stream Stage Message Types */
 143 enum ipc_stg_operation {
 144         IPC_STG_GET_VOLUME = 0,
 145         IPC_STG_SET_VOLUME,
 146         IPC_STG_SET_WRITE_POSITION,
 147         IPC_STG_SET_FX_ENABLE,
 148         IPC_STG_SET_FX_DISABLE,
 149         IPC_STG_SET_FX_GET_PARAM,
 150         IPC_STG_SET_FX_SET_PARAM,
 151         IPC_STG_SET_FX_GET_INFO,
 152         IPC_STG_MUTE_LOOPBACK,
 153         IPC_STG_MAX_MESSAGE
 154 };
 155
 156 /* Stream Stage Message Types For Notification*/
 157 enum ipc_stg_operation_notify {
 158         IPC_POSITION_CHANGED = 0,
 159         IPC_STG_GLITCH,
 160         IPC_STG_MAX_NOTIFY
 161 };
 162
 163 enum ipc_glitch_type {
 164         IPC_GLITCH_UNDERRUN = 1,
 165         IPC_GLITCH_DECODER_ERROR,
 166         IPC_GLITCH_DOUBLED_WRITE_POS,
 167         IPC_GLITCH_MAX
 168 };
 169
 170 /* Debug Control */
 171 enum ipc_debug_operation {
 172         IPC_DEBUG_ENABLE_LOG = 0,
 173         IPC_DEBUG_DISABLE_LOG = 1,
 174         IPC_DEBUG_REQUEST_LOG_DUMP = 2,
 175         IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
 176         IPC_DEBUG_MAX_DEBUG_LOG
 177 };
 178
 179 /* Firmware Ready */
 180 struct sst_hsw_ipc_fw_ready {
 181         u32 inbox_offset;
 182         u32 outbox_offset;
 183         u32 inbox_size;
 184         u32 outbox_size;
 185         u32 fw_info_size;
 186         u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
 187 } __attribute__((packed));
 188
 189 struct ipc_message {
 190         struct list_head list;
 191         u32 header;
 192
 193         /* direction wrt host CPU */
 194         char tx_data[IPC_MAX_MAILBOX_BYTES];
 195         size_t tx_size;
 196         char rx_data[IPC_MAX_MAILBOX_BYTES];
 197         size_t rx_size;
 198
 199         wait_queue_head_t waitq;
 200         bool pending;
 201         bool complete;
 202         bool wait;
 203         int errno;
 204 };
 205
 206 struct sst_hsw_stream;
 207 struct sst_hsw;
 208
 209 /* Stream infomation */
 210 struct sst_hsw_stream {
 211         /* configuration */
 212         struct sst_hsw_ipc_stream_alloc_req request;
 213         struct sst_hsw_ipc_stream_alloc_reply reply;
 214         struct sst_hsw_ipc_stream_free_req free_req;
 215
 216         /* Mixer info */
 217         u32 mute_volume[SST_HSW_NO_CHANNELS];
 218         u32 mute[SST_HSW_NO_CHANNELS];
 219
 220         /* runtime info */
 221         struct sst_hsw *hsw;
 222         int host_id;
 223         bool commited;
 224         bool running;
 225
 226         /* Notification work */
 227         struct work_struct notify_work;
 228         u32 header;
 229
 230         /* Position info from DSP */
 231         struct sst_hsw_ipc_stream_set_position wpos;
 232         struct sst_hsw_ipc_stream_get_position rpos;
 233         struct sst_hsw_ipc_stream_glitch_position glitch;
 234
 235         /* Volume info */
 236         struct sst_hsw_ipc_volume_req vol_req;
 237
 238         /* driver callback */
 239         u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
 240         void *pdata;
 241
 242         struct list_head node;
 243 };
 244
 245 /* FW log ring information */
 246 struct sst_hsw_log_stream {
 247         dma_addr_t dma_addr;
 248         unsigned char *dma_area;
 249         unsigned char *ring_descr;
 250         int pages;
 251         int size;
 252
 253         /* Notification work */
 254         struct work_struct notify_work;
 255         wait_queue_head_t readers_wait_q;
 256         struct mutex rw_mutex;
 257
 258         u32 last_pos;
 259         u32 curr_pos;
 260         u32 reader_pos;
 261
 262         /* fw log config */
 263         u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
 264
 265         struct sst_hsw *hsw;
 266 };
 267
 268 /* SST Haswell IPC data */
 269 struct sst_hsw {
 270         struct device *dev;
 271         struct sst_dsp *dsp;
 272         struct platform_device *pdev_pcm;
 273
 274         /* FW config */
 275         struct sst_hsw_ipc_fw_ready fw_ready;
 276         struct sst_hsw_ipc_fw_version version;
 277         struct sst_module *scratch;
 278         bool fw_done;
 279
 280         /* stream */
 281         struct list_head stream_list;
 282
 283         /* global mixer */
 284         struct sst_hsw_ipc_stream_info_reply mixer_info;
 285         enum sst_hsw_volume_curve curve_type;
 286         u32 curve_duration;
 287         u32 mute[SST_HSW_NO_CHANNELS];
 288         u32 mute_volume[SST_HSW_NO_CHANNELS];
 289
 290         /* DX */
 291         struct sst_hsw_ipc_dx_reply dx;
 292
 293         /* boot */
 294         wait_queue_head_t boot_wait;
 295         bool boot_complete;
 296         bool shutdown;
 297
 298         /* IPC messaging */
 299         struct list_head tx_list;
 300         struct list_head rx_list;
 301         struct list_head empty_list;
 302         wait_queue_head_t wait_txq;
 303         struct task_struct *tx_thread;
 304         struct kthread_worker kworker;
 305         struct kthread_work kwork;
 306         bool pending;
 307         struct ipc_message *msg;
 308
 309         /* FW log stream */
 310         struct sst_hsw_log_stream log_stream;
 311 };
 312
 313 #define CREATE_TRACE_POINTS
 314 #include <trace/events/hswadsp.h>
 315
 316 static inline u32 msg_get_global_type(u32 msg)
 317 {
 318         return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
 319 }
 320
 321 static inline u32 msg_get_global_reply(u32 msg)
 322 {
 323         return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
 324 }
 325
 326 static inline u32 msg_get_stream_type(u32 msg)
 327 {
 328         return (msg & IPC_STR_TYPE_MASK) >>  IPC_STR_TYPE_SHIFT;
 329 }
 330
 331 static inline u32 msg_get_stage_type(u32 msg)
 332 {
 333         return (msg & IPC_STG_TYPE_MASK) >>  IPC_STG_TYPE_SHIFT;
 334 }
 335
 336 static inline u32 msg_set_stage_type(u32 msg, u32 type)
 337 {
 338         return (msg & ~IPC_STG_TYPE_MASK) +
 339                 (type << IPC_STG_TYPE_SHIFT);
 340 }
 341
 342 static inline u32 msg_get_stream_id(u32 msg)
 343 {
 344         return (msg & IPC_STR_ID_MASK) >>  IPC_STR_ID_SHIFT;
 345 }
 346
 347 static inline u32 msg_get_notify_reason(u32 msg)
 348 {
 349         return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
 350 }
 351
 352 u32 create_channel_map(enum sst_hsw_channel_config config)
 353 {
 354         switch (config) {
 355         case SST_HSW_CHANNEL_CONFIG_MONO:
 356                 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
 357         case SST_HSW_CHANNEL_CONFIG_STEREO:
 358                 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
 359                         | (SST_HSW_CHANNEL_RIGHT << 4));
 360         case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
 361                 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
 362                         | (SST_HSW_CHANNEL_RIGHT << 4)
 363                         | (SST_HSW_CHANNEL_LFE << 8 ));
 364         case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
 365                 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
 366                         | (SST_HSW_CHANNEL_CENTER << 4)
 367                         | (SST_HSW_CHANNEL_RIGHT << 8));
 368         case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
 369                 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
 370                         | (SST_HSW_CHANNEL_CENTER << 4)
 371                         | (SST_HSW_CHANNEL_RIGHT << 8)
 372                         | (SST_HSW_CHANNEL_LFE << 12));
 373         case SST_HSW_CHANNEL_CONFIG_QUATRO:
 374                 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
 375                         | (SST_HSW_CHANNEL_RIGHT << 4)
 376                         | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
 377                         | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
 378         case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
 379                 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
 380                         | (SST_HSW_CHANNEL_CENTER << 4)
 381                         | (SST_HSW_CHANNEL_RIGHT << 8)
 382                         | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
 383         case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
 384                 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
 385                         | (SST_HSW_CHANNEL_CENTER << 4)
 386                         | (SST_HSW_CHANNEL_RIGHT << 8)
 387                         | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
 388                         | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
 389         case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
 390                 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
 391                         | (SST_HSW_CHANNEL_LEFT << 4)
 392                         | (SST_HSW_CHANNEL_RIGHT << 8)
 393                         | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
 394                         | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
 395                         | (SST_HSW_CHANNEL_LFE << 20));
 396         case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
 397                 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
 398                         | (SST_HSW_CHANNEL_LEFT << 4));
 399         default:
 400                 return 0xFFFFFFFF;
 401         }
 402 }
 403
 404 static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
 405         int stream_id)
 406 {
 407         struct sst_hsw_stream *stream;
 408
 409         list_for_each_entry(stream, &hsw->stream_list, node) {
 410                 if (stream->reply.stream_hw_id == stream_id)
 411                         return stream;
 412         }
 413
 414         return NULL;
 415 }
 416
 417 static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text)
 418 {
 419         struct sst_dsp *sst = hsw->dsp;
 420         u32 isr, ipcd, imrx, ipcx;
 421
 422         ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
 423         isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
 424         ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
 425         imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
 426
 427         dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
 428                 text, ipcx, isr, ipcd, imrx);
 429 }
 430
 431 /* locks held by caller */
 432 static struct ipc_message *msg_get_empty(struct sst_hsw *hsw)
 433 {
 434         struct ipc_message *msg = NULL;
 435
 436         if (!list_empty(&hsw->empty_list)) {
 437                 msg = list_first_entry(&hsw->empty_list, struct ipc_message,
 438                         list);
 439                 list_del(&msg->list);
 440         }
 441
 442         return msg;
 443 }
 444
 445 static void ipc_tx_msgs(struct kthread_work *work)
 446 {
 447         struct sst_hsw *hsw =
 448                 container_of(work, struct sst_hsw, kwork);
 449         struct ipc_message *msg;
 450         unsigned long flags;
 451         u32 ipcx;
 452
 453         spin_lock_irqsave(&hsw->dsp->spinlock, flags);
 454
 455         if (list_empty(&hsw->tx_list) || hsw->pending) {
 456                 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
 457                 return;
 458         }
 459
 460         /* if the DSP is busy, we will TX messages after IRQ.
 461          * also postpone if we are in the middle of procesing completion irq*/
 462         ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX);
 463         if (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE)) {
 464                 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
 465                 return;
 466         }
 467
 468         msg = list_first_entry(&hsw->tx_list, struct ipc_message, list);
 469
 470         list_move(&msg->list, &hsw->rx_list);
 471
 472         /* send the message */
 473         sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size);
 474         sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY);
 475
 476         spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
 477 }
 478
 479 /* locks held by caller */
 480 static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg)
 481 {
 482         msg->complete = true;
 483         trace_ipc_reply("completed", msg->header);
 484
 485         if (!msg->wait)
 486                 list_add_tail(&msg->list, &hsw->empty_list);
 487         else
 488                 wake_up(&msg->waitq);
 489 }
 490
 491 static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg,
 492         void *rx_data)
 493 {
 494         unsigned long flags;
 495         int ret;
 496
 497         /* wait for DSP completion (in all cases atm inc pending) */
 498         ret = wait_event_timeout(msg->waitq, msg->complete,
 499                 msecs_to_jiffies(IPC_TIMEOUT_MSECS));
 500
 501         spin_lock_irqsave(&hsw->dsp->spinlock, flags);
 502         if (ret == 0) {
 503                 ipc_shim_dbg(hsw, "message timeout");
 504
 505                 trace_ipc_error("error message timeout for", msg->header);
 506                 list_del(&msg->list);
 507                 ret = -ETIMEDOUT;
 508         } else {
 509
 510                 /* copy the data returned from DSP */
 511                 if (msg->rx_size)
 512                         memcpy(rx_data, msg->rx_data, msg->rx_size);
 513                 ret = msg->errno;
 514         }
 515
 516         list_add_tail(&msg->list, &hsw->empty_list);
 517         spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
 518         return ret;
 519 }
 520
 521 static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data,
 522         size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait)
 523 {
 524         struct ipc_message *msg;
 525         unsigned long flags;
 526
 527         spin_lock_irqsave(&hsw->dsp->spinlock, flags);
 528
 529         msg = msg_get_empty(hsw);
 530         if (msg == NULL) {
 531                 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
 532                 return -EBUSY;
 533         }
 534
 535         if (tx_bytes)
 536                 memcpy(msg->tx_data, tx_data, tx_bytes);
 537
 538         msg->header = header;
 539         msg->tx_size = tx_bytes;
 540         msg->rx_size = rx_bytes;
 541         msg->wait = wait;
 542         msg->errno = 0;
 543         msg->pending = false;
 544         msg->complete = false;
 545
 546         list_add_tail(&msg->list, &hsw->tx_list);
 547         spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
 548
 549         queue_kthread_work(&hsw->kworker, &hsw->kwork);
 550
 551         if (wait)
 552                 return tx_wait_done(hsw, msg, rx_data);
 553         else
 554                 return 0;
 555 }
 556
 557 static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header,
 558         void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
 559 {
 560         return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data,
 561                 rx_bytes, 1);
 562 }
 563
 564 static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header,
 565         void *tx_data, size_t tx_bytes)
 566 {
 567         return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0);
 568 }
 569
 570 static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
 571 {
 572         struct sst_hsw_ipc_fw_ready fw_ready;
 573         u32 offset;
 574         u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
 575         char *tmp[5], *pinfo;
 576         int i = 0;
 577
 578         offset = (header & 0x1FFFFFFF) << 3;
 579
 580         dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
 581                 header, offset);
 582
 583         /* copy data from the DSP FW ready offset */
 584         sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
 585
 586         sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
 587                 fw_ready.inbox_size, fw_ready.outbox_offset,
 588                 fw_ready.outbox_size);
 589
 590         hsw->boot_complete = true;
 591         wake_up(&hsw->boot_wait);
 592
 593         dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
 594                 fw_ready.inbox_offset, fw_ready.inbox_size);
 595         dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
 596                 fw_ready.outbox_offset, fw_ready.outbox_size);
 597         if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
 598                 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
 599                 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
 600
 601                 /* log the FW version info got from the mailbox here. */
 602                 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
 603                 pinfo = &fw_info[0];
 604                 for (i = 0; i < sizeof(tmp) / sizeof(char *); i++)
 605                         tmp[i] = strsep(&pinfo, " ");
 606                 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
 607                         "version: %s.%s, build %s, source commit id: %s\n",
 608                         tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
 609         }
 610 }
 611
 612 static void hsw_notification_work(struct work_struct *work)
 613 {
 614         struct sst_hsw_stream *stream = container_of(work,
 615                         struct sst_hsw_stream, notify_work);
 616         struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
 617         struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
 618         struct sst_hsw *hsw = stream->hsw;
 619         u32 reason;
 620
 621         reason = msg_get_notify_reason(stream->header);
 622
 623         switch (reason) {
 624         case IPC_STG_GLITCH:
 625                 trace_ipc_notification("DSP stream under/overrun",
 626                         stream->reply.stream_hw_id);
 627                 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
 628
 629                 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
 630                         glitch->glitch_type, glitch->present_pos,
 631                         glitch->write_pos);
 632                 break;
 633
 634         case IPC_POSITION_CHANGED:
 635                 trace_ipc_notification("DSP stream position changed for",
 636                         stream->reply.stream_hw_id);
 637                 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
 638
 639                 if (stream->notify_position)
 640                         stream->notify_position(stream, stream->pdata);
 641
 642                 break;
 643         default:
 644                 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
 645                         stream->header);
 646                 break;
 647         }
 648
 649         /* tell DSP that notification has been handled */
 650         sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IPCD,
 651                 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
 652
 653         /* unmask busy interrupt */
 654         sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
 655 }
 656
 657 static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)
 658 {
 659         struct ipc_message *msg;
 660
 661         /* clear reply bits & status bits */
 662         header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
 663
 664         if (list_empty(&hsw->rx_list)) {
 665                 dev_err(hsw->dev, "error: rx list empty but received 0x%x\n",
 666                         header);
 667                 return NULL;
 668         }
 669
 670         list_for_each_entry(msg, &hsw->rx_list, list) {
 671                 if (msg->header == header)
 672                         return msg;
 673         }
 674
 675         return NULL;
 676 }
 677
 678 static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
 679 {
 680         struct sst_hsw_stream *stream;
 681         u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
 682         u32 stream_id = msg_get_stream_id(header);
 683         u32 stream_msg = msg_get_stream_type(header);
 684
 685         stream = get_stream_by_id(hsw, stream_id);
 686         if (stream == NULL)
 687                 return;
 688
 689         switch (stream_msg) {
 690         case IPC_STR_STAGE_MESSAGE:
 691         case IPC_STR_NOTIFICATION:
 692                 break;
 693         case IPC_STR_RESET:
 694                 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
 695                 break;
 696         case IPC_STR_PAUSE:
 697                 stream->running = false;
 698                 trace_ipc_notification("stream paused",
 699                         stream->reply.stream_hw_id);
 700                 break;
 701         case IPC_STR_RESUME:
 702                 stream->running = true;
 703                 trace_ipc_notification("stream running",
 704                         stream->reply.stream_hw_id);
 705                 break;
 706         }
 707 }
 708
 709 static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
 710 {
 711         struct ipc_message *msg;
 712         u32 reply = msg_get_global_reply(header);
 713
 714         trace_ipc_reply("processing -->", header);
 715
 716         msg = reply_find_msg(hsw, header);
 717         if (msg == NULL) {
 718                 trace_ipc_error("error: can't find message header", header);
 719                 return -EIO;
 720         }
 721
 722         /* first process the header */
 723         switch (reply) {
 724         case IPC_GLB_REPLY_PENDING:
 725                 trace_ipc_pending_reply("received", header);
 726                 msg->pending = true;
 727                 hsw->pending = true;
 728                 return 1;
 729         case IPC_GLB_REPLY_SUCCESS:
 730                 if (msg->pending) {
 731                         trace_ipc_pending_reply("completed", header);
 732                         sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
 733                                 msg->rx_size);
 734                         hsw->pending = false;
 735                 } else {
 736                         /* copy data from the DSP */
 737                         sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
 738                                 msg->rx_size);
 739                 }
 740                 break;
 741         /* these will be rare - but useful for debug */
 742         case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
 743                 trace_ipc_error("error: unknown message type", header);
 744                 msg->errno = -EBADMSG;
 745                 break;
 746         case IPC_GLB_REPLY_OUT_OF_RESOURCES:
 747                 trace_ipc_error("error: out of resources", header);
 748                 msg->errno = -ENOMEM;
 749                 break;
 750         case IPC_GLB_REPLY_BUSY:
 751                 trace_ipc_error("error: reply busy", header);
 752                 msg->errno = -EBUSY;
 753                 break;
 754         case IPC_GLB_REPLY_FAILURE:
 755                 trace_ipc_error("error: reply failure", header);
 756                 msg->errno = -EINVAL;
 757                 break;
 758         case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
 759                 trace_ipc_error("error: stage uninitialized", header);
 760                 msg->errno = -EINVAL;
 761                 break;
 762         case IPC_GLB_REPLY_NOT_FOUND:
 763                 trace_ipc_error("error: reply not found", header);
 764                 msg->errno = -EINVAL;
 765                 break;
 766         case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
 767                 trace_ipc_error("error: source not started", header);
 768                 msg->errno = -EINVAL;
 769                 break;
 770         case IPC_GLB_REPLY_INVALID_REQUEST:
 771                 trace_ipc_error("error: invalid request", header);
 772                 msg->errno = -EINVAL;
 773                 break;
 774         case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
 775                 trace_ipc_error("error: invalid parameter", header);
 776                 msg->errno = -EINVAL;
 777                 break;
 778         default:
 779                 trace_ipc_error("error: unknown reply", header);
 780                 msg->errno = -EINVAL;
 781                 break;
 782         }
 783
 784         /* update any stream states */
 785         if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
 786                 hsw_stream_update(hsw, msg);
 787
 788         /* wake up and return the error if we have waiters on this message ? */
 789         list_del(&msg->list);
 790         tx_msg_reply_complete(hsw, msg);
 791
 792         return 1;
 793 }
 794
 795 static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
 796 {
 797         u32 stream_msg, stream_id, stage_type;
 798         struct sst_hsw_stream *stream;
 799         int handled = 0;
 800
 801         stream_msg = msg_get_stream_type(header);
 802         stream_id = msg_get_stream_id(header);
 803         stage_type = msg_get_stage_type(header);
 804
 805         stream = get_stream_by_id(hsw, stream_id);
 806         if (stream == NULL)
 807                 return handled;
 808
 809         stream->header = header;
 810
 811         switch (stream_msg) {
 812         case IPC_STR_STAGE_MESSAGE:
 813                 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
 814                         header);
 815                 break;
 816         case IPC_STR_NOTIFICATION:
 817                 schedule_work(&stream->notify_work);
 818                 break;
 819         default:
 820                 /* handle pending message complete request */
 821                 handled = hsw_process_reply(hsw, header);
 822                 break;
 823         }
 824
 825         return handled;
 826 }
 827
 828 static int hsw_log_message(struct sst_hsw *hsw, u32 header)
 829 {
 830         u32 operation = (header & IPC_LOG_OP_MASK) >>  IPC_LOG_OP_SHIFT;
 831         struct sst_hsw_log_stream *stream = &hsw->log_stream;
 832         int ret = 1;
 833
 834         if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
 835                 dev_err(hsw->dev,
 836                         "error: log msg not implemented 0x%8.8x\n", header);
 837                 return 0;
 838         }
 839
 840         mutex_lock(&stream->rw_mutex);
 841         stream->last_pos = stream->curr_pos;
 842         sst_dsp_inbox_read(
 843                 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
 844         mutex_unlock(&stream->rw_mutex);
 845
 846         schedule_work(&stream->notify_work);
 847
 848         return ret;
 849 }
 850
 851 static int hsw_process_notification(struct sst_hsw *hsw)
 852 {
 853         struct sst_dsp *sst = hsw->dsp;
 854         u32 type, header;
 855         int handled = 1;
 856
 857         header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
 858         type = msg_get_global_type(header);
 859
 860         trace_ipc_request("processing -->", header);
 861
 862         /* FW Ready is a special case */
 863         if (!hsw->boot_complete && header & IPC_FW_READY) {
 864                 hsw_fw_ready(hsw, header);
 865                 return handled;
 866         }
 867
 868         switch (type) {
 869         case IPC_GLB_GET_FW_VERSION:
 870         case IPC_GLB_ALLOCATE_STREAM:
 871         case IPC_GLB_FREE_STREAM:
 872         case IPC_GLB_GET_FW_CAPABILITIES:
 873         case IPC_GLB_REQUEST_DUMP:
 874         case IPC_GLB_GET_DEVICE_FORMATS:
 875         case IPC_GLB_SET_DEVICE_FORMATS:
 876         case IPC_GLB_ENTER_DX_STATE:
 877         case IPC_GLB_GET_MIXER_STREAM_INFO:
 878         case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
 879         case IPC_GLB_RESTORE_CONTEXT:
 880         case IPC_GLB_SHORT_REPLY:
 881                 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
 882                         type, header);
 883                 break;
 884         case IPC_GLB_STREAM_MESSAGE:
 885                 handled = hsw_stream_message(hsw, header);
 886                 break;
 887         case IPC_GLB_DEBUG_LOG_MESSAGE:
 888                 handled = hsw_log_message(hsw, header);
 889                 break;
 890         default:
 891                 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
 892                         type, header);
 893                 break;
 894         }
 895
 896         return handled;
 897 }
 898
 899 static irqreturn_t hsw_irq_thread(int irq, void *context)
 900 {
 901         struct sst_dsp *sst = (struct sst_dsp *) context;
 902         struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
 903         u32 ipcx, ipcd;
 904         int handled;
 905         unsigned long flags;
 906
 907         spin_lock_irqsave(&sst->spinlock, flags);
 908
 909         ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
 910         ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
 911
 912         /* reply message from DSP */
 913         if (ipcx & SST_IPCX_DONE) {
 914
 915                 /* Handle Immediate reply from DSP Core */
 916                 handled = hsw_process_reply(hsw, ipcx);
 917
 918                 if (handled > 0) {
 919                         /* clear DONE bit - tell DSP we have completed */
 920                         sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
 921                                 SST_IPCX_DONE, 0);
 922
 923                         /* unmask Done interrupt */
 924                         sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 925                                 SST_IMRX_DONE, 0);
 926                 }
 927         }
 928
 929         /* new message from DSP */
 930         if (ipcd & SST_IPCD_BUSY) {
 931
 932                 /* Handle Notification and Delayed reply from DSP Core */
 933                 handled = hsw_process_notification(hsw);
 934
 935                 /* clear BUSY bit and set DONE bit - accept new messages */
 936                 if (handled > 0) {
 937                         sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
 938                                 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
 939
 940                         /* unmask busy interrupt */
 941                         sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
 942                                 SST_IMRX_BUSY, 0);
 943                 }
 944         }
 945
 946         spin_unlock_irqrestore(&sst->spinlock, flags);
 947
 948         /* continue to send any remaining messages... */
 949         queue_kthread_work(&hsw->kworker, &hsw->kwork);
 950
 951         return IRQ_HANDLED;
 952 }
 953
 954 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
 955         struct sst_hsw_ipc_fw_version *version)
 956 {
 957         int ret;
 958
 959         ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
 960                 NULL, 0, version, sizeof(*version));
 961         if (ret < 0)
 962                 dev_err(hsw->dev, "error: get version failed\n");
 963
 964         return ret;
 965 }
 966
 967 /* Mixer Controls */
 968 int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 969         u32 stage_id, u32 channel)
 970 {
 971         int ret;
 972
 973         ret = sst_hsw_stream_get_volume(hsw, stream, stage_id, channel,
 974                 &stream->mute_volume[channel]);
 975         if (ret < 0)
 976                 return ret;
 977
 978         ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel, 0);
 979         if (ret < 0) {
 980                 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
 981                         stream->reply.stream_hw_id, channel);
 982                 return ret;
 983         }
 984
 985         stream->mute[channel] = 1;
 986         return 0;
 987 }
 988
 989 int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
 990         u32 stage_id, u32 channel)
 991
 992 {
 993         int ret;
 994
 995         stream->mute[channel] = 0;
 996         ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel,
 997                 stream->mute_volume[channel]);
 998         if (ret < 0) {
 999                 dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
1000                         stream->reply.stream_hw_id, channel);
1001                 return ret;
1002         }
1003
1004         return 0;
1005 }
1006
1007 int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1008         u32 stage_id, u32 channel, u32 *volume)
1009 {
1010         if (channel > 1)
1011                 return -EINVAL;
1012
1013         sst_dsp_read(hsw->dsp, volume,
1014                 stream->reply.volume_register_address[channel],
1015                 sizeof(*volume));
1016
1017         return 0;
1018 }
1019
1020 int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
1021         struct sst_hsw_stream *stream, u64 curve_duration,
1022         enum sst_hsw_volume_curve curve)
1023 {
1024         /* curve duration in steps of 100ns */
1025         stream->vol_req.curve_duration = curve_duration;
1026         stream->vol_req.curve_type = curve;
1027
1028         return 0;
1029 }
1030
1031 /* stream volume */
1032 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
1033         struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
1034 {
1035         struct sst_hsw_ipc_volume_req *req;
1036         u32 header;
1037         int ret;
1038
1039         trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
1040
1041         if (channel > 1)
1042                 return -EINVAL;
1043
1044         if (stream->mute[channel]) {
1045                 stream->mute_volume[channel] = volume;
1046                 return 0;
1047         }
1048
1049         header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1050                 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1051         header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1052         header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1053         header |= (stage_id << IPC_STG_ID_SHIFT);
1054
1055         req = &stream->vol_req;
1056         req->channel = channel;
1057         req->target_volume = volume;
1058
1059         ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0);
1060         if (ret < 0) {
1061                 dev_err(hsw->dev, "error: set stream volume failed\n");
1062                 return ret;
1063         }
1064
1065         return 0;
1066 }
1067
1068 int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1069 {
1070         int ret;
1071
1072         ret = sst_hsw_mixer_get_volume(hsw, stage_id, channel,
1073                 &hsw->mute_volume[channel]);
1074         if (ret < 0)
1075                 return ret;
1076
1077         ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel, 0);
1078         if (ret < 0) {
1079                 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1080                         channel);
1081                 return ret;
1082         }
1083
1084         hsw->mute[channel] = 1;
1085         return 0;
1086 }
1087
1088 int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
1089 {
1090         int ret;
1091
1092         ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel,
1093                 hsw->mixer_info.volume_register_address[channel]);
1094         if (ret < 0) {
1095                 dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
1096                         channel);
1097                 return ret;
1098         }
1099
1100         hsw->mute[channel] = 0;
1101         return 0;
1102 }
1103
1104 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1105         u32 *volume)
1106 {
1107         if (channel > 1)
1108                 return -EINVAL;
1109
1110         sst_dsp_read(hsw->dsp, volume,
1111                 hsw->mixer_info.volume_register_address[channel],
1112                 sizeof(*volume));
1113
1114         return 0;
1115 }
1116
1117 int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
1118          u64 curve_duration, enum sst_hsw_volume_curve curve)
1119 {
1120         /* curve duration in steps of 100ns */
1121         hsw->curve_duration = curve_duration;
1122         hsw->curve_type = curve;
1123
1124         return 0;
1125 }
1126
1127 /* global mixer volume */
1128 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1129         u32 volume)
1130 {
1131         struct sst_hsw_ipc_volume_req req;
1132         u32 header;
1133         int ret;
1134
1135         trace_ipc_request("set mixer volume", volume);
1136
1137         /* set both at same time ? */
1138         if (channel == 2) {
1139                 if (hsw->mute[0] && hsw->mute[1]) {
1140                         hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
1141                         return 0;
1142                 } else if (hsw->mute[0])
1143                         req.channel = 1;
1144                 else if (hsw->mute[1])
1145                         req.channel = 0;
1146                 else
1147                         req.channel = 0xffffffff;
1148         } else {
1149                 /* set only 1 channel */
1150                 if (hsw->mute[channel]) {
1151                         hsw->mute_volume[channel] = volume;
1152                         return 0;
1153                 }
1154                 req.channel = channel;
1155         }
1156
1157         header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1158                 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1159         header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
1160         header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1161         header |= (stage_id << IPC_STG_ID_SHIFT);
1162
1163         req.curve_duration = hsw->curve_duration;
1164         req.curve_type = hsw->curve_type;
1165         req.target_volume = volume;
1166
1167         ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0);
1168         if (ret < 0) {
1169                 dev_err(hsw->dev, "error: set mixer volume failed\n");
1170                 return ret;
1171         }
1172
1173         return 0;
1174 }
1175
1176 /* Stream API */
1177 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
1178         u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
1179         void *data)
1180 {
1181         struct sst_hsw_stream *stream;
1182         struct sst_dsp *sst = hsw->dsp;
1183         unsigned long flags;
1184
1185         stream = kzalloc(sizeof(*stream), GFP_KERNEL);
1186         if (stream == NULL)
1187                 return NULL;
1188
1189         spin_lock_irqsave(&sst->spinlock, flags);
1190         list_add(&stream->node, &hsw->stream_list);
1191         stream->notify_position = notify_position;
1192         stream->pdata = data;
1193         stream->hsw = hsw;
1194         stream->host_id = id;
1195
1196         /* work to process notification messages */
1197         INIT_WORK(&stream->notify_work, hsw_notification_work);
1198         spin_unlock_irqrestore(&sst->spinlock, flags);
1199
1200         return stream;
1201 }
1202
1203 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1204 {
1205         u32 header;
1206         int ret = 0;
1207         struct sst_dsp *sst = hsw->dsp;
1208         unsigned long flags;
1209
1210         /* dont free DSP streams that are not commited */
1211         if (!stream->commited)
1212                 goto out;
1213
1214         trace_ipc_request("stream free", stream->host_id);
1215
1216         stream->free_req.stream_id = stream->reply.stream_hw_id;
1217         header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1218
1219         ret = ipc_tx_message_wait(hsw, header, &stream->free_req,
1220                 sizeof(stream->free_req), NULL, 0);
1221         if (ret < 0) {
1222                 dev_err(hsw->dev, "error: free stream %d failed\n",
1223                         stream->free_req.stream_id);
1224                 return -EAGAIN;
1225         }
1226
1227         trace_hsw_stream_free_req(stream, &stream->free_req);
1228
1229 out:
1230         cancel_work_sync(&stream->notify_work);
1231         spin_lock_irqsave(&sst->spinlock, flags);
1232         list_del(&stream->node);
1233         kfree(stream);
1234         spin_unlock_irqrestore(&sst->spinlock, flags);
1235
1236         return ret;
1237 }
1238
1239 int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1240         struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1241 {
1242         if (stream->commited) {
1243                 dev_err(hsw->dev, "error: stream committed for set bits\n");
1244                 return -EINVAL;
1245         }
1246
1247         stream->request.format.bitdepth = bits;
1248         return 0;
1249 }
1250
1251 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1252         struct sst_hsw_stream *stream, int channels)
1253 {
1254         if (stream->commited) {
1255                 dev_err(hsw->dev, "error: stream committed for set channels\n");
1256                 return -EINVAL;
1257         }
1258
1259         /* stereo is only supported atm */
1260         if (channels != 2)
1261                 return -EINVAL;
1262
1263         stream->request.format.ch_num = channels;
1264         return 0;
1265 }
1266
1267 int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1268         struct sst_hsw_stream *stream, int rate)
1269 {
1270         if (stream->commited) {
1271                 dev_err(hsw->dev, "error: stream committed for set rate\n");
1272                 return -EINVAL;
1273         }
1274
1275         stream->request.format.frequency = rate;
1276         return 0;
1277 }
1278
1279 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1280         struct sst_hsw_stream *stream, u32 map,
1281         enum sst_hsw_channel_config config)
1282 {
1283         if (stream->commited) {
1284                 dev_err(hsw->dev, "error: stream committed for set map\n");
1285                 return -EINVAL;
1286         }
1287
1288         stream->request.format.map = map;
1289         stream->request.format.config = config;
1290         return 0;
1291 }
1292
1293 int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1294         struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1295 {
1296         if (stream->commited) {
1297                 dev_err(hsw->dev, "error: stream committed for set style\n");
1298                 return -EINVAL;
1299         }
1300
1301         stream->request.format.style = style;
1302         return 0;
1303 }
1304
1305 int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1306         struct sst_hsw_stream *stream, u32 bits)
1307 {
1308         if (stream->commited) {
1309                 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1310                 return -EINVAL;
1311         }
1312
1313         stream->request.format.valid_bit = bits;
1314         return 0;
1315 }
1316
1317 /* Stream Configuration */
1318 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1319         enum sst_hsw_stream_path_id path_id,
1320         enum sst_hsw_stream_type stream_type,
1321         enum sst_hsw_stream_format format_id)
1322 {
1323         if (stream->commited) {
1324                 dev_err(hsw->dev, "error: stream committed for set format\n");
1325                 return -EINVAL;
1326         }
1327
1328         stream->request.path_id = path_id;
1329         stream->request.stream_type = stream_type;
1330         stream->request.format_id = format_id;
1331
1332         trace_hsw_stream_alloc_request(stream, &stream->request);
1333
1334         return 0;
1335 }
1336
1337 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1338         u32 ring_pt_address, u32 num_pages,
1339         u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1340 {
1341         if (stream->commited) {
1342                 dev_err(hsw->dev, "error: stream committed for buffer\n");
1343                 return -EINVAL;
1344         }
1345
1346         stream->request.ringinfo.ring_pt_address = ring_pt_address;
1347         stream->request.ringinfo.num_pages = num_pages;
1348         stream->request.ringinfo.ring_size = ring_size;
1349         stream->request.ringinfo.ring_offset = ring_offset;
1350         stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1351
1352         trace_hsw_stream_buffer(stream);
1353
1354         return 0;
1355 }
1356
1357 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1358         struct sst_hsw_stream *stream, enum sst_hsw_module_id module_id,
1359         u32 entry_point)
1360 {
1361         struct sst_hsw_module_map *map = &stream->request.map;
1362
1363         if (stream->commited) {
1364                 dev_err(hsw->dev, "error: stream committed for set module\n");
1365                 return -EINVAL;
1366         }
1367
1368         /* only support initial module atm */
1369         map->module_entries_count = 1;
1370         map->module_entries[0].module_id = module_id;
1371         map->module_entries[0].entry_point = entry_point;
1372
1373         return 0;
1374 }
1375
1376 int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
1377         struct sst_hsw_stream *stream, u32 offset, u32 size)
1378 {
1379         if (stream->commited) {
1380                 dev_err(hsw->dev, "error: stream committed for set pmem\n");
1381                 return -EINVAL;
1382         }
1383
1384         stream->request.persistent_mem.offset = offset;
1385         stream->request.persistent_mem.size = size;
1386
1387         return 0;
1388 }
1389
1390 int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
1391         struct sst_hsw_stream *stream, u32 offset, u32 size)
1392 {
1393         if (stream->commited) {
1394                 dev_err(hsw->dev, "error: stream committed for set smem\n");
1395                 return -EINVAL;
1396         }
1397
1398         stream->request.scratch_mem.offset = offset;
1399         stream->request.scratch_mem.size = size;
1400
1401         return 0;
1402 }
1403
1404 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1405 {
1406         struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1407         struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1408         u32 header;
1409         int ret;
1410
1411         trace_ipc_request("stream alloc", stream->host_id);
1412
1413         header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1414
1415         ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req),
1416                 reply, sizeof(*reply));
1417         if (ret < 0) {
1418                 dev_err(hsw->dev, "error: stream commit failed\n");
1419                 return ret;
1420         }
1421
1422         stream->commited = 1;
1423         trace_hsw_stream_alloc_reply(stream);
1424
1425         return 0;
1426 }
1427
1428 /* Stream Information - these calls could be inline but we want the IPC
1429  ABI to be opaque to client PCM drivers to cope with any future ABI changes */
1430 int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
1431         struct sst_hsw_stream *stream)
1432 {
1433         return stream->reply.stream_hw_id;
1434 }
1435
1436 int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
1437         struct sst_hsw_stream *stream)
1438 {
1439         return stream->reply.mixer_hw_id;
1440 }
1441
1442 u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
1443         struct sst_hsw_stream *stream)
1444 {
1445         return stream->reply.read_position_register_address;
1446 }
1447
1448 u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
1449         struct sst_hsw_stream *stream)
1450 {
1451         return stream->reply.presentation_position_register_address;
1452 }
1453
1454 u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
1455         struct sst_hsw_stream *stream, u32 channel)
1456 {
1457         if (channel >= 2)
1458                 return 0;
1459
1460         return stream->reply.peak_meter_register_address[channel];
1461 }
1462
1463 u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
1464         struct sst_hsw_stream *stream, u32 channel)
1465 {
1466         if (channel >= 2)
1467                 return 0;
1468
1469         return stream->reply.volume_register_address[channel];
1470 }
1471
1472 int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1473 {
1474         struct sst_hsw_ipc_stream_info_reply *reply;
1475         u32 header;
1476         int ret;
1477
1478         reply = &hsw->mixer_info;
1479         header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1480
1481         trace_ipc_request("get global mixer info", 0);
1482
1483         ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply));
1484         if (ret < 0) {
1485                 dev_err(hsw->dev, "error: get stream info failed\n");
1486                 return ret;
1487         }
1488
1489         trace_hsw_mixer_info_reply(reply);
1490
1491         return 0;
1492 }
1493
1494 /* Send stream command */
1495 static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1496         int stream_id, int wait)
1497 {
1498         u32 header;
1499
1500         header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1501         header |= (stream_id << IPC_STR_ID_SHIFT);
1502
1503         if (wait)
1504                 return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
1505         else
1506                 return ipc_tx_message_nowait(hsw, header, NULL, 0);
1507 }
1508
1509 /* Stream ALSA trigger operations */
1510 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1511         int wait)
1512 {
1513         int ret;
1514
1515         trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1516
1517         ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1518                 stream->reply.stream_hw_id, wait);
1519         if (ret < 0)
1520                 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1521                         stream->reply.stream_hw_id);
1522
1523         return ret;
1524 }
1525
1526 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1527         int wait)
1528 {
1529         int ret;
1530
1531         trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1532
1533         ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1534                 stream->reply.stream_hw_id, wait);
1535         if (ret < 0)
1536                 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1537                         stream->reply.stream_hw_id);
1538
1539         return ret;
1540 }
1541
1542 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1543 {
1544         int ret, tries = 10;
1545
1546         /* dont reset streams that are not commited */
1547         if (!stream->commited)
1548                 return 0;
1549
1550         /* wait for pause to complete before we reset the stream */
1551         while (stream->running && tries--)
1552                 msleep(1);
1553         if (!tries) {
1554                 dev_err(hsw->dev, "error: reset stream %d still running\n",
1555                         stream->reply.stream_hw_id);
1556                 return -EINVAL;
1557         }
1558
1559         trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1560
1561         ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1562                 stream->reply.stream_hw_id, 1);
1563         if (ret < 0)
1564                 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1565                         stream->reply.stream_hw_id);
1566         return ret;
1567 }
1568
1569 /* Stream pointer positions */
1570 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
1571         struct sst_hsw_stream *stream)
1572 {
1573         u32 rpos;
1574
1575         sst_dsp_read(hsw->dsp, &rpos,
1576                 stream->reply.read_position_register_address, sizeof(rpos));
1577
1578         return rpos;
1579 }
1580
1581 /* Stream presentation (monotonic) positions */
1582 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1583         struct sst_hsw_stream *stream)
1584 {
1585         u64 ppos;
1586
1587         sst_dsp_read(hsw->dsp, &ppos,
1588                 stream->reply.presentation_position_register_address,
1589                 sizeof(ppos));
1590
1591         return ppos;
1592 }
1593
1594 int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
1595         struct sst_hsw_stream *stream, u32 stage_id, u32 position)
1596 {
1597         u32 header;
1598         int ret;
1599
1600         trace_stream_write_position(stream->reply.stream_hw_id, position);
1601
1602         header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1603                 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1604         header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1605         header |= (IPC_STG_SET_WRITE_POSITION << IPC_STG_TYPE_SHIFT);
1606         header |= (stage_id << IPC_STG_ID_SHIFT);
1607         stream->wpos.position = position;
1608
1609         ret = ipc_tx_message_nowait(hsw, header, &stream->wpos,
1610                 sizeof(stream->wpos));
1611         if (ret < 0)
1612                 dev_err(hsw->dev, "error: stream %d set position %d failed\n",
1613                         stream->reply.stream_hw_id, position);
1614
1615         return ret;
1616 }
1617
1618 /* physical BE config */
1619 int sst_hsw_device_set_config(struct sst_hsw *hsw,
1620         enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1621         enum sst_hsw_device_mode mode, u32 clock_divider)
1622 {
1623         struct sst_hsw_ipc_device_config_req config;
1624         u32 header;
1625         int ret;
1626
1627         trace_ipc_request("set device config", dev);
1628
1629         config.ssp_interface = dev;
1630         config.clock_frequency = mclk;
1631         config.mode = mode;
1632         config.clock_divider = clock_divider;
1633
1634         trace_hsw_device_config_req(&config);
1635
1636         header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1637
1638         ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config),
1639                 NULL, 0);
1640         if (ret < 0)
1641                 dev_err(hsw->dev, "error: set device formats failed\n");
1642
1643         return ret;
1644 }
1645 EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1646
1647 /* DX Config */
1648 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1649         enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1650 {
1651         u32 header, state_;
1652         int ret, item;
1653
1654         header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1655         state_ = state;
1656
1657         trace_ipc_request("PM enter Dx state", state);
1658
1659         ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_),
1660                 dx, sizeof(*dx));
1661         if (ret < 0) {
1662                 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1663                 return ret;
1664         }
1665
1666         for (item = 0; item < dx->entries_no; item++) {
1667                 dev_dbg(hsw->dev,
1668                         "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1669                         item, dx->mem_info[item].offset,
1670                         dx->mem_info[item].size,
1671                         dx->mem_info[item].source);
1672         }
1673         dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1674                 dx->entries_no, state);
1675
1676         memcpy(&hsw->dx, dx, sizeof(*dx));
1677         return 0;
1678 }
1679
1680 /* Used to save state into hsw->dx_reply */
1681 int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
1682         u32 *offset, u32 *size, u32 *source)
1683 {
1684         struct sst_hsw_ipc_dx_memory_item *dx_mem;
1685         struct sst_hsw_ipc_dx_reply *dx_reply;
1686         int entry_no;
1687
1688         dx_reply = &hsw->dx;
1689         entry_no = dx_reply->entries_no;
1690
1691         trace_ipc_request("PM get Dx state", entry_no);
1692
1693         if (item >= entry_no)
1694                 return -EINVAL;
1695
1696         dx_mem = &dx_reply->mem_info[item];
1697         *offset = dx_mem->offset;
1698         *size = dx_mem->size;
1699         *source = dx_mem->source;
1700
1701         return 0;
1702 }
1703
1704 static int msg_empty_list_init(struct sst_hsw *hsw)
1705 {
1706         int i;
1707
1708         hsw->msg = kzalloc(sizeof(struct ipc_message) *
1709                 IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
1710         if (hsw->msg == NULL)
1711                 return -ENOMEM;
1712
1713         for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
1714                 init_waitqueue_head(&hsw->msg[i].waitq);
1715                 list_add(&hsw->msg[i].list, &hsw->empty_list);
1716         }
1717
1718         return 0;
1719 }
1720
1721 void sst_hsw_set_scratch_module(struct sst_hsw *hsw,
1722         struct sst_module *scratch)
1723 {
1724         hsw->scratch = scratch;
1725 }
1726
1727 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1728 {
1729         return hsw->dsp;
1730 }
1731
1732 static struct sst_dsp_device hsw_dev = {
1733         .thread = hsw_irq_thread,
1734         .ops = &haswell_ops,
1735 };
1736
1737 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
1738 {
1739         struct sst_hsw_ipc_fw_version version;
1740         struct sst_hsw *hsw;
1741         struct sst_fw *hsw_sst_fw;
1742         int ret;
1743
1744         dev_dbg(dev, "initialising Audio DSP IPC\n");
1745
1746         hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
1747         if (hsw == NULL)
1748                 return -ENOMEM;
1749
1750         hsw->dev = dev;
1751         INIT_LIST_HEAD(&hsw->stream_list);
1752         INIT_LIST_HEAD(&hsw->tx_list);
1753         INIT_LIST_HEAD(&hsw->rx_list);
1754         INIT_LIST_HEAD(&hsw->empty_list);
1755         init_waitqueue_head(&hsw->boot_wait);
1756         init_waitqueue_head(&hsw->wait_txq);
1757
1758         ret = msg_empty_list_init(hsw);
1759         if (ret < 0)
1760                 return -ENOMEM;
1761
1762         /* start the IPC message thread */
1763         init_kthread_worker(&hsw->kworker);
1764         hsw->tx_thread = kthread_run(kthread_worker_fn,
1765                                            &hsw->kworker, "%s",
1766                                            dev_name(hsw->dev));
1767         if (IS_ERR(hsw->tx_thread)) {
1768                 ret = PTR_ERR(hsw->tx_thread);
1769                 dev_err(hsw->dev, "error: failed to create message TX task\n");
1770                 goto err_free_msg;
1771         }
1772         init_kthread_work(&hsw->kwork, ipc_tx_msgs);
1773
1774         hsw_dev.thread_context = hsw;
1775
1776         /* init SST shim */
1777         hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
1778         if (hsw->dsp == NULL) {
1779                 ret = -ENODEV;
1780                 goto dsp_err;
1781         }
1782
1783         /* keep the DSP in reset state for base FW loading */
1784         sst_dsp_reset(hsw->dsp);
1785
1786         hsw_sst_fw = sst_fw_new(hsw->dsp, pdata->fw, hsw);
1787
1788         if (hsw_sst_fw == NULL) {
1789                 ret = -ENODEV;
1790                 dev_err(dev, "error: failed to load firmware\n");
1791                 goto fw_err;
1792         }
1793
1794         /* wait for DSP boot completion */
1795         sst_dsp_boot(hsw->dsp);
1796         ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1797                 msecs_to_jiffies(IPC_BOOT_MSECS));
1798         if (ret == 0) {
1799                 ret = -EIO;
1800                 dev_err(hsw->dev, "error: ADSP boot timeout\n");
1801                 goto boot_err;
1802         }
1803
1804         /* get the FW version */
1805         sst_hsw_fw_get_version(hsw, &version);
1806
1807         /* get the globalmixer */
1808         ret = sst_hsw_mixer_get_info(hsw);
1809         if (ret < 0) {
1810                 dev_err(hsw->dev, "error: failed to get stream info\n");
1811                 goto boot_err;
1812         }
1813
1814         pdata->dsp = hsw;
1815         return 0;
1816
1817 boot_err:
1818         sst_dsp_reset(hsw->dsp);
1819         sst_fw_free(hsw_sst_fw);
1820 fw_err:
1821         sst_dsp_free(hsw->dsp);
1822 dsp_err:
1823         kthread_stop(hsw->tx_thread);
1824 err_free_msg:
1825         kfree(hsw->msg);
1826
1827         return ret;
1828 }
1829 EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
1830
1831 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
1832 {
1833         struct sst_hsw *hsw = pdata->dsp;
1834
1835         sst_dsp_reset(hsw->dsp);
1836         sst_fw_free_all(hsw->dsp);
1837         sst_dsp_free(hsw->dsp);
1838         kfree(hsw->scratch);
1839         kthread_stop(hsw->tx_thread);
1840         kfree(hsw->msg);
1841 }
1842 EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);