select CPU_ARM720T
select GENERIC_CLOCKEVENTS
select MFD_SYSCON
+ select SOC_BUS
help
Support for Cirrus Logic 711x/721x/731x based boards.
};
};
+&extal1_clk {
+ clock-frequency = <25000000>;
+};
+&extal2_clk {
+ clock-frequency = <48000000>;
+};
+&fsibck_clk {
+ clock-frequency = <12288000>;
+};
+&cpg_clocks {
+ renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */
+};
+
+&cmt1 {
+ status = "ok";
+};
+
&i2c0 {
status = "okay";
touchscreen@55 {
/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/r8a7740-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
};
+ cmt1: timer@e6138000 {
+ compatible = "renesas,cmt-48";
+ reg = <0xe6138000 0x170>;
+ interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
+ clock-names = "fck";
+
+ renesas,channels-mask = <0x3f>;
+
+ status = "disabled";
+ };
+
/* irqpin0: IRQ0 - IRQ7 */
irqpin0: irqpin@e6900000 {
compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
reg = <0xe9a00000 0x800>,
<0xe9a01800 0x800>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
- /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */
+ clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
phy-mode = "mii";
#address-cells = <1>;
#size-cells = <0>;
0 202 IRQ_TYPE_LEVEL_HIGH
0 203 IRQ_TYPE_LEVEL_HIGH
0 204 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
status = "disabled";
};
0 71 IRQ_TYPE_LEVEL_HIGH
0 72 IRQ_TYPE_LEVEL_HIGH
0 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
status = "disabled";
};
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c40000 0x100>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
+ clock-names = "sci_ick";
status = "disabled";
};
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c50000 0x100>;
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
+ clock-names = "sci_ick";
status = "disabled";
};
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c60000 0x100>;
interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
+ clock-names = "sci_ick";
status = "disabled";
};
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c70000 0x100>;
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
+ clock-names = "sci_ick";
status = "disabled";
};
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c80000 0x100>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
+ clock-names = "sci_ick";
status = "disabled";
};
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6cb0000 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
+ clock-names = "sci_ick";
status = "disabled";
};
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6cc0000 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
+ clock-names = "sci_ick";
status = "disabled";
};
compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6cd0000 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
+ clock-names = "sci_ick";
status = "disabled";
};
compatible = "renesas,scifb-r8a7740", "renesas,scifb";
reg = <0xe6c30000 0x100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
+ clock-names = "sci_ick";
status = "disabled";
};
tpu: pwm@e6600000 {
compatible = "renesas,tpu-r8a7740", "renesas,tpu";
reg = <0xe6600000 0x100>;
+ clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
status = "disabled";
#pwm-cells = <3>;
};
reg = <0xe6bd0000 0x100>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
0 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7740_CLK_MMC>;
status = "disabled";
};
interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
0 118 IRQ_TYPE_LEVEL_HIGH
0 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
0 122 IRQ_TYPE_LEVEL_HIGH
0 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
0 126 IRQ_TYPE_LEVEL_HIGH
0 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
cap-sd-highspeed;
cap-sdio-irq;
status = "disabled";
compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
reg = <0xfe1f0000 0x400>;
interrupts = <0 9 0x4>;
+ clocks = <&mstp3_clks R8A7740_CLK_FSI>;
status = "disabled";
};
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* External root clock */
+ extalr_clk: extalr_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "extalr";
+ };
+ extal1_clk: extal1_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "extal1";
+ };
+ extal2_clk: extal2_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "extal2";
+ };
+ dv_clk: dv_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "dv";
+ };
+ fsiack_clk: fsiack_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "fsiack";
+ };
+ fsibck_clk: fsibck_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ clock-output-names = "fsibck";
+ };
+
+ /* Special CPG clocks */
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a7740-cpg-clocks";
+ reg = <0xe6150000 0x10000>;
+ clocks = <&extal1_clk>, <&extalr_clk>;
+ #clock-cells = <1>;
+ clock-output-names = "system", "pllc0", "pllc1",
+ "pllc2", "r",
+ "usb24s",
+ "i", "zg", "b", "m1", "hp",
+ "hpp", "usbp", "s", "zb", "m3",
+ "cp";
+ };
+
+ /* Variable factor clocks (DIV6) */
+ sub_clk: sub_clk@e6150080 {
+ compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe6150080 4>;
+ clocks = <&pllc1_div2_clk>;
+ #clock-cells = <0>;
+ clock-output-names = "sub";
+ };
+
+ /* Fixed factor clocks */
+ pllc1_div2_clk: pllc1_div2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "pllc1_div2";
+ };
+ extal1_div2_clk: extal1_div2_clk {
+ compatible = "fixed-factor-clock";
+ clocks = <&extal1_clk>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ clock-output-names = "extal1_div2";
+ };
+
+ /* Gate clocks */
+ subck_clks: subck_clks@e6150080 {
+ compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xe6150080 4>;
+ clocks = <&sub_clk>, <&sub_clk>;
+ #clock-cells = <1>;
+ renesas,clock-indices = <
+ R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
+ >;
+ clock-output-names =
+ "subck", "subck2";
+ };
+ mstp1_clks: mstp1_clks@e6150134 {
+ compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xe6150134 4>, <0xe6150038 4>;
+ clocks = <&cpg_clocks R8A7740_CLK_S>,
+ <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
+ <&cpg_clocks R8A7740_CLK_B>,
+ <&sub_clk>, <&sub_clk>,
+ <&cpg_clocks R8A7740_CLK_B>;
+ #clock-cells = <1>;
+ renesas,clock-indices = <
+ R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
+ R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
+ R8A7740_CLK_LCDC0
+ >;
+ clock-output-names =
+ "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
+ "tmu1", "lcdc0";
+ };
+ mstp2_clks: mstp2_clks@e6150138 {
+ compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xe6150138 4>, <0xe6150040 4>;
+ clocks = <&sub_clk>, <&sub_clk>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&sub_clk>, <&sub_clk>, <&sub_clk>,
+ <&sub_clk>, <&sub_clk>, <&sub_clk>,
+ <&sub_clk>;
+ #clock-cells = <1>;
+ renesas,clock-indices = <
+ R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
+ R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
+ R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
+ R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
+ R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
+ R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
+ R8A7740_CLK_SCIFA4
+ >;
+ clock-output-names =
+ "scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
+ "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
+ "scifa2", "scifa3", "scifa4";
+ };
+ mstp3_clks: mstp3_clks@e615013c {
+ compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xe615013c 4>, <0xe6150048 4>;
+ clocks = <&cpg_clocks R8A7740_CLK_R>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&sub_clk>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>;
+ #clock-cells = <1>;
+ renesas,clock-indices = <
+ R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
+ R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
+ R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
+ >;
+ clock-output-names =
+ "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
+ "mmc", "gether", "tpu0";
+ };
+ mstp4_clks: mstp4_clks@e6150140 {
+ compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xe6150140 4>, <0xe615004c 4>;
+ clocks = <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>,
+ <&cpg_clocks R8A7740_CLK_HP>;
+ #clock-cells = <1>;
+ renesas,clock-indices = <
+ R8A7740_CLK_USBH R8A7740_CLK_SDHI2
+ R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
+ >;
+ clock-output-names =
+ "usbhost", "sdhi2", "usbfunc", "usphy";
+ };
+ };
};
interrupt-parent = <&gic>;
cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
cpu@0 {
+ device_type = "cpu";
compatible = "arm,cortex-a9";
+ reg = <0>;
+ clock-frequency = <800000000>;
};
};
compatible = "arm,cortex-a8";
device_type = "cpu";
reg = <0x0>;
+ clock-frequency = <800000000>;
};
};
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ clock-frequency = <1196000000>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ clock-frequency = <1196000000>;
};
};
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_CLPS711X=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_PWM=y
# CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_PWM_CLPS711X=y
CONFIG_EXT2_FS=y
CONFIG_CRAMFS=y
CONFIG_MINIX_FS=y
#include <linux/types.h>
#include <linux/i2c-gpio.h>
#include <linux/interrupt.h>
-#include <linux/backlight.h>
#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/pwm_backlight.h>
#include <linux/memblock.h>
#include <linux/mtd/physmap.h>
.set_power = edb7211_lcd_power_set,
};
-static void edb7211_lcd_backlight_set_intensity(int intensity)
-{
- gpio_set_value(EDB7211_LCDBL, !!intensity);
- clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON);
-}
+static struct pwm_lookup edb7211_pwm_lookup[] = {
+ PWM_LOOKUP("clps711x-pwm", 0, "pwm-backlight.0", NULL,
+ 0, PWM_POLARITY_NORMAL),
+};
-static struct generic_bl_info edb7211_lcd_backlight_pdata = {
- .name = "lcd-backlight.0",
- .default_intensity = 0x01,
- .max_intensity = 0x0f,
- .set_bl_intensity = edb7211_lcd_backlight_set_intensity,
+static struct platform_pwm_backlight_data pwm_bl_pdata = {
+ .dft_brightness = 0x01,
+ .max_brightness = 0x0f,
+ .enable_gpio = EDB7211_LCDBL,
};
+static struct resource clps711x_pwm_res =
+ DEFINE_RES_MEM(CLPS711X_PHYS_BASE + PMPCON, SZ_4);
+
static struct gpio edb7211_gpios[] __initconst = {
{ EDB7211_LCD_DC_DC_EN, GPIOF_OUT_INIT_LOW, "LCD DC-DC" },
{ EDB7211_LCDEN, GPIOF_OUT_INIT_LOW, "LCD POWER" },
- { EDB7211_LCDBL, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT" },
};
/* Reserve screen memory region at the start of main system memory. */
gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
platform_device_register(&edb7211_flash_pdev);
+
platform_device_register_data(NULL, "platform-lcd", 0,
&edb7211_lcd_power_pdata,
sizeof(edb7211_lcd_power_pdata));
- platform_device_register_data(NULL, "generic-bl", 0,
- &edb7211_lcd_backlight_pdata,
- sizeof(edb7211_lcd_backlight_pdata));
+
+ platform_device_register_simple("clps711x-pwm", PLATFORM_DEVID_NONE,
+ &clps711x_pwm_res, 1);
+ pwm_add_table(edb7211_pwm_lookup, ARRAY_SIZE(edb7211_pwm_lookup));
+
+ platform_device_register_data(&platform_bus, "pwm-backlight", 0,
+ &pwm_bl_pdata, sizeof(pwm_bl_pdata));
+
platform_device_register_simple("video-clps711x", 0, NULL, 0);
platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
ARRAY_SIZE(edb7211_cs8900_resource));
/*
* CLPS711X common devices definitions
*
- * Author: Alexander Shiyan <shc_work@mail.ru>, 2013
+ * Author: Alexander Shiyan <shc_work@mail.ru>, 2013-2014
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* (at your option) any later version.
*/
+#include <linux/io.h>
+#include <linux/of_fdt.h>
#include <linux/platform_device.h>
+#include <linux/random.h>
#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
+
+#include <asm/system_info.h>
#include <mach/hardware.h>
ARRAY_SIZE(clps711x_uart2_res));
};
+static void __init clps711x_soc_init(void)
+{
+ struct soc_device_attribute *soc_dev_attr;
+ struct soc_device *soc_dev;
+ void __iomem *base;
+ u32 id[5];
+
+ base = ioremap(CLPS711X_PHYS_BASE, SZ_32K);
+ if (!base)
+ return;
+
+ id[0] = readl(base + UNIQID);
+ id[1] = readl(base + RANDID0);
+ id[2] = readl(base + RANDID1);
+ id[3] = readl(base + RANDID2);
+ id[4] = readl(base + RANDID3);
+ system_rev = SYSFLG1_VERID(readl(base + SYSFLG1));
+
+ add_device_randomness(id, sizeof(id));
+
+ system_serial_low = id[0];
+
+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+ if (!soc_dev_attr)
+ goto out_unmap;
+
+ soc_dev_attr->machine = of_flat_dt_get_machine_name();
+ soc_dev_attr->family = "Cirrus Logic CLPS711X";
+ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", system_rev);
+ soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%08x", id[0]);
+
+ soc_dev = soc_device_register(soc_dev_attr);
+ if (IS_ERR(soc_dev)) {
+ kfree(soc_dev_attr->revision);
+ kfree(soc_dev_attr->soc_id);
+ kfree(soc_dev_attr);
+ }
+
+out_unmap:
+ iounmap(base);
+}
+
void __init clps711x_devices_init(void)
{
clps711x_add_cpuidle();
clps711x_add_gpio();
clps711x_add_syscon();
clps711x_add_uart();
+ clps711x_soc_init();
}
# Makefile for the linux kernel.
#
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/mach-shmobile/include
-
# Common objects
obj-y := timer.o console.o
r8a73a4_add_dt_devices();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
- platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
}
static const char *ape6evm_boards_compat_dt[] __initdata = {
};
DT_MACHINE_START(APE6EVM_DT, "ape6evm")
- .init_early = r8a73a4_init_early,
+ .init_early = shmobile_init_delay,
.init_machine = ape6evm_add_standard_devices,
+ .init_late = shmobile_init_late,
.dt_compat = ape6evm_boards_compat_dt,
MACHINE_END
};
DT_MACHINE_START(APE6EVM_DT, "ape6evm")
- .init_early = r8a73a4_init_early,
+ .init_early = shmobile_init_delay,
.init_machine = ape6evm_add_standard_devices,
+ .init_late = shmobile_init_late,
.dt_compat = ape6evm_boards_compat_dt,
MACHINE_END
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
+#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>
l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
#endif
- r8a7740_add_standard_devices_dt();
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
r8a7740_pm_init();
}
};
DT_MACHINE_START(BOCKW_DT, "bockw")
- .init_early = r8a7778_init_delay,
+ .init_early = shmobile_init_delay,
.init_irq = r8a7778_init_irq_dt,
.init_machine = bockw_init,
+ .init_late = shmobile_init_late,
.dt_compat = bockw_boards_compat_dt,
MACHINE_END
};
DT_MACHINE_START(BOCKW_DT, "bockw")
- .init_early = r8a7778_init_delay,
+ .init_early = shmobile_init_delay,
.init_irq = r8a7778_init_irq_dt,
.init_machine = bockw_init,
.dt_compat = bockw_boards_compat_dt,
DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
.smp = smp_ops(sh73a0_smp_ops),
.map_io = sh73a0_map_io,
- .init_early = sh73a0_init_delay,
- .nr_irqs = NR_IRQS_LEGACY,
+ .init_early = shmobile_init_delay,
.init_machine = kzm_init,
+ .init_late = shmobile_init_late,
.dt_compat = kzm9g_boards_compat_dt,
MACHINE_END
#include <video/sh_mobile_lcdc.h>
#include "common.h"
+#include "intc.h"
#include "irqs.h"
#include "sh73a0.h"
.smp = smp_ops(sh73a0_smp_ops),
.map_io = sh73a0_map_io,
.init_early = sh73a0_add_early_devices,
- .nr_irqs = NR_IRQS_LEGACY,
.init_irq = sh73a0_init_irq,
.init_machine = kzm_init,
.init_late = shmobile_init_late,
#include <asm/mach-types.h>
#include "common.h"
+#include "intc.h"
#include "irqs.h"
#include "pm-rmobile.h"
#include "sh-gpio.h"
.map_io = r8a7779_map_io,
.init_early = shmobile_init_delay,
.init_time = marzen_init_timer,
- .nr_irqs = NR_IRQS_LEGACY,
.init_irq = r8a7779_init_irq_dt,
.init_machine = marzen_init,
+ .init_late = shmobile_init_late,
.dt_compat = marzen_boards_compat_dt,
MACHINE_END
#define __ARCH_MACH_COMMON_H
extern void shmobile_earlytimer_init(void);
-extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
- unsigned int mult, unsigned int div);
extern void shmobile_init_delay(void);
struct twd_local_timer;
extern void shmobile_setup_console(void);
((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
(((i) & TS_HI_BIT) << TS_HI_SHIFT))
-#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
-#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz)))
/*
p ## _sense_registers, NULL), \
}
+/* INTCS */
+#define INTCS_VECT_BASE 0x3400
+#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
+
#endif /* __ASM_MACH_INTC_H */
#ifndef __SHMOBILE_IRQS_H
#define __SHMOBILE_IRQS_H
-#include <linux/sh_intc.h>
-#include <mach/irqs.h>
+#include "include/mach/irqs.h"
/* GIC */
#define gic_spi(nr) ((nr) + 32)
#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */
-/* INTCS */
-#define INTCS_VECT_BASE 0x3400
-#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
-#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
-
/* GPIO IRQ */
#define _GPIO_IRQ_BASE 2500
#define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x))
void r8a73a4_add_dt_devices(void);
void r8a73a4_clock_init(void);
void r8a73a4_pinmux_init(void);
-void r8a73a4_init_early(void);
#endif /* __ASM_R8A73A4_H__ */
extern void r8a7740_map_io(void);
extern void r8a7740_add_early_devices(void);
extern void r8a7740_add_standard_devices(void);
-extern void r8a7740_add_standard_devices_dt(void);
extern void r8a7740_clock_init(u8 md_ck);
extern void r8a7740_pinmux_init(void);
extern void r8a7740_pm_init(void);
DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
.init_early = shmobile_init_delay,
+ .init_late = shmobile_init_late,
.dt_compat = r7s72100_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
r8a73a4_register_dmac();
}
-void __init r8a73a4_init_early(void)
-{
-#ifndef CONFIG_ARM_ARCH_TIMER
- shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
-#endif
-}
-
#ifdef CONFIG_USE_OF
static const char *r8a73a4_boards_compat_dt[] __initdata = {
};
DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
- .init_early = r8a73a4_init_early,
+ .init_early = shmobile_init_delay,
+ .init_late = shmobile_init_late,
.dt_compat = r8a73a4_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
.num_resources = ARRAY_SIZE(ipmmu_resources),
};
-static struct platform_device *r8a7740_devices_dt[] __initdata = {
- &cmt1_device,
-};
-
static struct platform_device *r8a7740_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&irqpin3_device,
&tmu0_device,
&ipmmu_device,
+ &cmt1_device,
};
/* DMA */
/* add devices */
platform_add_devices(r8a7740_early_devices,
ARRAY_SIZE(r8a7740_early_devices));
- platform_add_devices(r8a7740_devices_dt,
- ARRAY_SIZE(r8a7740_devices_dt));
platform_add_devices(r8a7740_late_devices,
ARRAY_SIZE(r8a7740_late_devices));
{
early_platform_add_devices(r8a7740_early_devices,
ARRAY_SIZE(r8a7740_early_devices));
- early_platform_add_devices(r8a7740_devices_dt,
- ARRAY_SIZE(r8a7740_devices_dt));
/* setup early console here as well */
shmobile_setup_console();
#ifdef CONFIG_USE_OF
-void __init r8a7740_add_standard_devices_dt(void)
-{
- platform_add_devices(r8a7740_devices_dt,
- ARRAY_SIZE(r8a7740_devices_dt));
- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
void __init r8a7740_init_irq_of(void)
{
void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
static void __init r8a7740_generic_init(void)
{
r8a7740_clock_init(0);
- r8a7740_add_standard_devices_dt();
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char *r8a7740_boards_compat_dt[] __initdata = {
void __init r8a7778_init_late(void)
{
+ shmobile_init_late();
platform_device_register_full(&ehci_info);
platform_device_register_full(&ohci_info);
}
void __init r8a7778_init_delay(void)
{
- shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+ shmobile_init_delay();
}
#ifdef CONFIG_USE_OF
DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
.init_early = r8a7778_init_delay,
.init_irq = r8a7778_init_irq_dt,
+ .init_late = shmobile_init_late,
.dt_compat = r8a7778_compat_dt,
- .init_late = r8a7778_init_late,
MACHINE_END
#endif /* CONFIG_USE_OF */
DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
.map_io = r8a7779_map_io,
.init_early = shmobile_init_delay,
- .nr_irqs = NR_IRQS_LEGACY,
.init_irq = r8a7779_init_irq_dt,
- .init_late = r8a7779_init_late,
+ .init_late = shmobile_init_late,
.dt_compat = r8a7779_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
#include "common.h"
#include "dma-register.h"
+#include "intc.h"
#include "irqs.h"
#include "pm-rmobile.h"
#include "sh7372.h"
void __init sh7372_add_early_devices_dt(void)
{
- shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
+ shmobile_init_delay();
sh7372_add_early_devices();
}
DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
.map_io = sh7372_map_io,
.init_early = sh7372_add_early_devices_dt,
- .nr_irqs = NR_IRQS_LEGACY,
.init_irq = sh7372_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = sh7372_add_standard_devices_dt,
#include "common.h"
#include "dma-register.h"
+#include "intc.h"
#include "irqs.h"
#include "sh73a0.h"
void __init sh73a0_init_delay(void)
{
- shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
+ shmobile_init_delay();
}
/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
void __init sh73a0_add_standard_devices_dt(void)
{
- struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
-
/* clocks are setup late during boot in the case of DT */
sh73a0_clock_init();
platform_add_devices(sh73a0_devices_dt,
ARRAY_SIZE(sh73a0_devices_dt));
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-
- /* Instantiate cpufreq-cpu0 */
- platform_device_register_full(&devinfo);
}
static const char *sh73a0_boards_compat_dt[] __initdata = {
.smp = smp_ops(sh73a0_smp_ops),
.map_io = sh73a0_map_io,
.init_early = sh73a0_init_delay,
- .nr_irqs = NR_IRQS_LEGACY,
.init_machine = sh73a0_add_standard_devices_dt,
+ .init_late = shmobile_init_late,
.dt_compat = sh73a0_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
#include <linux/delay.h>
#include <linux/of_address.h>
-void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
- unsigned int mult, unsigned int div)
+static void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
+ unsigned int mult, unsigned int div)
{
/* calculate a worst-case loops-per-jiffy value
* based on maximum cpu core hz setting and the
preset_lpj = max_cpu_core_hz / value;
}
-void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
- unsigned int mult, unsigned int div)
-{
- /* calculate a worst-case loops-per-jiffy value
- * based on maximum cpu core mhz setting and the
- * __delay() implementation in arch/arm/lib/delay.S
- *
- * this will result in a longer delay than expected
- * when the cpu core runs on lower frequencies.
- */
-
- unsigned int value = (1000000 * mult) / (HZ * div);
-
- if (!preset_lpj)
- preset_lpj = max_cpu_core_mhz * value;
-}
-
void __init shmobile_init_delay(void)
{
struct device_node *np, *cpus;
--- /dev/null
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
+#define __DT_BINDINGS_CLOCK_R8A7740_H__
+
+/* CPG */
+#define R8A7740_CLK_SYSTEM 0
+#define R8A7740_CLK_PLLC0 1
+#define R8A7740_CLK_PLLC1 2
+#define R8A7740_CLK_PLLC2 3
+#define R8A7740_CLK_R 4
+#define R8A7740_CLK_USB24S 5
+#define R8A7740_CLK_I 6
+#define R8A7740_CLK_ZG 7
+#define R8A7740_CLK_B 8
+#define R8A7740_CLK_M1 9
+#define R8A7740_CLK_HP 10
+#define R8A7740_CLK_HPP 11
+#define R8A7740_CLK_USBP 12
+#define R8A7740_CLK_S 13
+#define R8A7740_CLK_ZB 14
+#define R8A7740_CLK_M3 15
+#define R8A7740_CLK_CP 16
+
+/* MSTP1 */
+#define R8A7740_CLK_CEU21 28
+#define R8A7740_CLK_CEU20 27
+#define R8A7740_CLK_TMU0 25
+#define R8A7740_CLK_LCDC1 17
+#define R8A7740_CLK_IIC0 16
+#define R8A7740_CLK_TMU1 11
+#define R8A7740_CLK_LCDC0 0
+
+/* MSTP2 */
+#define R8A7740_CLK_SCIFA6 30
+#define R8A7740_CLK_SCIFA7 22
+#define R8A7740_CLK_DMAC1 18
+#define R8A7740_CLK_DMAC2 17
+#define R8A7740_CLK_DMAC3 16
+#define R8A7740_CLK_USBDMAC 14
+#define R8A7740_CLK_SCIFA5 7
+#define R8A7740_CLK_SCIFB 6
+#define R8A7740_CLK_SCIFA0 4
+#define R8A7740_CLK_SCIFA1 3
+#define R8A7740_CLK_SCIFA2 2
+#define R8A7740_CLK_SCIFA3 1
+#define R8A7740_CLK_SCIFA4 0
+
+/* MSTP3 */
+#define R8A7740_CLK_CMT1 29
+#define R8A7740_CLK_FSI 28
+#define R8A7740_CLK_IIC1 23
+#define R8A7740_CLK_USBF 20
+#define R8A7740_CLK_SDHI0 14
+#define R8A7740_CLK_SDHI1 13
+#define R8A7740_CLK_MMC 12
+#define R8A7740_CLK_GETHER 9
+#define R8A7740_CLK_TPU0 4
+
+/* MSTP4 */
+#define R8A7740_CLK_USBH 16
+#define R8A7740_CLK_SDHI2 15
+#define R8A7740_CLK_USBFUNC 7
+#define R8A7740_CLK_USBPHY 6
+
+/* SUBCK* */
+#define R8A7740_CLK_SUBCK 9
+#define R8A7740_CLK_SUBCK2 10
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */
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