Merge tag 'dt2-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC DT updates part 2 from Arnd Bergmann:
 "This is a follow-up to the early ARM SoC DT changes, with additional
  content that has external dependencies:

   - The Tegra IOMMU DT support depends on changes from the iommu tree,
     plus the contents of the arm-soc drivers branch
   - The MVEBU PHY support depends on changes from the phy tree
   - The AT91 DT support depends on changes from the RTC and DMA-slave
     trees

  All of these changes just enable additional devices for existing
  platforms"

* tag 'dt2-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: tegra: Enable IOMMU for display controllers on Tegra124
  ARM: tegra: Enable IOMMU for display controllers on Tegra114
  ARM: tegra: Enable IOMMU for display controllers on Tegra30
  ARM: tegra: Add memory controller support for Tegra124
  ARM: tegra: Add memory controller support for Tegra114
  ARM: tegra: Add memory controller support for Tegra30
  ARM: tegra: Add APB_MISC_GP as a MIPI pad control bank
  ARM: mvebu: add PHY support to the dts for the USB controllers on Armada 375
  ARM: mvebu: add Device Tree description of USB cluster controller on Armada 375
  ARM: at91/dt: at91sam9g45: add ISI node
  ARM: at91/dt: enable the RTT block on the at91sam9m10g45ek board
  ARM: at91/dt: enable the RTT block on the sam9g20ek board
  ARM: at91/dt: add GPBR nodes
  ARM: at91/dt: add RTT nodes to at91 dtsis
  ARM: at91/dt: at91sam9rl: add rtc
  ARM: at91: fix GPLv2 wording
  ARM: at91/dt: sama5d4: add DMA support
  ARM: at91/dt: sama5d4: use macro instead of numeric value

diff --combined arch/arm/boot/dts/at91sam9g45.dtsi
index 6c0637a,c134242..2a8da8a
--- 1/arch/arm/boot/dts/at91sam9g45.dtsi
--- 2/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@@ -492,6 -492,27 +492,27 @@@
                                        };
                                };
  
+                               isi {
+                                       pinctrl_isi: isi-0 {
+                                               atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
+                                                             AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* D9 */
+                                                             AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
+                                                             AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* D11 */
+                                                             AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
+                                                             AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
+                                                             AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
+                                                             AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
+                                                             AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
+                                                             AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
+                                                             AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
+                                                             AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
+                                                             AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
+                                                             AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
+                                                             AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* HSYNC */
+                                                             AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* MCK */>;
+                                       };
+                               };
+ 
                                usart0 {
                                        pinctrl_usart0: usart0-0 {
                                                atmel,pins =
@@@ -940,13 -961,6 +961,13 @@@
                                status = "disabled";
                        };
  
 +                      trng@fffcc000 {
 +                              compatible = "atmel,at91sam9g45-trng";
 +                              reg = <0xfffcc000 0x4000>;
 +                              interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
 +                              clocks = <&trng_clk>;
 +                      };
 +
                        i2c0: i2c@fff84000 {
                                compatible = "atmel,at91sam9g10-i2c";
                                reg = <0xfff84000 0x100>;
@@@ -1035,6 -1049,17 +1056,17 @@@
                                };
                        };
  
+                       isi@fffb4000 {
+                               compatible = "atmel,at91sam9g45-isi";
+                               reg = <0xfffb4000 0x4000>;
+                               interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
+                               clocks = <&isi_clk>;
+                               clock-names = "isi_clk";
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_isi>;
+                               status = "disabled";
+                       };
+ 
                        pwm0: pwm@fffb8000 {
                                compatible = "atmel,at91sam9rl-pwm";
                                reg = <0xfffb8000 0x300>;
@@@ -1199,12 -1224,26 +1231,26 @@@
                                };
                        };
  
+                       rtc@fffffd20 {
+                               compatible = "atmel,at91sam9260-rtt";
+                               reg = <0xfffffd20 0x10>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                               clocks = <&clk32k>;
+                               status = "disabled";
+                       };
+ 
                        rtc@fffffdb0 {
                                compatible = "atmel,at91rm9200-rtc";
                                reg = <0xfffffdb0 0x30>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                status = "disabled";
                        };
+ 
+                       gpbr: syscon@fffffd60 {
+                               compatible = "atmel,at91sam9260-gpbr", "syscon";
+                               reg = <0xfffffd60 0x10>;
+                               status = "disabled";
+                       };
                };
  
                fb0: fb@0x00500000 {

diff --combined arch/arm/boot/dts/tegra114.dtsi
index 222f3b3,c8c3b64..4296b53
--- 1/arch/arm/boot/dts/tegra114.dtsi
--- 2/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@@ -1,5 -1,6 +1,6 @@@
  #include <dt-bindings/clock/tegra114-car.h>
  #include <dt-bindings/gpio/tegra-gpio.h>
+ #include <dt-bindings/memory/tegra114-mc.h>
  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
  #include <dt-bindings/interrupt-controller/arm-gic.h>
  
@@@ -9,6 -10,13 +10,6 @@@
        compatible = "nvidia,tegra114";
        interrupt-parent = <&gic>;
  
 -      aliases {
 -              serial0 = &uarta;
 -              serial1 = &uartb;
 -              serial2 = &uartc;
 -              serial3 = &uartd;
 -      };
 -
        host1x@50000000 {
                compatible = "nvidia,tegra114-host1x", "simple-bus";
                reg = <0x50000000 0x00028000>;
@@@ -50,6 -58,8 +51,8 @@@
                        resets = <&tegra_car 27>;
                        reset-names = "dc";
  
+                       iommus = <&mc TEGRA_SWGROUP_DC>;
+ 
                        nvidia,head = <0>;
  
                        rgb {
@@@ -67,6 -77,8 +70,8 @@@
                        resets = <&tegra_car 26>;
                        reset-names = "dc";
  
+                       iommus = <&mc TEGRA_SWGROUP_DCB>;
+ 
                        nvidia,head = <1>;
  
                        rgb {
@@@ -498,15 -510,15 +503,15 @@@
                reset-names = "fuse";
        };
  
-       iommu@70019010 {
-               compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
-               reg = <0x70019010 0x02c
-                      0x700191f0 0x010
-                      0x70019228 0x074>;
-               nvidia,#asids = <4>;
-               dma-window = <0 0x40000000>;
-               nvidia,swgroups = <0x18659fe>;
-               nvidia,ahb = <&ahb>;
+       mc: memory-controller@70019000 {
+               compatible = "nvidia,tegra114-mc";
+               reg = <0x70019000 0x1000>;
+               clocks = <&tegra_car TEGRA114_CLK_MC>;
+               clock-names = "mc";
+ 
+               interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ 
+               #iommu-cells = <1>;
        };
  
        ahub@70080000 {

diff --combined arch/arm/boot/dts/tegra124.dtsi
index df2b06b,a9f3a3e..3ad2e3c
--- 1/arch/arm/boot/dts/tegra124.dtsi
--- 2/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@@ -1,5 -1,6 +1,6 @@@
  #include <dt-bindings/clock/tegra124-car.h>
  #include <dt-bindings/gpio/tegra-gpio.h>
+ #include <dt-bindings/memory/tegra124-mc.h>
  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
  #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  #include <dt-bindings/interrupt-controller/arm-gic.h>
@@@ -102,6 -103,8 +103,8 @@@
                        resets = <&tegra_car 27>;
                        reset-names = "dc";
  
+                       iommus = <&mc TEGRA_SWGROUP_DC>;
+ 
                        nvidia,head = <0>;
                };
  
@@@ -115,6 -118,8 +118,8 @@@
                        resets = <&tegra_car 26>;
                        reset-names = "dc";
  
+                       iommus = <&mc TEGRA_SWGROUP_DCB>;
+ 
                        nvidia,head = <1>;
                };
  
@@@ -275,7 -280,8 +280,8 @@@
        pinmux: pinmux@0,70000868 {
                compatible = "nvidia,tegra124-pinmux";
                reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
-                     <0x0 0x70003000 0x0 0x434>; /* Mux registers */
+                     <0x0 0x70003000 0x0 0x434>, /* Mux registers */
+                     <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
        };
  
        /*
@@@ -286,7 -292,7 +292,7 @@@
         * the APB DMA based serial driver, the comptible is
         * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
         */
 -      serial@0,70006000 {
 +      uarta: serial@0,70006000 {
                compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
                reg = <0x0 0x70006000 0x0 0x40>;
                reg-shift = <2>;
@@@ -299,7 -305,7 +305,7 @@@
                status = "disabled";
        };
  
 -      serial@0,70006040 {
 +      uartb: serial@0,70006040 {
                compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
                reg = <0x0 0x70006040 0x0 0x40>;
                reg-shift = <2>;
@@@ -312,7 -318,7 +318,7 @@@
                status = "disabled";
        };
  
 -      serial@0,70006200 {
 +      uartc: serial@0,70006200 {
                compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
                reg = <0x0 0x70006200 0x0 0x40>;
                reg-shift = <2>;
@@@ -325,7 -331,7 +331,7 @@@
                status = "disabled";
        };
  
 -      serial@0,70006300 {
 +      uartd: serial@0,70006300 {
                compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
                reg = <0x0 0x70006300 0x0 0x40>;
                reg-shift = <2>;
@@@ -551,6 -557,17 +557,17 @@@
                reset-names = "fuse";
        };
  
+       mc: memory-controller@0,70019000 {
+               compatible = "nvidia,tegra124-mc";
+               reg = <0x0 0x70019000 0x0 0x1000>;
+               clocks = <&tegra_car TEGRA124_CLK_MC>;
+               clock-names = "mc";
+ 
+               interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ 
+               #iommu-cells = <1>;
+       };
+ 
        sata@0,70020000 {
                compatible = "nvidia,tegra124-ahci";
  

diff --combined arch/arm/boot/dts/tegra30.dtsi
index b270b9e,976eb9b..99475f6
--- 1/arch/arm/boot/dts/tegra30.dtsi
--- 2/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@@ -1,5 -1,6 +1,6 @@@
  #include <dt-bindings/clock/tegra30-car.h>
  #include <dt-bindings/gpio/tegra-gpio.h>
+ #include <dt-bindings/memory/tegra30-mc.h>
  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
  #include <dt-bindings/interrupt-controller/arm-gic.h>
  
@@@ -9,6 -10,14 +10,6 @@@
        compatible = "nvidia,tegra30";
        interrupt-parent = <&intc>;
  
 -      aliases {
 -              serial0 = &uarta;
 -              serial1 = &uartb;
 -              serial2 = &uartc;
 -              serial3 = &uartd;
 -              serial4 = &uarte;
 -      };
 -
        pcie-controller@00003000 {
                compatible = "nvidia,tegra30-pcie";
                device_type = "pci";
@@@ -166,6 -175,8 +167,8 @@@
                        resets = <&tegra_car 27>;
                        reset-names = "dc";
  
+                       iommus = <&mc TEGRA_SWGROUP_DC>;
+ 
                        nvidia,head = <0>;
  
                        rgb {
@@@ -183,6 -194,8 +186,8 @@@
                        resets = <&tegra_car 26>;
                        reset-names = "dc";
  
+                       iommus = <&mc TEGRA_SWGROUP_DCB>;
+ 
                        nvidia,head = <1>;
  
                        rgb {
@@@ -615,23 -628,15 +620,15 @@@
                clock-names = "pclk", "clk32k_in";
        };
  
-       memory-controller@7000f000 {
+       mc: memory-controller@7000f000 {
                compatible = "nvidia,tegra30-mc";
-               reg = <0x7000f000 0x010
-                      0x7000f03c 0x1b4
-                      0x7000f200 0x028
-                      0x7000f284 0x17c>;
+               reg = <0x7000f000 0x400>;
+               clocks = <&tegra_car TEGRA30_CLK_MC>;
+               clock-names = "mc";
+ 
                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-       };
  
-       iommu@7000f010 {
-               compatible = "nvidia,tegra30-smmu";
-               reg = <0x7000f010 0x02c
-                      0x7000f1f0 0x010
-                      0x7000f228 0x05c>;
-               nvidia,#asids = <4>;            /* # of ASIDs */
-               dma-window = <0 0x40000000>;    /* IOVA start & length */
-               nvidia,ahb = <&ahb>;
+               #iommu-cells = <1>;
        };
  
        fuse@7000f800 {