coresight: remove the unnecessary configuration coresight-default-sink
authorKaixu Xia <xiakaixu@huawei.com>
Mon, 30 Mar 2015 20:13:39 +0000 (14:13 -0600)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 3 Apr 2015 14:17:03 +0000 (16:17 +0200)
The coresight-default-sink configuration option has been
removed from the framework. As such remove it from DT and bindings.

Signed-off-by: Kaixu Xia <xiakaixu@huawei.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Documentation/devicetree/bindings/arm/coresight.txt
arch/arm/boot/dts/hip04.dtsi
arch/arm/boot/dts/omap3-beagle-xm.dts
arch/arm/boot/dts/omap3-beagle.dts
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

index a308935..88602b7 100644 (file)
@@ -61,7 +61,6 @@ Example:
                compatible = "arm,coresight-etb10", "arm,primecell";
                reg = <0 0x20010000 0 0x1000>;
 
-               coresight-default-sink;
                clocks = <&oscclk6a>;
                clock-names = "apb_pclk";
                port {
index 2388145..44044f2 100644 (file)
                compatible = "arm,coresight-etb10", "arm,primecell";
                reg = <0 0xe3c42000 0 0x1000>;
 
-               coresight-default-sink;
                clocks = <&clk_375m>;
                clock-names = "apb_pclk";
                port {
index 25f7b0a..8cdca51 100644 (file)
                compatible = "arm,coresight-etb10", "arm,primecell";
                reg = <0x5401b000 0x1000>;
 
-               coresight-default-sink;
                clocks = <&emu_src_ck>;
                clock-names = "apb_pclk";
                port {
index c792391..6d4c46b 100644 (file)
                compatible = "arm,coresight-etb10", "arm,primecell";
                reg = <0x5401b000 0x1000>;
 
-               coresight-default-sink;
                clocks = <&emu_src_ck>;
                clock-names = "apb_pclk";
                port {
index 33920df..7a2aeac 100644 (file)
                compatible = "arm,coresight-etb10", "arm,primecell";
                reg = <0 0x20010000 0 0x1000>;
 
-               coresight-default-sink;
                clocks = <&oscclk6a>;
                clock-names = "apb_pclk";
                port {