ARM: dts: uniphier: switch over to PSCI

Use PSCI for enable-method instead of SoC specific implementation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi
index be4e3b0..7fa6edb 100644 (file)
--- a/arch/arm/boot/dts/uniphier-common32.dtsi
+++ b/arch/arm/boot/dts/uniphier-common32.dtsi
@@ -45,6 +45,11 @@
 /include/ "skeleton.dtsi"
 
 / {
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
        clocks {
                refclk: ref {
                        #clock-cells = <0>;

diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 298fb38..72f8c35 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -56,6 +56,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
        };

diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index fd450f3..109046d 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -51,12 +51,12 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "socionext,uniphier-smp";
 
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
 
@@ -64,6 +64,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
        };

diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 9f9fd8c..ce8e549 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -51,12 +51,12 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "socionext,uniphier-smp";
 
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
 
@@ -64,6 +64,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
        };

diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 6d702d2..63c12e8 100644 (file)
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -51,12 +51,12 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "socionext,uniphier-smp";
 
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
 
@@ -64,6 +64,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
 
@@ -71,6 +72,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <2>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
 
@@ -78,6 +80,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <3>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
        };

diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi
index f33caf4..55f9afa 100644 (file)
--- a/arch/arm/boot/dts/uniphier-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld3.dtsi
@@ -51,12 +51,12 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               enable-method = "socionext,uniphier-smp";
 
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
 
@@ -64,10 +64,16 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
        };
 
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
        clocks {
                refclk: ref {
                        #clock-cells = <0>;

diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index 8bab1df..6191051 100644 (file)
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -56,6 +56,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       enable-method = "psci";
                        next-level-cache = <&l2>;
                };
        };