ARM: dts: zynq: Add SDHCI nodes
authorSoren Brinkmann <soren.brinkmann@xilinx.com>
Mon, 2 Dec 2013 18:02:37 +0000 (10:02 -0800)
committerOlof Johansson <olof@lixom.net>
Fri, 31 Jan 2014 22:58:56 +0000 (14:58 -0800)
Add nodes for the Arasan SDHCI controller to Zynq dts files.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
arch/arm/boot/dts/zynq-7000.dtsi
arch/arm/boot/dts/zynq-zc702.dts
arch/arm/boot/dts/zynq-zc706.dts
arch/arm/boot/dts/zynq-zed.dts

index 5d7681b..8b67b19 100644 (file)
                        clock-names = "pclk", "hclk", "tx_clk";
                };
 
+               sdhci0: ps7-sdhci@e0100000 {
+                       compatible = "arasan,sdhci-8.9a";
+                       status = "disabled";
+                       clock-names = "clk_xin", "clk_ahb";
+                       clocks = <&clkc 21>, <&clkc 32>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 24 4>;
+                       reg = <0xe0100000 0x1000>;
+               } ;
+
+               sdhci1: ps7-sdhci@e0101000 {
+                       compatible = "arasan,sdhci-8.9a";
+                       status = "disabled";
+                       clock-names = "clk_xin", "clk_ahb";
+                       clocks = <&clkc 22>, <&clkc 33>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 47 4>;
+                       reg = <0xe0101000 0x1000>;
+               } ;
+
                slcr: slcr@f8000000 {
                        compatible = "xlnx,zynq-slcr";
                        reg = <0xF8000000 0x1000>;
index 34d680a..c913f77 100644 (file)
        phy-mode = "rgmii";
 };
 
+&sdhci0 {
+       status = "okay";
+};
+
 &uart1 {
        status = "okay";
 };
index b2835d5..88f62c5 100644 (file)
        phy-mode = "rgmii";
 };
 
+&sdhci0 {
+       status = "okay";
+};
+
 &uart1 {
        status = "okay";
 };
index 2eda068..82d7ef1 100644 (file)
        phy-mode = "rgmii";
 };
 
+&sdhci0 {
+       status = "okay";
+};
+
 &uart1 {
        status = "okay";
 };